diff --git a/src/guest/pvr/ta.c b/src/guest/pvr/ta.c index 5b22e857..7d1cad32 100644 --- a/src/guest/pvr/ta.c +++ b/src/guest/pvr/ta.c @@ -319,20 +319,20 @@ void ta_texture_info(struct ta *ta, union tsp tsp, union tcw tcw, if (tcw.pixel_format == TA_PIXEL_4BPP || tcw.pixel_format == TA_PIXEL_8BPP) { uint32_t palette_addr = 0; - /* palette ram is 4096 bytes, with each palette tex being 4 bytes each, + /* palette ram is 4096 bytes, with each palette entry being 4 bytes each, resulting in 1 << 10 indexes */ if (tcw.pixel_format == TA_PIXEL_4BPP) { /* in 4bpp mode, the palette selector represents the upper 6 bits of the palette index, with the remaining 4 bits being filled in by the texture */ - palette_addr = (tcw.p.palette_selector << 4) * 4; - *palette_size = (1 << 4) * 4; + palette_addr = tcw.p.palette_selector << 6; + *palette_size = 1 << 6; } else if (tcw.pixel_format == TA_PIXEL_8BPP) { /* in 8bpp mode, the palette selector represents the upper 2 bits of the palette index, with the remaining 8 bits being filled in by the texture */ - palette_addr = ((tcw.p.palette_selector & 0x30) << 4) * 4; - *palette_size = (1 << 8) * 4; + palette_addr = (tcw.p.palette_selector >> 4) << 10; + *palette_size = 1 << 10; } *palette = &ta->pvr->palette_ram[palette_addr]; diff --git a/src/guest/pvr/ta.h b/src/guest/pvr/ta.h index 26fcd195..ad15aec5 100644 --- a/src/guest/pvr/ta.h +++ b/src/guest/pvr/ta.h @@ -48,7 +48,9 @@ static inline uint32_t ta_texture_addr(union tcw tcw) { } static inline int ta_texture_twiddled(union tcw tcw) { - return !tcw.scan_order; + return !tcw.scan_order || + /* paletted textures are always twiddled */ + tcw.pixel_format == TA_PIXEL_8BPP || tcw.pixel_format == TA_PIXEL_4BPP; } static inline int ta_texture_compressed(union tcw tcw) { @@ -56,7 +58,7 @@ static inline int ta_texture_compressed(union tcw tcw) { } static inline int ta_texture_mipmaps(union tcw tcw) { - return !tcw.scan_order && tcw.mip_mapped; + return ta_texture_twiddled(tcw) && tcw.mip_mapped; } static inline int ta_texture_width(union tsp tsp, union tcw tcw) {