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redream
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moved maple code out of holly/ 

added hw/ and jit/ folders, restructured accordingly
This commit is contained in:
Anthony Pesch 2015-09-10 13:52:41 -07:00
parent 0849868672
commit e83cad251a
83 changed files with 603 additions and 552 deletions
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59
CMakeLists.txt
View File

@ -103,40 +103,41 @@ add_custom_target(format ${CLANG_FORMAT_EXECUTABLE} -style=Google -i ${CLANG_FOR
#--------------------------------------------------
set(DREAVM_SOURCES
src/aica/aica.cc
src/core/assert.cc
src/core/filesystem.cc
src/core/log.cc
src/cpu/backend/interpreter/interpreter_backend.cc
src/cpu/backend/interpreter/interpreter_block.cc
src/cpu/backend/interpreter/interpreter_callbacks.cc
src/cpu/backend/x64/x64_backend.cc
src/cpu/backend/x64/x64_block.cc
src/cpu/backend/x64/x64_emitter.cc
src/cpu/frontend/sh4/sh4_builder.cc
src/cpu/frontend/sh4/sh4_emit.cc
src/cpu/frontend/sh4/sh4_frontend.cc
src/cpu/frontend/sh4/sh4_instr.cc
src/cpu/ir/ir_builder.cc
src/cpu/ir/passes/constant_propagation_pass.cc
src/cpu/ir/passes/context_promotion_pass.cc
src/cpu/ir/passes/control_flow_analysis_pass.cc
src/cpu/ir/passes/pass_runner.cc
src/cpu/ir/passes/register_allocation_pass.cc
src/cpu/ir/passes/validate_pass.cc
src/cpu/sh4.cc
src/cpu/runtime.cc
src/emu/disc.cc
src/emu/dreamcast.cc
src/emu/profiler.cc
src/emu/scheduler.cc
src/gdrom/gdrom.cc
src/holly/holly.cc
src/holly/maple.cc
src/holly/maple_controller.cc
src/holly/pvr2.cc
src/holly/tile_accelerator.cc
src/holly/tile_renderer.cc
src/hw/aica/aica.cc
src/hw/gdrom/disc.cc
src/hw/gdrom/gdrom.cc
src/hw/holly/holly.cc
src/hw/holly/pvr2.cc
src/hw/holly/tile_accelerator.cc
src/hw/holly/tile_renderer.cc
src/hw/maple/maple.cc
src/hw/maple/maple_controller.cc
src/hw/sh4/sh4.cc
src/hw/scheduler.cc
src/jit/backend/interpreter/interpreter_backend.cc
src/jit/backend/interpreter/interpreter_block.cc
src/jit/backend/interpreter/interpreter_callbacks.cc
src/jit/backend/x64/x64_backend.cc
src/jit/backend/x64/x64_block.cc
src/jit/backend/x64/x64_emitter.cc
src/jit/frontend/sh4/sh4_builder.cc
src/jit/frontend/sh4/sh4_context.cc
src/jit/frontend/sh4/sh4_emit.cc
src/jit/frontend/sh4/sh4_frontend.cc
src/jit/frontend/sh4/sh4_instr.cc
src/jit/ir/ir_builder.cc
src/jit/ir/passes/constant_propagation_pass.cc
src/jit/ir/passes/context_promotion_pass.cc
src/jit/ir/passes/control_flow_analysis_pass.cc
src/jit/ir/passes/pass_runner.cc
src/jit/ir/passes/register_allocation_pass.cc
src/jit/ir/passes/validate_pass.cc
src/jit/runtime.cc
src/renderer/gl_backend.cc
src/renderer/gl_shader.cc
src/system/keys.cc

10
src/core/platform.h
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@ -11,14 +11,4 @@
#error "Unsupported platform"
#endif
#if defined(__GNUC__)
#define COMPILER_GCC
#elif defined(__clang__)
#define COMPILER_CLANG
#elif defined(_MSC_VER)
#define COMPILER_MSVC
#else
#error "Unsupported compiler"
#endif
#endif

79
src/emu/dreamcast.cc
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@ -1,21 +1,24 @@
#include "core/core.h"
#include "cpu/backend/interpreter/interpreter_backend.h"
#include "cpu/backend/x64/x64_backend.h"
#include "cpu/frontend/sh4/sh4_frontend.h"
#include "jit/backend/interpreter/interpreter_backend.h"
#include "jit/backend/x64/x64_backend.h"
#include "jit/frontend/sh4/sh4_frontend.h"
#include "emu/dreamcast.h"
#include "emu/profiler.h"
#include "holly/maple_controller.h"
#include "hw/maple/maple_controller.h"
#include "renderer/gl_backend.h"
using namespace dreavm::aica;
using namespace dreavm::core;
using namespace dreavm::cpu;
using namespace dreavm::cpu::backend::interpreter;
using namespace dreavm::cpu::backend::x64;
using namespace dreavm::cpu::frontend::sh4;
using namespace dreavm::emu;
using namespace dreavm::gdrom;
using namespace dreavm::holly;
using namespace dreavm::hw;
using namespace dreavm::hw::aica;
using namespace dreavm::hw::gdrom;
using namespace dreavm::hw::holly;
using namespace dreavm::hw::maple;
using namespace dreavm::hw::sh4;
using namespace dreavm::jit;
using namespace dreavm::jit::backend::interpreter;
using namespace dreavm::jit::backend::x64;
using namespace dreavm::jit::frontend::sh4;
using namespace dreavm::renderer;
using namespace dreavm::system;
using namespace dreavm::trace;
@ -32,7 +35,7 @@ Dreamcast::Dreamcast() {
rt_backend_ = std::unique_ptr<backend::Backend>(new X64Backend(*memory()));
runtime_ = std::unique_ptr<Runtime>(
new Runtime(*memory(), *rt_frontend_.get(), *rt_backend_.get()));
cpu_ = std::unique_ptr<SH4>(new SH4(*memory(), *runtime()));
sh4_ = std::unique_ptr<SH4>(new SH4(*memory(), *runtime()));
aica_ = std::unique_ptr<AICA>(new AICA(this));
holly_ = std::unique_ptr<Holly>(new Holly(this));
pvr_ = std::unique_ptr<PVR2>(new PVR2(this));
@ -103,7 +106,7 @@ bool Dreamcast::Init() {
InitMemory();
InitRegisters();
cpu_->Init();
sh4_->Init();
aica_->Init();
holly_->Init();
pvr_->Init();
@ -111,7 +114,7 @@ bool Dreamcast::Init() {
gdrom_->Init();
maple_->Init();
scheduler_->AddDevice(cpu());
scheduler_->AddDevice(sh4());
scheduler_->AddDevice(aica());
return true;
@ -235,43 +238,43 @@ void Dreamcast::InitMemory() {
// cpu
memory_->Handle(SH4_REG_START, SH4_REG_END, MIRROR_MASK,
std::bind(&SH4::ReadRegister8, cpu(), _1), //
std::bind(&SH4::ReadRegister16, cpu(), _1), //
std::bind(&SH4::ReadRegister32, cpu(), _1), //
std::bind(&SH4::ReadRegister8, sh4(), _1), //
std::bind(&SH4::ReadRegister16, sh4(), _1), //
std::bind(&SH4::ReadRegister32, sh4(), _1), //
nullptr, //
std::bind(&SH4::WriteRegister8, cpu(), _1, _2), //
std::bind(&SH4::WriteRegister16, cpu(), _1, _2), //
std::bind(&SH4::WriteRegister32, cpu(), _1, _2), //
std::bind(&SH4::WriteRegister8, sh4(), _1, _2), //
std::bind(&SH4::WriteRegister16, sh4(), _1, _2), //
std::bind(&SH4::WriteRegister32, sh4(), _1, _2), //
nullptr);
memory_->Handle(SH4_CACHE_START, SH4_CACHE_END, 0x0,
std::bind(&SH4::ReadCache8, cpu(), _1), //
std::bind(&SH4::ReadCache16, cpu(), _1), //
std::bind(&SH4::ReadCache32, cpu(), _1), //
std::bind(&SH4::ReadCache64, cpu(), _1), //
std::bind(&SH4::WriteCache8, cpu(), _1, _2), //
std::bind(&SH4::WriteCache16, cpu(), _1, _2), //
std::bind(&SH4::WriteCache32, cpu(), _1, _2), //
std::bind(&SH4::WriteCache64, cpu(), _1, _2));
std::bind(&SH4::ReadCache8, sh4(), _1), //
std::bind(&SH4::ReadCache16, sh4(), _1), //
std::bind(&SH4::ReadCache32, sh4(), _1), //
std::bind(&SH4::ReadCache64, sh4(), _1), //
std::bind(&SH4::WriteCache8, sh4(), _1, _2), //
std::bind(&SH4::WriteCache16, sh4(), _1, _2), //
std::bind(&SH4::WriteCache32, sh4(), _1, _2), //
std::bind(&SH4::WriteCache64, sh4(), _1, _2));
memory_->Handle(SH4_SQ_START, SH4_SQ_END, 0x0,
std::bind(&SH4::ReadSQ8, cpu(), _1), //
std::bind(&SH4::ReadSQ16, cpu(), _1), //
std::bind(&SH4::ReadSQ32, cpu(), _1), //
std::bind(&SH4::ReadSQ8, sh4(), _1), //
std::bind(&SH4::ReadSQ16, sh4(), _1), //
std::bind(&SH4::ReadSQ32, sh4(), _1), //
nullptr, //
std::bind(&SH4::WriteSQ8, cpu(), _1, _2), //
std::bind(&SH4::WriteSQ16, cpu(), _1, _2), //
std::bind(&SH4::WriteSQ32, cpu(), _1, _2), //
std::bind(&SH4::WriteSQ8, sh4(), _1, _2), //
std::bind(&SH4::WriteSQ16, sh4(), _1, _2), //
std::bind(&SH4::WriteSQ32, sh4(), _1, _2), //
nullptr);
}
void Dreamcast::InitRegisters() {
#define HOLLY_REG(addr, name, flags, default, type) \
holly_regs_[name##_OFFSET] = {flags, default};
#include "holly/holly_regs.inc"
#include "hw/holly/holly_regs.inc"
#undef HOLLY_REG
#define PVR_REG(addr, name, flags, default, type) \
pvr_regs_[name##_OFFSET] = {flags, default};
#include "holly/pvr2_regs.inc"
#include "hw/holly/pvr2_regs.inc"
#undef PVR_REG
}
@ -355,7 +358,7 @@ bool Dreamcast::LaunchBIN(const char *path) {
memory_->Memcpy(0x0c010000, data, size);
free(data);
cpu_->SetPC(0x0c010000);
sh4_->SetPC(0x0c010000);
return true;
}
@ -368,7 +371,7 @@ bool Dreamcast::LaunchGDI(const char *path) {
}
gdrom_->SetDisc(std::move(gdi));
cpu_->SetPC(0xa0000000);
sh4_->SetPC(0xa0000000);
return true;
}

80
src/emu/dreamcast.h
View File

@ -2,18 +2,18 @@
#define DREAMCAST_H
#include <memory>
#include "aica/aica.h"
#include "cpu/backend/backend.h"
#include "cpu/frontend/frontend.h"
#include "cpu/runtime.h"
#include "cpu/sh4.h"
#include "emu/memory.h"
#include "emu/scheduler.h"
#include "gdrom/gdrom.h"
#include "holly/holly.h"
#include "holly/maple.h"
#include "holly/pvr2.h"
#include "holly/tile_accelerator.h"
#include "hw/aica/aica.h"
#include "hw/sh4/sh4.h"
#include "hw/gdrom/gdrom.h"
#include "hw/holly/holly.h"
#include "hw/holly/pvr2.h"
#include "hw/holly/tile_accelerator.h"
#include "hw/maple/maple.h"
#include "hw/memory.h"
#include "hw/scheduler.h"
#include "jit/backend/backend.h"
#include "jit/frontend/frontend.h"
#include "jit/runtime.h"
#include "renderer/backend.h"
#include "system/system.h"
#include "trace/trace.h"
@ -29,7 +29,7 @@ namespace emu {
enum {
// ignore all access modifier bits
MIRROR_MASK = ~cpu::ADDR_MASK,
MIRROR_MASK = ~hw::sh4::ADDR_MASK,
// main ram is mirrored an additional four times:
// 0x0c000000 - 0x0cffffff
@ -81,33 +81,33 @@ struct Register {
enum {
#define AICA_REG(addr, name, flags, default, type) \
name##_OFFSET = addr - emu::AICA_REG_START,
#include "aica/aica_regs.inc"
#include "hw/aica/aica_regs.inc"
#undef AICA_REG
#define HOLLY_REG(addr, name, flags, default, type) \
name##_OFFSET = (addr - emu::HOLLY_REG_START) >> 2,
#include "holly/holly_regs.inc"
#include "hw/holly/holly_regs.inc"
#undef HOLLY_REG
#define PVR_REG(addr, name, flags, default_value, type) \
name##_OFFSET = (addr - emu::PVR_REG_START) >> 2,
#include "holly/pvr2_regs.inc"
#include "hw/holly/pvr2_regs.inc"
#undef PVR_REG
};
class Dreamcast {
public:
emu::Scheduler *scheduler() { return scheduler_.get(); }
emu::Memory *memory() { return memory_.get(); }
hw::Memory *memory() { return memory_.get(); }
hw::Scheduler *scheduler() { return scheduler_.get(); }
renderer::Backend *rb() { return rb_.get(); }
cpu::Runtime *runtime() { return runtime_.get(); }
cpu::SH4 *cpu() { return cpu_.get(); }
aica::AICA *aica() { return aica_.get(); }
holly::Holly *holly() { return holly_.get(); }
holly::PVR2 *pvr() { return pvr_.get(); }
holly::TileAccelerator *ta() { return ta_.get(); }
gdrom::GDROM *gdrom() { return gdrom_.get(); }
holly::Maple *maple() { return maple_.get(); }
jit::Runtime *runtime() { return runtime_.get(); }
hw::aica::AICA *aica() { return aica_.get(); }
hw::gdrom::GDROM *gdrom() { return gdrom_.get(); }
hw::holly::Holly *holly() { return holly_.get(); }
hw::holly::PVR2 *pvr() { return pvr_.get(); }
hw::holly::TileAccelerator *ta() { return ta_.get(); }
hw::maple::Maple *maple() { return maple_.get(); }
hw::sh4::SH4 *sh4() { return sh4_.get(); }
trace::TraceWriter *trace_writer() { return trace_writer_.get(); }
uint8_t *aica_regs() { return aica_regs_; }
@ -124,12 +124,12 @@ class Dreamcast {
#define HOLLY_REG(offset, name, flags, default, type) \
type &name{reinterpret_cast<type &>(holly_regs_[name##_OFFSET].value)};
#include "holly/holly_regs.inc"
#include "hw/holly/holly_regs.inc"
#undef HOLLY_REG
#define PVR_REG(offset, name, flags, default, type) \
type &name{reinterpret_cast<type &>(pvr_regs_[name##_OFFSET].value)};
#include "holly/pvr2_regs.inc"
#include "hw/holly/pvr2_regs.inc"
#undef PVR_REG
private:
@ -147,19 +147,19 @@ class Dreamcast {
void RenderFrame();
system::System sys_;
std::unique_ptr<emu::Scheduler> scheduler_;
std::unique_ptr<emu::Memory> memory_;
std::unique_ptr<hw::Memory> memory_;
std::unique_ptr<hw::Scheduler> scheduler_;
std::unique_ptr<renderer::Backend> rb_;
std::unique_ptr<cpu::frontend::Frontend> rt_frontend_;
std::unique_ptr<cpu::backend::Backend> rt_backend_;
std::unique_ptr<cpu::Runtime> runtime_;
std::unique_ptr<cpu::SH4> cpu_;
std::unique_ptr<aica::AICA> aica_;
std::unique_ptr<holly::Holly> holly_;
std::unique_ptr<holly::PVR2> pvr_;
std::unique_ptr<holly::TileAccelerator> ta_;
std::unique_ptr<gdrom::GDROM> gdrom_;
std::unique_ptr<holly::Maple> maple_;
std::unique_ptr<jit::frontend::Frontend> rt_frontend_;
std::unique_ptr<jit::backend::Backend> rt_backend_;
std::unique_ptr<jit::Runtime> runtime_;
std::unique_ptr<hw::aica::AICA> aica_;
std::unique_ptr<hw::gdrom::GDROM> gdrom_;
std::unique_ptr<hw::holly::Holly> holly_;
std::unique_ptr<hw::holly::PVR2> pvr_;
std::unique_ptr<hw::holly::TileAccelerator> ta_;
std::unique_ptr<hw::maple::Maple> maple_;
std::unique_ptr<hw::sh4::SH4> sh4_;
std::unique_ptr<trace::TraceWriter> trace_writer_;
Register holly_regs_[HOLLY_REG_SIZE >> 2];

6
src/aica/aica.cc → src/hw/aica/aica.cc
View File

@ -1,9 +1,9 @@
#include "aica/aica.h"
#include "emu/dreamcast.h"
#include "hw/aica/aica.h"
using namespace dreavm::aica;
using namespace dreavm::emu;
using namespace dreavm::holly;
using namespace dreavm::hw::aica;
using namespace dreavm::hw::holly;
AICA::AICA(Dreamcast *dc) : dc_(dc) {}

6
src/aica/aica.h → src/hw/aica/aica.h
View File

@ -2,16 +2,17 @@
#define AICA_H
#include <stdint.h>
#include "emu/device.h"
#include "hw/device.h"
namespace dreavm {
namespace emu {
class Dreamcast;
}
namespace hw {
namespace aica {
class AICA : public emu::Device {
class AICA : public hw::Device {
public:
AICA(emu::Dreamcast *dc);
@ -33,5 +34,6 @@ class AICA : public emu::Device {
};
}
}
}
#endif

0
src/aica/aica_regs.inc → src/hw/aica/aica_regs.inc
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2
src/emu/device.h → src/hw/device.h
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@ -4,7 +4,7 @@
#include <stdint.h>
namespace dreavm {
namespace emu {
namespace hw {
class Device {
public:

4
src/emu/disc.cc → src/hw/gdrom/disc.cc
View File

@ -1,10 +1,10 @@
#include "core/core.h"
#include "emu/disc.h"
#include "hw/gdrom/disc.h"
#define PREGAP_SIZE 150
using namespace dreavm::core;
using namespace dreavm::emu;
using namespace dreavm::hw::gdrom;
//
// GDI format

4
src/emu/disc.h → src/hw/gdrom/disc.h
View File

@ -5,7 +5,8 @@
#include "core/filesystem.h"
namespace dreavm {
namespace emu {
namespace hw {
namespace gdrom {
enum { SECTOR_SIZE = 2352 };
@ -53,5 +54,6 @@ class GDI : public Disc {
};
}
}
}
#endif

8
src/gdrom/gdrom.cc → src/hw/gdrom/gdrom.cc
View File

@ -1,12 +1,12 @@
#include "core/core.h"
#include "emu/dreamcast.h"
#include "gdrom/gdrom_replies.inc"
#include "hw/gdrom/gdrom_replies.inc"
using namespace dreavm::core;
using namespace dreavm::cpu;
using namespace dreavm::emu;
using namespace dreavm::gdrom;
using namespace dreavm::holly;
using namespace dreavm::hw::gdrom;
using namespace dreavm::hw::holly;
using namespace dreavm::hw::sh4;
#define SWAP_24(fad) \
(((fad & 0xff) << 16) | (fad & 0x00ff00) | ((fad & 0xff0000) >> 16))

15
src/gdrom/gdrom.h → src/hw/gdrom/gdrom.h
View File

@ -2,19 +2,21 @@
#define GDROM_H
#include <memory>
#include "emu/disc.h"
#include "hw/gdrom/disc.h"
namespace dreavm {
namespace emu {
class Dreamcast;
class Memory;
struct Register;
}
namespace hw {
namespace holly {
class Holly;
}
class Memory;
namespace gdrom {
enum GDState { //
@ -210,7 +212,7 @@ class GDROM {
void Init();
void SetDisc(std::unique_ptr<emu::Disc> disc);
void SetDisc(std::unique_ptr<Disc> disc);
uint8_t ReadRegister8(uint32_t addr);
uint16_t ReadRegister16(uint32_t addr);
@ -233,8 +235,8 @@ class GDROM {
uint8_t *dst);
emu::Dreamcast *dc_;
emu::Memory *memory_;
holly::Holly *holly_;
hw::Memory *memory_;
hw::holly::Holly *holly_;
emu::Register *holly_regs_;
GD_FEATURES_T features_;
@ -251,9 +253,10 @@ class GDROM {
GDState state_;
int spi_read_offset_;
std::unique_ptr<emu::Disc> current_disc_;
std::unique_ptr<Disc> current_disc_;
};
}
}
}
#endif

0
src/gdrom/gdrom_replies.inc → src/hw/gdrom/gdrom_replies.inc
View File

20
src/holly/holly.cc → src/hw/holly/holly.cc
View File

@ -2,16 +2,16 @@
#include "emu/dreamcast.h"
using namespace dreavm::core;
using namespace dreavm::cpu;
using namespace dreavm::emu;
using namespace dreavm::holly;
using namespace dreavm::hw::holly;
using namespace dreavm::hw::sh4;
using namespace dreavm::renderer;
using namespace dreavm::system;
Holly::Holly(Dreamcast *dc) : dc_(dc) {}
void Holly::Init() {
cpu_ = dc_->cpu();
sh4_ = dc_->sh4();
holly_regs_ = dc_->holly_regs();
}
@ -163,7 +163,7 @@ void Holly::WriteRegister32(uint32_t addr, uint32_t value) {
// FIXME what are SB_LMMODE0 / SB_LMMODE1
void Holly::CH2DMATransfer() {
cpu_->DDT(2, DDT_W, dc_->SB_C2DSTAT);
sh4_->DDT(2, DDT_W, dc_->SB_C2DSTAT);
dc_->SB_C2DLEN = 0;
dc_->SB_C2DST = 0;
@ -182,9 +182,9 @@ void Holly::ForwardRequestInterrupts() {
if ((dc_->SB_ISTNRM & dc_->SB_IML6NRM) ||
(dc_->SB_ISTERR & dc_->SB_IML6ERR) ||
(dc_->SB_ISTEXT & dc_->SB_IML6EXT)) {
cpu_->RequestInterrupt(SH4_INTC_IRL_9);
sh4_->RequestInterrupt(SH4_INTC_IRL_9);
} else {
cpu_->UnrequestInterrupt(SH4_INTC_IRL_9);
sh4_->UnrequestInterrupt(SH4_INTC_IRL_9);
}
}
@ -192,9 +192,9 @@ void Holly::ForwardRequestInterrupts() {
if ((dc_->SB_ISTNRM & dc_->SB_IML4NRM) ||
(dc_->SB_ISTERR & dc_->SB_IML4ERR) ||
(dc_->SB_ISTEXT & dc_->SB_IML4EXT)) {
cpu_->RequestInterrupt(SH4_INTC_IRL_11);
sh4_->RequestInterrupt(SH4_INTC_IRL_11);
} else {
cpu_->UnrequestInterrupt(SH4_INTC_IRL_11);
sh4_->UnrequestInterrupt(SH4_INTC_IRL_11);
}
}
@ -202,9 +202,9 @@ void Holly::ForwardRequestInterrupts() {
if ((dc_->SB_ISTNRM & dc_->SB_IML2NRM) ||
(dc_->SB_ISTERR & dc_->SB_IML2ERR) ||
(dc_->SB_ISTEXT & dc_->SB_IML2EXT)) {
cpu_->RequestInterrupt(SH4_INTC_IRL_13);
sh4_->RequestInterrupt(SH4_INTC_IRL_13);
} else {
cpu_->UnrequestInterrupt(SH4_INTC_IRL_13);
sh4_->UnrequestInterrupt(SH4_INTC_IRL_13);
}
}
}

11
src/holly/holly.h → src/hw/holly/holly.h
View File

@ -4,14 +4,16 @@
#include <stdint.h>
namespace dreavm {
namespace cpu {
class SH4;
}
namespace emu {
class Dreamcast;
struct Register;
}
namespace hw {
namespace sh4 {
class SH4;
}
namespace holly {
// interrupts
@ -167,10 +169,11 @@ class Holly {
void ForwardRequestInterrupts();
emu::Dreamcast *dc_;
cpu::SH4 *cpu_;
emu::Register *holly_regs_;
hw::sh4::SH4 *sh4_;
};
}
}
}
#endif

0
src/holly/holly_regs.inc → src/hw/holly/holly_regs.inc
View File

2
src/holly/pixel_convert.h → src/hw/holly/pixel_convert.h
View File

@ -18,6 +18,7 @@
(x / min + y / min) * min * min)
namespace dreavm {
namespace hw {
namespace holly {
class ARGB1555 {
@ -242,5 +243,6 @@ class PixelConvert {
};
}
}
}
#endif

4
src/holly/pvr2.cc → src/hw/holly/pvr2.cc
View File

@ -1,9 +1,9 @@
#include "core/core.h"
#include "emu/dreamcast.h"
using namespace dreavm::cpu;
using namespace dreavm::emu;
using namespace dreavm::holly;
using namespace dreavm::hw::holly;
using namespace dreavm::hw::sh4;
using namespace dreavm::renderer;
PVR2::PVR2(Dreamcast *dc)

14
src/holly/pvr2.h → src/hw/holly/pvr2.h
View File

@ -1,14 +1,15 @@
#ifndef PVR_CLX2_H
#define PVR_CLX2_H
#include "emu/scheduler.h"
#include <stdint.h>
#include "hw/scheduler.h"
namespace dreavm {
namespace emu {
class Dreamcast;
class Scheduler;
}
namespace hw {
namespace holly {
class Holly;
@ -218,13 +219,13 @@ class PVR2 {
void LineClockUpdate();
emu::Dreamcast *dc_;
emu::Scheduler *scheduler_;
holly::Holly *holly_;
holly::TileAccelerator *ta_;
hw::Scheduler *scheduler_;
hw::holly::Holly *holly_;
hw::holly::TileAccelerator *ta_;
emu::Register *pvr_regs_;
uint8_t *video_ram_;
emu::TimerHandle line_timer_;
hw::TimerHandle line_timer_;
uint32_t current_scanline_;
std::chrono::high_resolution_clock::time_point last_frame_;
float fps_;
@ -233,5 +234,6 @@ class PVR2 {
};
}
}
}
#endif

32
src/holly/pvr2_regs.inc → src/hw/holly/pvr2_regs.inc
View File

@ -3,12 +3,12 @@ PVR_REG(0x005f8004, REVISION, R, 0x00000011, uint32_t)
PVR_REG(0x005f8008, SOFTRESET, RW, 0x00000007, uint32_t)
PVR_REG(0x005f8014, STARTRENDER, RW, 0x00000000, uint32_t)
PVR_REG(0x005f8018, TEST_SELECT, RW, 0x00000000, uint32_t)
PVR_REG(0x005f8020, PARAM_BASE, RW, 0x00000000, holly::PARAM_BASE_T)
PVR_REG(0x005f8020, PARAM_BASE, RW, 0x00000000, hw::holly::PARAM_BASE_T)
PVR_REG(0x005f802c, REGION_BASE, RW, 0x00000000, uint32_t)
PVR_REG(0x005f8030, SPAN_SORT_CFG, RW, 0x00000000, uint32_t)
PVR_REG(0x005f8040, VO_BORDER_COL, RW, 0x00000000, uint32_t)
PVR_REG(0x005f8044, FB_R_CTRL, RW, 0x00000000, holly::FB_R_CTRL_T)
PVR_REG(0x005f8048, FB_W_CTRL, RW, 0x00000000, holly::FB_W_CTRL_T)
PVR_REG(0x005f8044, FB_R_CTRL, RW, 0x00000000, hw::holly::FB_R_CTRL_T)
PVR_REG(0x005f8048, FB_W_CTRL, RW, 0x00000000, hw::holly::FB_W_CTRL_T)
PVR_REG(0x005f804c, FB_W_LINESTRIDE, RW, 0x00000000, uint32_t)
PVR_REG(0x005f8050, FB_R_SOF1, RW, 0x00000000, uint32_t)
PVR_REG(0x005f8054, FB_R_SOF2, RW, 0x00000000, uint32_t)
@ -17,14 +17,14 @@ PVR_REG(0x005f8060, FB_W_SOF1, RW, 0x00000000, uint32_t)
PVR_REG(0x005f8064, FB_W_SOF2, RW, 0x00000000, uint32_t)
PVR_REG(0x005f8068, FB_X_CLIP, RW, 0x00000000, uint32_t)
PVR_REG(0x005f806c, FB_Y_CLIP, RW, 0x00000000, uint32_t)
PVR_REG(0x005f8074, FPU_SHAD_SCALE, RW, 0x00000000, holly::FPU_SHAD_SCALE_T)
PVR_REG(0x005f8074, FPU_SHAD_SCALE, RW, 0x00000000, hw::holly::FPU_SHAD_SCALE_T)
PVR_REG(0x005f8078, FPU_CULL_VAL, RW, 0x00000000, uint32_t)
PVR_REG(0x005f807c, FPU_PARAM_CFG, RW, 0x0007df77, holly::FPU_PARAM_CFG_T)
PVR_REG(0x005f807c, FPU_PARAM_CFG, RW, 0x0007df77, hw::holly::FPU_PARAM_CFG_T)
PVR_REG(0x005f8080, HALF_OFFSET, RW, 0x00000007, uint32_t)
PVR_REG(0x005f8084, FPU_PERP_VAL, RW, 0x00000000, uint32_t)
PVR_REG(0x005f8088, ISP_BACKGND_D, RW, 0x00000000, uint32_t)
PVR_REG(0x005f808c, ISP_BACKGND_T, RW, 0x00000000, holly::ISP_BACKGND_T_T)
PVR_REG(0x005f8098, ISP_FEED_CFG, RW, 0x00402000, holly::ISP_FEED_CFG_T)
PVR_REG(0x005f808c, ISP_BACKGND_T, RW, 0x00000000, hw::holly::ISP_BACKGND_T_T)
PVR_REG(0x005f8098, ISP_FEED_CFG, RW, 0x00402000, hw::holly::ISP_FEED_CFG_T)
PVR_REG(0x005f80a0, SDRAM_REFRESH, RW, 0x00000020, uint32_t)
PVR_REG(0x005f80a4, SDRAM_ARB_CFG, RW, 0x0000001f, uint32_t)
PVR_REG(0x005f80a8, SDRAM_CFG, RW, 0x15f28997, uint32_t)
@ -34,26 +34,26 @@ PVR_REG(0x005f80b8, FOG_DENSITY, RW, 0x00000000, uint32_t)
PVR_REG(0x005f80bc, FOG_CLAMP_MAX, RW, 0x00000000, uint32_t)
PVR_REG(0x005f80c0, FOG_CLAMP_MIN, RW, 0x00000000, uint32_t)
PVR_REG(0x005f80c4, SPG_TRIGGER_POS, RW, 0x00000000, uint32_t)
PVR_REG(0x005f80c8, SPG_HBLANK_INT, RW, 0x031d0000, holly::SPG_HBLANK_INT_T)
PVR_REG(0x005f80cc, SPG_VBLANK_INT, RW, 0x01500104, holly::SPG_VBLANK_INT_T)
PVR_REG(0x005f80d0, SPG_CONTROL, RW, 0x00000000, holly::SPG_CONTROL_T)
PVR_REG(0x005f80c8, SPG_HBLANK_INT, RW, 0x031d0000, hw::holly::SPG_HBLANK_INT_T)
PVR_REG(0x005f80cc, SPG_VBLANK_INT, RW, 0x01500104, hw::holly::SPG_VBLANK_INT_T)
PVR_REG(0x005f80d0, SPG_CONTROL, RW, 0x00000000, hw::holly::SPG_CONTROL_T)
PVR_REG(0x005f80d4, SPG_HBLANK, RW, 0x007e0345, uint32_t)
PVR_REG(0x005f80d8, SPG_LOAD, RW, 0x01060359, holly::SPG_LOAD_T)
PVR_REG(0x005f80dc, SPG_VBLANK, RW, 0x01500104, holly::SPG_VBLANK_T)
PVR_REG(0x005f80d8, SPG_LOAD, RW, 0x01060359, hw::holly::SPG_LOAD_T)
PVR_REG(0x005f80dc, SPG_VBLANK, RW, 0x01500104, hw::holly::SPG_VBLANK_T)
PVR_REG(0x005f80e0, SPG_WIDTH, RW, 0x07f1933f, uint32_t)
PVR_REG(0x005f80e4, TEXT_CONTROL, RW, 0x00000000, holly::TEXT_CONTROL_T)
PVR_REG(0x005f80e4, TEXT_CONTROL, RW, 0x00000000, hw::holly::TEXT_CONTROL_T)
PVR_REG(0x005f80e8, VO_CONTROL, RW, 0x00000108, uint32_t)
PVR_REG(0x005f80ec, VO_STARTX, RW, 0x0000009d, uint32_t)
PVR_REG(0x005f80f0, VO_STARTY, RW, 0x00000015, uint32_t)
PVR_REG(0x005f80f4, SCALER_CTL, RW, 0x00000400, uint32_t)
PVR_REG(0x005f8108, PAL_RAM_CTRL, RW, 0x00000000, holly::PAL_RAM_CTRL_T)
PVR_REG(0x005f810c, SPG_STATUS, R, 0x00000000, holly::SPG_STATUS_T)
PVR_REG(0x005f8108, PAL_RAM_CTRL, RW, 0x00000000, hw::holly::PAL_RAM_CTRL_T)
PVR_REG(0x005f810c, SPG_STATUS, R, 0x00000000, hw::holly::SPG_STATUS_T)
PVR_REG(0x005f8110, FB_BURSTCTRL, RW, 0x00090639, uint32_t)
PVR_REG(0x005f8114, FB_C_SOF, R, 0x00000000, uint32_t)
PVR_REG(0x005f8118, Y_COEFF, RW, 0x00000000, uint32_t)
PVR_REG(0x005f811c, PT_ALPHA_REF, RW, 0x000000ff, uint32_t)
PVR_REG(0x005f8124, TA_OL_BASE, RW, 0x00000000, uint32_t)
PVR_REG(0x005f8128, TA_ISP_BASE, RW, 0x00000000, holly::TA_ISP_BASE_T)
PVR_REG(0x005f8128, TA_ISP_BASE, RW, 0x00000000, hw::holly::TA_ISP_BASE_T)
PVR_REG(0x005f812c, TA_OL_LIMIT, RW, 0x00000000, uint32_t)
PVR_REG(0x005f8130, TA_ISP_LIMIT, RW, 0x00000000, uint32_t)
PVR_REG(0x005f8134, TA_NEXT_OPB, R, 0x00000000, uint32_t)

4
src/holly/tile_accelerator.cc → src/hw/holly/tile_accelerator.cc
View File

@ -1,10 +1,10 @@
#include "core/core.h"
#include "emu/dreamcast.h"
#include "holly/pixel_convert.h"
#include "hw/holly/pixel_convert.h"
using namespace dreavm::core;
using namespace dreavm::emu;
using namespace dreavm::holly;
using namespace dreavm::hw::holly;
using namespace dreavm::renderer;
using namespace dreavm::trace;

11
src/holly/tile_accelerator.h → src/hw/holly/tile_accelerator.h
View File

@ -3,19 +3,21 @@
#include <memory>
#include <unordered_map>
#include "holly/tile_renderer.h"
#include "hw/holly/tile_renderer.h"
#include "renderer/backend.h"
namespace dreavm {
namespace emu {
class Dreamcast;
class Memory;
}
namespace trace {
class TraceWriter;
}
namespace hw {
class Memory;
namespace holly {
class Holly;
@ -521,8 +523,8 @@ class TileAccelerator {
void WriteBackgroundState(TileContext *tactx);
emu::Dreamcast *dc_;
emu::Memory *memory_;
holly::Holly *holly_;
hw::Memory *memory_;
hw::holly::Holly *holly_;
uint8_t *video_ram_;
TileTextureCache texcache_;
@ -533,5 +535,6 @@ class TileAccelerator {
};
}
}
}
#endif

8
src/holly/tile_renderer.cc → src/hw/holly/tile_renderer.cc
View File

@ -1,10 +1,10 @@
#include "core/core.h"
#include "emu/profiler.h"
#include "holly/pixel_convert.h"
#include "holly/tile_accelerator.h"
#include "holly/tile_renderer.h"
#include "hw/holly/pixel_convert.h"
#include "hw/holly/tile_accelerator.h"
#include "hw/holly/tile_renderer.h"
using namespace dreavm::holly;
using namespace dreavm::hw::holly;
using namespace dreavm::renderer;
static int compressed_mipmap_offsets[] = {

2
src/holly/tile_renderer.h → src/hw/holly/tile_renderer.h
View File

@ -6,6 +6,7 @@
#include "renderer/backend.h"
namespace dreavm {
namespace hw {
namespace holly {
union TSP;
@ -91,5 +92,6 @@ class TileRenderer {
};
}
}
}
#endif

7
src/holly/maple.cc → src/hw/maple/maple.cc
View File

@ -1,11 +1,12 @@
#include "core/core.h"
#include "emu/dreamcast.h"
#include "holly/maple_controller.h"
#include "hw/maple/maple_controller.h"
using namespace dreavm::core;
using namespace dreavm::cpu;
using namespace dreavm::emu;
using namespace dreavm::holly;
using namespace dreavm::hw::holly;
using namespace dreavm::hw::maple;
using namespace dreavm::hw::sh4;
using namespace dreavm::system;
Maple::Maple(Dreamcast *dc) : dc_(dc), devices_() {

13
src/holly/maple.h → src/hw/maple/maple.h
View File

@ -6,13 +6,17 @@
namespace dreavm {
namespace emu {
class Dreamcast;
class Memory;
struct Register;
}
namespace hw {
namespace holly {
class Holly;
}
class Memory;
namespace maple {
enum { MAX_PORTS = 4 };
@ -114,13 +118,14 @@ class Maple {
void StartDMA();
emu::Dreamcast *dc_;
emu::Memory *memory_;
holly::Holly *holly_;
hw::Memory *memory_;
hw::holly::Holly *holly_;
emu::Register *holly_regs_;
std::unique_ptr<MapleDevice> devices_[MAX_PORTS];
};
}
}
}
#endif

4
src/holly/maple_controller.cc → src/hw/maple/maple_controller.cc
View File

@ -2,9 +2,9 @@
#include <fstream>
#include <sstream>
#include "core/core.h"
#include "holly/maple_controller.h"
#include "hw/maple/maple_controller.h"
using namespace dreavm::holly;
using namespace dreavm::hw::maple;
using namespace dreavm::system;
using namespace json11;

6
src/holly/maple_controller.h → src/hw/maple/maple_controller.h
View File

@ -1,10 +1,11 @@
#ifndef MAPLE_CONTROLLER_H
#define MAPLE_CONTROLLER_H
#include "holly/maple.h"
#include "hw/maple/maple.h"
namespace dreavm {
namespace holly {
namespace hw {
namespace maple {
enum {
CONT_C = 0x1,
@ -68,5 +69,6 @@ class MapleController : public MapleDevice {
};
}
}
}
#endif

2
src/emu/memory.h → src/hw/memory.h
View File

@ -10,7 +10,7 @@
#include "core/core.h"
namespace dreavm {
namespace emu {
namespace hw {
//
// single level page table implementation

4
src/emu/scheduler.cc → src/hw/scheduler.cc
View File

@ -1,8 +1,8 @@
#include <cmath>
#include <chrono>
#include "emu/scheduler.h"
#include "hw/scheduler.h"
using namespace dreavm::emu;
using namespace dreavm::hw;
Scheduler::Scheduler() : next_timer_handle_(0), base_time_() {}

4
src/emu/scheduler.h → src/hw/scheduler.h
View File

@ -5,10 +5,10 @@
#include <functional>
#include <set>
#include <vector>
#include "emu/device.h"
#include "hw/device.h"
namespace dreavm {
namespace emu {
namespace hw {
typedef std::function<void()> TimerCallback;

74
src/cpu/sh4.cc → src/hw/sh4/sh4.cc
View File

@ -1,79 +1,23 @@
#include "core/core.h"
#include "cpu/runtime.h"
#include "cpu/sh4.h"
#include "emu/memory.h"
#include "emu/profiler.h"
#include "hw/sh4/sh4.h"
#include "hw/memory.h"
#include "jit/runtime.h"
using namespace dreavm::core;
using namespace dreavm::cpu;
using namespace dreavm::emu;
using namespace dreavm::hw::sh4;
using namespace dreavm::jit;
using namespace dreavm::jit::frontend::sh4;
InterruptInfo interrupts[NUM_INTERRUPTS] = {
#define SH4_INT(name, intevt, pri, ipr, ipr_shift) \
{ intevt, pri, ipr, ipr_shift } \
,
#include "cpu/sh4_int.inc"
#include "hw/sh4/sh4_int.inc"
#undef SH4_INT
};
static void SetRegisterBank(SH4Context *ctx, int bank) {
if (bank == 0) {
for (int s = 0; s < 8; s++) {
ctx->rbnk[1][s] = ctx->r[s];
ctx->r[s] = ctx->rbnk[0][s];
}
} else {
for (int s = 0; s < 8; s++) {
ctx->rbnk[0][s] = ctx->r[s];
ctx->r[s] = ctx->rbnk[1][s];
}
}
}
static void SwapFPRegisters(SH4Context *ctx) {
uint32_t z;
for (int s = 0; s <= 15; s++) {
z = ctx->fr[s];
ctx->fr[s] = ctx->xf[s];
ctx->xf[s] = z;
}
}
static void SwapFPCouples(SH4Context *ctx) {
uint32_t z;
for (int s = 0; s <= 15; s = s + 2) {
z = ctx->fr[s];
ctx->fr[s] = ctx->fr[s + 1];
ctx->fr[s + 1] = z;
z = ctx->xf[s];
ctx->xf[s] = ctx->xf[s + 1];
ctx->xf[s + 1] = z;
}
}
void SH4Context::SRUpdated(SH4Context *ctx) {
if (ctx->sr.RB != ctx->old_sr.RB) {
SetRegisterBank(ctx, ctx->sr.RB ? 1 : 0);
}
ctx->old_sr = ctx->sr;
}
void SH4Context::FPSCRUpdated(SH4Context *ctx) {
if (ctx->fpscr.FR != ctx->old_fpscr.FR) {
SwapFPRegisters(ctx);
}
if (ctx->fpscr.PR != ctx->old_fpscr.PR) {
SwapFPCouples(ctx);
}
ctx->old_fpscr = ctx->fpscr;
}
SH4::SH4(Memory &memory, Runtime &runtime)
: memory_(memory),
runtime_(runtime),
@ -93,7 +37,7 @@ void SH4::Init() {
if (default != HELD) { \
*(uint32_t *)&area7_[name##_OFFSET] = default; \
}
#include "cpu/sh4_regs.inc"
#include "hw/sh4/sh4_regs.inc"
#undef SH4_REG
memset(cache_, 0, sizeof(cache_));
@ -480,7 +424,7 @@ void SH4::CheckPendingInterrupts() {
ctx_.sr.RB = 1;
ctx_.pc = ctx_.vbr + 0x600;
SH4Context::SRUpdated(&ctx_);
SRUpdated(&ctx_);
}
bool SH4::TimerEnabled(int n) { //

84
src/cpu/sh4.h → src/hw/sh4/sh4.h
View File

@ -1,18 +1,20 @@
#ifndef SH4_H
#define SH4_H
#include "emu/device.h"
#include "hw/device.h"
#include "jit/frontend/sh4/sh4_context.h"
struct SH4Test;
namespace dreavm {
namespace emu {
class Memory;
namespace jit {
class Runtime;
}
namespace cpu {
namespace hw {
class Memory;
class Runtime;
namespace sh4 {
// translate address to 29-bit physical space, ignoring all modifier bits
enum { ADDR_MASK = 0x1fffffff };
@ -23,40 +25,6 @@ enum {
HELD = 0x1,
};
union SR_T {
uint32_t full;
struct {
uint32_t T : 1;
uint32_t S : 1;
uint32_t reserved : 2;
uint32_t IMASK : 4;
uint32_t Q : 1;
uint32_t M : 1;
uint32_t reserved1 : 5;
uint32_t FD : 1;
uint32_t reserved2 : 12;
uint32_t BL : 1;
uint32_t RB : 1;
uint32_t MD : 1;
uint32_t reserved3 : 1;
};
};
union FPSCR_T {
uint32_t full;
struct {
uint32_t RM : 2;
uint32_t flag : 5;
uint32_t enable : 5;
uint32_t cause : 6;
uint32_t DN : 1;
uint32_t PR : 1;
uint32_t SZ : 1;
uint32_t FR : 1;
uint32_t reserved : 10;
};
};
union CCR_T {
uint32_t full;
struct {
@ -121,7 +89,7 @@ union DMAOR_T {
enum {
#define SH4_REG(addr, name, flags, default, reset, sleep, standby, type) \
name##_OFFSET = ((addr & 0x1fe0000) >> 11) | ((addr & 0xfc) >> 2),
#include "cpu/sh4_regs.inc"
#include "hw/sh4/sh4_regs.inc"
#undef SH4_REG
};
@ -132,7 +100,7 @@ struct InterruptInfo {
enum Interrupt {
#define SH4_INT(name, intevt, pri, ipr, ipr_shift) SH4_INTC_##name,
#include "cpu/sh4_int.inc"
#include "hw/sh4/sh4_int.inc"
#undef SH4_INT
NUM_INTERRUPTS
};
@ -143,31 +111,12 @@ enum DDTRW { //
DDT_W
};
struct SH4Context {
static void SRUpdated(SH4Context *ctx);
static void FPSCRUpdated(SH4Context *ctx);
uint32_t pc, spc;
uint32_t pr;
uint32_t gbr, vbr;
uint32_t mach, macl;
uint32_t r[16], rbnk[2][8], sgr;
uint32_t fr[16], xf[16];
uint32_t fpul;
uint32_t dbr;
uint32_t sq[2][8];
uint32_t sq_ext_addr[2];
uint32_t preserve;
SR_T sr, ssr, old_sr;
FPSCR_T fpscr, old_fpscr;
};
class SH4 : public emu::Device {
class SH4 : public hw::Device {
template <typename BACKEND>
friend void RunSH4Test(const SH4Test &);
public:
SH4(emu::Memory &memory, cpu::Runtime &runtime);
SH4(hw::Memory &memory, jit::Runtime &runtime);
uint32_t GetClockFrequency() { return 200000000; }
@ -220,14 +169,14 @@ class SH4 : public emu::Device {
bool TimerEnabled(int n);
void RunTimer(int n, uint32_t cycles);
emu::Memory &memory_;
Runtime &runtime_;
hw::Memory &memory_;
jit::Runtime &runtime_;
SH4Context ctx_;
SR_T old_sr_;
jit::frontend::sh4::SH4Context ctx_;
jit::frontend::sh4::SR_T old_sr_;
#define SH4_REG(addr, name, flags, default, reset, sleep, standby, type) \
type &name{reinterpret_cast<type &>(area7_[name##_OFFSET])};
#include "cpu/sh4_regs.inc"
#include "hw/sh4/sh4_regs.inc"
#undef SH4_REG
bool pending_cache_reset_;
@ -243,5 +192,6 @@ class SH4 : public emu::Device {
};
}
}
}
#endif

0
src/cpu/sh4_int.inc → src/hw/sh4/sh4_int.inc
View File

0
src/cpu/sh4_regs.inc → src/hw/sh4/sh4_regs.inc
View File

10
src/cpu/backend/backend.h → src/jit/backend/backend.h
View File

@ -2,11 +2,11 @@
#define BACKEND_H
#include <memory>
#include "cpu/ir/ir_builder.h"
#include "emu/memory.h"
#include "hw/memory.h"
#include "jit/ir/ir_builder.h"
namespace dreavm {
namespace cpu {
namespace jit {
class RuntimeBlock;
@ -19,7 +19,7 @@ struct Register {
class Backend {
public:
Backend(emu::Memory &memory) : memory_(memory) {}
Backend(hw::Memory &memory) : memory_(memory) {}
virtual ~Backend() {}
virtual const Register *registers() const = 0;
@ -30,7 +30,7 @@ class Backend {
ir::IRBuilder &builder) = 0;
protected:
emu::Memory &memory_;
hw::Memory &memory_;
};
}
}

16
src/cpu/backend/interpreter/interpreter_backend.cc → src/jit/backend/interpreter/interpreter_backend.cc
View File

@ -1,12 +1,12 @@
#include "cpu/backend/interpreter/interpreter_backend.h"
#include "cpu/backend/interpreter/interpreter_block.h"
#include "cpu/backend/interpreter/interpreter_callbacks.h"
#include "jit/backend/interpreter/interpreter_backend.h"
#include "jit/backend/interpreter/interpreter_block.h"
#include "jit/backend/interpreter/interpreter_callbacks.h"
using namespace dreavm::cpu;
using namespace dreavm::cpu::backend;
using namespace dreavm::cpu::backend::interpreter;
using namespace dreavm::cpu::ir;
using namespace dreavm::emu;
using namespace dreavm::hw;
using namespace dreavm::jit;
using namespace dreavm::jit::backend;
using namespace dreavm::jit::backend::interpreter;
using namespace dreavm::jit::ir;
static IntSig GetSignature(Instr &ir_i) {
IntSig sig = 0;

8
src/cpu/backend/interpreter/interpreter_backend.h → src/jit/backend/interpreter/interpreter_backend.h
View File

@ -1,11 +1,11 @@
#ifndef INTERPRETER_BACKEND_H
#define INTERPRETER_BACKEND_H
#include "cpu/backend/backend.h"
#include "cpu/runtime.h"
#include "jit/backend/backend.h"
#include "jit/runtime.h"
namespace dreavm {
namespace cpu {
namespace jit {
namespace backend {
namespace interpreter {
@ -56,7 +56,7 @@ constexpr Register int_registers[] = {{"a", ir::VALUE_INT_MASK},
class InterpreterBackend : public Backend {
public:
InterpreterBackend(emu::Memory &memory);
InterpreterBackend(hw::Memory &memory);
~InterpreterBackend();
const Register *registers() const;

9
src/cpu/backend/interpreter/interpreter_block.cc → src/jit/backend/interpreter/interpreter_block.cc
View File

@ -1,9 +1,8 @@
#include "cpu/backend/interpreter/interpreter_block.h"
#include "jit/backend/interpreter/interpreter_block.h"
using namespace dreavm::emu;
using namespace dreavm::cpu;
using namespace dreavm::emu;
using namespace dreavm::cpu::backend::interpreter;
using namespace dreavm::hw;
using namespace dreavm::jit;
using namespace dreavm::jit::backend::interpreter;
InterpreterBlock::InterpreterBlock(int guest_cycles, IntInstr *instrs,
int num_instrs, int locals_size)

10
src/cpu/backend/interpreter/interpreter_block.h → src/jit/backend/interpreter/interpreter_block.h
View File

@ -1,12 +1,12 @@
#ifndef INTERPRETER_BLOCK_H
#define INTERPRETER_BLOCK_H
#include "cpu/backend/interpreter/interpreter_callbacks.h"
#include "cpu/runtime.h"
#include "emu/memory.h"
#include "hw/memory.h"
#include "jit/backend/interpreter/interpreter_callbacks.h"
#include "jit/runtime.h"
namespace dreavm {
namespace cpu {
namespace jit {
namespace backend {
namespace interpreter {
@ -29,7 +29,7 @@ class InterpreterBlock : public RuntimeBlock {
InterpreterBlock(int guest_cycles, IntInstr *instrs, int num_instrs,
int locals_size);
uint32_t Call(emu::Memory *memory, void *guest_ctx);
uint32_t Call(hw::Memory *memory, void *guest_ctx);
void Dump();
private:

16
src/cpu/backend/interpreter/interpreter_callbacks.cc → src/jit/backend/interpreter/interpreter_callbacks.cc
View File

@ -1,13 +1,13 @@
#include <unordered_map>
#include "cpu/backend/interpreter/interpreter_backend.h"
#include "cpu/backend/interpreter/interpreter_block.h"
#include "cpu/backend/interpreter/interpreter_callbacks.h"
#include "jit/backend/interpreter/interpreter_backend.h"
#include "jit/backend/interpreter/interpreter_block.h"
#include "jit/backend/interpreter/interpreter_callbacks.h"
using namespace dreavm::core;
using namespace dreavm::cpu;
using namespace dreavm::cpu::backend::interpreter;
using namespace dreavm::cpu::ir;
using namespace dreavm::emu;
using namespace dreavm::hw;
using namespace dreavm::jit;
using namespace dreavm::jit::backend::interpreter;
using namespace dreavm::jit::ir;
// callbacks for each IR operation. callback functions are generated per
// operation, per signature, per access mask.
@ -54,7 +54,7 @@ static std::unordered_map<int, IntFn> int_cbs;
} \
} int_##op##_##r##_##a0##_##a1##_init
IntFn dreavm::cpu::backend::interpreter::GetCallback(
IntFn dreavm::jit::backend::interpreter::GetCallback(
Opcode op, const IntSig &sig, IntAccessMask access_mask) {
auto it = int_cbs.find(CALLBACK_IDX(op, GetArgSignature(sig, 3),
GetArgSignature(sig, 0),

8
src/cpu/backend/interpreter/interpreter_callbacks.h → src/jit/backend/interpreter/interpreter_callbacks.h
View File

@ -1,11 +1,11 @@
#ifndef INTERPRETER_EMIT_H
#define INTERPRETER_EMIT_H
#include "cpu/backend/interpreter/interpreter_backend.h"
#include "cpu/ir/ir_builder.h"
#include "jit/backend/interpreter/interpreter_backend.h"
#include "jit/ir/ir_builder.h"
namespace dreavm {
namespace cpu {
namespace jit {
namespace backend {
namespace interpreter {
@ -13,7 +13,7 @@ union IntValue;
struct IntInstr;
typedef uint32_t (*IntFn)(const IntInstr *instr, uint32_t idx,
emu::Memory *memory, IntValue *registers,
hw::Memory *memory, IntValue *registers,
uint8_t *locals, void *guest_ctx);
IntFn GetCallback(ir::Opcode op, const IntSig &sig, IntAccessMask access_mask);

14
src/cpu/backend/x64/x64_backend.cc → src/jit/backend/x64/x64_backend.cc
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@ -1,13 +1,13 @@
#include "core/core.h"
#include "cpu/backend/x64/x64_backend.h"
#include "cpu/backend/x64/x64_block.h"
#include "jit/backend/x64/x64_backend.h"
#include "jit/backend/x64/x64_block.h"
using namespace dreavm::core;
using namespace dreavm::cpu;
using namespace dreavm::cpu::backend;
using namespace dreavm::cpu::backend::x64;
using namespace dreavm::cpu::ir;
using namespace dreavm::emu;
using namespace dreavm::hw;
using namespace dreavm::jit;
using namespace dreavm::jit::backend;
using namespace dreavm::jit::backend::x64;
using namespace dreavm::jit::ir;
X64Backend::X64Backend(Memory &memory)
: Backend(memory), codegen_(1024 * 1024 * 8), emitter_(memory, codegen_) {}

10
src/cpu/backend/x64/x64_backend.h → src/jit/backend/x64/x64_backend.h
View File

@ -2,12 +2,12 @@
#define X64_BACKEND_H
#include <xbyak/xbyak.h>
#include "cpu/backend/backend.h"
#include "cpu/backend/x64/x64_emitter.h"
#include "cpu/runtime.h"
#include "jit/backend/backend.h"
#include "jit/backend/x64/x64_emitter.h"
#include "jit/runtime.h"
namespace dreavm {
namespace cpu {
namespace jit {
namespace backend {
namespace x64 {
@ -26,7 +26,7 @@ constexpr Register x64_registers[] = {{"rbx", ir::VALUE_INT_MASK},
class X64Backend : public Backend {
public:
X64Backend(emu::Memory &memory);
X64Backend(hw::Memory &memory);
~X64Backend();
const Register *registers() const;

8
src/cpu/backend/x64/x64_block.cc → src/jit/backend/x64/x64_block.cc
View File

@ -1,11 +1,11 @@
#include <iomanip>
#include <sstream>
#include <beaengine/BeaEngine.h>
#include "cpu/backend/x64/x64_block.h"
#include "jit/backend/x64/x64_block.h"
using namespace dreavm::cpu;
using namespace dreavm::emu;
using namespace dreavm::cpu::backend::x64;
using namespace dreavm::hw;
using namespace dreavm::jit;
using namespace dreavm::jit::backend::x64;
X64Block::X64Block(int guest_cycles, X64Fn fn)
: RuntimeBlock(guest_cycles), fn_(fn) {}

10
src/cpu/backend/x64/x64_block.h → src/jit/backend/x64/x64_block.h
View File

@ -1,12 +1,12 @@
#ifndef X64_BLOCK_H
#define X64_BLOCK_H
#include "cpu/backend/x64/x64_emitter.h"
#include "cpu/runtime.h"
#include "emu/memory.h"
#include "hw/memory.h"
#include "jit/backend/x64/x64_emitter.h"
#include "jit/runtime.h"
namespace dreavm {
namespace cpu {
namespace jit {
namespace backend {
namespace x64 {
@ -14,7 +14,7 @@ class X64Block : public RuntimeBlock {
public:
X64Block(int guest_cycles, X64Fn fn);
uint32_t Call(emu::Memory *memory, void *guest_ctx);
uint32_t Call(hw::Memory *memory, void *guest_ctx);
void Dump();
private:

8
src/cpu/backend/x64/x64_emitter.cc → src/jit/backend/x64/x64_emitter.cc
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@ -1,11 +1,11 @@
#include "core/core.h"
#include "cpu/backend/x64/x64_emitter.h"
#include "emu/profiler.h"
#include "jit/backend/x64/x64_emitter.h"
using namespace dreavm::core;
using namespace dreavm::cpu::backend::x64;
using namespace dreavm::cpu::ir;
using namespace dreavm::emu;
using namespace dreavm::hw;
using namespace dreavm::jit::backend::x64;
using namespace dreavm::jit::ir;
//
// x64 register layout

12
src/cpu/backend/x64/x64_emitter.h → src/jit/backend/x64/x64_emitter.h
View File

@ -5,11 +5,11 @@
#include <xbyak/xbyak.h>
#include "core/arena.h"
#include "core/platform.h"
#include "cpu/runtime.h"
#include "emu/memory.h"
#include "hw/memory.h"
#include "jit/runtime.h"
namespace dreavm {
namespace cpu {
namespace jit {
namespace backend {
namespace x64 {
@ -25,11 +25,11 @@ enum {
STACK_SIZE = STACK_OFFSET_LOCALS
};
typedef uint32_t (*X64Fn)(void *guest_ctx, emu::Memory *memory);
typedef uint32_t (*X64Fn)(void *guest_ctx, hw::Memory *memory);
class X64Emitter {
public:
X64Emitter(emu::Memory &memory, Xbyak::CodeGenerator &codegen);
X64Emitter(hw::Memory &memory, Xbyak::CodeGenerator &codegen);
Xbyak::Label &epilog_label() { return *epilog_label_; }
@ -51,7 +51,7 @@ class X64Emitter {
Xbyak::Label *AllocLabel();
Xbyak::Address *AllocAddress(const Xbyak::Address &addr);
emu::Memory &memory_;
hw::Memory &memory_;
Xbyak::CodeGenerator &c_;
core::Arena arena_;
Xbyak::Label *epilog_label_;

10
src/cpu/frontend/frontend.h → src/jit/frontend/frontend.h
View File

@ -2,23 +2,23 @@
#define FRONTEND_H
#include <memory>
#include "cpu/ir/ir_builder.h"
#include "emu/memory.h"
#include "hw/memory.h"
#include "jit/ir/ir_builder.h"
namespace dreavm {
namespace cpu {
namespace jit {
namespace frontend {
class Frontend {
public:
Frontend(emu::Memory &memory) : memory_(memory) {}
Frontend(hw::Memory &memory) : memory_(memory) {}
virtual ~Frontend() {}
virtual std::unique_ptr<ir::IRBuilder> BuildBlock(uint32_t addr,
const void *guest_ctx) = 0;
protected:
emu::Memory &memory_;
hw::Memory &memory_;
};
}
}

22
src/cpu/frontend/sh4/sh4_builder.cc → src/jit/frontend/sh4/sh4_builder.cc
View File

@ -1,14 +1,14 @@
#include "cpu/frontend/sh4/sh4_emit.h"
#include "cpu/frontend/sh4/sh4_frontend.h"
#include "cpu/frontend/sh4/sh4_instr.h"
#include "cpu/runtime.h"
#include "emu/profiler.h"
#include "jit/frontend/sh4/sh4_emit.h"
#include "jit/frontend/sh4/sh4_frontend.h"
#include "jit/frontend/sh4/sh4_instr.h"
#include "jit/runtime.h"
using namespace dreavm::cpu;
using namespace dreavm::cpu::frontend;
using namespace dreavm::cpu::frontend::sh4;
using namespace dreavm::cpu::ir;
using namespace dreavm::emu;
using namespace dreavm::hw;
using namespace dreavm::jit;
using namespace dreavm::jit::frontend;
using namespace dreavm::jit::frontend::sh4;
using namespace dreavm::jit::ir;
SH4Builder::SH4Builder(Memory &memory)
: memory_(memory),
@ -116,7 +116,7 @@ Value *SH4Builder::LoadSR() {
void SH4Builder::StoreSR(Value *v) {
CHECK_EQ(v->type(), VALUE_I32);
StoreAndPreserveContext(offsetof(SH4Context, sr), v, IF_INVALIDATE_CONTEXT);
CallExternal((ExternalFn)&SH4Context::SRUpdated);
CallExternal((ExternalFn)&SRUpdated);
}
ir::Value *SH4Builder::LoadT() { return And(LoadSR(), AllocConstant(T)); }
@ -144,7 +144,7 @@ void SH4Builder::StoreFPSCR(ir::Value *v) {
CHECK_EQ(v->type(), VALUE_I32);
v = And(v, AllocConstant(0x003fffff));
StoreAndPreserveContext(offsetof(SH4Context, fpscr), v);
CallExternal((ExternalFn)&SH4Context::FPSCRUpdated);
CallExternal((ExternalFn)&FPSCRUpdated);
}
ir::Value *SH4Builder::LoadPR() {

16
src/cpu/frontend/sh4/sh4_builder.h → src/jit/frontend/sh4/sh4_builder.h
View File

@ -1,15 +1,13 @@
#ifndef SH4_BUILDER_H
#define SH4_BUILDER_H
#include "cpu/frontend/sh4/sh4_instr.h"
#include "cpu/ir/ir_builder.h"
#include "emu/memory.h"
#include "hw/memory.h"
#include "jit/frontend/sh4/sh4_context.h"
#include "jit/frontend/sh4/sh4_instr.h"
#include "jit/ir/ir_builder.h"
namespace dreavm {
namespace cpu {
struct SH4Context;
namespace jit {
namespace frontend {
namespace sh4 {
@ -43,7 +41,7 @@ struct FPUState {
class SH4Builder : public ir::IRBuilder {
public:
SH4Builder(emu::Memory &memory);
SH4Builder(hw::Memory &memory);
~SH4Builder();
void Emit(uint32_t start_addr, const SH4Context &ctx);
@ -76,7 +74,7 @@ class SH4Builder : public ir::IRBuilder {
void StoreAndPreserveContext(size_t offset, ir::Value *v,
ir::InstrFlag flags = ir::IF_NONE);
emu::Memory &memory_;
hw::Memory &memory_;
FPUState fpu_state_;
Instr delay_instr_;
bool has_delay_instr_;

68
src/jit/frontend/sh4/sh4_context.cc Normal file
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@ -0,0 +1,68 @@
#include "jit/frontend/sh4/sh4_context.h"
namespace dreavm {
namespace jit {
namespace frontend {
namespace sh4 {
static void SetRegisterBank(SH4Context *ctx, int bank) {
if (bank == 0) {
for (int s = 0; s < 8; s++) {
ctx->rbnk[1][s] = ctx->r[s];
ctx->r[s] = ctx->rbnk[0][s];
}
} else {
for (int s = 0; s < 8; s++) {
ctx->rbnk[0][s] = ctx->r[s];
ctx->r[s] = ctx->rbnk[1][s];
}
}
}
static void SwapFPRegisters(SH4Context *ctx) {
uint32_t z;
for (int s = 0; s <= 15; s++) {
z = ctx->fr[s];
ctx->fr[s] = ctx->xf[s];
ctx->xf[s] = z;
}
}
static void SwapFPCouples(SH4Context *ctx) {
uint32_t z;
for (int s = 0; s <= 15; s = s + 2) {
z = ctx->fr[s];
ctx->fr[s] = ctx->fr[s + 1];
ctx->fr[s + 1] = z;
z = ctx->xf[s];
ctx->xf[s] = ctx->xf[s + 1];
ctx->xf[s + 1] = z;
}
}
void SRUpdated(SH4Context *ctx) {
if (ctx->sr.RB != ctx->old_sr.RB) {
SetRegisterBank(ctx, ctx->sr.RB ? 1 : 0);
}
ctx->old_sr = ctx->sr;
}
void FPSCRUpdated(SH4Context *ctx) {
if (ctx->fpscr.FR != ctx->old_fpscr.FR) {
SwapFPRegisters(ctx);
}
if (ctx->fpscr.PR != ctx->old_fpscr.PR) {
SwapFPCouples(ctx);
}
ctx->old_fpscr = ctx->fpscr;
}
}
}
}
}

68
src/jit/frontend/sh4/sh4_context.h Normal file
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@ -0,0 +1,68 @@
#ifndef SH4_CONTEXT_H
#define SH4_CONTEXT_H
#include <stdint.h>
namespace dreavm {
namespace jit {
namespace frontend {
namespace sh4 {
union SR_T {
uint32_t full;
struct {
uint32_t T : 1;
uint32_t S : 1;
uint32_t reserved : 2;
uint32_t IMASK : 4;
uint32_t Q : 1;
uint32_t M : 1;
uint32_t reserved1 : 5;
uint32_t FD : 1;
uint32_t reserved2 : 12;
uint32_t BL : 1;
uint32_t RB : 1;
uint32_t MD : 1;
uint32_t reserved3 : 1;
};
};
union FPSCR_T {
uint32_t full;
struct {
uint32_t RM : 2;
uint32_t flag : 5;
uint32_t enable : 5;
uint32_t cause : 6;
uint32_t DN : 1;
uint32_t PR : 1;
uint32_t SZ : 1;
uint32_t FR : 1;
uint32_t reserved : 10;
};
};
struct SH4Context {
uint32_t pc, spc;
uint32_t pr;
uint32_t gbr, vbr;
uint32_t mach, macl;
uint32_t r[16], rbnk[2][8], sgr;
uint32_t fr[16], xf[16];
uint32_t fpul;
uint32_t dbr;
uint32_t sq[2][8];
uint32_t sq_ext_addr[2];
uint32_t preserve;
SR_T sr, ssr, old_sr;
FPSCR_T fpscr, old_fpscr;
};
void SRUpdated(SH4Context *ctx);
void FPSCRUpdated(SH4Context *ctx);
}
}
}
}
#endif

16
src/cpu/frontend/sh4/sh4_emit.cc → src/jit/frontend/sh4/sh4_emit.cc
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@ -1,17 +1,17 @@
#define _USE_MATH_DEFINES
#include <math.h>
#include "cpu/frontend/sh4/sh4_emit.h"
#include "cpu/frontend/sh4/sh4_frontend.h"
#include "jit/frontend/sh4/sh4_emit.h"
#include "jit/frontend/sh4/sh4_frontend.h"
using namespace dreavm::cpu;
using namespace dreavm::cpu::frontend;
using namespace dreavm::cpu::frontend::sh4;
using namespace dreavm::cpu::ir;
using namespace dreavm::emu;
using namespace dreavm::hw;
using namespace dreavm::jit;
using namespace dreavm::jit::frontend;
using namespace dreavm::jit::frontend::sh4;
using namespace dreavm::jit::ir;
EmitCallback sh4::emit_callbacks[sh4::NUM_OPCODES] = {
#define SH4_INSTR(name, instr_code, cycles, flags) &sh4::Emit_OP_##name,
#include "cpu/frontend/sh4/sh4_instr.inc"
#include "jit/frontend/sh4/sh4_instr.inc"
#undef SH4_INSTR
};

6
src/cpu/frontend/sh4/sh4_emit.h → src/jit/frontend/sh4/sh4_emit.h
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@ -1,10 +1,10 @@
#ifndef SH4_EMIT_H
#define SH4_EMIT_H
#include "cpu/frontend/sh4/sh4_builder.h"
#include "jit/frontend/sh4/sh4_builder.h"
namespace dreavm {
namespace cpu {
namespace jit {
namespace frontend {
namespace sh4 {
@ -12,7 +12,7 @@ typedef void (*EmitCallback)(SH4Builder &b, const FPUState &, const Instr &i);
#define SH4_INSTR(name, instr_code, cycles, flags) \
void Emit_OP_##name(SH4Builder &b, const FPUState &fpu, const Instr &instr);
#include "cpu/frontend/sh4/sh4_instr.inc"
#include "jit/frontend/sh4/sh4_instr.inc"
#undef SH4_INSTR
extern EmitCallback emit_callbacks[NUM_OPCODES];

10
src/cpu/frontend/sh4/sh4_frontend.cc → src/jit/frontend/sh4/sh4_frontend.cc
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@ -1,9 +1,9 @@
#include "cpu/frontend/sh4/sh4_frontend.h"
#include "jit/frontend/sh4/sh4_frontend.h"
using namespace dreavm::cpu;
using namespace dreavm::cpu::frontend::sh4;
using namespace dreavm::cpu::ir;
using namespace dreavm::emu;
using namespace dreavm::hw;
using namespace dreavm::jit;
using namespace dreavm::jit::frontend::sh4;
using namespace dreavm::jit::ir;
SH4Frontend::SH4Frontend(Memory &memory) : Frontend(memory) {}

11
src/cpu/frontend/sh4/sh4_frontend.h → src/jit/frontend/sh4/sh4_frontend.h
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@ -1,19 +1,18 @@
#ifndef SH4_FRONTEND_H
#define SH4_FRONTEND_H
#include "cpu/frontend/frontend.h"
#include "cpu/frontend/sh4/sh4_builder.h"
#include "cpu/frontend/sh4/sh4_instr.h"
#include "cpu/sh4.h"
#include "jit/frontend/frontend.h"
#include "jit/frontend/sh4/sh4_builder.h"
#include "jit/frontend/sh4/sh4_instr.h"
namespace dreavm {
namespace cpu {
namespace jit {
namespace frontend {
namespace sh4 {
class SH4Frontend : public Frontend {
public:
SH4Frontend(emu::Memory &memory);
SH4Frontend(hw::Memory &memory);
std::unique_ptr<ir::IRBuilder> BuildBlock(uint32_t addr,
const void *guest_ctx);

6
src/cpu/frontend/sh4/sh4_instr.cc → src/jit/frontend/sh4/sh4_instr.cc
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@ -1,7 +1,7 @@
#include "cpu/frontend/sh4/sh4_instr.h"
#include "jit/frontend/sh4/sh4_instr.h"
namespace dreavm {
namespace cpu {
namespace jit {
namespace frontend {
namespace sh4 {
@ -9,7 +9,7 @@ InstrType instrs[NUM_OPCODES] = {
#define SH4_INSTR(name, instr_code, cycles, flags) \
{ #name, OP_##name, #instr_code, cycles, flags } \
,
#include "cpu/frontend/sh4/sh4_instr.inc"
#include "jit/frontend/sh4/sh4_instr.inc"
#undef SH4_INSTR
};
InstrType *instr_lookup[UINT16_MAX];

6
src/cpu/frontend/sh4/sh4_instr.h → src/jit/frontend/sh4/sh4_instr.h
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@ -1,16 +1,16 @@
#ifndef SH4_INSTR_H
#define SH4_INSTR_H
#include "cpu/ir/ir_builder.h"
#include "jit/ir/ir_builder.h"
namespace dreavm {
namespace cpu {
namespace jit {
namespace frontend {
namespace sh4 {
enum Opcode {
#define SH4_INSTR(name, instr_code, cycles, flags) OP_##name,
#include "cpu/frontend/sh4/sh4_instr.inc"
#include "jit/frontend/sh4/sh4_instr.inc"
#undef SH4_INSTR
NUM_OPCODES
};

0
src/cpu/frontend/sh4/sh4_instr.inc → src/jit/frontend/sh4/sh4_instr.inc
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10
src/cpu/ir/ir_builder.cc → src/jit/ir/ir_builder.cc
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@ -1,14 +1,14 @@
#include <iomanip>
#include <sstream>
#include <unordered_map>
#include "cpu/ir/ir_builder.h"
#include "jit/ir/ir_builder.h"
using namespace dreavm::cpu;
using namespace dreavm::cpu::ir;
using namespace dreavm::jit;
using namespace dreavm::jit::ir;
const char *dreavm::cpu::ir::Opnames[NUM_OPCODES] = {
const char *dreavm::jit::ir::Opnames[NUM_OPCODES] = {
#define IR_OP(name) #name,
#include "cpu/ir/ir_ops.inc"
#include "jit/ir/ir_ops.inc"
};
//

4
src/cpu/ir/ir_builder.h → src/jit/ir/ir_builder.h
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@ -5,12 +5,12 @@
#include "core/core.h"
namespace dreavm {
namespace cpu {
namespace jit {
namespace ir {
enum Opcode {
#define IR_OP(name) OP_##name,
#include "cpu/ir/ir_ops.inc"
#include "jit/ir/ir_ops.inc"
#undef IR_OP
NUM_OPCODES
};

0
src/cpu/ir/ir_ops.inc → src/jit/ir/ir_ops.inc
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6
src/cpu/ir/passes/constant_propagation_pass.cc → src/jit/ir/passes/constant_propagation_pass.cc
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@ -1,11 +1,11 @@
#include <type_traits>
#include <unordered_map>
#include "core/core.h"
#include "cpu/ir/passes/constant_propagation_pass.h"
#include "emu/profiler.h"
#include "jit/ir/passes/constant_propagation_pass.h"
using namespace dreavm::cpu::ir;
using namespace dreavm::cpu::ir::passes;
using namespace dreavm::jit::ir;
using namespace dreavm::jit::ir::passes;
typedef void (*FoldFn)(IRBuilder &, Block *, Instr *i);

4
src/cpu/ir/passes/constant_propagation_pass.h → src/jit/ir/passes/constant_propagation_pass.h
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@ -1,10 +1,10 @@
#ifndef CONSTANT_PROPAGATION_PASS_H
#define CONSTANT_PROPAGATION_PASS_H
#include "cpu/ir/passes/pass_runner.h"
#include "jit/ir/passes/pass_runner.h"
namespace dreavm {
namespace cpu {
namespace jit {
namespace ir {
namespace passes {

6
src/cpu/ir/passes/context_promotion_pass.cc → src/jit/ir/passes/context_promotion_pass.cc
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@ -1,9 +1,9 @@
#include "core/core.h"
#include "cpu/ir/passes/context_promotion_pass.h"
#include "emu/profiler.h"
#include "jit/ir/passes/context_promotion_pass.h"
using namespace dreavm::cpu::ir;
using namespace dreavm::cpu::ir::passes;
using namespace dreavm::jit::ir;
using namespace dreavm::jit::ir::passes;
void ContextPromotionPass::Run(IRBuilder &builder) {
PROFILER_RUNTIME("ContextPromotionPass::Run");

4
src/cpu/ir/passes/context_promotion_pass.h → src/jit/ir/passes/context_promotion_pass.h
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@ -2,10 +2,10 @@
#define CONTEXT_PROMOTION_PASS_H
#include <vector>
#include "cpu/ir/passes/pass_runner.h"
#include "jit/ir/passes/pass_runner.h"
namespace dreavm {
namespace cpu {
namespace jit {
namespace ir {
namespace passes {

6
src/cpu/ir/passes/control_flow_analysis_pass.cc → src/jit/ir/passes/control_flow_analysis_pass.cc
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@ -1,9 +1,9 @@
#include "core/core.h"
#include "cpu/ir/passes/control_flow_analysis_pass.h"
#include "emu/profiler.h"
#include "jit/ir/passes/control_flow_analysis_pass.h"
using namespace dreavm::cpu::ir;
using namespace dreavm::cpu::ir::passes;
using namespace dreavm::jit::ir;
using namespace dreavm::jit::ir::passes;
void ControlFlowAnalysisPass::Run(IRBuilder &builder) {
PROFILER_RUNTIME("ControlFlowAnalysisPass::Run");

4
src/cpu/ir/passes/control_flow_analysis_pass.h → src/jit/ir/passes/control_flow_analysis_pass.h
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@ -1,10 +1,10 @@
#ifndef CONTROL_FLOW_ANALYSIS_PASS_H
#define CONTROL_FLOW_ANALYSIS_PASS_H
#include "cpu/ir/passes/pass_runner.h"
#include "jit/ir/passes/pass_runner.h"
namespace dreavm {
namespace cpu {
namespace jit {
namespace ir {
namespace passes {

8
src/cpu/ir/passes/pass_runner.cc → src/jit/ir/passes/pass_runner.cc
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@ -1,10 +1,10 @@
#include "core/core.h"
#include "cpu/ir/ir_builder.h"
#include "cpu/ir/passes/pass_runner.h"
#include "emu/profiler.h"
#include "jit/ir/ir_builder.h"
#include "jit/ir/passes/pass_runner.h"
using namespace dreavm::cpu::ir;
using namespace dreavm::cpu::ir::passes;
using namespace dreavm::jit::ir;
using namespace dreavm::jit::ir::passes;
PassRunner::PassRunner() {}

4
src/cpu/ir/passes/pass_runner.h → src/jit/ir/passes/pass_runner.h
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@ -3,10 +3,10 @@
#include <memory>
#include <vector>
#include "cpu/ir/ir_builder.h"
#include "jit/ir/ir_builder.h"
namespace dreavm {
namespace cpu {
namespace jit {
namespace ir {
namespace passes {

8
src/cpu/ir/passes/register_allocation_pass.cc → src/jit/ir/passes/register_allocation_pass.cc
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@ -1,10 +1,10 @@
#include "core/core.h"
#include "cpu/ir/passes/register_allocation_pass.h"
#include "emu/profiler.h"
#include "jit/ir/passes/register_allocation_pass.h"
using namespace dreavm::cpu::backend;
using namespace dreavm::cpu::ir;
using namespace dreavm::cpu::ir::passes;
using namespace dreavm::jit::backend;
using namespace dreavm::jit::ir;
using namespace dreavm::jit::ir::passes;
static inline int GetOrdinal(const Instr *i) { return (int)i->tag(); }

6
src/cpu/ir/passes/register_allocation_pass.h → src/jit/ir/passes/register_allocation_pass.h
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@ -2,11 +2,11 @@
#define REGISTER_ALLOCATION_PASS_H
#include "core/ring_buffer.h"
#include "cpu/backend/backend.h"
#include "cpu/ir/passes/pass_runner.h"
#include "jit/backend/backend.h"
#include "jit/ir/passes/pass_runner.h"
namespace dreavm {
namespace cpu {
namespace jit {
namespace ir {
namespace passes {

6
src/cpu/ir/passes/validate_pass.cc → src/jit/ir/passes/validate_pass.cc
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@ -1,9 +1,9 @@
#include "core/core.h"
#include "cpu/ir/passes/validate_pass.h"
#include "emu/profiler.h"
#include "jit/ir/passes/validate_pass.h"
using namespace dreavm::cpu::ir;
using namespace dreavm::cpu::ir::passes;
using namespace dreavm::jit::ir;
using namespace dreavm::jit::ir::passes;
void ValidatePass::Run(IRBuilder &builder) {
PROFILER_RUNTIME("ValidatePass::Run");

4
src/cpu/ir/passes/validate_pass.h → src/jit/ir/passes/validate_pass.h
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@ -1,10 +1,10 @@
#ifndef VALIDATE_BLOCK_PASS_H
#define VALIDATE_BLOCK_PASS_H
#include "cpu/ir/passes/pass_runner.h"
#include "jit/ir/passes/pass_runner.h"
namespace dreavm {
namespace cpu {
namespace jit {
namespace ir {
namespace passes {

28
src/cpu/runtime.cc → src/jit/runtime.cc
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@ -1,19 +1,19 @@
#include "cpu/backend/backend.h"
#include "cpu/frontend/frontend.h"
#include "cpu/ir/ir_builder.h"
#include "cpu/ir/passes/constant_propagation_pass.h"
#include "cpu/ir/passes/context_promotion_pass.h"
#include "cpu/ir/passes/control_flow_analysis_pass.h"
#include "cpu/ir/passes/register_allocation_pass.h"
#include "cpu/ir/passes/validate_pass.h"
#include "cpu/runtime.h"
#include "emu/profiler.h"
#include "jit/backend/backend.h"
#include "jit/frontend/frontend.h"
#include "jit/ir/ir_builder.h"
#include "jit/ir/passes/constant_propagation_pass.h"
#include "jit/ir/passes/context_promotion_pass.h"
#include "jit/ir/passes/control_flow_analysis_pass.h"
#include "jit/ir/passes/register_allocation_pass.h"
#include "jit/ir/passes/validate_pass.h"
#include "jit/runtime.h"
using namespace dreavm::cpu;
using namespace dreavm::cpu::backend;
using namespace dreavm::cpu::ir;
using namespace dreavm::cpu::ir::passes;
using namespace dreavm::emu;
using namespace dreavm::hw;
using namespace dreavm::jit;
using namespace dreavm::jit::backend;
using namespace dreavm::jit::ir;
using namespace dreavm::jit::ir::passes;
// executable code sits between 0x0c000000 and 0x0d000000 (16mb). each instr
// is 2 bytes, making for a maximum of 0x1000000 >> 1 blocks

14
src/cpu/runtime.h → src/jit/runtime.h
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@ -1,11 +1,11 @@
#ifndef RUNTIME_H
#define RUNTIME_H
#include "cpu/ir/passes/pass_runner.h"
#include "emu/memory.h"
#include "hw/memory.h"
#include "jit/ir/passes/pass_runner.h"
namespace dreavm {
namespace cpu {
namespace jit {
namespace backend {
class Backend;
@ -21,7 +21,7 @@ class RuntimeBlock {
virtual ~RuntimeBlock() {}
int guest_cycles() { return guest_cycles_; }
virtual uint32_t Call(emu::Memory *memory, void *guest_ctx) = 0;
virtual uint32_t Call(hw::Memory *memory, void *guest_ctx) = 0;
virtual void Dump() = 0;
private:
@ -30,11 +30,11 @@ class RuntimeBlock {
class Runtime {
public:
Runtime(emu::Memory &memory, frontend::Frontend &frontend,
Runtime(hw::Memory &memory, frontend::Frontend &frontend,
backend::Backend &backend);
~Runtime();
emu::Memory &memory() { return memory_; }
hw::Memory &memory() { return memory_; }
RuntimeBlock *GetBlock(uint32_t addr, const void *guest_ctx);
void ResetBlocks();
@ -42,7 +42,7 @@ class Runtime {
private:
RuntimeBlock *CompileBlock(uint32_t addr, const void *guest_ctx);
emu::Memory &memory_;
hw::Memory &memory_;
frontend::Frontend &frontend_;
backend::Backend &backend_;
ir::passes::PassRunner pass_runner_;

2
src/trace/trace.cc
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@ -3,7 +3,7 @@
#include "trace/trace.h"
using namespace dreavm::core;
using namespace dreavm::holly;
using namespace dreavm::hw::holly;
using namespace dreavm::trace;
void dreavm::trace::GetNextTraceFilename(char *filename, size_t size) {

16
src/trace/trace.h
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@ -1,7 +1,7 @@
#ifndef TRACE_H
#define TRACE_H
#include "holly/tile_accelerator.h"
#include "hw/holly/tile_accelerator.h"
namespace dreavm {
namespace trace {
@ -22,8 +22,8 @@ struct TraceCommand {
// and patched to absolute pointers on read
union {
struct {
holly::TSP tsp;
holly::TCW tcw;
hw::holly::TSP tsp;
hw::holly::TCW tcw;
uint32_t palette_size;
const uint8_t *palette;
uint32_t texture_size;
@ -38,9 +38,9 @@ struct TraceCommand {
uint32_t pal_pxl_format;
uint32_t video_width;
uint32_t video_height;
holly::ISP_TSP bg_isp;
holly::TSP bg_tsp;
holly::TCW bg_tcw;
hw::holly::ISP_TSP bg_isp;
hw::holly::TSP bg_tsp;
hw::holly::TCW bg_tcw;
float bg_depth;
uint32_t bg_vertices_size;
const uint8_t *bg_vertices;
@ -78,10 +78,10 @@ class TraceWriter {
bool Open(const char *filename);
void Close();
void WriteInsertTexture(const holly::TSP &tsp, const holly::TCW &tcw,
void WriteInsertTexture(const hw::holly::TSP &tsp, const hw::holly::TCW &tcw,
const uint8_t *palette, int palette_size,
const uint8_t *texture, int texture_size);
void WriteRenderContext(holly::TileContext *tactx);
void WriteRenderContext(hw::holly::TileContext *tactx);
private:
FILE *file_;

4
src/trace/trace_viewer.cc
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@ -1,12 +1,12 @@
#include <algorithm>
#include "core/core.h"
#include "holly/tile_accelerator.h"
#include "hw/holly/tile_accelerator.h"
#include "renderer/gl_backend.h"
#include "trace/trace.h"
#include "trace/trace_viewer.h"
using namespace dreavm::core;
using namespace dreavm::holly;
using namespace dreavm::hw::holly;
using namespace dreavm::renderer;
using namespace dreavm::system;
using namespace dreavm::trace;

25
src/trace/trace_viewer.h
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@ -3,7 +3,7 @@
#include <unordered_map>
#include <vector>
#include "holly/tile_renderer.h"
#include "hw/holly/tile_renderer.h"
#include "system/system.h"
#include "trace/trace.h"
@ -11,25 +11,25 @@ namespace dreavm {
namespace trace {
struct TextureInst {
holly::TSP tsp;
holly::TCW tcw;
hw::holly::TSP tsp;
hw::holly::TCW tcw;
const uint8_t *palette;
const uint8_t *texture;
renderer::TextureHandle handle;
};
class TraceTextureCache : public holly::TextureCache {
class TraceTextureCache : public hw::holly::TextureCache {
public:
void AddTexture(const holly::TSP &tsp, holly::TCW &tcw,
void AddTexture(const hw::holly::TSP &tsp, hw::holly::TCW &tcw,
const uint8_t *palette, const uint8_t *texture);
void RemoveTexture(const holly::TSP &tsp, holly::TCW &tcw);
void RemoveTexture(const hw::holly::TSP &tsp, hw::holly::TCW &tcw);
renderer::TextureHandle GetTexture(
const holly::TSP &tsp, const holly::TCW &tcw,
holly::RegisterTextureCallback register_cb);
const hw::holly::TSP &tsp, const hw::holly::TCW &tcw,
hw::holly::RegisterTextureCallback register_cb);
private:
std::unordered_map<holly::TextureKey, TextureInst> textures_;
std::unordered_map<hw::holly::TextureKey, TextureInst> textures_;
};
class TraceViewer {
@ -47,20 +47,21 @@ class TraceViewer {
void RenderFrame();
int GetNumFrames();
void CopyCommandToContext(const TraceCommand *cmd, holly::TileContext *ctx);
void CopyCommandToContext(const TraceCommand *cmd,
hw::holly::TileContext *ctx);
void PrevContext();
void NextContext();
system::System sys_;
TraceTextureCache texcache_;
holly::TileRenderer tile_renderer_;
hw::holly::TileRenderer tile_renderer_;
renderer::Backend *rb_;
TraceReader reader_;
TraceCommand *current_cmd_;
int num_frames_;
int current_frame_;
holly::TileContext current_ctx_;
hw::holly::TileContext current_ctx_;
};
}
}

4
test/sh4_test.cc
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@ -1,8 +1,8 @@
#include "sh4_test.h"
#include "cpu/sh4.h"
#include "jit/frontend/sh4/sh4_context.h"
using namespace dreavm;
using namespace dreavm::cpu;
using namespace dreavm::jit::frontend::sh4;
SH4CTXReg sh4ctx_reg[] = {
#define SH4CTX(name, member, type) \

25
test/test_sh4.cc
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@ -2,23 +2,25 @@
#include <unordered_map>
#include "gtest/gtest.h"
#include "core/core.h"
#include "cpu/frontend/sh4/sh4_frontend.h"
#include "cpu/backend/interpreter/interpreter_backend.h"
#include "cpu/backend/x64/x64_backend.h"
#include "cpu/sh4.h"
#include "emu/memory.h"
#include "hw/sh4/sh4.h"
#include "hw/memory.h"
#include "jit/frontend/sh4/sh4_frontend.h"
#include "jit/backend/interpreter/interpreter_backend.h"
#include "jit/backend/x64/x64_backend.h"
#include "sh4_test.h"
using namespace dreavm;
using namespace dreavm::cpu;
using namespace dreavm::cpu::backend::interpreter;
using namespace dreavm::cpu::backend::x64;
using namespace dreavm::cpu::frontend::sh4;
using namespace dreavm::core;
using namespace dreavm::emu;
using namespace dreavm::hw;
using namespace dreavm::hw::sh4;
using namespace dreavm::jit;
using namespace dreavm::jit::backend::interpreter;
using namespace dreavm::jit::backend::x64;
using namespace dreavm::jit::frontend::sh4;
namespace dreavm {
namespace cpu {
namespace hw {
namespace sh4 {
template <typename BACKEND>
void RunSH4Test(const SH4Test &test) {
@ -73,6 +75,7 @@ void RunSH4Test(const SH4Test &test) {
}
}
}
}
#define SH4_TEST(name, ...) \
TEST(sh4_interpreter, name) { \