mirror of https://github.com/inolen/redream.git
added sh4 interpreter
added OP_FLUSH_CONTEXT fixed bug in ldcsr now that the GPRs are properly flushed when a bank change occurs
This commit is contained in:
Anthony Pesch
parent
94df004840
commit
c703da40f7
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@ -187,6 +187,7 @@ set(REDREAM_SOURCES
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src/jit/frontend/armv3/armv3_fallback.c
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src/jit/frontend/armv3/armv3_frontend.c
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src/jit/frontend/sh4/sh4_disasm.c
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src/jit/frontend/sh4/sh4_fallbacks.c
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src/jit/frontend/sh4/sh4_frontend.c
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src/jit/frontend/sh4/sh4_translate.c
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src/jit/ir/ir.c
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@ -12,6 +12,7 @@
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#include "hw/rom/flash.h"
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#include "hw/scheduler.h"
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#include "jit/backend/x64/x64_backend.h"
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#include "jit/frontend/sh4/sh4_fallbacks.h"
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#include "jit/frontend/sh4/sh4_frontend.h"
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#include "jit/frontend/sh4/sh4_guest.h"
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#include "jit/ir/ir.h"
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@ -138,11 +139,33 @@ static void sh4_run(struct device *dev, int64_t ns) {
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PROF_ENTER("cpu", "sh4_run");
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struct sh4 *sh4 = (struct sh4 *)dev;
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struct sh4_ctx *ctx = &sh4->ctx;
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struct jit *jit = sh4->jit;
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int64_t cycles = NANO_TO_CYCLES(ns, SH4_CLOCK_FREQ);
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cycles = MAX(cycles, INT64_C(1));
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jit_run(sh4->jit, cycles);
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int cache_enabled = sh4->CCR->ICE;
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if (cache_enabled) {
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jit_run(sh4->jit, cycles);
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} else {
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ctx->run_cycles = cycles;
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ctx->ran_instrs = 0;
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while (ctx->run_cycles-- > 0) {
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sh4_intc_check_pending(sh4);
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uint16_t data = as_read16(sh4->memory_if->space, ctx->pc);
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union sh4_instr instr = {data};
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sh4_fallback_cb cb = sh4_get_fallback(data);
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cb(sh4->guest, ctx->pc, instr);
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ctx->ran_instrs++;
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}
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}
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prof_counter_add(COUNTER_sh4_instrs, sh4->ctx.ran_instrs);
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PROF_LEAVE();
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@ -25,13 +25,10 @@ static void sh4_ccn_reset(struct sh4 *sh4) {
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void sh4_ccn_sq_prefetch(void *data, uint32_t addr) {
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PROF_ENTER("cpu", "sh4_ccn_sq_prefetch");
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struct sh4 *sh4 = data;
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/* make sure this is a sq related prefetch */
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// DCHECK(addr >= 0xe0000000 && addr <= 0xe3ffffff);
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if (!(addr >= 0xe0000000 && addr <= 0xe3ffffff))
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return;
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DCHECK(addr >= 0xe0000000 && addr <= 0xe3ffffff);
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struct sh4 *sh4 = data;
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uint32_t dst = addr & 0x03ffffe0;
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uint32_t sqi = (addr & 0x20) >> 5;
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if (sqi) {
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@ -82,6 +79,8 @@ REG_W32(sh4_cb, MMUCR) {
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REG_W32(sh4_cb, CCR) {
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struct sh4 *sh4 = dc->sh4;
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/* TODO check for cache toggle
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union ccr CCR_OLD = *sh4->CCR;*/
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sh4->CCR->full = value;
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if (sh4->CCR->ICI) {
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@ -1642,6 +1642,8 @@ EMITTER(CALL_COND) {
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e.outLocalLabel();
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}
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EMITTER(FLUSH_CONTEXT) {}
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EMITTER(DEBUG_INFO) {}
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EMITTER(DEBUG_BREAK) {
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@ -1,38 +1,18 @@
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#include "jit/frontend/sh4/sh4_disasm.h"
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#include "core/assert.h"
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#include "core/constructor.h"
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#include "core/string.h"
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static struct sh4_opdef *sh4_opdef_lookup[UINT16_MAX + 1];
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int sh4_optable[UINT16_MAX + 1];
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struct sh4_opdef sh4_opdefs[NUM_SH4_OPS] = {
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#define SH4_INSTR(name, desc, sig, cycles, flags) \
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{SH4_OP_##name, #name, desc, #sig, cycles, flags, 0, 0, 0, 0, 0, 0, 0, 0, 0},
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{SH4_OP_##name, #name, desc, #sig, cycles, flags},
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#include "jit/frontend/sh4/sh4_instr.inc"
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#undef SH4_INSTR
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};
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static void sh4_arg_mask(const char *instr_code, char c, uint16_t *mask,
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uint16_t *shift) {
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size_t len = strlen(instr_code);
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if (mask) {
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*mask = 0;
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}
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if (shift) {
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*shift = 0;
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}
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for (size_t i = 0; i < len; i++) {
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if ((!c && instr_code[i] == '1') || (c && instr_code[i] == c)) {
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if (mask) {
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*mask |= (1 << (len - i - 1));
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}
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if (shift) {
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*shift = (uint16_t)(len - i - 1);
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}
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}
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}
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}
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static void sh4_init_opdefs() {
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static void sh4_init_op_table() {
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static int initialized = 0;
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if (initialized) {
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@ -41,61 +21,41 @@ static void sh4_init_opdefs() {
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initialized = 1;
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/*
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* finalize type information by extracting argument encoding information
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* from signatures
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*/
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for (int i = 1 /* skip SH4_OP_INVALID */; i < NUM_SH4_OPS; i++) {
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struct sh4_opdef *def = &sh4_opdefs[i];
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uint16_t opcodes[NUM_SH4_OPS] = {0};
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uint16_t opcode_masks[NUM_SH4_OPS] = {0};
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sh4_arg_mask(def->sig, 'i', &def->imm_mask, &def->imm_shift);
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sh4_arg_mask(def->sig, 'd', &def->disp_mask, &def->disp_shift);
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sh4_arg_mask(def->sig, 'm', &def->rm_mask, &def->rm_shift);
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sh4_arg_mask(def->sig, 'n', &def->rn_mask, &def->rn_shift);
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sh4_arg_mask(def->sig, 0, &def->opcode_mask, NULL);
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for (int i = 1; i < NUM_SH4_OPS; i++) {
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struct sh4_opdef *def = &sh4_opdefs[i];
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size_t len = strlen(def->sig);
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/* 0 or 1 represents part of the opcode, anything else is a flag */
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for (size_t j = 0; j < len; j++) {
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char c = def->sig[len - j - 1];
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if (c == '0' || c == '1') {
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opcodes[i] |= (uint32_t)(c - '0') << j;
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opcode_masks[i] |= (uint32_t)1 << j;
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}
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}
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}
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/* initialize lookup table */
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for (int value = 0; value <= UINT16_MAX; value++) {
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for (int i = 1 /* skip SH4_OP_INVALID */; i < NUM_SH4_OPS; i++) {
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struct sh4_opdef *def = &sh4_opdefs[i];
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uint16_t arg_mask =
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def->imm_mask | def->disp_mask | def->rm_mask | def->rn_mask;
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if ((value & ~arg_mask) == def->opcode_mask) {
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sh4_opdef_lookup[value] = def;
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if ((value & opcode_masks[i]) == opcodes[i]) {
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sh4_optable[value] = i;
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break;
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}
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}
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}
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}
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int sh4_disasm(struct sh4_instr *i) {
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sh4_init_opdefs();
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struct sh4_opdef *def = sh4_opdef_lookup[i->opcode];
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void sh4_format(uint32_t addr, union sh4_instr i, char *buffer,
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size_t buffer_size) {
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struct sh4_opdef *def = sh4_opdef(i.raw);
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if (!def) {
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i->op = SH4_OP_INVALID;
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return 0;
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}
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i->op = def->op;
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i->cycles = def->cycles;
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i->flags = def->flags;
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i->Rm = (i->opcode & def->rm_mask) >> def->rm_shift;
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i->Rn = (i->opcode & def->rn_mask) >> def->rn_shift;
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i->disp = (i->opcode & def->disp_mask) >> def->disp_shift;
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i->imm = (i->opcode & def->imm_mask) >> def->imm_shift;
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return 1;
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}
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void sh4_format(const struct sh4_instr *i, char *buffer, size_t buffer_size) {
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sh4_init_opdefs();
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if (i->op == SH4_OP_INVALID) {
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snprintf(buffer, buffer_size, "%08x .word 0x%04x", i->addr, i->opcode);
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snprintf(buffer, buffer_size, "%08x .word 0x%04x", addr, i.raw);
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return;
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}
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@ -105,7 +65,7 @@ void sh4_format(const struct sh4_instr *i, char *buffer, size_t buffer_size) {
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uint32_t pcmask;
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/* copy initial formatted description */
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snprintf(buffer, buffer_size, "%08x %s", i->addr, sh4_opdefs[i->op].desc);
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snprintf(buffer, buffer_size, "%08x %s", addr, def->desc);
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/* used by mov operators with displacements */
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if (strnstr(buffer, ".b", buffer_size)) {
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@ -123,70 +83,75 @@ void sh4_format(const struct sh4_instr *i, char *buffer, size_t buffer_size) {
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}
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/* (disp:4,rn) */
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value_len = snprintf(value, sizeof(value), "(0x%x,rn)", i->disp * movsize);
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value_len = snprintf(value, sizeof(value), "(0x%x,rn)", i.def.disp * movsize);
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CHECK_EQ(strnrep(buffer, buffer_size, "(disp:4,rn)", 11, value, value_len),
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0);
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/* (disp:4,rm) */
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value_len = snprintf(value, sizeof(value), "(0x%x,rm)", i->disp * movsize);
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value_len = snprintf(value, sizeof(value), "(0x%x,rm)", i.def.disp * movsize);
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CHECK_EQ(strnrep(buffer, buffer_size, "(disp:4,rm)", 11, value, value_len),
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0);
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/* (disp:8,gbr) */
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value_len = snprintf(value, sizeof(value), "(0x%x,gbr)", i->disp * movsize);
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value_len =
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snprintf(value, sizeof(value), "(0x%x,gbr)", i.disp_8.disp * movsize);
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CHECK_EQ(strnrep(buffer, buffer_size, "(disp:8,gbr)", 12, value, value_len),
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0);
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/* (disp:8,pc) */
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value_len = snprintf(value, sizeof(value), "(0x%08x)",
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(i->disp * movsize) + (i->addr & pcmask) + 4);
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(i.disp_8.disp * movsize) + (addr & pcmask) + 4);
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CHECK_EQ(strnrep(buffer, buffer_size, "(disp:8,pc)", 11, value, value_len),
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0);
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/* disp:8 */
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value_len = snprintf(value, sizeof(value), "0x%08x",
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((int8_t)i->disp * 2) + i->addr + 4);
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((int8_t)i.disp_8.disp * 2) + addr + 4);
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CHECK_EQ(strnrep(buffer, buffer_size, "disp:8", 6, value, value_len), 0);
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/* disp:12 */
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value_len =
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snprintf(value, sizeof(value), "0x%08x",
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((((int32_t)(i->disp & 0xfff) << 20) >> 20) * 2) + i->addr + 4);
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value_len = snprintf(
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value, sizeof(value), "0x%08x",
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((((int32_t)(i.disp_12.disp & 0xfff) << 20) >> 20) * 2) + addr + 4);
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CHECK_EQ(strnrep(buffer, buffer_size, "disp:12", 7, value, value_len), 0);
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/* drm */
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value_len = snprintf(value, sizeof(value), "dr%d", i->Rm);
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value_len = snprintf(value, sizeof(value), "dr%d", i.def.rm);
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CHECK_EQ(strnrep(buffer, buffer_size, "drm", 3, value, value_len), 0);
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/* drn */
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value_len = snprintf(value, sizeof(value), "dr%d", i->Rn);
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value_len = snprintf(value, sizeof(value), "dr%d", i.def.rn);
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CHECK_EQ(strnrep(buffer, buffer_size, "drn", 3, value, value_len), 0);
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/* frm */
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value_len = snprintf(value, sizeof(value), "fr%d", i->Rm);
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value_len = snprintf(value, sizeof(value), "fr%d", i.def.rm);
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CHECK_EQ(strnrep(buffer, buffer_size, "frm", 3, value, value_len), 0);
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/* frn */
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value_len = snprintf(value, sizeof(value), "fr%d", i->Rn);
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value_len = snprintf(value, sizeof(value), "fr%d", i.def.rn);
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CHECK_EQ(strnrep(buffer, buffer_size, "frn", 3, value, value_len), 0);
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/* fvm */
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value_len = snprintf(value, sizeof(value), "fv%d", i->Rm);
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value_len = snprintf(value, sizeof(value), "fv%d", (i.def.rm & 0x3) << 2);
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CHECK_EQ(strnrep(buffer, buffer_size, "fvm", 3, value, value_len), 0);
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/* fvn */
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value_len = snprintf(value, sizeof(value), "fv%d", i->Rn);
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value_len = snprintf(value, sizeof(value), "fv%d", (i.def.rm & 0xc));
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CHECK_EQ(strnrep(buffer, buffer_size, "fvn", 3, value, value_len), 0);
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/* rm */
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value_len = snprintf(value, sizeof(value), "r%d", i->Rm);
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value_len = snprintf(value, sizeof(value), "r%d", i.def.rm);
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CHECK_EQ(strnrep(buffer, buffer_size, "rm", 2, value, value_len), 0);
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/* rn */
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value_len = snprintf(value, sizeof(value), "r%d", i->Rn);
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value_len = snprintf(value, sizeof(value), "r%d", i.def.rn);
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CHECK_EQ(strnrep(buffer, buffer_size, "rn", 2, value, value_len), 0);
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/* #imm8 */
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value_len = snprintf(value, sizeof(value), "0x%02x", i->imm);
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value_len = snprintf(value, sizeof(value), "0x%02x", i.imm.imm);
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CHECK_EQ(strnrep(buffer, buffer_size, "#imm8", 5, value, value_len), 0);
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}
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CONSTRUCTOR(sh4_disasm_init) {
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sh4_init_op_table();
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}
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@ -28,29 +28,53 @@ struct sh4_opdef {
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const char *sig;
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int cycles;
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int flags;
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uint16_t opcode_mask;
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uint16_t imm_mask, imm_shift;
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uint16_t disp_mask, disp_shift;
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uint16_t rm_mask, rm_shift;
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uint16_t rn_mask, rn_shift;
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};
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struct sh4_instr {
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uint32_t addr;
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uint16_t opcode;
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union sh4_instr {
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uint16_t raw;
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enum sh4_op op;
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int cycles;
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int flags;
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uint16_t Rm;
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uint16_t Rn;
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uint16_t disp;
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uint16_t imm;
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struct {
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uint32_t disp : 4;
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uint32_t rm : 4;
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uint32_t rn : 4;
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uint32_t : 4;
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} def;
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struct {
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uint32_t imm : 8;
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uint32_t rn : 4;
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uint32_t : 4;
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} imm;
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struct {
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uint32_t disp : 8;
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uint32_t rn : 4;
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uint32_t : 4;
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} disp_pc;
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struct {
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uint32_t disp : 8;
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uint32_t : 8;
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} disp_8;
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struct {
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uint32_t disp : 12;
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uint32_t : 4;
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} disp_12;
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};
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extern int sh4_optable[UINT16_MAX + 1];
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extern struct sh4_opdef sh4_opdefs[NUM_SH4_OPS];
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int sh4_disasm(struct sh4_instr *i);
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void sh4_format(const struct sh4_instr *i, char *buffer, size_t buffer_size);
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static inline int sh4_op(uint16_t instr) {
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return sh4_optable[instr];
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}
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static struct sh4_opdef *sh4_opdef(uint16_t instr) {
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return &sh4_opdefs[sh4_op(instr)];
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}
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void sh4_format(uint32_t addr, union sh4_instr i, char *buffer,
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size_t buffer_size);
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#endif
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@ -0,0 +1,395 @@
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#include <math.h>
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#include "jit/frontend/sh4/sh4_fallbacks.h"
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#include "core/assert.h"
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#include "core/log.h"
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#include "jit/frontend/sh4/sh4_context.h"
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#include "jit/frontend/sh4/sh4_frontend.h"
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#include "jit/frontend/sh4/sh4_guest.h"
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#include "jit/jit.h"
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static uint32_t load_sr(struct sh4_ctx *ctx) {
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sh4_implode_sr(ctx);
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return ctx->sr;
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}
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static void store_sr(struct sh4_guest *guest, struct sh4_ctx *ctx,
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uint32_t new_sr) {
|
||||
uint32_t old_sr = load_sr(ctx);
|
||||
ctx->sr = new_sr;
|
||||
sh4_explode_sr(ctx);
|
||||
guest->sr_updated(guest->data, old_sr);
|
||||
}
|
||||
|
||||
static uint32_t load_fpscr(struct sh4_ctx *ctx) {
|
||||
return ctx->fpscr & 0x003fffff;
|
||||
}
|
||||
|
||||
static void store_fpscr(struct sh4_guest *guest, struct sh4_ctx *ctx,
|
||||
uint32_t new_fpscr) {
|
||||
uint32_t old_fpscr = load_fpscr(ctx);
|
||||
ctx->fpscr = new_fpscr & 0x003fffff;
|
||||
guest->fpscr_updated(guest->data, old_fpscr);
|
||||
}
|
||||
|
||||
static inline int32_t vadd_f32_el(int32_t a, int32_t b) {
|
||||
float r = *(float *)&a + *(float *)&b;
|
||||
return *(int32_t *)&r;
|
||||
}
|
||||
|
||||
static inline int32_t vmul_f32_el(int32_t a, int32_t b) {
|
||||
float r = *(float *)&a * *(float *)&b;
|
||||
return *(int32_t *)&r;
|
||||
}
|
||||
|
||||
static inline float vdot_f32(int32_t *a, int32_t *b) {
|
||||
return *(float *)&a[0] * *(float *)&b[0] + *(float *)&a[1] * *(float *)&b[1] +
|
||||
*(float *)&a[2] * *(float *)&b[2] + *(float *)&a[3] * *(float *)&b[3];
|
||||
}
|
||||
|
||||
/* clang-format off */
|
||||
typedef int32_t int128_t[4];
|
||||
|
||||
#define I8 int8_t
|
||||
#define I16 int16_t
|
||||
#define I32 int32_t
|
||||
#define I64 int64_t
|
||||
#define F32 float
|
||||
#define F64 double
|
||||
#define V128 int128_t
|
||||
|
||||
#define CTX ((struct sh4_ctx *)guest->ctx)
|
||||
#define FPU_DOUBLE_PR (CTX->fpscr & PR_MASK)
|
||||
#define FPU_DOUBLE_SZ (CTX->fpscr & SZ_MASK)
|
||||
|
||||
#define DELAY_INSTR() { \
|
||||
uint32_t delay_addr = addr + 2; \
|
||||
uint16_t delay_data = guest->r16(guest->space, delay_addr); \
|
||||
union sh4_instr delay_instr = {delay_data}; \
|
||||
sh4_fallback_cb cb = sh4_get_fallback(delay_data); \
|
||||
CHECK_NOTNULL(cb); \
|
||||
cb(guest, delay_addr, delay_instr); \
|
||||
}
|
||||
#define NEXT_INSTR() (CTX->pc = addr + 2)
|
||||
#define NEXT_NEXT_INSTR() (CTX->pc = addr + 4)
|
||||
|
||||
#define LOAD_GPR_I8(n) ((int8_t)CTX->r[n])
|
||||
#define LOAD_GPR_I16(n) ((int16_t)CTX->r[n])
|
||||
#define LOAD_GPR_I32(n) ((int32_t)CTX->r[n])
|
||||
#define STORE_GPR_I32(n, v) (CTX->r[n] = (v))
|
||||
#define STORE_GPR_IMM_I32(n, v) STORE_GPR_I32(n, v)
|
||||
|
||||
#define LOAD_GPR_ALT_I32(n) ((int32_t)CTX->ralt[n])
|
||||
#define STORE_GPR_ALT_I32(n, v) (CTX->ralt[n] = (v))
|
||||
|
||||
#define LOAD_FPR_I32(n) ((int32_t)CTX->fr[(n)^1])
|
||||
#define LOAD_FPR_I64(n) (*(int64_t *)&CTX->fr[n])
|
||||
#define LOAD_FPR_F32(n) (*(float *)&CTX->fr[(n)^1])
|
||||
#define LOAD_FPR_F64(n) (*(double *)&CTX->fr[n])
|
||||
#define LOAD_FPR_V128(n) {CTX->fr[(n)+0],CTX->fr[(n)+1],CTX->fr[(n)+2],CTX->fr[(n)+3]}
|
||||
#define STORE_FPR_I32(n, v) (CTX->fr[(n)^1] = (v))
|
||||
#define STORE_FPR_I64(n, v) (*(int64_t *)&CTX->fr[n] = (v))
|
||||
#define STORE_FPR_F32(n, v) (*(float *)&CTX->fr[(n)^1] = (v))
|
||||
#define STORE_FPR_F64(n, v) (*(double *)&CTX->fr[n] = (v))
|
||||
#define STORE_FPR_V128(n, v) memcpy(&CTX->fr[n], v, sizeof(v))
|
||||
#define STORE_FPR_IMM_I32(n, v) STORE_FPR_I32(n, v)
|
||||
|
||||
#define LOAD_XFR_I32(n) ((int32_t)CTX->xf[(n)^1])
|
||||
#define LOAD_XFR_I64(n) (*(int64_t *)&CTX->xf[n])
|
||||
#define LOAD_XFR_V128(n) {CTX->xf[(n)+0],CTX->xf[(n)+1],CTX->xf[(n)+2],CTX->xf[(n)+3]}
|
||||
#define STORE_XFR_I32(n, v) (CTX->xf[(n)^1] = (v))
|
||||
#define STORE_XFR_I64(n, v) (*(int64_t *)&CTX->xf[n] = (v))
|
||||
|
||||
#define LOAD_PR_I32() (CTX->pr)
|
||||
#define STORE_PR_I32(v) (CTX->pr = v)
|
||||
#define STORE_PR_IMM_I32(v) STORE_PR_I32(v)
|
||||
|
||||
#define LOAD_SR_I32() load_sr(CTX)
|
||||
#define STORE_SR_I32(v) store_sr(guest, CTX, v)
|
||||
#define STORE_SR_IMM_I32(v) STORE_SR_I32(v)
|
||||
|
||||
#define LOAD_T_I32() (CTX->sr_t)
|
||||
#define STORE_T_I8(v) (CTX->sr_t = v)
|
||||
#define STORE_T_I32(v) STORE_T_I8(v);
|
||||
#define STORE_T_IMM_I32(v) STORE_T_I8(v)
|
||||
|
||||
#define LOAD_S_I32() (CTX->sr_s)
|
||||
#define STORE_S_I32(v) (CTX->sr_s = v)
|
||||
#define STORE_S_IMM_I32(v) STORE_S_I32(v)
|
||||
|
||||
#define LOAD_QM_I32() (CTX->sr_qm)
|
||||
#define STORE_QM_I32(v) (CTX->sr_qm = v)
|
||||
#define STORE_QM_IMM_I32(v) STORE_QM_I32(v)
|
||||
|
||||
#define LOAD_FPSCR_I32() load_fpscr(CTX)
|
||||
#define STORE_FPSCR_I32(v) store_fpscr(guest, CTX, v)
|
||||
#define STORE_FPSCR_IMM_I32(v) STORE_FPSCR_I32(v)
|
||||
|
||||
#define LOAD_DBR_I32() (CTX->dbr)
|
||||
#define STORE_DBR_I32(v) (CTX->dbr = v)
|
||||
#define STORE_DBR_IMM_I32(v) STORE_DBR_I32(v)
|
||||
|
||||
#define LOAD_GBR_I32() (CTX->gbr)
|
||||
#define STORE_GBR_I32(v) (CTX->gbr = v)
|
||||
#define STORE_GBR_IMM_I32(v) STORE_GBR_I32(v)
|
||||
|
||||
#define LOAD_VBR_I32() (CTX->vbr)
|
||||
#define STORE_VBR_I32(v) (CTX->vbr = v)
|
||||
#define STORE_VBR_IMM_I32(v) STORE_VBR_I32(v)
|
||||
|
||||
#define LOAD_FPUL_I16() (*(uint16_t *)&CTX->fpul)
|
||||
#define LOAD_FPUL_I32() (CTX->fpul)
|
||||
#define LOAD_FPUL_F32() (*(float *)&CTX->fpul)
|
||||
#define STORE_FPUL_I32(v) (CTX->fpul = v)
|
||||
#define STORE_FPUL_F32(v) (*(float *)&CTX->fpul = v)
|
||||
#define STORE_FPUL_IMM_I32(v) STORE_FPUL_I32(v)
|
||||
|
||||
#define LOAD_MACH_I32() (CTX->mach)
|
||||
#define STORE_MACH_I32(v) (CTX->mach = v)
|
||||
#define STORE_MACH_IMM_I32(v) STORE_MACH_I32(v)
|
||||
|
||||
#define LOAD_MACL_I32() (CTX->macl)
|
||||
#define STORE_MACL_I32(v) (CTX->macl = v)
|
||||
#define STORE_MACL_IMM_I32(v) STORE_MACL_I32(v)
|
||||
|
||||
#define LOAD_SGR_I32() (CTX->sgr)
|
||||
#define STORE_SGR_I32(v) (CTX->sgr = v)
|
||||
#define STORE_SGR_IMM_I32(v) STORE_SGR_I32(v)
|
||||
|
||||
#define LOAD_SPC_I32() (CTX->spc)
|
||||
#define STORE_SPC_I32(v) (CTX->spc = v)
|
||||
#define STORE_SPC_IMM_I32(v) STORE_SPC_I32(v)
|
||||
|
||||
#define LOAD_SSR_I32() (CTX->ssr)
|
||||
#define STORE_SSR_I32(v) (CTX->ssr = v)
|
||||
#define STORE_SSR_IMM_I32(v) STORE_SSR_I32(v)
|
||||
|
||||
#define LOAD_I8(addr) guest->r8(guest->space, addr)
|
||||
#define LOAD_I16(addr) guest->r16(guest->space, addr)
|
||||
#define LOAD_I32(addr) guest->r32(guest->space, addr)
|
||||
#define LOAD_I64(addr) guest->r64(guest->space, addr)
|
||||
#define LOAD_IMM_I8(addr) LOAD_I8(addr)
|
||||
#define LOAD_IMM_I16(addr) LOAD_I16(addr)
|
||||
#define LOAD_IMM_I32(addr) LOAD_I32(addr)
|
||||
#define LOAD_IMM_I64(addr) LOAD_I64(addr)
|
||||
|
||||
#define STORE_I8(addr, v) guest->w8(guest->space, addr, v)
|
||||
#define STORE_I16(addr, v) guest->w16(guest->space, addr, v)
|
||||
#define STORE_I32(addr, v) guest->w32(guest->space, addr, v)
|
||||
#define STORE_I64(addr, v) guest->w64(guest->space, addr, v)
|
||||
|
||||
#define LOAD_HOST_F32(addr) (*(float *)(uintptr_t)addr)
|
||||
#define LOAD_HOST_F64(addr) (*(double *)(uintptr_t)addr)
|
||||
|
||||
#define FTOI_I32(v) ((int32_t)(v))
|
||||
#define FTOI_I64(v) ((int64_t)(v))
|
||||
|
||||
#define ITOF_F32(v) ((float)(v))
|
||||
#define ITOF_F64(v) ((double)(v))
|
||||
|
||||
#define SEXT_I8_I32(v) ((int32_t)(int8_t)(v))
|
||||
#define SEXT_I16_I32(v) ((int32_t)(int16_t)(v))
|
||||
#define SEXT_I16_I64(v) ((int64_t)(int16_t)(v))
|
||||
#define SEXT_I32_I64(v) ((int64_t)(int32_t)(v))
|
||||
|
||||
#define ZEXT_I8_I32(v) ((uint32_t)(uint8_t)(v))
|
||||
#define ZEXT_I16_I32(v) ((uint32_t)(uint16_t)(v))
|
||||
#define ZEXT_I16_I64(v) ((uint64_t)(uint16_t)(v))
|
||||
#define ZEXT_I32_I64(v) ((uint64_t)(uint32_t)(v))
|
||||
|
||||
#define TRUNC_I64_I32(a) ((uint32_t)(a))
|
||||
#define FEXT_F32_F64(a) ((double)(a))
|
||||
#define FTRUNC_F64_F32(a) ((float)(a))
|
||||
|
||||
#define SELECT_I8(c, a, b) ((c) ? (a) : (b))
|
||||
#define SELECT_I16 SELECT_I8
|
||||
#define SELECT_I32 SELECT_I8
|
||||
#define SELECT_I64 SELECT_I8
|
||||
|
||||
#define CMPEQ_I8(a, b) ((a) == (b))
|
||||
#define CMPEQ_I16 CMPEQ_I8
|
||||
#define CMPEQ_I32 CMPEQ_I8
|
||||
#define CMPEQ_I64 CMPEQ_I8
|
||||
#define CMPEQ_IMM_I8 CMPEQ_I8
|
||||
#define CMPEQ_IMM_I16 CMPEQ_I8
|
||||
#define CMPEQ_IMM_I32 CMPEQ_I8
|
||||
#define CMPEQ_IMM_I64 CMPEQ_I8
|
||||
|
||||
#define CMPSLT_I32(a, b) ((a) < (b))
|
||||
#define CMPSLT_IMM_I32 CMPSLT_I32
|
||||
#define CMPSLE_I32(a, b) ((a) <= (b))
|
||||
#define CMPSLE_IMM_I32 CMPSLE_I32
|
||||
#define CMPSGT_I32(a, b) ((a) > (b))
|
||||
#define CMPSGT_IMM_I32 CMPSGT_I32
|
||||
#define CMPSGE_I32(a, b) ((a) >= (b))
|
||||
#define CMPSGE_IMM_I32 CMPSGE_I32
|
||||
|
||||
#define CMPULT_I32(a, b) ((uint32_t)(a) < (uint32_t)(b))
|
||||
#define CMPULT_IMM_I32 CMPULT_I32
|
||||
#define CMPULE_I32(a, b) ((uint32_t)(a) <= (uint32_t)(b))
|
||||
#define CMPULE_IMM_I32 CMPULE_I32
|
||||
#define CMPUGT_I32(a, b) ((uint32_t)(a) > (uint32_t)(b))
|
||||
#define CMPUGT_IMM_I32 CMPUGT_I32
|
||||
#define CMPUGE_I32(a, b) ((uint32_t)(a) >= (uint32_t)(b))
|
||||
#define CMPUGE_IMM_I32 CMPUGE_I32
|
||||
|
||||
#define FCMPEQ_F32(a, b) ((a) == (b))
|
||||
#define FCMPEQ_F64(a, b) FCMPEQ_F32(a, b)
|
||||
|
||||
#define FCMPGT_F32(a, b) ((a) > (b))
|
||||
#define FCMPGT_F64(a, b) FCMPGT_F32(a, b)
|
||||
|
||||
#define ADD_I8(a, b) ((a) + (b))
|
||||
#define ADD_I16 ADD_I8
|
||||
#define ADD_I32 ADD_I8
|
||||
#define ADD_I64 ADD_I8
|
||||
#define ADD_IMM_I8 ADD_I8
|
||||
#define ADD_IMM_I16 ADD_I8
|
||||
#define ADD_IMM_I32 ADD_I8
|
||||
#define ADD_IMM_I64 ADD_I8
|
||||
|
||||
#define SUB_I8(a, b) ((a) - (b))
|
||||
#define SUB_I16 SUB_I8
|
||||
#define SUB_I32 SUB_I8
|
||||
#define SUB_I64 SUB_I8
|
||||
#define SUB_IMM_I8 SUB_I8
|
||||
#define SUB_IMM_I16 SUB_I8
|
||||
#define SUB_IMM_I32 SUB_I8
|
||||
#define SUB_IMM_I64 SUB_I8
|
||||
|
||||
#define SMUL_I8(a, b) ((int8_t)(a) * (int8_t)(b))
|
||||
#define SMUL_I16(a, b) ((int16_t)(a) * (int16_t)(b))
|
||||
#define SMUL_I32(a, b) ((int32_t)(a) * (int32_t)(b))
|
||||
#define SMUL_I64(a, b) ((int64_t)(a) * (int64_t)(b))
|
||||
#define SMUL_IMM_I8 SMUL_I8
|
||||
#define SMUL_IMM_I16 SMUL_I16
|
||||
#define SMUL_IMM_I32 SMUL_I32
|
||||
#define SMUL_IMM_I64 SMUL_I64
|
||||
|
||||
#define UMUL_I8(a, b) ((uint8_t)(a) * (uint8_t)(b))
|
||||
#define UMUL_I16(a, b) ((uint16_t)(a) * (uint16_t)(b))
|
||||
#define UMUL_I32(a, b) ((uint32_t)(a) * (uint32_t)(b))
|
||||
#define UMUL_I64(a, b) ((uint64_t)(a) * (uint64_t)(b))
|
||||
#define UMUL_IMM_I8 UMUL_I8
|
||||
#define UMUL_IMM_I16 UMUL_I16
|
||||
#define UMUL_IMM_I32 UMUL_I32
|
||||
#define UMUL_IMM_I64 UMUL_I64
|
||||
|
||||
#define NEG_I8(a) (-(a))
|
||||
#define NEG_I16 NEG_I8
|
||||
#define NEG_I32 NEG_I8
|
||||
#define NEG_I64 NEG_I8
|
||||
|
||||
#define FADD_F32(a, b) ((a) + (b))
|
||||
#define FADD_F64 FADD_F32
|
||||
|
||||
#define FSUB_F32(a, b) ((a) - (b))
|
||||
#define FSUB_F64 FSUB_F32
|
||||
|
||||
#define FMUL_F32(a, b) ((a) * (b))
|
||||
#define FMUL_F64 FMUL_F32
|
||||
|
||||
#define FDIV_F32(a, b) ((a) / (b))
|
||||
#define FDIV_F64 FDIV_F32
|
||||
|
||||
#define FNEG_F32(a) (-(a))
|
||||
#define FNEG_F64 FNEG_F32
|
||||
|
||||
#define FABS_F32(a) fabsf(a)
|
||||
#define FABS_F64(a) fabs(a)
|
||||
|
||||
#define FSQRT_F32(a) sqrtf(a)
|
||||
#define FSQRT_F64(a) sqrt(a)
|
||||
#define FRSQRT_F32(a) (1.0f / sqrtf(a))
|
||||
|
||||
#define VBROADCAST_F32(a) {*(int32_t *)&(a), *(int32_t *)&(a), *(int32_t *)&(a), *(int32_t *)&(a)}
|
||||
#define VADD_F32(a, b) {vadd_f32_el((a)[0], (b)[0]), \
|
||||
vadd_f32_el((a)[1], (b)[1]), \
|
||||
vadd_f32_el((a)[2], (b)[2]), \
|
||||
vadd_f32_el((a)[3], (b)[3])}
|
||||
#define VMUL_F32(a, b) {vmul_f32_el((a)[0], (b)[0]), \
|
||||
vmul_f32_el((a)[1], (b)[1]), \
|
||||
vmul_f32_el((a)[2], (b)[2]), \
|
||||
vmul_f32_el((a)[3], (b)[3])}
|
||||
#define VDOT_F32(a, b) vdot_f32(a, b)
|
||||
|
||||
#define AND_I8(a, b) ((a) & (b))
|
||||
#define AND_I16 AND_I8
|
||||
#define AND_I32 AND_I8
|
||||
#define AND_I64 AND_I8
|
||||
#define AND_IMM_I8 AND_I8
|
||||
#define AND_IMM_I16 AND_I8
|
||||
#define AND_IMM_I32 AND_I8
|
||||
#define AND_IMM_I64 AND_I8
|
||||
|
||||
#define OR_I8(a, b) ((a) | (b))
|
||||
#define OR_I16 OR_I8
|
||||
#define OR_I32 OR_I8
|
||||
#define OR_I64 OR_I8
|
||||
#define OR_IMM_I8 OR_I8
|
||||
#define OR_IMM_I16 OR_I8
|
||||
#define OR_IMM_I32 OR_I8
|
||||
#define OR_IMM_I64 OR_I8
|
||||
|
||||
#define XOR_I8(a, b) ((a) ^ (b))
|
||||
#define XOR_I16 XOR_I8
|
||||
#define XOR_I32 XOR_I8
|
||||
#define XOR_I64 XOR_I8
|
||||
#define XOR_IMM_I8 XOR_I8
|
||||
#define XOR_IMM_I16 XOR_I8
|
||||
#define XOR_IMM_I32 XOR_I8
|
||||
#define XOR_IMM_I64 XOR_I8
|
||||
|
||||
#define NOT_I8(a) (~(a))
|
||||
#define NOT_I16 NOT_I8
|
||||
#define NOT_I32 NOT_I8
|
||||
#define NOT_I64 NOT_I8
|
||||
|
||||
#define SHL_I8(v, n) (v << n)
|
||||
#define SHL_I16(v, n) (v << n)
|
||||
#define SHL_I32(v, n) (v << n)
|
||||
#define SHL_I64(v, n) (v << n)
|
||||
#define SHL_IMM_I8 SHL_I8
|
||||
#define SHL_IMM_I16 SHL_I16
|
||||
#define SHL_IMM_I32 SHL_I32
|
||||
#define SHL_IMM_I64 SHL_I64
|
||||
|
||||
#define ASHR_I8(v, n) ((int8_t)v >> n)
|
||||
#define ASHR_I16(v, n) ((int16_t)v >> n)
|
||||
#define ASHR_I32(v, n) ((int32_t)v >> n)
|
||||
#define ASHR_I64(v, n) ((int64_t)v >> n)
|
||||
#define ASHR_IMM_I8 ASHR_I8
|
||||
#define ASHR_IMM_I16 ASHR_I16
|
||||
#define ASHR_IMM_I32 ASHR_I32
|
||||
#define ASHR_IMM_I64 ASHR_I64
|
||||
|
||||
#define LSHR_I8(v, n) ((uint8_t)v >> n)
|
||||
#define LSHR_I16(v, n) ((uint16_t)v >> n)
|
||||
#define LSHR_I32(v, n) ((uint32_t)v >> n)
|
||||
#define LSHR_I64(v, n) ((uint64_t)v >> n)
|
||||
#define LSHR_IMM_I8 LSHR_I8
|
||||
#define LSHR_IMM_I16 LSHR_I16
|
||||
#define LSHR_IMM_I32 LSHR_I32
|
||||
#define LSHR_IMM_I64 LSHR_I64
|
||||
|
||||
#define ASHD_I32(v, n) (((n) & 0x80000000) ? (((n) & 0x1f) ? ((v) >> -((n) & 0x1f)) : ((v) >> 31)) : ((v) << ((n) & 0x1f)))
|
||||
#define LSHD_I32(v, n) (((n) & 0x80000000) ? (((n) & 0x1f) ? ((uint32_t)(v) >> -((n) & 0x1f)) : 0) : ((uint32_t)(v) << ((n) & 0x1f)))
|
||||
|
||||
#define BRANCH_I32(d) (CTX->pc = d)
|
||||
#define BRANCH_IMM_I32 BRANCH_I32
|
||||
#define BRANCH_TRUE_IMM_I32(c, d) if (c) { CTX->pc = d; return; }
|
||||
#define BRANCH_FALSE_IMM_I32(c, d) if (!c) { CTX->pc = d; return; }
|
||||
|
||||
#define PREF_SQ_COND(c, addr) if (c) { guest->sq_prefetch(guest->data, addr); }
|
||||
/* clang-format on */
|
||||
|
||||
#define INSTR(name) \
|
||||
void sh4_fallback_##name(struct sh4_guest *guest, uint32_t addr, \
|
||||
union sh4_instr i)
|
||||
#include "jit/frontend/sh4/sh4_instr.h"
|
||||
#undef INSTR
|
||||
|
||||
sh4_fallback_cb sh4_fallbacks[NUM_SH4_OPS] = {
|
||||
#define SH4_INSTR(name, desc, sig, cycles, flags) &sh4_fallback_##name,
|
||||
#include "jit/frontend/sh4/sh4_instr.inc"
|
||||
#undef SH4_INSTR
|
||||
};
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
#ifndef SH4_FALLBACKS_H
|
||||
#define SH4_FALLBACKS_H
|
||||
|
||||
#include "jit/frontend/sh4/sh4_disasm.h"
|
||||
|
||||
struct sh4_guest;
|
||||
|
||||
typedef void (*sh4_fallback_cb)(struct sh4_guest *, uint32_t, union sh4_instr);
|
||||
|
||||
extern sh4_fallback_cb sh4_fallbacks[NUM_SH4_OPS];
|
||||
|
||||
static inline sh4_fallback_cb sh4_get_fallback(uint16_t instr) {
|
||||
return sh4_fallbacks[sh4_op(instr)];
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -3,6 +3,7 @@
|
|||
#include "jit/frontend/jit_frontend.h"
|
||||
#include "jit/frontend/sh4/sh4_context.h"
|
||||
#include "jit/frontend/sh4/sh4_disasm.h"
|
||||
#include "jit/frontend/sh4/sh4_fallbacks.h"
|
||||
#include "jit/frontend/sh4/sh4_guest.h"
|
||||
#include "jit/frontend/sh4/sh4_translate.h"
|
||||
#include "jit/ir/ir.h"
|
||||
|
|
@ -28,29 +29,27 @@ static void sh4_analyze_block(const struct sh4_guest *guest,
|
|||
block->num_instrs = 0;
|
||||
|
||||
while (1) {
|
||||
struct sh4_instr instr = {0};
|
||||
instr.addr = addr;
|
||||
instr.opcode = guest->r16(guest->space, instr.addr);
|
||||
uint32_t data = guest->r16(guest->space, addr);
|
||||
struct sh4_opdef *def = sh4_opdef(data);
|
||||
int valid = def != NULL;
|
||||
|
||||
int valid = sh4_disasm(&instr);
|
||||
addr += 2;
|
||||
block->guest_size += 2;
|
||||
block->num_cycles += instr.cycles;
|
||||
block->num_cycles += def ? def->cycles : 0;
|
||||
block->num_instrs++;
|
||||
|
||||
if (instr.flags & SH4_FLAG_DELAYED) {
|
||||
struct sh4_instr delay_instr = {0};
|
||||
delay_instr.addr = addr;
|
||||
delay_instr.opcode = guest->r16(guest->space, delay_instr.addr);
|
||||
if (def->flags & SH4_FLAG_DELAYED) {
|
||||
uint32_t delay_data = guest->r16(guest->space, addr);
|
||||
struct sh4_opdef *delay_def = sh4_opdef(delay_data);
|
||||
valid |= delay_def != NULL;
|
||||
|
||||
valid = sh4_disasm(&delay_instr);
|
||||
addr += 2;
|
||||
block->guest_size += 2;
|
||||
block->num_cycles += delay_instr.cycles;
|
||||
block->num_cycles += delay_def ? delay_def->cycles : 0;
|
||||
block->num_instrs++;
|
||||
|
||||
/* delay slots can't have another delay slot */
|
||||
CHECK(!(delay_instr.flags & SH4_FLAG_DELAYED));
|
||||
CHECK(!(delay_def->flags & SH4_FLAG_DELAYED));
|
||||
}
|
||||
|
||||
/* end block on invalid instruction */
|
||||
|
|
@ -62,8 +61,7 @@ static void sh4_analyze_block(const struct sh4_guest *guest,
|
|||
changed, stop emitting since the fpu state is invalidated. also, if
|
||||
sr has changed, stop emitting as there are interrupts that possibly
|
||||
need to be handled */
|
||||
if (instr.flags &
|
||||
(SH4_FLAG_BRANCH | SH4_FLAG_SET_FPSCR | SH4_FLAG_SET_SR)) {
|
||||
if (def->flags & (SH4_FLAG_BRANCH | SH4_FLAG_SET_FPSCR | SH4_FLAG_SET_SR)) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -96,24 +94,26 @@ static void sh4_frontend_translate_code(struct jit_frontend *base,
|
|||
uint32_t end = block->guest_addr + block->guest_size;
|
||||
|
||||
while (addr < end) {
|
||||
struct sh4_instr instr = {0};
|
||||
struct sh4_instr delay_instr = {0};
|
||||
uint16_t data = guest->r16(guest->space, addr);
|
||||
union sh4_instr instr = {data};
|
||||
struct sh4_opdef *def = sh4_opdef(data);
|
||||
sh4_translate_cb cb = sh4_get_translator(data);
|
||||
|
||||
instr.addr = addr;
|
||||
instr.opcode = guest->r16(guest->space, instr.addr);
|
||||
sh4_disasm(&instr);
|
||||
|
||||
addr += 2;
|
||||
|
||||
if (instr.flags & SH4_FLAG_DELAYED) {
|
||||
delay_instr.addr = addr;
|
||||
delay_instr.opcode = guest->r16(guest->space, delay_instr.addr);
|
||||
sh4_disasm(&delay_instr);
|
||||
cb(guest, ir, flags, addr, instr);
|
||||
|
||||
if (def->flags & SH4_FLAG_DELAYED) {
|
||||
addr += 4;
|
||||
} else {
|
||||
addr += 2;
|
||||
}
|
||||
|
||||
sh4_emit_instr(guest, ir, flags, &instr, &delay_instr);
|
||||
#if 0
|
||||
/* emit extra debug info for recc */
|
||||
if (guest->jit->dump_blocks) {
|
||||
const char *name = sh4_opdefs[instr->op].name;
|
||||
ir_debug_info(ir, name, instr->addr, instr->opcode);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/* if the block terminates in something other than an unconditional branch,
|
||||
|
|
@ -123,7 +123,17 @@ static void sh4_frontend_translate_code(struct jit_frontend *base,
|
|||
struct ir_instr *tail_instr =
|
||||
list_last_entry(&tail_block->instrs, struct ir_instr, it);
|
||||
|
||||
if (tail_instr->op != OP_BRANCH) {
|
||||
int ends_in_branch = tail_instr->op == OP_BRANCH;
|
||||
|
||||
if (tail_instr->op == OP_FALLBACK) {
|
||||
struct sh4_opdef *opdef = sh4_opdef(tail_instr->arg[2]->i32);
|
||||
|
||||
if (opdef->flags & SH4_FLAG_BRANCH) {
|
||||
ends_in_branch = 1;
|
||||
}
|
||||
}
|
||||
|
||||
if (!ends_in_branch) {
|
||||
ir_set_current_instr(ir, tail_instr);
|
||||
ir_branch(ir, ir_alloc_i32(ir, addr));
|
||||
}
|
||||
|
|
@ -138,29 +148,26 @@ static void sh4_frontend_dump_code(struct jit_frontend *base, uint32_t addr,
|
|||
|
||||
char buffer[128];
|
||||
|
||||
int i = 0;
|
||||
uint32_t end = addr + size / 2;
|
||||
|
||||
while (i < size) {
|
||||
struct sh4_instr instr = {0};
|
||||
instr.addr = addr + i;
|
||||
instr.opcode = guest->r16(guest->space, instr.addr);
|
||||
sh4_disasm(&instr);
|
||||
while (addr < end) {
|
||||
uint16_t data = guest->r16(guest->space, addr);
|
||||
union sh4_instr instr = {data};
|
||||
struct sh4_opdef *def = sh4_opdef(data);
|
||||
|
||||
sh4_format(&instr, buffer, sizeof(buffer));
|
||||
sh4_format(addr, instr, buffer, sizeof(buffer));
|
||||
LOG_INFO(buffer);
|
||||
|
||||
i += 2;
|
||||
addr += 2;
|
||||
|
||||
if (instr.flags & SH4_FLAG_DELAYED) {
|
||||
struct sh4_instr delay = {0};
|
||||
delay.addr = addr + i;
|
||||
delay.opcode = guest->r16(guest->space, delay.addr);
|
||||
sh4_disasm(&delay);
|
||||
if (def->flags & SH4_FLAG_DELAYED) {
|
||||
uint16_t delay_data = guest->r16(guest->space, addr);
|
||||
union sh4_instr delay_instr = {delay_data};
|
||||
|
||||
sh4_format(&delay, buffer, sizeof(buffer));
|
||||
sh4_format(addr, delay_instr, buffer, sizeof(buffer));
|
||||
LOG_INFO(buffer);
|
||||
|
||||
i += 2;
|
||||
addr += 2;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,246 +1,246 @@
|
|||
//
|
||||
// NAME DESC INSTR_CODE CYCLES FLAGS
|
||||
// NAME DESC INSTR_CODE CYCLES FLAGS
|
||||
//
|
||||
|
||||
SH4_INSTR(INVALID, "invalid", 0000000000000000, 1, 0)
|
||||
SH4_INSTR(INVALID, "invalid", 0000000000000000, 1, 0)
|
||||
|
||||
// fixed-point transfer instructions
|
||||
SH4_INSTR(MOVI, "mov #imm8, rn", 1110nnnniiiiiiii, 1, 0)
|
||||
SH4_INSTR(MOVWLPC, "mov.w @(disp:8,pc), rn", 1001nnnndddddddd, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOVLLPC, "mov.l @(disp:8,pc), rn", 1101nnnndddddddd, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOV, "mov rm, rn", 0110nnnnmmmm0011, 1, 0)
|
||||
SH4_INSTR(MOVBS, "mov.b rm, @rn", 0010nnnnmmmm0000, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(MOVWS, "mov.w rm, @rn", 0010nnnnmmmm0001, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(MOVLS, "mov.l rm, @rn", 0010nnnnmmmm0010, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(MOVBL, "mov.b @rm, rn", 0110nnnnmmmm0000, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOVWL, "mov.w @rm, rn", 0110nnnnmmmm0001, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOVLL, "mov.l @rm, rn", 0110nnnnmmmm0010, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOVBM, "mov.b rm,@-rn", 0010nnnnmmmm0100, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(MOVWM, "mov.w rm,@-rn", 0010nnnnmmmm0101, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(MOVLM, "mov.l rm,@-rn", 0010nnnnmmmm0110, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(MOVBP, "mov.b @rm+,rn", 0110nnnnmmmm0100, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOVWP, "mov.w @rm+,rn", 0110nnnnmmmm0101, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOVLP, "mov.l @rm+,rn", 0110nnnnmmmm0110, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOVBS0D, "mov.b r0, @(disp:4,rn)", 10000000nnnndddd, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(MOVWS0D, "mov.w r0, @(disp:4,rn)", 10000001nnnndddd, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(MOVLSMD, "mov.l rm, @(disp:4,rn)", 0001nnnnmmmmdddd, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(MOVBLD0, "mov.b @(disp:4,rm), r0", 10000100mmmmdddd, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOVWLD0, "mov.w @(disp:4,rm), r0", 10000101mmmmdddd, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOVLLDN, "mov.l @(disp:4,rm), rn", 0101nnnnmmmmdddd, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOVBS0, "mov.b rm, @(r0,rn)", 0000nnnnmmmm0100, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(MOVWS0, "mov.w rm, @(r0,rn)", 0000nnnnmmmm0101, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(MOVLS0, "mov.l rm, @(r0,rn)", 0000nnnnmmmm0110, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(MOVBL0, "mov.b @(r0,rm), rn", 0000nnnnmmmm1100, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOVWL0, "mov.w @(r0,rm), rn", 0000nnnnmmmm1101, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOVLL0, "mov.l @(r0,rm), rn", 0000nnnnmmmm1110, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOVBS0G, "mov.b r0, @(disp:8,gbr)", 11000000dddddddd, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(MOVWS0G, "mov.w r0, @(disp:8,gbr)", 11000001dddddddd, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(MOVLS0G, "mov.l r0, @(disp:8,gbr)", 11000010dddddddd, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(MOVBLG0, "mov.b @(disp:8,gbr), r0", 11000100dddddddd, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOVWLG0, "mov.w @(disp:8,gbr), r0", 11000101dddddddd, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOVLLG0, "mov.l @(disp:8,gbr), r0", 11000110dddddddd, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOVA, "mova (disp:8,pc), r0", 11000111dddddddd, 1, 0)
|
||||
SH4_INSTR(MOVT, "movt rn", 0000nnnn00101001, 1, 0)
|
||||
SH4_INSTR(SWAPB, "swap.b rm, rn", 0110nnnnmmmm1000, 1, 0)
|
||||
SH4_INSTR(SWAPW, "swap.w rm, rn", 0110nnnnmmmm1001, 1, 0)
|
||||
SH4_INSTR(XTRCT, "xtrct rm, rn", 0010nnnnmmmm1101, 1, 0)
|
||||
SH4_INSTR(MOVI, "mov #imm8, rn", 1110nnnniiiiiiii, 1, 0)
|
||||
SH4_INSTR(MOVWLPC, "mov.w @(disp:8,pc), rn", 1001nnnndddddddd, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOVLLPC, "mov.l @(disp:8,pc), rn", 1101nnnndddddddd, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOV, "mov rm, rn", 0110nnnnmmmm0011, 1, 0)
|
||||
SH4_INSTR(MOVBS, "mov.b rm, @rn", 0010nnnnmmmm0000, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(MOVWS, "mov.w rm, @rn", 0010nnnnmmmm0001, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(MOVLS, "mov.l rm, @rn", 0010nnnnmmmm0010, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(MOVBL, "mov.b @rm, rn", 0110nnnnmmmm0000, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOVWL, "mov.w @rm, rn", 0110nnnnmmmm0001, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOVLL, "mov.l @rm, rn", 0110nnnnmmmm0010, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOVBM, "mov.b rm,@-rn", 0010nnnnmmmm0100, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(MOVWM, "mov.w rm,@-rn", 0010nnnnmmmm0101, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(MOVLM, "mov.l rm,@-rn", 0010nnnnmmmm0110, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(MOVBP, "mov.b @rm+,rn", 0110nnnnmmmm0100, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOVWP, "mov.w @rm+,rn", 0110nnnnmmmm0101, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOVLP, "mov.l @rm+,rn", 0110nnnnmmmm0110, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOVBS0D, "mov.b r0, @(disp:4,rm)", 10000000nnnndddd, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(MOVWS0D, "mov.w r0, @(disp:4,rm)", 10000001nnnndddd, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(MOVLSMD, "mov.l rm, @(disp:4,rn)", 0001nnnnmmmmdddd, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(MOVBLD0, "mov.b @(disp:4,rm), r0", 10000100mmmmdddd, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOVWLD0, "mov.w @(disp:4,rm), r0", 10000101mmmmdddd, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOVLLDN, "mov.l @(disp:4,rm), rn", 0101nnnnmmmmdddd, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOVBS0, "mov.b rm, @(r0,rn)", 0000nnnnmmmm0100, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(MOVWS0, "mov.w rm, @(r0,rn)", 0000nnnnmmmm0101, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(MOVLS0, "mov.l rm, @(r0,rn)", 0000nnnnmmmm0110, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(MOVBL0, "mov.b @(r0,rm), rn", 0000nnnnmmmm1100, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOVWL0, "mov.w @(r0,rm), rn", 0000nnnnmmmm1101, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOVLL0, "mov.l @(r0,rm), rn", 0000nnnnmmmm1110, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOVBS0G, "mov.b r0, @(disp:8,gbr)", 11000000dddddddd, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(MOVWS0G, "mov.w r0, @(disp:8,gbr)", 11000001dddddddd, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(MOVLS0G, "mov.l r0, @(disp:8,gbr)", 11000010dddddddd, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(MOVBLG0, "mov.b @(disp:8,gbr), r0", 11000100dddddddd, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOVWLG0, "mov.w @(disp:8,gbr), r0", 11000101dddddddd, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOVLLG0, "mov.l @(disp:8,gbr), r0", 11000110dddddddd, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOVA, "mova (disp:8,pc), r0", 11000111dddddddd, 1, 0)
|
||||
SH4_INSTR(MOVT, "movt rn", 0000nnnn00101001, 1, 0)
|
||||
SH4_INSTR(SWAPB, "swap.b rm, rn", 0110nnnnmmmm1000, 1, 0)
|
||||
SH4_INSTR(SWAPW, "swap.w rm, rn", 0110nnnnmmmm1001, 1, 0)
|
||||
SH4_INSTR(XTRCT, "xtrct rm, rn", 0010nnnnmmmm1101, 1, 0)
|
||||
|
||||
|
||||
// arithmetric operation instructions
|
||||
SH4_INSTR(ADD, "add rm, rn", 0011nnnnmmmm1100, 1, 0)
|
||||
SH4_INSTR(ADDI, "add #imm8, rn", 0111nnnniiiiiiii, 1, 0)
|
||||
SH4_INSTR(ADDC, "addc rm, rn", 0011nnnnmmmm1110, 1, 0)
|
||||
SH4_INSTR(ADDV, "addv rm, rn", 0011nnnnmmmm1111, 1, 0)
|
||||
SH4_INSTR(CMPEQI, "cmp/eq #imm8, r0", 10001000iiiiiiii, 1, 0)
|
||||
SH4_INSTR(CMPEQ, "cmp/eq rm, rn", 0011nnnnmmmm0000, 1, 0)
|
||||
SH4_INSTR(CMPHS, "cmp/hs rm, rn", 0011nnnnmmmm0010, 1, 0)
|
||||
SH4_INSTR(CMPGE, "cmp/ge rm, rn", 0011nnnnmmmm0011, 1, 0)
|
||||
SH4_INSTR(CMPHI, "cmp/hi rm, rn", 0011nnnnmmmm0110, 1, 0)
|
||||
SH4_INSTR(CMPGT, "cmp/gt rm, rn", 0011nnnnmmmm0111, 1, 0)
|
||||
SH4_INSTR(CMPPZ, "cmp/pz rn", 0100nnnn00010001, 1, 0)
|
||||
SH4_INSTR(CMPPL, "cmp/pl rn", 0100nnnn00010101, 1, 0)
|
||||
SH4_INSTR(CMPSTR, "cmp/str rm, rn", 0010nnnnmmmm1100, 1, 0)
|
||||
SH4_INSTR(DIV0S, "div0s rm, rn", 0010nnnnmmmm0111, 1, 0)
|
||||
SH4_INSTR(DIV0U, "div0u", 0000000000011001, 1, 0)
|
||||
SH4_INSTR(DIV1, "div1 rm, rn", 0011nnnnmmmm0100, 1, 0)
|
||||
SH4_INSTR(DMULS, "dmuls.l rm, rn", 0011nnnnmmmm1101, 2, 0)
|
||||
SH4_INSTR(DMULU, "dmulu.l rm, rn", 0011nnnnmmmm0101, 2, 0)
|
||||
SH4_INSTR(DT, "dt rn", 0100nnnn00010000, 1, 0)
|
||||
SH4_INSTR(EXTSB, "exts.b rm, rn", 0110nnnnmmmm1110, 1, 0)
|
||||
SH4_INSTR(EXTSW, "exts.w rm, rn", 0110nnnnmmmm1111, 1, 0)
|
||||
SH4_INSTR(EXTUB, "extu.b rm, rn", 0110nnnnmmmm1100, 1, 0)
|
||||
SH4_INSTR(EXTUW, "extu.w rm, rn", 0110nnnnmmmm1101, 1, 0)
|
||||
SH4_INSTR(MACL, "mac.l @rm+, @rn+", 0000nnnnmmmm1111, 2, SH4_FLAG_LOAD | SH4_FLAG_STORE)
|
||||
SH4_INSTR(MACW, "mac.w @rm+, @rn+", 0100nnnnmmmm1111, 2, SH4_FLAG_LOAD | SH4_FLAG_STORE)
|
||||
SH4_INSTR(MULL, "mul.l rm, rn", 0000nnnnmmmm0111, 2, 0)
|
||||
SH4_INSTR(MULS, "muls rm, rn", 0010nnnnmmmm1111, 2, 0)
|
||||
SH4_INSTR(MULU, "mulu rm, rn", 0010nnnnmmmm1110, 2, 0)
|
||||
SH4_INSTR(NEG, "neg rm, rn", 0110nnnnmmmm1011, 1, 0)
|
||||
SH4_INSTR(NEGC, "negc rm, rn", 0110nnnnmmmm1010, 1, 0)
|
||||
SH4_INSTR(SUB, "sub rm, rn", 0011nnnnmmmm1000, 1, 0)
|
||||
SH4_INSTR(SUBC, "subc rm, rn", 0011nnnnmmmm1010, 1, 0)
|
||||
SH4_INSTR(SUBV, "subv rm, rn", 0011nnnnmmmm1011, 1, 0)
|
||||
SH4_INSTR(ADD, "add rm, rn", 0011nnnnmmmm1100, 1, 0)
|
||||
SH4_INSTR(ADDI, "add #imm8, rn", 0111nnnniiiiiiii, 1, 0)
|
||||
SH4_INSTR(ADDC, "addc rm, rn", 0011nnnnmmmm1110, 1, 0)
|
||||
SH4_INSTR(ADDV, "addv rm, rn", 0011nnnnmmmm1111, 1, 0)
|
||||
SH4_INSTR(CMPEQI, "cmp/eq #imm8, r0", 10001000iiiiiiii, 1, 0)
|
||||
SH4_INSTR(CMPEQ, "cmp/eq rm, rn", 0011nnnnmmmm0000, 1, 0)
|
||||
SH4_INSTR(CMPHS, "cmp/hs rm, rn", 0011nnnnmmmm0010, 1, 0)
|
||||
SH4_INSTR(CMPGE, "cmp/ge rm, rn", 0011nnnnmmmm0011, 1, 0)
|
||||
SH4_INSTR(CMPHI, "cmp/hi rm, rn", 0011nnnnmmmm0110, 1, 0)
|
||||
SH4_INSTR(CMPGT, "cmp/gt rm, rn", 0011nnnnmmmm0111, 1, 0)
|
||||
SH4_INSTR(CMPPZ, "cmp/pz rn", 0100nnnn00010001, 1, 0)
|
||||
SH4_INSTR(CMPPL, "cmp/pl rn", 0100nnnn00010101, 1, 0)
|
||||
SH4_INSTR(CMPSTR, "cmp/str rm, rn", 0010nnnnmmmm1100, 1, 0)
|
||||
SH4_INSTR(DIV0S, "div0s rm, rn", 0010nnnnmmmm0111, 1, 0)
|
||||
SH4_INSTR(DIV0U, "div0u", 0000000000011001, 1, 0)
|
||||
SH4_INSTR(DIV1, "div1 rm, rn", 0011nnnnmmmm0100, 1, 0)
|
||||
SH4_INSTR(DMULS, "dmuls.l rm, rn", 0011nnnnmmmm1101, 2, 0)
|
||||
SH4_INSTR(DMULU, "dmulu.l rm, rn", 0011nnnnmmmm0101, 2, 0)
|
||||
SH4_INSTR(DT, "dt rn", 0100nnnn00010000, 1, 0)
|
||||
SH4_INSTR(EXTSB, "exts.b rm, rn", 0110nnnnmmmm1110, 1, 0)
|
||||
SH4_INSTR(EXTSW, "exts.w rm, rn", 0110nnnnmmmm1111, 1, 0)
|
||||
SH4_INSTR(EXTUB, "extu.b rm, rn", 0110nnnnmmmm1100, 1, 0)
|
||||
SH4_INSTR(EXTUW, "extu.w rm, rn", 0110nnnnmmmm1101, 1, 0)
|
||||
SH4_INSTR(MACL, "mac.l @rm+, @rn+", 0000nnnnmmmm1111, 2, SH4_FLAG_LOAD | SH4_FLAG_STORE)
|
||||
SH4_INSTR(MACW, "mac.w @rm+, @rn+", 0100nnnnmmmm1111, 2, SH4_FLAG_LOAD | SH4_FLAG_STORE)
|
||||
SH4_INSTR(MULL, "mul.l rm, rn", 0000nnnnmmmm0111, 2, 0)
|
||||
SH4_INSTR(MULS, "muls rm, rn", 0010nnnnmmmm1111, 2, 0)
|
||||
SH4_INSTR(MULU, "mulu rm, rn", 0010nnnnmmmm1110, 2, 0)
|
||||
SH4_INSTR(NEG, "neg rm, rn", 0110nnnnmmmm1011, 1, 0)
|
||||
SH4_INSTR(NEGC, "negc rm, rn", 0110nnnnmmmm1010, 1, 0)
|
||||
SH4_INSTR(SUB, "sub rm, rn", 0011nnnnmmmm1000, 1, 0)
|
||||
SH4_INSTR(SUBC, "subc rm, rn", 0011nnnnmmmm1010, 1, 0)
|
||||
SH4_INSTR(SUBV, "subv rm, rn", 0011nnnnmmmm1011, 1, 0)
|
||||
|
||||
|
||||
// logic operation instructions
|
||||
SH4_INSTR(AND, "and rm, rn", 0010nnnnmmmm1001, 1, 0)
|
||||
SH4_INSTR(ANDI, "and #imm8, r0", 11001001iiiiiiii, 1, 0)
|
||||
SH4_INSTR(ANDB, "and.b #imm8, @(r0,gbr)", 11001101iiiiiiii, 4, SH4_FLAG_STORE)
|
||||
SH4_INSTR(NOT, "not rm, rn", 0110nnnnmmmm0111, 1, 0)
|
||||
SH4_INSTR(OR, "or rm, rn", 0010nnnnmmmm1011, 1, 0)
|
||||
SH4_INSTR(ORI, "or #imm8, r0", 11001011iiiiiiii, 1, 0)
|
||||
SH4_INSTR(ORB, "or.b #imm8, @(r0,gbr)", 11001111iiiiiiii, 4, SH4_FLAG_STORE)
|
||||
SH4_INSTR(TAS, "tas.b @rn", 0100nnnn00011011, 5, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(TST, "tst rm, rn", 0010nnnnmmmm1000, 1, 0)
|
||||
SH4_INSTR(TSTI, "tst #imm8, r0", 11001000iiiiiiii, 1, 0)
|
||||
SH4_INSTR(TSTB, "tst.b #imm8, @(r0,gbr)", 11001100iiiiiiii, 3, SH4_FLAG_STORE)
|
||||
SH4_INSTR(XOR, "xor rm, rn", 0010nnnnmmmm1010, 1, 0)
|
||||
SH4_INSTR(XORI, "xor #imm8, r0", 11001010iiiiiiii, 1, 0)
|
||||
SH4_INSTR(XORB, "xor.b #imm8, @(r0,gbr)", 11001110iiiiiiii, 4, SH4_FLAG_STORE)
|
||||
SH4_INSTR(AND, "and rm, rn", 0010nnnnmmmm1001, 1, 0)
|
||||
SH4_INSTR(ANDI, "and #imm8, r0", 11001001iiiiiiii, 1, 0)
|
||||
SH4_INSTR(ANDB, "and.b #imm8, @(r0,gbr)", 11001101iiiiiiii, 4, SH4_FLAG_STORE)
|
||||
SH4_INSTR(NOT, "not rm, rn", 0110nnnnmmmm0111, 1, 0)
|
||||
SH4_INSTR(OR, "or rm, rn", 0010nnnnmmmm1011, 1, 0)
|
||||
SH4_INSTR(ORI, "or #imm8, r0", 11001011iiiiiiii, 1, 0)
|
||||
SH4_INSTR(ORB, "or.b #imm8, @(r0,gbr)", 11001111iiiiiiii, 4, SH4_FLAG_STORE)
|
||||
SH4_INSTR(TAS, "tas.b @rn", 0100nnnn00011011, 5, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(TST, "tst rm, rn", 0010nnnnmmmm1000, 1, 0)
|
||||
SH4_INSTR(TSTI, "tst #imm8, r0", 11001000iiiiiiii, 1, 0)
|
||||
SH4_INSTR(TSTB, "tst.b #imm8, @(r0,gbr)", 11001100iiiiiiii, 3, SH4_FLAG_STORE)
|
||||
SH4_INSTR(XOR, "xor rm, rn", 0010nnnnmmmm1010, 1, 0)
|
||||
SH4_INSTR(XORI, "xor #imm8, r0", 11001010iiiiiiii, 1, 0)
|
||||
SH4_INSTR(XORB, "xor.b #imm8, @(r0,gbr)", 11001110iiiiiiii, 4, SH4_FLAG_STORE)
|
||||
|
||||
|
||||
// shift instructions
|
||||
SH4_INSTR(ROTL, "rotl rn", 0100nnnn00000100, 1, 0)
|
||||
SH4_INSTR(ROTR, "rotr rn", 0100nnnn00000101, 1, 0)
|
||||
SH4_INSTR(ROTCL, "rotcl rn", 0100nnnn00100100, 1, 0)
|
||||
SH4_INSTR(ROTCR, "rotcr rn", 0100nnnn00100101, 1, 0)
|
||||
SH4_INSTR(SHAD, "shad rm, rn", 0100nnnnmmmm1100, 1, 0)
|
||||
SH4_INSTR(SHAL, "shal rn", 0100nnnn00100000, 1, 0)
|
||||
SH4_INSTR(SHAR, "shar rn", 0100nnnn00100001, 1, 0)
|
||||
SH4_INSTR(SHLD, "shld rm, rn", 0100nnnnmmmm1101, 1, 0)
|
||||
SH4_INSTR(SHLL, "shll rn", 0100nnnn00000000, 1, 0)
|
||||
SH4_INSTR(SHLR, "shlr rn", 0100nnnn00000001, 1, 0)
|
||||
SH4_INSTR(SHLL2, "shll2 rn", 0100nnnn00001000, 1, 0)
|
||||
SH4_INSTR(SHLR2, "shlr2 rn", 0100nnnn00001001, 1, 0)
|
||||
SH4_INSTR(SHLL8, "shll8 rn", 0100nnnn00011000, 1, 0)
|
||||
SH4_INSTR(SHLR8, "shlr8 rn", 0100nnnn00011001, 1, 0)
|
||||
SH4_INSTR(SHLL16, "shll16 rn", 0100nnnn00101000, 1, 0)
|
||||
SH4_INSTR(SHLR16, "shlr16 rn", 0100nnnn00101001, 1, 0)
|
||||
SH4_INSTR(ROTL, "rotl rn", 0100nnnn00000100, 1, 0)
|
||||
SH4_INSTR(ROTR, "rotr rn", 0100nnnn00000101, 1, 0)
|
||||
SH4_INSTR(ROTCL, "rotcl rn", 0100nnnn00100100, 1, 0)
|
||||
SH4_INSTR(ROTCR, "rotcr rn", 0100nnnn00100101, 1, 0)
|
||||
SH4_INSTR(SHAD, "shad rm, rn", 0100nnnnmmmm1100, 1, 0)
|
||||
SH4_INSTR(SHAL, "shal rn", 0100nnnn00100000, 1, 0)
|
||||
SH4_INSTR(SHAR, "shar rn", 0100nnnn00100001, 1, 0)
|
||||
SH4_INSTR(SHLD, "shld rm, rn", 0100nnnnmmmm1101, 1, 0)
|
||||
SH4_INSTR(SHLL, "shll rn", 0100nnnn00000000, 1, 0)
|
||||
SH4_INSTR(SHLR, "shlr rn", 0100nnnn00000001, 1, 0)
|
||||
SH4_INSTR(SHLL2, "shll2 rn", 0100nnnn00001000, 1, 0)
|
||||
SH4_INSTR(SHLR2, "shlr2 rn", 0100nnnn00001001, 1, 0)
|
||||
SH4_INSTR(SHLL8, "shll8 rn", 0100nnnn00011000, 1, 0)
|
||||
SH4_INSTR(SHLR8, "shlr8 rn", 0100nnnn00011001, 1, 0)
|
||||
SH4_INSTR(SHLL16, "shll16 rn", 0100nnnn00101000, 1, 0)
|
||||
SH4_INSTR(SHLR16, "shlr16 rn", 0100nnnn00101001, 1, 0)
|
||||
|
||||
|
||||
// branch instructions
|
||||
// can we sign extend bdisp12 in sh4_instr code, not inside of sh4_builder
|
||||
// then, we can reuse some more of these disp* types
|
||||
SH4_INSTR(BF, "bf disp:8", 10001011dddddddd, 1, SH4_FLAG_CONDITIONAL | SH4_FLAG_BRANCH)
|
||||
SH4_INSTR(BFS, "bfs disp:8", 10001111dddddddd, 1, SH4_FLAG_CONDITIONAL | SH4_FLAG_BRANCH | SH4_FLAG_DELAYED)
|
||||
SH4_INSTR(BT, "bt disp:8", 10001001dddddddd, 1, SH4_FLAG_CONDITIONAL | SH4_FLAG_BRANCH)
|
||||
SH4_INSTR(BTS, "bts disp:8", 10001101dddddddd, 1, SH4_FLAG_CONDITIONAL | SH4_FLAG_BRANCH | SH4_FLAG_DELAYED)
|
||||
SH4_INSTR(BRA, "bra disp:12", 1010dddddddddddd, 1, SH4_FLAG_BRANCH | SH4_FLAG_DELAYED)
|
||||
SH4_INSTR(BRAF, "braf rn", 0000nnnn00100011, 2, SH4_FLAG_BRANCH | SH4_FLAG_DELAYED)
|
||||
SH4_INSTR(BSR, "bsr disp:12", 1011dddddddddddd, 1, SH4_FLAG_BRANCH | SH4_FLAG_DELAYED)
|
||||
SH4_INSTR(BSRF, "bsrf rn", 0000nnnn00000011, 2, SH4_FLAG_BRANCH | SH4_FLAG_DELAYED)
|
||||
SH4_INSTR(JMP, "jmp @rm", 0100nnnn00101011, 2, SH4_FLAG_BRANCH | SH4_FLAG_DELAYED)
|
||||
SH4_INSTR(JSR, "jsr @rn", 0100nnnn00001011, 2, SH4_FLAG_BRANCH | SH4_FLAG_DELAYED)
|
||||
SH4_INSTR(RTS, "rts", 0000000000001011, 2, SH4_FLAG_BRANCH | SH4_FLAG_DELAYED)
|
||||
SH4_INSTR(BF, "bf disp:8", 10001011dddddddd, 1, SH4_FLAG_CONDITIONAL | SH4_FLAG_BRANCH)
|
||||
SH4_INSTR(BFS, "bfs disp:8", 10001111dddddddd, 1, SH4_FLAG_CONDITIONAL | SH4_FLAG_BRANCH | SH4_FLAG_DELAYED)
|
||||
SH4_INSTR(BT, "bt disp:8", 10001001dddddddd, 1, SH4_FLAG_CONDITIONAL | SH4_FLAG_BRANCH)
|
||||
SH4_INSTR(BTS, "bts disp:8", 10001101dddddddd, 1, SH4_FLAG_CONDITIONAL | SH4_FLAG_BRANCH | SH4_FLAG_DELAYED)
|
||||
SH4_INSTR(BRA, "bra disp:12", 1010dddddddddddd, 1, SH4_FLAG_BRANCH | SH4_FLAG_DELAYED)
|
||||
SH4_INSTR(BRAF, "braf rn", 0000nnnn00100011, 2, SH4_FLAG_BRANCH | SH4_FLAG_DELAYED)
|
||||
SH4_INSTR(BSR, "bsr disp:12", 1011dddddddddddd, 1, SH4_FLAG_BRANCH | SH4_FLAG_DELAYED)
|
||||
SH4_INSTR(BSRF, "bsrf rn", 0000nnnn00000011, 2, SH4_FLAG_BRANCH | SH4_FLAG_DELAYED)
|
||||
SH4_INSTR(JMP, "jmp @rm", 0100nnnn00101011, 2, SH4_FLAG_BRANCH | SH4_FLAG_DELAYED)
|
||||
SH4_INSTR(JSR, "jsr @rn", 0100nnnn00001011, 2, SH4_FLAG_BRANCH | SH4_FLAG_DELAYED)
|
||||
SH4_INSTR(RTS, "rts", 0000000000001011, 2, SH4_FLAG_BRANCH | SH4_FLAG_DELAYED)
|
||||
|
||||
|
||||
// system control instructions
|
||||
SH4_INSTR(CLRMAC, "clrmac", 0000000000101000, 1, 0)
|
||||
SH4_INSTR(CLRS, "clrs", 0000000001001000, 1, 0)
|
||||
SH4_INSTR(CLRT, "clrt", 0000000000001000, 1, 0)
|
||||
SH4_INSTR(LDCSR, "ldc rm, sr", 0100mmmm00001110, 4, SH4_FLAG_SET_SR)
|
||||
SH4_INSTR(LDCGBR, "ldc rm, gbr", 0100mmmm00011110, 3, 0)
|
||||
SH4_INSTR(LDCVBR, "ldc rm, vbr", 0100mmmm00101110, 1, 0)
|
||||
SH4_INSTR(LDCSSR, "ldc rm, ssr", 0100mmmm00111110, 1, 0)
|
||||
SH4_INSTR(LDCSPC, "ldc rm, spc", 0100mmmm01001110, 1, 0)
|
||||
SH4_INSTR(LDCDBR, "ldc rm, dbr", 0100mmmm11111010, 1, 0)
|
||||
SH4_INSTR(LDCRBANK, "ldc.l rm, rn_bank", 0100mmmm1nnn1110, 1, 0)
|
||||
SH4_INSTR(LDCMSR, "ldc.l @rm+, sr", 0100mmmm00000111, 4, SH4_FLAG_LOAD | SH4_FLAG_SET_SR)
|
||||
SH4_INSTR(LDCMGBR, "ldc.l @rm+, gbr", 0100mmmm00010111, 3, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(LDCMVBR, "ldc.l @rm+, vbr", 0100mmmm00100111, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(LDCMSSR, "ldc.l @rm+, ssr", 0100mmmm00110111, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(LDCMSPC, "ldc.l @rm+, spc", 0100mmmm01000111, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(LDCMDBR, "ldc.l @rm+, dbr", 0100mmmm11110110, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(LDCMRBANK, "ldc.l @rm+, rn_bank", 0100mmmm1nnn0111, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(LDSMACH, "lds rm, mach", 0100mmmm00001010, 1, 0)
|
||||
SH4_INSTR(LDSMACL, "lds rm, macl", 0100mmmm00011010, 1, 0)
|
||||
SH4_INSTR(LDSPR, "lds rm, pr", 0100mmmm00101010, 2, 0)
|
||||
SH4_INSTR(LDSMMACH, "lds.l @rm+, mach", 0100mmmm00000110, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(LDSMMACL, "lds.l @rm+, macl", 0100mmmm00010110, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(LDSMPR, "lds.l @rm+, pr", 0100mmmm00100110, 2, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOVCAL, "movca.l r0, @rn", 0000nnnn11000011, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(NOP, "nop", 0000000000001001, 1, 0)
|
||||
SH4_INSTR(OCBI, "ocbi", 0000nnnn10010011, 1, 0)
|
||||
SH4_INSTR(OCBP, "ocbp", 0000nnnn10100011, 1, 0)
|
||||
SH4_INSTR(OCBWB, "ocbwb", 0000nnnn10110011, 1, 0)
|
||||
SH4_INSTR(PREF, "pref @rn", 0000nnnn10000011, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(RTE, "rte", 0000000000101011, 5, SH4_FLAG_BRANCH | SH4_FLAG_DELAYED | SH4_FLAG_SET_SR)
|
||||
SH4_INSTR(SETS, "sets", 0000000001011000, 1, 0)
|
||||
SH4_INSTR(SETT, "sett", 0000000000011000, 1, 0)
|
||||
SH4_INSTR(SLEEP, "sleep", 0000000000011011, 4, 0)
|
||||
SH4_INSTR(STCSR, "stc sr, rn", 0000nnnn00000010, 2, 0)
|
||||
SH4_INSTR(STCGBR, "stc gbr, rn", 0000nnnn00010010, 2, 0)
|
||||
SH4_INSTR(STCVBR, "stc vbr, rn", 0000nnnn00100010, 2, 0)
|
||||
SH4_INSTR(STCSSR, "stc ssr, rn", 0000nnnn00110010, 2, 0)
|
||||
SH4_INSTR(STCSPC, "stc spc, rn", 0000nnnn01000010, 2, 0)
|
||||
SH4_INSTR(STCSGR, "stc sgr, rn", 0000nnnn00111010, 3, 0)
|
||||
SH4_INSTR(STCDBR, "stc dbr, rn", 0000nnnn11111010, 2, 0)
|
||||
SH4_INSTR(STCRBANK, "stc rm_bank, rn", 0000nnnn1mmm0010, 2, 0)
|
||||
SH4_INSTR(STCMSR, "stc.l sr, @-rn", 0100nnnn00000011, 2, SH4_FLAG_STORE)
|
||||
SH4_INSTR(STCMGBR, "stc.l gbr, @-rn", 0100nnnn00010011, 2, SH4_FLAG_STORE)
|
||||
SH4_INSTR(STCMVBR, "stc.l vbr, @-rn", 0100nnnn00100011, 2, SH4_FLAG_STORE)
|
||||
SH4_INSTR(STCMSSR, "stc.l ssr, @-rn", 0100nnnn00110011, 2, SH4_FLAG_STORE)
|
||||
SH4_INSTR(STCMSPC, "stc.l spc, @-rn", 0100nnnn01000011, 2, SH4_FLAG_STORE)
|
||||
SH4_INSTR(STCMSGR, "stc.l sgr, @-rn", 0100nnnn00110010, 3, SH4_FLAG_STORE)
|
||||
SH4_INSTR(STCMDBR, "stc.l dbr, @-rn", 0100nnnn11110010, 2, SH4_FLAG_STORE)
|
||||
SH4_INSTR(STCMRBANK, "stc.l rm_bank, @-rn", 0100nnnn1mmm0011, 2, SH4_FLAG_STORE)
|
||||
SH4_INSTR(STSMACH, "sts mach, rn", 0000nnnn00001010, 1, 0)
|
||||
SH4_INSTR(STSMACL, "sts macl, rn", 0000nnnn00011010, 1, 0)
|
||||
SH4_INSTR(STSPR, "sts pr, rn", 0000nnnn00101010, 2, 0)
|
||||
SH4_INSTR(STSMMACH, "sts.l mach, @-rn", 0100nnnn00000010, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(STSMMACL, "sts.l macl, @-rn", 0100nnnn00010010, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(STSMPR, "sts.l pr, @-rn", 0100nnnn00100010, 2, SH4_FLAG_STORE)
|
||||
SH4_INSTR(TRAPA, "trapa #imm8", 11000011iiiiiiii, 7, SH4_FLAG_BRANCH)
|
||||
SH4_INSTR(CLRMAC, "clrmac", 0000000000101000, 1, 0)
|
||||
SH4_INSTR(CLRS, "clrs", 0000000001001000, 1, 0)
|
||||
SH4_INSTR(CLRT, "clrt", 0000000000001000, 1, 0)
|
||||
SH4_INSTR(LDCSR, "ldc rn, sr", 0100mmmm00001110, 4, SH4_FLAG_SET_SR)
|
||||
SH4_INSTR(LDCGBR, "ldc rn, gbr", 0100mmmm00011110, 3, 0)
|
||||
SH4_INSTR(LDCVBR, "ldc rn, vbr", 0100mmmm00101110, 1, 0)
|
||||
SH4_INSTR(LDCSSR, "ldc rn, ssr", 0100mmmm00111110, 1, 0)
|
||||
SH4_INSTR(LDCSPC, "ldc rn, spc", 0100mmmm01001110, 1, 0)
|
||||
SH4_INSTR(LDCDBR, "ldc rn, dbr", 0100mmmm11111010, 1, 0)
|
||||
SH4_INSTR(LDCRBANK, "ldc.l rn, rn_bank", 0100mmmm1nnn1110, 1, 0)
|
||||
SH4_INSTR(LDCMSR, "ldc.l @rn+, sr", 0100mmmm00000111, 4, SH4_FLAG_LOAD | SH4_FLAG_SET_SR)
|
||||
SH4_INSTR(LDCMGBR, "ldc.l @rn+, gbr", 0100mmmm00010111, 3, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(LDCMVBR, "ldc.l @rn+, vbr", 0100mmmm00100111, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(LDCMSSR, "ldc.l @rn+, ssr", 0100mmmm00110111, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(LDCMSPC, "ldc.l @rn+, spc", 0100mmmm01000111, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(LDCMDBR, "ldc.l @rn+, dbr", 0100mmmm11110110, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(LDCMRBANK, "ldc.l @rn+, rm_bank", 0100mmmm1nnn0111, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(LDSMACH, "lds rn, mach", 0100mmmm00001010, 1, 0)
|
||||
SH4_INSTR(LDSMACL, "lds rn, macl", 0100mmmm00011010, 1, 0)
|
||||
SH4_INSTR(LDSPR, "lds rn, pr", 0100mmmm00101010, 2, 0)
|
||||
SH4_INSTR(LDSMMACH, "lds.l @rn+, mach", 0100mmmm00000110, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(LDSMMACL, "lds.l @rn+, macl", 0100mmmm00010110, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(LDSMPR, "lds.l @rn+, pr", 0100mmmm00100110, 2, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(MOVCAL, "movca.l r0, @rn", 0000nnnn11000011, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(NOP, "nop", 0000000000001001, 1, 0)
|
||||
SH4_INSTR(OCBI, "ocbi", 0000nnnn10010011, 1, 0)
|
||||
SH4_INSTR(OCBP, "ocbp", 0000nnnn10100011, 1, 0)
|
||||
SH4_INSTR(OCBWB, "ocbwb", 0000nnnn10110011, 1, 0)
|
||||
SH4_INSTR(PREF, "pref @rn", 0000nnnn10000011, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(RTE, "rte", 0000000000101011, 5, SH4_FLAG_BRANCH | SH4_FLAG_DELAYED | SH4_FLAG_SET_SR)
|
||||
SH4_INSTR(SETS, "sets", 0000000001011000, 1, 0)
|
||||
SH4_INSTR(SETT, "sett", 0000000000011000, 1, 0)
|
||||
SH4_INSTR(SLEEP, "sleep", 0000000000011011, 4, 0)
|
||||
SH4_INSTR(STCSR, "stc sr, rn", 0000nnnn00000010, 2, 0)
|
||||
SH4_INSTR(STCGBR, "stc gbr, rn", 0000nnnn00010010, 2, 0)
|
||||
SH4_INSTR(STCVBR, "stc vbr, rn", 0000nnnn00100010, 2, 0)
|
||||
SH4_INSTR(STCSSR, "stc ssr, rn", 0000nnnn00110010, 2, 0)
|
||||
SH4_INSTR(STCSPC, "stc spc, rn", 0000nnnn01000010, 2, 0)
|
||||
SH4_INSTR(STCSGR, "stc sgr, rn", 0000nnnn00111010, 3, 0)
|
||||
SH4_INSTR(STCDBR, "stc dbr, rn", 0000nnnn11111010, 2, 0)
|
||||
SH4_INSTR(STCRBANK, "stc rm_bank, rn", 0000nnnn1mmm0010, 2, 0)
|
||||
SH4_INSTR(STCMSR, "stc.l sr, @-rn", 0100nnnn00000011, 2, SH4_FLAG_STORE)
|
||||
SH4_INSTR(STCMGBR, "stc.l gbr, @-rn", 0100nnnn00010011, 2, SH4_FLAG_STORE)
|
||||
SH4_INSTR(STCMVBR, "stc.l vbr, @-rn", 0100nnnn00100011, 2, SH4_FLAG_STORE)
|
||||
SH4_INSTR(STCMSSR, "stc.l ssr, @-rn", 0100nnnn00110011, 2, SH4_FLAG_STORE)
|
||||
SH4_INSTR(STCMSPC, "stc.l spc, @-rn", 0100nnnn01000011, 2, SH4_FLAG_STORE)
|
||||
SH4_INSTR(STCMSGR, "stc.l sgr, @-rn", 0100nnnn00110010, 3, SH4_FLAG_STORE)
|
||||
SH4_INSTR(STCMDBR, "stc.l dbr, @-rn", 0100nnnn11110010, 2, SH4_FLAG_STORE)
|
||||
SH4_INSTR(STCMRBANK, "stc.l rm_bank, @-rn", 0100nnnn1mmm0011, 2, SH4_FLAG_STORE)
|
||||
SH4_INSTR(STSMACH, "sts mach, rn", 0000nnnn00001010, 1, 0)
|
||||
SH4_INSTR(STSMACL, "sts macl, rn", 0000nnnn00011010, 1, 0)
|
||||
SH4_INSTR(STSPR, "sts pr, rn", 0000nnnn00101010, 2, 0)
|
||||
SH4_INSTR(STSMMACH, "sts.l mach, @-rn", 0100nnnn00000010, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(STSMMACL, "sts.l macl, @-rn", 0100nnnn00010010, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(STSMPR, "sts.l pr, @-rn", 0100nnnn00100010, 2, SH4_FLAG_STORE)
|
||||
SH4_INSTR(TRAPA, "trapa #imm8", 11000011iiiiiiii, 7, SH4_FLAG_BRANCH)
|
||||
|
||||
|
||||
// floating-point single and double precision instructions
|
||||
SH4_INSTR(FLDI0, "fldi0 frn", 1111nnnn10001101, 1, 0)
|
||||
SH4_INSTR(FLDI1, "fldi1 frn", 1111nnnn10011101, 1, 0)
|
||||
SH4_INSTR(FMOV, "fmov frm, frn", 1111nnnnmmmm1100, 1, 0)
|
||||
SH4_INSTR(FMOV_LOAD, "fmov.s @(rm), frn", 1111nnnnmmmm1000, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(FMOV_INDEX_LOAD, "fmov.s @(r0,rm), frn", 1111nnnnmmmm0110, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(FMOV_STORE, "fmov.s frm, @rn", 1111nnnnmmmm1010, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(FMOV_INDEX_STORE, "fmov.s frm, @(r0,rn)", 1111nnnnmmmm0111, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(FMOV_SAVE, "fmov.s frm, @-rn", 1111nnnnmmmm1011, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(FMOV_RESTORE, "fmov.s @rm+, frn", 1111nnnnmmmm1001, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(FLDS, "flds frm, fpul", 1111mmmm00011101, 1, 0)
|
||||
SH4_INSTR(FSTS, "fsts fpul, frn", 1111nnnn00001101, 1, 0)
|
||||
SH4_INSTR(FABS, "fabs frn", 1111nnnn01011101, 1, 0)
|
||||
SH4_INSTR(FSRRA, "fsrra frn", 1111nnnn01111101, 1, 0)
|
||||
SH4_INSTR(FADD, "fadd frm, frn", 1111nnnnmmmm0000, 1, 0)
|
||||
SH4_INSTR(FCMPEQ, "fcmp/eq frm, frn", 1111nnnnmmmm0100, 2, 0)
|
||||
SH4_INSTR(FCMPGT, "fcmp/gt frm, frn", 1111nnnnmmmm0101, 2, 0)
|
||||
SH4_INSTR(FDIV, "fdiv frm, frn", 1111nnnnmmmm0011, 1, 0)
|
||||
SH4_INSTR(FLOAT, "float fpul, frn", 1111nnnn00101101, 1, 0)
|
||||
SH4_INSTR(FMAC, "fmac fr0, frm, frn", 1111nnnnmmmm1110, 1, 0)
|
||||
SH4_INSTR(FMUL, "fmul frm, frn", 1111nnnnmmmm0010, 1, 0)
|
||||
SH4_INSTR(FNEG, "fneg frn", 1111nnnn01001101, 1, 0)
|
||||
SH4_INSTR(FSQRT, "fsqrt frn", 1111nnnn01101101, 1, 0)
|
||||
SH4_INSTR(FSUB, "fsub frm, frn", 1111nnnnmmmm0001, 1, 0)
|
||||
SH4_INSTR(FTRC, "ftrc frm, fpul", 1111mmmm00111101, 1, 0)
|
||||
SH4_INSTR(FLDI0, "fldi0 frn", 1111nnnn10001101, 1, 0)
|
||||
SH4_INSTR(FLDI1, "fldi1 frn", 1111nnnn10011101, 1, 0)
|
||||
SH4_INSTR(FMOV, "fmov frm, frn", 1111nnnnmmmm1100, 1, 0)
|
||||
SH4_INSTR(FMOV_LOAD, "fmov.s @(rm), frn", 1111nnnnmmmm1000, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(FMOV_INDEX_LOAD, "fmov.s @(r0,rm), frn", 1111nnnnmmmm0110, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(FMOV_STORE, "fmov.s frm, @rn", 1111nnnnmmmm1010, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(FMOV_INDEX_STORE, "fmov.s frm, @(r0,rn)", 1111nnnnmmmm0111, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(FMOV_SAVE, "fmov.s frm, @-rn", 1111nnnnmmmm1011, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(FMOV_RESTORE, "fmov.s @rm+, frn", 1111nnnnmmmm1001, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(FLDS, "flds frn, fpul", 1111mmmm00011101, 1, 0)
|
||||
SH4_INSTR(FSTS, "fsts fpul, frn", 1111nnnn00001101, 1, 0)
|
||||
SH4_INSTR(FABS, "fabs frn", 1111nnnn01011101, 1, 0)
|
||||
SH4_INSTR(FSRRA, "fsrra frn", 1111nnnn01111101, 1, 0)
|
||||
SH4_INSTR(FADD, "fadd frm, frn", 1111nnnnmmmm0000, 1, 0)
|
||||
SH4_INSTR(FCMPEQ, "fcmp/eq frm, frn", 1111nnnnmmmm0100, 2, 0)
|
||||
SH4_INSTR(FCMPGT, "fcmp/gt frm, frn", 1111nnnnmmmm0101, 2, 0)
|
||||
SH4_INSTR(FDIV, "fdiv frm, frn", 1111nnnnmmmm0011, 1, 0)
|
||||
SH4_INSTR(FLOAT, "float fpul, frn", 1111nnnn00101101, 1, 0)
|
||||
SH4_INSTR(FMAC, "fmac fr0, frm, frn", 1111nnnnmmmm1110, 1, 0)
|
||||
SH4_INSTR(FMUL, "fmul frm, frn", 1111nnnnmmmm0010, 1, 0)
|
||||
SH4_INSTR(FNEG, "fneg frn", 1111nnnn01001101, 1, 0)
|
||||
SH4_INSTR(FSQRT, "fsqrt frn", 1111nnnn01101101, 1, 0)
|
||||
SH4_INSTR(FSUB, "fsub frm, frn", 1111nnnnmmmm0001, 1, 0)
|
||||
SH4_INSTR(FTRC, "ftrc frn, fpul", 1111mmmm00111101, 1, 0)
|
||||
|
||||
|
||||
// floating-point double precision instructions,
|
||||
// some merged with single precision instructions
|
||||
SH4_INSTR(FCNVDS, "fcnvds drm, fpul", 1111mmmm10111101, 1, 0)
|
||||
SH4_INSTR(FCNVSD, "fcnvsd fpul, drn", 1111nnnn10101101, 1, 0)
|
||||
SH4_INSTR(FCNVDS, "fcnvds drn, fpul", 1111mmmm10111101, 1, 0)
|
||||
SH4_INSTR(FCNVSD, "fcnvsd fpul, drn", 1111nnnn10101101, 1, 0)
|
||||
|
||||
|
||||
// floating-point control instructions
|
||||
SH4_INSTR(LDSFPSCR, "lds rm, fpscr", 0100mmmm01101010, 1, SH4_FLAG_SET_FPSCR)
|
||||
SH4_INSTR(LDSFPUL, "lds rm, fpul", 0100mmmm01011010, 1, 0)
|
||||
SH4_INSTR(LDSMFPSCR, "lds.l @rm+, fpscr", 0100mmmm01100110, 1, SH4_FLAG_LOAD | SH4_FLAG_SET_FPSCR)
|
||||
SH4_INSTR(LDSMFPUL, "lds.l @rm+, fpul", 0100mmmm01010110, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(STSFPSCR, "sts fpscr, rn", 0000nnnn01101010, 1, 0)
|
||||
SH4_INSTR(STSFPUL, "sts fpul, rn", 0000nnnn01011010, 1, 0)
|
||||
SH4_INSTR(STSMFPSCR, "sts.l fpscr, @-rn", 0100nnnn01100010, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(STSMFPUL, "sts.l fpul, @-rn", 0100nnnn01010010, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(LDSFPSCR, "lds rn, fpscr", 0100mmmm01101010, 1, SH4_FLAG_SET_FPSCR)
|
||||
SH4_INSTR(LDSFPUL, "lds rn, fpul", 0100mmmm01011010, 1, 0)
|
||||
SH4_INSTR(LDSMFPSCR, "lds.l @rn+, fpscr", 0100mmmm01100110, 1, SH4_FLAG_LOAD | SH4_FLAG_SET_FPSCR)
|
||||
SH4_INSTR(LDSMFPUL, "lds.l @rn+, fpul", 0100mmmm01010110, 1, SH4_FLAG_LOAD)
|
||||
SH4_INSTR(STSFPSCR, "sts fpscr, rn", 0000nnnn01101010, 1, 0)
|
||||
SH4_INSTR(STSFPUL, "sts fpul, rn", 0000nnnn01011010, 1, 0)
|
||||
SH4_INSTR(STSMFPSCR, "sts.l fpscr, @-rn", 0100nnnn01100010, 1, SH4_FLAG_STORE)
|
||||
SH4_INSTR(STSMFPUL, "sts.l fpul, @-rn", 0100nnnn01010010, 1, SH4_FLAG_STORE)
|
||||
|
||||
|
||||
// floating-point graphics acceleration instructions,
|
||||
// some merged with single precision instructions
|
||||
SH4_INSTR(FIPR, "fipr fvm, fvn", 1111nnmm11101101, 1, 0)
|
||||
SH4_INSTR(FSCA, "fsca fpul, drn", 1111nnn011111101, 1, 0)
|
||||
SH4_INSTR(FTRV, "ftrv xmtrx, fvn", 1111nn0111111101, 1, 0)
|
||||
SH4_INSTR(FRCHG, "frchg", 1111101111111101, 1, SH4_FLAG_SET_FPSCR)
|
||||
SH4_INSTR(FSCHG, "fschg", 1111001111111101, 1, SH4_FLAG_SET_FPSCR)
|
||||
SH4_INSTR(FIPR, "fipr fvm, fvn", 1111nnmm11101101, 1, 0)
|
||||
SH4_INSTR(FSCA, "fsca fpul, drn", 1111nnn011111101, 1, 0)
|
||||
SH4_INSTR(FTRV, "ftrv xmtrx, fvn", 1111nn0111111101, 1, 0)
|
||||
SH4_INSTR(FRCHG, "frchg", 1111101111111101, 1, SH4_FLAG_SET_FPSCR)
|
||||
SH4_INSTR(FSCHG, "fschg", 1111001111111101, 1, SH4_FLAG_SET_FPSCR)
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,12 +1,18 @@
|
|||
#ifndef SH4_TRANSLATE_H
|
||||
#define SH4_TRANSLATE_H
|
||||
|
||||
#include "jit/frontend/sh4/sh4_disasm.h"
|
||||
|
||||
struct ir;
|
||||
struct sh4_guest;
|
||||
struct sh4_instr;
|
||||
|
||||
void sh4_emit_instr(struct sh4_guest *guest, struct ir *ir, int flags,
|
||||
const struct sh4_instr *instr,
|
||||
const struct sh4_instr *delay);
|
||||
typedef void (*sh4_translate_cb)(struct sh4_guest *, struct ir *, int, uint32_t,
|
||||
union sh4_instr);
|
||||
|
||||
extern sh4_translate_cb sh4_translators[NUM_SH4_OPS];
|
||||
|
||||
static inline sh4_translate_cb sh4_get_translator(uint16_t instr) {
|
||||
return sh4_translators[sh4_op(instr)];
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -981,6 +981,10 @@ void ir_call_cond_2(struct ir *ir, struct ir_value *cond, struct ir_value *fn,
|
|||
ir_set_arg3(ir, instr, arg1);
|
||||
}
|
||||
|
||||
void ir_flush_context(struct ir *ir) {
|
||||
ir_append_instr(ir, OP_FLUSH_CONTEXT, VALUE_V);
|
||||
}
|
||||
|
||||
void ir_debug_info(struct ir *ir, const char *desc, uint32_t addr,
|
||||
uint32_t raw_instr) {
|
||||
struct ir_instr *instr = ir_append_instr(ir, OP_DEBUG_INFO, VALUE_V);
|
||||
|
|
|
|||
|
|
@ -405,6 +405,8 @@ void ir_call_cond_1(struct ir *ir, struct ir_value *fn, struct ir_value *arg0,
|
|||
void ir_call_cond_2(struct ir *ir, struct ir_value *fn, struct ir_value *arg0,
|
||||
struct ir_value *arg1, struct ir_value *cond);
|
||||
|
||||
void ir_flush_context(struct ir *ir);
|
||||
|
||||
/* debug */
|
||||
void ir_debug_info(struct ir *ir, const char *desc, uint32_t addr,
|
||||
uint32_t instr);
|
||||
|
|
|
|||
|
|
@ -51,6 +51,7 @@ IR_OP(BRANCH_FALSE)
|
|||
IR_OP(BRANCH_TRUE)
|
||||
IR_OP(CALL)
|
||||
IR_OP(CALL_COND)
|
||||
IR_OP(FLUSH_CONTEXT)
|
||||
IR_OP(DEBUG_INFO)
|
||||
IR_OP(DEBUG_BREAK)
|
||||
IR_OP(ASSERT_LT)
|
||||
|
|
|
|||
|
|
@ -133,7 +133,7 @@ static void lse_set_available(struct lse *lse, int offset, struct ir_value *v) {
|
|||
static void lse_eliminate_loads_r(struct lse *lse, struct ir *ir,
|
||||
struct ir_block *block) {
|
||||
list_for_each_entry_safe(instr, &block->instrs, struct ir_instr, it) {
|
||||
if (instr->op == OP_FALLBACK) {
|
||||
if (instr->op == OP_FALLBACK || instr->op == OP_FLUSH_CONTEXT) {
|
||||
lse_clear_available(lse);
|
||||
} else if (instr->op == OP_BRANCH) {
|
||||
if (instr->arg[0]->type != VALUE_BLOCK) {
|
||||
|
|
@ -215,7 +215,7 @@ static void lse_eliminate_stores_r(struct lse *lse, struct ir *ir,
|
|||
}
|
||||
|
||||
list_for_each_entry_safe_reverse(instr, &block->instrs, struct ir_instr, it) {
|
||||
if (instr->op == OP_FALLBACK) {
|
||||
if (instr->op == OP_FALLBACK || instr->op == OP_FLUSH_CONTEXT) {
|
||||
lse_clear_available(lse);
|
||||
} else if (instr->op == OP_BRANCH) {
|
||||
if (instr->arg[0]->type != VALUE_BLOCK) {
|
||||
|
|
|
|||
|
|
@ -19,7 +19,6 @@ test_ldcl_stcl_sr:
|
|||
# r0 in alt bank should have been post-incremented by 4
|
||||
mov.l .ALT_SR, r1
|
||||
stc r0_bank, r4
|
||||
sub r1, r4
|
||||
# r1 in alt bank should have been pre-decremented by 4
|
||||
mov.l .DATA_ADDR, r1
|
||||
stc r1_bank, r5
|
||||
|
|
|
|||
|
|
@ -112,13 +112,13 @@ TEST_SH4(test_ldc_stc_sr,(uint8_t *)"\x0d\xe2\x1b\xd0\x0e\x40\x63\xe2\x02\x01\x1
|
|||
TEST_SH4(test_ldc_stc_rbank,(uint8_t *)"\x0d\xe2\x1b\xd0\x0e\x40\x63\xe2\x02\x01\x15\xd0\x12\x20\x1c\xd0\x0e\x40\x13\xd0\x02\x63\x0b\x00\x09\x00\x9e\x40\x63\xe1\x92\x01\x0b\x00\x09\x00\x1e\x40\x12\x01\x0b\x00\x09\x00\x2e\x40\x22\x01\x0b\x00\x09\x00\x3e\x40\x32\x01\x0b\x00\x09\x00\x4e\x40\x42\x01\x0b\x00\x09\x00\xfa\x40\xfa\x01\x0b\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x50\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x50\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x70\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00",144,0x1a,0xbaadf00d,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d)
|
||||
TEST_SH4(test_ldc_stc_ssr,(uint8_t *)"\x0d\xe2\x1b\xd0\x0e\x40\x63\xe2\x02\x01\x15\xd0\x12\x20\x1c\xd0\x0e\x40\x13\xd0\x02\x63\x0b\x00\x09\x00\x9e\x40\x63\xe1\x92\x01\x0b\x00\x09\x00\x1e\x40\x12\x01\x0b\x00\x09\x00\x2e\x40\x22\x01\x0b\x00\x09\x00\x3e\x40\x32\x01\x0b\x00\x09\x00\x4e\x40\x42\x01\x0b\x00\x09\x00\xfa\x40\xfa\x01\x0b\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x50\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x50\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x70\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00",144,0x34,0xbaadf00d,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d)
|
||||
TEST_SH4(test_ldc_stc_dbr,(uint8_t *)"\x0d\xe2\x1b\xd0\x0e\x40\x63\xe2\x02\x01\x15\xd0\x12\x20\x1c\xd0\x0e\x40\x13\xd0\x02\x63\x0b\x00\x09\x00\x9e\x40\x63\xe1\x92\x01\x0b\x00\x09\x00\x1e\x40\x12\x01\x0b\x00\x09\x00\x2e\x40\x22\x01\x0b\x00\x09\x00\x3e\x40\x32\x01\x0b\x00\x09\x00\x4e\x40\x42\x01\x0b\x00\x09\x00\xfa\x40\xfa\x01\x0b\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x50\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x50\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x70\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00",144,0x44,0xbaadf00d,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d)
|
||||
TEST_SH4(test_ldcl_stcl_spc,(uint8_t *)"\x0d\xe2\x33\xd0\x07\x40\x63\xe2\x2d\xd1\x04\x71\x03\x41\x34\xd3\x07\x43\x2b\xd0\x02\x63\x2e\xd1\x82\x04\x18\x34\x28\xd1\x92\x05\x18\x35\x0b\x00\x09\x00\x26\xd1\x02\x21\xb7\x41\x63\xe3\x24\xd2\x08\x72\xb3\x42\x10\x32\x29\x04\x22\x65\x0b\x00\x09\x00\x20\xd1\x02\x21\x1f\xd2\x08\x72\x17\x41\x13\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x1a\xd1\x02\x21\x19\xd2\x08\x72\x27\x41\x23\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x15\xd1\x02\x21\x14\xd2\x08\x72\x37\x41\x33\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x0f\xd1\x02\x21\x0e\xd2\x08\x72\x47\x41\x43\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x0a\xd1\x02\x21\x09\xd2\x08\x72\xf6\x41\xf2\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x50\xf0\x00\x00\x70\x00\x00\x00\x00\x00\x00\x00\x00\xb8\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb0\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb4\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00",240,0x80,0xbaadf00d,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0x1,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d)
|
||||
TEST_SH4(test_ldcl_stcl_sr,(uint8_t *)"\x0d\xe2\x33\xd0\x07\x40\x63\xe2\x2d\xd1\x04\x71\x03\x41\x34\xd3\x07\x43\x2b\xd0\x02\x63\x2e\xd1\x82\x04\x18\x34\x28\xd1\x92\x05\x18\x35\x0b\x00\x09\x00\x26\xd1\x02\x21\xb7\x41\x63\xe3\x24\xd2\x08\x72\xb3\x42\x10\x32\x29\x04\x22\x65\x0b\x00\x09\x00\x20\xd1\x02\x21\x1f\xd2\x08\x72\x17\x41\x13\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x1a\xd1\x02\x21\x19\xd2\x08\x72\x27\x41\x23\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x15\xd1\x02\x21\x14\xd2\x08\x72\x37\x41\x33\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x0f\xd1\x02\x21\x0e\xd2\x08\x72\x47\x41\x43\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x0a\xd1\x02\x21\x09\xd2\x08\x72\xf6\x41\xf2\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x50\xf0\x00\x00\x70\x00\x00\x00\x00\x00\x00\x00\x00\xb8\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb0\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb4\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00",240,0x0,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xd,0x500000f0,0x4,0x0,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d)
|
||||
TEST_SH4(test_ldcl_stcl_rbank,(uint8_t *)"\x0d\xe2\x33\xd0\x07\x40\x63\xe2\x2d\xd1\x04\x71\x03\x41\x34\xd3\x07\x43\x2b\xd0\x02\x63\x2e\xd1\x82\x04\x18\x34\x28\xd1\x92\x05\x18\x35\x0b\x00\x09\x00\x26\xd1\x02\x21\xb7\x41\x63\xe3\x24\xd2\x08\x72\xb3\x42\x10\x32\x29\x04\x22\x65\x0b\x00\x09\x00\x20\xd1\x02\x21\x1f\xd2\x08\x72\x17\x41\x13\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x1a\xd1\x02\x21\x19\xd2\x08\x72\x27\x41\x23\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x15\xd1\x02\x21\x14\xd2\x08\x72\x37\x41\x33\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x0f\xd1\x02\x21\x0e\xd2\x08\x72\x47\x41\x43\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x0a\xd1\x02\x21\x09\xd2\x08\x72\xf6\x41\xf2\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x50\xf0\x00\x00\x70\x00\x00\x00\x00\x00\x00\x00\x00\xb8\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb0\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb4\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00",240,0x26,0xbaadf00d,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0x1,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d)
|
||||
TEST_SH4(test_ldcl_stcl_vbr,(uint8_t *)"\x0d\xe2\x33\xd0\x07\x40\x63\xe2\x2d\xd1\x04\x71\x03\x41\x34\xd3\x07\x43\x2b\xd0\x02\x63\x2e\xd1\x82\x04\x18\x34\x28\xd1\x92\x05\x18\x35\x0b\x00\x09\x00\x26\xd1\x02\x21\xb7\x41\x63\xe3\x24\xd2\x08\x72\xb3\x42\x10\x32\x29\x04\x22\x65\x0b\x00\x09\x00\x20\xd1\x02\x21\x1f\xd2\x08\x72\x17\x41\x13\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x1a\xd1\x02\x21\x19\xd2\x08\x72\x27\x41\x23\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x15\xd1\x02\x21\x14\xd2\x08\x72\x37\x41\x33\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x0f\xd1\x02\x21\x0e\xd2\x08\x72\x47\x41\x43\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x0a\xd1\x02\x21\x09\xd2\x08\x72\xf6\x41\xf2\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x50\xf0\x00\x00\x70\x00\x00\x00\x00\x00\x00\x00\x00\xb8\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb0\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb4\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00",240,0x54,0xbaadf00d,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0x1,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d)
|
||||
TEST_SH4(test_ldcl_stcl_gbr,(uint8_t *)"\x0d\xe2\x33\xd0\x07\x40\x63\xe2\x2d\xd1\x04\x71\x03\x41\x34\xd3\x07\x43\x2b\xd0\x02\x63\x2e\xd1\x82\x04\x18\x34\x28\xd1\x92\x05\x18\x35\x0b\x00\x09\x00\x26\xd1\x02\x21\xb7\x41\x63\xe3\x24\xd2\x08\x72\xb3\x42\x10\x32\x29\x04\x22\x65\x0b\x00\x09\x00\x20\xd1\x02\x21\x1f\xd2\x08\x72\x17\x41\x13\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x1a\xd1\x02\x21\x19\xd2\x08\x72\x27\x41\x23\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x15\xd1\x02\x21\x14\xd2\x08\x72\x37\x41\x33\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x0f\xd1\x02\x21\x0e\xd2\x08\x72\x47\x41\x43\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x0a\xd1\x02\x21\x09\xd2\x08\x72\xf6\x41\xf2\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x50\xf0\x00\x00\x70\x00\x00\x00\x00\x00\x00\x00\x00\xb8\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb0\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb4\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00",240,0x3e,0xbaadf00d,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0x1,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d)
|
||||
TEST_SH4(test_ldcl_stcl_ssr,(uint8_t *)"\x0d\xe2\x33\xd0\x07\x40\x63\xe2\x2d\xd1\x04\x71\x03\x41\x34\xd3\x07\x43\x2b\xd0\x02\x63\x2e\xd1\x82\x04\x18\x34\x28\xd1\x92\x05\x18\x35\x0b\x00\x09\x00\x26\xd1\x02\x21\xb7\x41\x63\xe3\x24\xd2\x08\x72\xb3\x42\x10\x32\x29\x04\x22\x65\x0b\x00\x09\x00\x20\xd1\x02\x21\x1f\xd2\x08\x72\x17\x41\x13\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x1a\xd1\x02\x21\x19\xd2\x08\x72\x27\x41\x23\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x15\xd1\x02\x21\x14\xd2\x08\x72\x37\x41\x33\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x0f\xd1\x02\x21\x0e\xd2\x08\x72\x47\x41\x43\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x0a\xd1\x02\x21\x09\xd2\x08\x72\xf6\x41\xf2\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x50\xf0\x00\x00\x70\x00\x00\x00\x00\x00\x00\x00\x00\xb8\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb0\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb4\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00",240,0x6a,0xbaadf00d,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0x1,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d)
|
||||
TEST_SH4(test_ldcl_stcl_dbr,(uint8_t *)"\x0d\xe2\x33\xd0\x07\x40\x63\xe2\x2d\xd1\x04\x71\x03\x41\x34\xd3\x07\x43\x2b\xd0\x02\x63\x2e\xd1\x82\x04\x18\x34\x28\xd1\x92\x05\x18\x35\x0b\x00\x09\x00\x26\xd1\x02\x21\xb7\x41\x63\xe3\x24\xd2\x08\x72\xb3\x42\x10\x32\x29\x04\x22\x65\x0b\x00\x09\x00\x20\xd1\x02\x21\x1f\xd2\x08\x72\x17\x41\x13\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x1a\xd1\x02\x21\x19\xd2\x08\x72\x27\x41\x23\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x15\xd1\x02\x21\x14\xd2\x08\x72\x37\x41\x33\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x0f\xd1\x02\x21\x0e\xd2\x08\x72\x47\x41\x43\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x0a\xd1\x02\x21\x09\xd2\x08\x72\xf6\x41\xf2\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x50\xf0\x00\x00\x70\x00\x00\x00\x00\x00\x00\x00\x00\xb8\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb0\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb4\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00",240,0x96,0xbaadf00d,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0x1,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d)
|
||||
TEST_SH4(test_ldcl_stcl_spc,(uint8_t *)"\x0d\xe2\x33\xd0\x07\x40\x63\xe2\x2d\xd1\x04\x71\x03\x41\x34\xd3\x07\x43\x2b\xd0\x02\x63\x2e\xd1\x82\x04\x29\xd1\x92\x05\x18\x35\x0b\x00\x09\x00\x26\xd1\x02\x21\xb7\x41\x63\xe3\x24\xd2\x08\x72\xb3\x42\x10\x32\x29\x04\x22\x65\x0b\x00\x09\x00\x20\xd1\x02\x21\x1f\xd2\x08\x72\x17\x41\x13\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x1b\xd1\x02\x21\x1a\xd2\x08\x72\x27\x41\x23\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x15\xd1\x02\x21\x14\xd2\x08\x72\x37\x41\x33\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x10\xd1\x02\x21\x0f\xd2\x08\x72\x47\x41\x43\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x0a\xd1\x02\x21\x09\xd2\x08\x72\xf6\x41\xf2\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x50\xf0\x00\x00\x70\x00\x00\x00\x00\x00\x00\x00\x00\xb8\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb0\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb4\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00",240,0x7e,0xbaadf00d,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0x1,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d)
|
||||
TEST_SH4(test_ldcl_stcl_sr,(uint8_t *)"\x0d\xe2\x33\xd0\x07\x40\x63\xe2\x2d\xd1\x04\x71\x03\x41\x34\xd3\x07\x43\x2b\xd0\x02\x63\x2e\xd1\x82\x04\x29\xd1\x92\x05\x18\x35\x0b\x00\x09\x00\x26\xd1\x02\x21\xb7\x41\x63\xe3\x24\xd2\x08\x72\xb3\x42\x10\x32\x29\x04\x22\x65\x0b\x00\x09\x00\x20\xd1\x02\x21\x1f\xd2\x08\x72\x17\x41\x13\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x1b\xd1\x02\x21\x1a\xd2\x08\x72\x27\x41\x23\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x15\xd1\x02\x21\x14\xd2\x08\x72\x37\x41\x33\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x10\xd1\x02\x21\x0f\xd2\x08\x72\x47\x41\x43\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x0a\xd1\x02\x21\x09\xd2\x08\x72\xf6\x41\xf2\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x50\xf0\x00\x00\x70\x00\x00\x00\x00\x00\x00\x00\x00\xb8\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb0\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb4\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00",240,0x0,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xd,0x500000f0,0x4,0x0,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d)
|
||||
TEST_SH4(test_ldcl_stcl_rbank,(uint8_t *)"\x0d\xe2\x33\xd0\x07\x40\x63\xe2\x2d\xd1\x04\x71\x03\x41\x34\xd3\x07\x43\x2b\xd0\x02\x63\x2e\xd1\x82\x04\x29\xd1\x92\x05\x18\x35\x0b\x00\x09\x00\x26\xd1\x02\x21\xb7\x41\x63\xe3\x24\xd2\x08\x72\xb3\x42\x10\x32\x29\x04\x22\x65\x0b\x00\x09\x00\x20\xd1\x02\x21\x1f\xd2\x08\x72\x17\x41\x13\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x1b\xd1\x02\x21\x1a\xd2\x08\x72\x27\x41\x23\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x15\xd1\x02\x21\x14\xd2\x08\x72\x37\x41\x33\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x10\xd1\x02\x21\x0f\xd2\x08\x72\x47\x41\x43\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x0a\xd1\x02\x21\x09\xd2\x08\x72\xf6\x41\xf2\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x50\xf0\x00\x00\x70\x00\x00\x00\x00\x00\x00\x00\x00\xb8\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb0\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb4\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00",240,0x24,0xbaadf00d,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0x1,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d)
|
||||
TEST_SH4(test_ldcl_stcl_vbr,(uint8_t *)"\x0d\xe2\x33\xd0\x07\x40\x63\xe2\x2d\xd1\x04\x71\x03\x41\x34\xd3\x07\x43\x2b\xd0\x02\x63\x2e\xd1\x82\x04\x29\xd1\x92\x05\x18\x35\x0b\x00\x09\x00\x26\xd1\x02\x21\xb7\x41\x63\xe3\x24\xd2\x08\x72\xb3\x42\x10\x32\x29\x04\x22\x65\x0b\x00\x09\x00\x20\xd1\x02\x21\x1f\xd2\x08\x72\x17\x41\x13\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x1b\xd1\x02\x21\x1a\xd2\x08\x72\x27\x41\x23\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x15\xd1\x02\x21\x14\xd2\x08\x72\x37\x41\x33\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x10\xd1\x02\x21\x0f\xd2\x08\x72\x47\x41\x43\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x0a\xd1\x02\x21\x09\xd2\x08\x72\xf6\x41\xf2\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x50\xf0\x00\x00\x70\x00\x00\x00\x00\x00\x00\x00\x00\xb8\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb0\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb4\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00",240,0x52,0xbaadf00d,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0x1,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d)
|
||||
TEST_SH4(test_ldcl_stcl_gbr,(uint8_t *)"\x0d\xe2\x33\xd0\x07\x40\x63\xe2\x2d\xd1\x04\x71\x03\x41\x34\xd3\x07\x43\x2b\xd0\x02\x63\x2e\xd1\x82\x04\x29\xd1\x92\x05\x18\x35\x0b\x00\x09\x00\x26\xd1\x02\x21\xb7\x41\x63\xe3\x24\xd2\x08\x72\xb3\x42\x10\x32\x29\x04\x22\x65\x0b\x00\x09\x00\x20\xd1\x02\x21\x1f\xd2\x08\x72\x17\x41\x13\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x1b\xd1\x02\x21\x1a\xd2\x08\x72\x27\x41\x23\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x15\xd1\x02\x21\x14\xd2\x08\x72\x37\x41\x33\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x10\xd1\x02\x21\x0f\xd2\x08\x72\x47\x41\x43\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x0a\xd1\x02\x21\x09\xd2\x08\x72\xf6\x41\xf2\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x50\xf0\x00\x00\x70\x00\x00\x00\x00\x00\x00\x00\x00\xb8\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb0\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb4\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00",240,0x3c,0xbaadf00d,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0x1,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d)
|
||||
TEST_SH4(test_ldcl_stcl_ssr,(uint8_t *)"\x0d\xe2\x33\xd0\x07\x40\x63\xe2\x2d\xd1\x04\x71\x03\x41\x34\xd3\x07\x43\x2b\xd0\x02\x63\x2e\xd1\x82\x04\x29\xd1\x92\x05\x18\x35\x0b\x00\x09\x00\x26\xd1\x02\x21\xb7\x41\x63\xe3\x24\xd2\x08\x72\xb3\x42\x10\x32\x29\x04\x22\x65\x0b\x00\x09\x00\x20\xd1\x02\x21\x1f\xd2\x08\x72\x17\x41\x13\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x1b\xd1\x02\x21\x1a\xd2\x08\x72\x27\x41\x23\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x15\xd1\x02\x21\x14\xd2\x08\x72\x37\x41\x33\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x10\xd1\x02\x21\x0f\xd2\x08\x72\x47\x41\x43\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x0a\xd1\x02\x21\x09\xd2\x08\x72\xf6\x41\xf2\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x50\xf0\x00\x00\x70\x00\x00\x00\x00\x00\x00\x00\x00\xb8\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb0\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb4\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00",240,0x68,0xbaadf00d,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0x1,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d)
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TEST_SH4(test_ldcl_stcl_dbr,(uint8_t *)"\x0d\xe2\x33\xd0\x07\x40\x63\xe2\x2d\xd1\x04\x71\x03\x41\x34\xd3\x07\x43\x2b\xd0\x02\x63\x2e\xd1\x82\x04\x29\xd1\x92\x05\x18\x35\x0b\x00\x09\x00\x26\xd1\x02\x21\xb7\x41\x63\xe3\x24\xd2\x08\x72\xb3\x42\x10\x32\x29\x04\x22\x65\x0b\x00\x09\x00\x20\xd1\x02\x21\x1f\xd2\x08\x72\x17\x41\x13\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x1b\xd1\x02\x21\x1a\xd2\x08\x72\x27\x41\x23\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x15\xd1\x02\x21\x14\xd2\x08\x72\x37\x41\x33\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x10\xd1\x02\x21\x0f\xd2\x08\x72\x47\x41\x43\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x0a\xd1\x02\x21\x09\xd2\x08\x72\xf6\x41\xf2\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x50\xf0\x00\x00\x70\x00\x00\x00\x00\x00\x00\x00\x00\xb8\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb0\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb4\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00",240,0x94,0xbaadf00d,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0x1,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d)
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TEST_SH4(test_lds_sts_mach,(uint8_t *)"\x0a\x40\x0a\x01\x0b\x00\x09\x00\x1a\x40\x1a\x01\x0b\x00\x09\x00\x2a\x02\x2a\x40\x2a\x01\x2a\x42\x0b\x00\x09\x00\x6a\x40\x6a\x01\x0b\x00\x09\x00\x5a\x40\x5a\x01\x0b\x00\x09\x00",44,0x0,0xbaadf00d,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d)
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TEST_SH4(test_lds_sts_fpul,(uint8_t *)"\x0a\x40\x0a\x01\x0b\x00\x09\x00\x1a\x40\x1a\x01\x0b\x00\x09\x00\x2a\x02\x2a\x40\x2a\x01\x2a\x42\x0b\x00\x09\x00\x6a\x40\x6a\x01\x0b\x00\x09\x00\x5a\x40\x5a\x01\x0b\x00\x09\x00",44,0x24,0xbaadf00d,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d)
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TEST_SH4(test_lds_sts_macl,(uint8_t *)"\x0a\x40\x0a\x01\x0b\x00\x09\x00\x1a\x40\x1a\x01\x0b\x00\x09\x00\x2a\x02\x2a\x40\x2a\x01\x2a\x42\x0b\x00\x09\x00\x6a\x40\x6a\x01\x0b\x00\x09\x00\x5a\x40\x5a\x01\x0b\x00\x09\x00",44,0x8,0xbaadf00d,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xd,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d,0xbaadf00d)
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Loading…
Reference in New Issue