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replace beaengine with capstone

This commit is contained in:
Anthony Pesch 2016-04-13 20:22:29 -07:00
parent b4e944ed63
commit aaecac5902
631 changed files with 840320 additions and 30048 deletions
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17
CMakeLists.txt
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@ -64,12 +64,17 @@ add_subdirectory(deps/sdl2-2.0.4 EXCLUDE_FROM_ALL)
list(APPEND REDREAM_INCLUDE_DIRS deps/sdl2-2.0.4/include)
list(APPEND REDREAM_LIBS SDL2main SDL2-static)
# beaengine
add_library(beaengine STATIC deps/beaengine-4.1/beaengineSources/BeaEngine.c)
target_include_directories(beaengine PUBLIC deps/beaengine-4.1/include)
list(APPEND REDREAM_DEFS BEA_ENGINE_STATIC)
list(APPEND REDREAM_INCLUDE_DIRS deps/beaengine-4.1/include)
list(APPEND REDREAM_LIBS beaengine)
# capstone
add_subdirectory(deps/capstone EXCLUDE_FROM_ALL)
set(CAPSTONE_ARM_SUPPORT OFF CACHE BOOL "")
set(CAPSTONE_ARM64_SUPPORT OFF CACHE BOOL "")
set(CAPSTONE_MIPS_SUPPORT OFF CACHE BOOL "")
set(CAPSTONE_PPC_SUPPORT OFF CACHE BOOL "")
set(CAPSTONE_SPARC_SUPPORT OFF CACHE BOOL "")
set(CAPSTONE_SYSZ_SUPPORT OFF CACHE BOOL "")
set(CAPSTONE_XCORE_SUPPORT OFF CACHE BOOL "")
list(APPEND REDREAM_INCLUDE_DIRS deps/capstone/include)
list(APPEND REDREAM_LIBS capstone-static)
# dirent
list(APPEND REDREAM_INCLUDE_DIRS deps/dirent-1.21)

384
deps/beaengine-4.1/CMakeLists.txt vendored
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@ -1,384 +0,0 @@
project (BeaEngine)
cmake_minimum_required (VERSION 2.6)
set (CMAKE_MODULE_PATH "${CMAKE_SOURCE_DIR}/cmake")
#set (CMAKE_VERBOSE_MAKEFILE ON)
option (optHAS_OPTIMIZED "Turn Optimizations ON" OFF)
option (optHAS_SYMBOLS "Build with debug Symbols" ON)
option (optBUILD_64BIT "Build 64 bits executable" OFF)
option (optBUILD_DLL "Build Shared Objects" OFF)
option (optBUILD_STDCALL "Build using stdcall" OFF)
option (optBUILD_LITE "Build without text disassembly" OFF)
if (optHAS_OPTIMIZED)
if (optHAS_SYMBOLS)
set (CMAKE_BUILD_TYPE relwithdebinfo)
else (optHAS_SYMBOLS)
set (CMAKE_BUILD_TYPE release)
endif (optHAS_SYMBOLS)
else (optHAS_OPTIMIZED)
if (optHAS_SYMBOLS)
set (CMAKE_BUILD_TYPE Debug)
else (optHAS_SYMBOLS)
set (CMAKE_BUILD_TYPE Debug)
endif (optHAS_SYMBOLS)
endif (optHAS_OPTIMIZED)
# determine BEA_COMPILER
if (NOT BEA_COMPILER)
if (${CMAKE_SYSTEM_NAME} STREQUAL Linux)
if (WATCOM)
set (BEA_COMPILER watcom)
else ()
set (BEA_COMPILER gnu)
endif ()
endif ()
if (${CMAKE_SYSTEM_NAME} STREQUAL FreeBSD)
set (BEA_COMPILER gnu)
endif ()
if (${CMAKE_SYSTEM_NAME} STREQUAL SunOS)
set (BEA_COMPILER suncc)
endif ()
if (${CMAKE_SYSTEM_NAME} STREQUAL Windows)
if (MINGW OR MSYS)
set (BEA_COMPILER gnu)
else ()
if (CYGWIN)
set (BEA_COMPILER gnu)
else ()
if (BORLAND)
set (BEA_COMPILER borland)
else ()
if (MSVC)
set (BEA_COMPILER msvc)
else ()
if (WATCOM)
set (BEA_COMPILER watcom)
endif ()
endif ()
endif ()
endif ()
endif ()
endif ()
endif ()
# =========================================
# gcc configuration
# =========================================
if (BEA_COMPILER STREQUAL gnu)
set (CMAKE_C_COMPILER gcc)
set (CMAKE_CXX_COMPILER g++)
set (BEA_WARNINGS -Wall -W -Wextra -Wconversion -Wno-long-long
-Wshadow -Wpointer-arith -Wcast-qual -Wcast-align -Wwrite-strings)
set (BEA_FLAGS -pedantic -ansi -pipe -fno-common -fshort-enums )
set (BEA_DEFINITIONS "")
if (optHAS_SYMBOLS)
list (APPEND BEA_FLAGS -g)
endif ()
if (optHAS_OPTIMIZED)
list (APPEND BEA_FLAGS -fomit-frame-pointer -O2)
endif ()
if (optBUILD_64BIT)
list (APPEND BEA_FLAGS -m64)
endif ()
if (optBUILD_STDCALL)
list (APPEND BEA_DEFINITIONS "-DBEA_USE_STDCALL")
endif ()
if (optBUILD_LITE)
list (APPEND BEA_DEFINITIONS "-DBEA_LIGHT_DISASSEMBLY")
endif ()
endif ()
# =========================================
# SunStudio configuration
# =========================================
if (BEA_COMPILER STREQUAL suncc)
set (CMAKE_C_COMPILER cc)
set (CMAKE_CXX_COMPILER CC)
list (APPEND BEA_FLAGS "-xmemalign=ab")
endif ()
# =========================================
# Visual Studio configuration
# =========================================
if (BEA_COMPILER STREQUAL msvc)
set (CMAKE_C_COMPILER cl)
set (CMAKE_CXX_COMPILER cl)
set (BEA_DEFINITIONS "/DBEA_LACKS_SNPRINTF /D_CRT_SECURE_NO_WARNINGS")
if (optBUILD_STDCALL)
set (BEA_DEFINITIONS "${BEA_DEFINITIONS} /DBEA_USE_STDCALL")
endif ()
if (optBUILD_LITE)
set (BEA_DEFINITIONS "${BEA_DEFINITIONS} /DBEA_LIGHT_DISASSEMBLY")
endif ()
if (MSVC60)
set (BEA_WARNINGS /W3)
else ()
if (NOT MSVC90)
set (BEA_WARNINGS /W3 /Wp64)
else ()
set (BEA_WARNINGS /W4)
endif ()
endif ()
if (optHAS_SYMBOLS)
list (APPEND BEA_FLAGS /ZI)
list (APPEND BEA_DEFINITIONS "/D_DEBUG=1")
endif ()
if (optHAS_OPTIMIZED)
list (APPEND BEA_FLAGS /O2)
list (APPEND BEA_DEFINITIONS "/DNDEBUG")
endif ()
# determine code generation model
if (optHAS_OPTIMIZED)
if (optBUILD_DLL)
list (APPEND BEA_FLAGS /MD)
else ()
list (APPEND BEA_FLAGS /MT)
endif ()
else ()
if (optBUILD_DLL)
list (APPEND BEA_FLAGS /MDd)
else ()
list (APPEND BEA_FLAGS /MTd)
endif ()
endif ()
endif ()
# =========================================
# Intel Compiler configuration
# =========================================
if (BEA_COMPILER STREQUAL intel)
set (CMAKE_C_COMPILER icc)
set (CMAKE_CXX_COMPILER icpc)
set (BEA_WARNINGS -Wall -Wcheck -Wp64 -wd981 -wd1419 -wd1418)
set (BEA_FLAGS -ansi -pipe)
set (BEA_DEFINITIONS "")
if (optHAS_SYMBOLS)
list (APPEND BEA_FLAGS -g)
endif ()
if (optHAS_OPTIMIZED)
list (APPEND BEA_FLAGS -fomit-frame-pointer -O3 -ip)
endif ()
if (optBUILD_64BIT)
list (APPEND BEA_FLAGS -m64)
endif ()
if (optBUILD_STDCALL)
list (APPEND BEA_DEFINITIONS "-DBEA_USE_STDCALL")
endif ()
if (optBUILD_LITE)
list (APPEND BEA_DEFINITIONS "-DBEA_LIGHT_DISASSEMBLY")
endif ()
endif ()
# =========================================
# Borland C configuration
# =========================================
if (BEA_COMPILER STREQUAL borland)
set (CMAKE_C_COMPILER bcc32)
set (CMAKE_CXX_COMPILER bcc32)
set (BEA_WARNINGS -w -wamb -wdef -wnod -wnak -wcln -wsig -wucp)
set (BEA_FLAGS -pc -p- -H- -b -d -Hu-)
set (BEA_DEFINITIONS "")
if (optHAS_SYMBOLS)
list (APPEND BEA_FLAGS -v -y -R)
endif ()
if (optHAS_OPTIMIZED)
list (APPEND BEA_FLAGS -O2)
endif ()
if (optBUILD_64BIT)
set (BEA_DEFINITIONS "-D_WIN64")
else ()
set (BEA_DEFINITIONS "-D_WIN32")
endif ()
if (optBUILD_STDCALL)
list (APPEND BEA_DEFINITIONS "-DBEA_USE_STDCALL")
endif ()
if (optBUILD_LITE)
list (APPEND BEA_DEFINITIONS "-DBEA_LIGHT_DISASSEMBLY")
endif ()
endif ()
# =========================================
# Watcom C configuration
# =========================================
if (BEA_COMPILER STREQUAL watcom)
set (CMAKE_C_COMPILER wcl386)
set (CMAKE_CXX_COMPILER wcl386)
set (BEA_DEFINITIONS "-DBEA_STL_CONTAINER_REQUIRES_DEFAULT_CTOR")
set (BEA_WARNINGS -w2 -wx )
set (BEA_FLAGS -q -fpi -fpi87 "-bt=nt" -zq -6r -mf)
if (optHAS_SYMBOLS)
list (APPEND BEA_FLAGS -db -d2 )
endif ()
if (optHAS_OPTIMIZED)
list (APPEND BEA_FLAGS -ox -s -ors )
endif ()
if (optBUILD_64BIT)
# list (APPEND BEA_FLAGS -m64)
endif ()
if (optBUILD_STDCALL)
set (BEA_DEFINITIONS "${BEA_DEFINITIONS} -DBEA_USE_STDCALL")
endif ()
if (optBUILD_LITE)
set (BEA_DEFINITIONS "${BEA_DEFINITIONS} -DBEA_LIGHT_DISASSEMBLY")
endif ()
set (CMAKE_EXE_LINKER_FLAGS "-l=nt")
set (CMAKE_SHARED_LINKER_FLAGS "-l=nt")
endif ()
# =========================================
# Pelles C configuration
# =========================================
if (BEA_COMPILER STREQUAL pelles)
set (CMAKE_C_COMPILER pocc)
#set (CMAKE_CXX_COMPILER pocc)
set (BEA_WARNINGS /W2)
set (BEA_FLAGS /Gm /Gn)
set (BEA_DEFINITIONS "")
if (optHAS_SYMBOLS)
list (APPEND BEA_FLAGS /Zi )
endif ()
if (optHAS_OPTIMIZED)
list (APPEND BEA_FLAGS /Ox )
endif ()
if (optBUILD_64BIT)
# list (APPEND BEA_FLAGS -m64)
endif ()
if (optBUILD_STDCALL)
list (APPEND BEA_DEFINITIONS "/DBEA_USE_STDCALL")
endif ()
if (optBUILD_LITE)
list (APPEND BEA_DEFINITIONS "/DBEA_LIGHT_DISASSEMBLY")
endif ()
endif ()
# ============================================
# construct compiler flags
# ============================================
set (myC_FLAGS "")
set (myCXX_FLAGS "")
foreach (flag ${BEA_FLAGS})
set (myC_FLAGS "${myC_FLAGS} ${flag}")
endforeach ()
foreach (flag ${BEA_WARNINGS})
set (myC_FLAGS "${myC_FLAGS} ${flag}")
endforeach ()
foreach (flag ${BEA_FLAGS})
set (myCXX_FLAGS "${myCXX_FLAGS} ${flag}")
endforeach ()
foreach (flag ${BEA_WARNINGS})
set (myCXX_FLAGS "${myCXX_FLAGS} ${flag}")
endforeach ()
# ================================================
# pass compiler flags to cmake
# ================================================
if (${CMAKE_BUILD_TYPE} STREQUAL RelWithDebInfo)
set (CMAKE_C_FLAGS_RELWITHDEBINFO ${myC_FLAGS})
set (CMAKE_CXX_FLAGS_RELWITHDEBINFO ${myCXX_FLAGS})
endif ()
if (${CMAKE_BUILD_TYPE} STREQUAL Release)
set (CMAKE_C_FLAGS_RELEASE ${myC_FLAGS})
set (CMAKE_CXX_FLAGS_RELEASE ${myCXX_FLAGS})
endif ()
if (${CMAKE_BUILD_TYPE} STREQUAL DebugFull)
set (CMAKE_C_FLAGS_DEBUGFULL ${myC_FLAGS})
set (CMAKE_CXX_FLAGS_DEBUGFULL ${myCXX_FLAGS})
endif ()
if (${CMAKE_BUILD_TYPE} STREQUAL Debug)
set (CMAKE_C_FLAGS_DEBUG ${myC_FLAGS})
set (CMAKE_CXX_FLAGS_DEBUG ${myCXX_FLAGS})
endif ()
set (BEA_INCLUDE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/include)
set (BEA_SRC_ROOT ${CMAKE_CURRENT_SOURCE_DIR}/beaengineSources)
# ======================================
# set output dirs
# ======================================
set (myQualification "${CMAKE_SYSTEM_NAME}.${BEA_COMPILER}.${CMAKE_BUILD_TYPE}")
set (myLIB_OUTPUT "${CMAKE_SOURCE_DIR}/lib/${myQualification}" )
set (myBIN_OUTPUT "${CMAKE_SOURCE_DIR}/bin/${myQualification}")
set (myOBJ_OUTPUT obj)
if (optBUILD_64BIT)
set (myLIB_OUTPUT "${myLIB_OUTPUT}.64" )
set (myBIN_OUTPUT "${myBIN_OUTPUT}.64")
set (myOBJ_OUTPUT "${myOBJ_OUTPUT}.64")
endif ()
set (CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${myLIB_OUTPUT})
set (CMAKE_LIBRARY_OUTPUT_DIRECTORY ${myLIB_OUTPUT})
set (CMAKE_RUNTIME_OUTPUT_DIRECTORY ${myBIN_OUTPUT})
FIND_PACKAGE (ZLIB)
set (build_modules
beaengineSources
#examples
#unittest
)
if (NOT ZLIB_FOUND)
set (ZLIB_INCLUDE_DIR unittest/thirdparty/zlib)
else ()
list (APPEND BEA_LIBS_PATH ${ZLIB_LIBRARIES})
endif ()
add_definitions (${BEA_DEFINITIONS})
include_directories (${BEA_SRC_ROOT} ${BEA_INCLUDE_PATH}
${CMAKE_SOURCE_DIR} ${ZLIB_INCLUDE_DIR})
link_directories (${BEA_LIBS_PATH})
set (BEA_TARGET "BeaEngine")
if (NOT optBUILD_DLL)
set (BEA_TARGET "${BEA_TARGET}_s")
endif ()
if (NOT optHAS_OPTIMIZED)
set (BEA_TARGET "${BEA_TARGET}_d")
endif ()
if (optBUILD_STDCALL)
set (BEA_TARGET "${BEA_TARGET}_stdcall")
endif ()
if (optBUILD_64BIT)
set (BEA_TARGET "${BEA_TARGET}_64")
endif ()
foreach (mdl ${build_modules})
set (MDL_SRC "${mdl}")
set (MDL_OBJ "${myOBJ_OUTPUT}/${myQualification}/${mdl}")
add_subdirectory (${MDL_SRC} ${MDL_OBJ})
endforeach ()

56
deps/beaengine-4.1/beaengineSources/BeaEngine.c vendored
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@ -1,56 +0,0 @@
/*
* BeaEngine 4 - x86 & x86-64 disassembler library
*
* Copyright 2006-2010, BeatriX
* File coded by BeatriX
*
* This file is part of BeaEngine.
*
* BeaEngine is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BeaEngine is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with BeaEngine. If not, see <http://www.gnu.org/licenses/>. */
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "beaengine/BeaEngine.h"
#include "Includes/protos.h"
#include "Includes/internal_datas.h"
#include "Includes/instr_set/Data_opcode.h"
#include "Includes/instr_set/opcodes_A_M.c"
#include "Includes/instr_set/opcodes_N_Z.c"
#include "Includes/instr_set/opcodes_Grp1.c"
#include "Includes/instr_set/opcodes_Grp2.c"
#include "Includes/instr_set/opcodes_Grp3.c"
#include "Includes/instr_set/opcodes_Grp4.c"
#include "Includes/instr_set/opcodes_Grp5.c"
#include "Includes/instr_set/opcodes_Grp6.c"
#include "Includes/instr_set/opcodes_Grp7.c"
#include "Includes/instr_set/opcodes_Grp8.c"
#include "Includes/instr_set/opcodes_Grp9.c"
#include "Includes/instr_set/opcodes_Grp12.c"
#include "Includes/instr_set/opcodes_Grp13.c"
#include "Includes/instr_set/opcodes_Grp14.c"
#include "Includes/instr_set/opcodes_Grp15.c"
#include "Includes/instr_set/opcodes_Grp16.c"
#include "Includes/instr_set/opcodes_FPU.c"
#include "Includes/instr_set/opcodes_MMX.c"
#include "Includes/instr_set/opcodes_SSE.c"
#include "Includes/instr_set/opcodes_AES.c"
#include "Includes/instr_set/opcodes_CLMUL.c"
#include "Includes/instr_set/opcodes_prefixes.c"
#include "Includes/Routines_ModRM.c"
#include "Includes/Routines_Disasm.c"
#include "Includes/BeaEngineVersion.c"
void BeaEngine(void){return;}

BIN
deps/beaengine-4.1/beaengineSources/BeaEngine.obj vendored
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9
deps/beaengine-4.1/beaengineSources/CMakeLists.txt vendored
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@ -1,9 +0,0 @@
set (BEA_SOURCES BeaEngine.c)
if (optBUILD_DLL)
add_library (${BEA_TARGET} SHARED BeaEngine.c)
set_target_properties (${BEA_TARGET} PROPERTIES COMPILE_FLAGS "-DBUILD_BEA_ENGINE_DLL")
else ()
add_library (${BEA_TARGET} STATIC BeaEngine.c)
set_target_properties (${BEA_TARGET} PROPERTIES COMPILE_FLAGS "-DBEA_ENGINE_STATIC")
endif ()

165
deps/beaengine-4.1/beaengineSources/COPYING.LESSER.txt vendored
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@ -1,165 +0,0 @@
GNU LESSER GENERAL PUBLIC LICENSE
Version 3, 29 June 2007
Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
This version of the GNU Lesser General Public License incorporates
the terms and conditions of version 3 of the GNU General Public
License, supplemented by the additional permissions listed below.
0. Additional Definitions.
As used herein, "this License" refers to version 3 of the GNU Lesser
General Public License, and the "GNU GPL" refers to version 3 of the GNU
General Public License.
"The Library" refers to a covered work governed by this License,
other than an Application or a Combined Work as defined below.
An "Application" is any work that makes use of an interface provided
by the Library, but which is not otherwise based on the Library.
Defining a subclass of a class defined by the Library is deemed a mode
of using an interface provided by the Library.
A "Combined Work" is a work produced by combining or linking an
Application with the Library. The particular version of the Library
with which the Combined Work was made is also called the "Linked
Version".
The "Minimal Corresponding Source" for a Combined Work means the
Corresponding Source for the Combined Work, excluding any source code
for portions of the Combined Work that, considered in isolation, are
based on the Application, and not on the Linked Version.
The "Corresponding Application Code" for a Combined Work means the
object code and/or source code for the Application, including any data
and utility programs needed for reproducing the Combined Work from the
Application, but excluding the System Libraries of the Combined Work.
1. Exception to Section 3 of the GNU GPL.
You may convey a covered work under sections 3 and 4 of this License
without being bound by section 3 of the GNU GPL.
2. Conveying Modified Versions.
If you modify a copy of the Library, and, in your modifications, a
facility refers to a function or data to be supplied by an Application
that uses the facility (other than as an argument passed when the
facility is invoked), then you may convey a copy of the modified
version:
a) under this License, provided that you make a good faith effort to
ensure that, in the event an Application does not supply the
function or data, the facility still operates, and performs
whatever part of its purpose remains meaningful, or
b) under the GNU GPL, with none of the additional permissions of
this License applicable to that copy.
3. Object Code Incorporating Material from Library Header Files.
The object code form of an Application may incorporate material from
a header file that is part of the Library. You may convey such object
code under terms of your choice, provided that, if the incorporated
material is not limited to numerical parameters, data structure
layouts and accessors, or small macros, inline functions and templates
(ten or fewer lines in length), you do both of the following:
a) Give prominent notice with each copy of the object code that the
Library is used in it and that the Library and its use are
covered by this License.
b) Accompany the object code with a copy of the GNU GPL and this license
document.
4. Combined Works.
You may convey a Combined Work under terms of your choice that,
taken together, effectively do not restrict modification of the
portions of the Library contained in the Combined Work and reverse
engineering for debugging such modifications, if you also do each of
the following:
a) Give prominent notice with each copy of the Combined Work that
the Library is used in it and that the Library and its use are
covered by this License.
b) Accompany the Combined Work with a copy of the GNU GPL and this license
document.
c) For a Combined Work that displays copyright notices during
execution, include the copyright notice for the Library among
these notices, as well as a reference directing the user to the
copies of the GNU GPL and this license document.
d) Do one of the following:
0) Convey the Minimal Corresponding Source under the terms of this
License, and the Corresponding Application Code in a form
suitable for, and under terms that permit, the user to
recombine or relink the Application with a modified version of
the Linked Version to produce a modified Combined Work, in the
manner specified by section 6 of the GNU GPL for conveying
Corresponding Source.
1) Use a suitable shared library mechanism for linking with the
Library. A suitable mechanism is one that (a) uses at run time
a copy of the Library already present on the user's computer
system, and (b) will operate properly with a modified version
of the Library that is interface-compatible with the Linked
Version.
e) Provide Installation Information, but only if you would otherwise
be required to provide such information under section 6 of the
GNU GPL, and only to the extent that such information is
necessary to install and execute a modified version of the
Combined Work produced by recombining or relinking the
Application with a modified version of the Linked Version. (If
you use option 4d0, the Installation Information must accompany
the Minimal Corresponding Source and Corresponding Application
Code. If you use option 4d1, you must provide the Installation
Information in the manner specified by section 6 of the GNU GPL
for conveying Corresponding Source.)
5. Combined Libraries.
You may place library facilities that are a work based on the
Library side by side in a single library together with other library
facilities that are not Applications and are not covered by this
License, and convey such a combined library under terms of your
choice, if you do both of the following:
a) Accompany the combined library with a copy of the same work based
on the Library, uncombined with any other library facilities,
conveyed under the terms of this License.
b) Give prominent notice with the combined library that part of it
is a work based on the Library, and explaining where to find the
accompanying uncombined form of the same work.
6. Revised Versions of the GNU Lesser General Public License.
The Free Software Foundation may publish revised and/or new versions
of the GNU Lesser General Public License from time to time. Such new
versions will be similar in spirit to the present version, but may
differ in detail to address new problems or concerns.
Each version is given a distinguishing version number. If the
Library as you received it specifies that a certain numbered version
of the GNU Lesser General Public License "or any later version"
applies to it, you have the option of following the terms and
conditions either of that published version or of any later version
published by the Free Software Foundation. If the Library as you
received it does not specify a version number of the GNU Lesser
General Public License, you may choose any version of the GNU Lesser
General Public License ever published by the Free Software Foundation.
If the Library as you received it specifies that a proxy can decide
whether future versions of the GNU Lesser General Public License shall
apply, that proxy's public statement of acceptance of any version is
permanent authorization for you to choose that version for the
Library.

674
deps/beaengine-4.1/beaengineSources/COPYING.txt vendored
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@ -1,674 +0,0 @@
GNU GENERAL PUBLIC LICENSE
Version 3, 29 June 2007
Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
Preamble
The GNU General Public License is a free, copyleft license for
software and other kinds of works.
The licenses for most software and other practical works are designed
to take away your freedom to share and change the works. By contrast,
the GNU General Public License is intended to guarantee your freedom to
share and change all versions of a program--to make sure it remains free
software for all its users. We, the Free Software Foundation, use the
GNU General Public License for most of our software; it applies also to
any other work released this way by its authors. You can apply it to
your programs, too.
When we speak of free software, we are referring to freedom, not
price. Our General Public Licenses are designed to make sure that you
have the freedom to distribute copies of free software (and charge for
them if you wish), that you receive source code or can get it if you
want it, that you can change the software or use pieces of it in new
free programs, and that you know you can do these things.
To protect your rights, we need to prevent others from denying you
these rights or asking you to surrender the rights. Therefore, you have
certain responsibilities if you distribute copies of the software, or if
you modify it: responsibilities to respect the freedom of others.
For example, if you distribute copies of such a program, whether
gratis or for a fee, you must pass on to the recipients the same
freedoms that you received. You must make sure that they, too, receive
or can get the source code. And you must show them these terms so they
know their rights.
Developers that use the GNU GPL protect your rights with two steps:
(1) assert copyright on the software, and (2) offer you this License
giving you legal permission to copy, distribute and/or modify it.
For the developers' and authors' protection, the GPL clearly explains
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Some devices are designed to deny users access to install or run
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The precise terms and conditions for copying, distribution and
modification follow.
TERMS AND CONDITIONS
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Nothing in this License shall be construed as excluding or limiting
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Notwithstanding any other provision of this License, you have
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If the Program specifies that a proxy can decide which future
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to choose that version for the Program.
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15. Disclaimer of Warranty.
THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
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ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
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IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
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USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
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EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES.
17. Interpretation of Sections 15 and 16.
If the disclaimer of warranty and limitation of liability provided
above cannot be given local legal effect according to their terms,
reviewing courts shall apply local law that most closely approximates
an absolute waiver of all civil liability in connection with the
Program, unless a warranty or assumption of liability accompanies a
copy of the Program in return for a fee.
END OF TERMS AND CONDITIONS
How to Apply These Terms to Your New Programs
If you develop a new program, and you want it to be of the greatest
possible use to the public, the best way to achieve this is to make it
free software which everyone can redistribute and change under these terms.
To do so, attach the following notices to the program. It is safest
to attach them to the start of each source file to most effectively
state the exclusion of warranty; and each file should have at least
the "copyright" line and a pointer to where the full notice is found.
<one line to give the program's name and a brief idea of what it does.>
Copyright (C) <year> <name of author>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
Also add information on how to contact you by electronic and paper mail.
If the program does terminal interaction, make it output a short
notice like this when it starts in an interactive mode:
<program> Copyright (C) <year> <name of author>
This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
The hypothetical commands `show w' and `show c' should show the appropriate
parts of the General Public License. Of course, your program's commands
might be different; for a GUI interface, you would use an "about box".
You should also get your employer (if you work as a programmer) or school,
if any, to sign a "copyright disclaimer" for the program, if necessary.
For more information on this, and how to apply and follow the GNU GPL, see
<http://www.gnu.org/licenses/>.
The GNU General Public License does not permit incorporating your program
into proprietary programs. If your program is a subroutine library, you
may consider it more useful to permit linking proprietary applications with
the library. If this is what you want to do, use the GNU Lesser General
Public License instead of this License. But first, please read
<http://www.gnu.org/philosophy/why-not-lgpl.html>.

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@ -1,23 +0,0 @@
/* Copyright 2006-2010, BeatriX
* File coded by BeatriX
*
* This file is part of BeaEngine.
*
* BeaEngine is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BeaEngine is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with BeaEngine. If not, see <http://www.gnu.org/licenses/>. */
const__ char* __bea_callspec__ BeaEngineVersion(void) {
return "4.1";
}
const__ char* __bea_callspec__ BeaEngineRevision(void) {
return "175";
}

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deps/beaengine-4.1/beaengineSources/Includes/Routines_ModRM.c vendored
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/* Copyright 2006-2009, BeatriX
* File coded by BeatriX
*
* This file is part of BeaEngine.
*
* BeaEngine is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BeaEngine is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with BeaEngine. If not, see <http://www.gnu.org/licenses/>. */
/* =============================================================================== */
/* */
/* */
/* 1 BYTE_OPCODE MAP */
/* */
/* */
/* =============================================================================== */
void (__bea_callspec__ * opcode_map1[])(PDISASM) = {
add_EbGb , add_EvGv , add_GbEb , add_GvEv , add_ALIb , add_eAX_Iv, push_es , pop_es , or_EbGb , or_EvGv , or_GbEb , or_GvEv , or_ALIb , or_eAX_Iv , push_cs , Esc_2byte ,
adc_EbGb , adc_EvGv , adc_GbEb , adc_GvEv , adc_ALIb , adc_eAX_Iv, push_ss , pop_ss , sbb_EbGb , sbb_EvGv , sbb_GbEb , sbb_GvEv , sbb_ALIb , sbb_eAX_Iv, push_ds , pop_ds ,
and_EbGb , and_EvGv , and_GbEb , and_GvEv , and_ALIb , and_eAX_Iv, PrefSEGES , daa_ , sub_EbGb , sub_EvGv , sub_GbEb , sub_GvEv , sub_ALIb , sub_eAX_Iv, PrefSEGCS , das_ ,
xor_EbGb , xor_EvGv , xor_GbEb , xor_GvEv , xor_ALIb , xor_eAX_Iv, PrefSEGSS , aaa_ , cmp_EbGb , cmp_EvGv , cmp_GbEb , cmp_GvEv , cmp_ALIb , cmp_eAX_Iv, PrefSEGDS , aas_ ,
inc_eax , inc_ecx , inc_edx , inc_ebx , inc_esp , inc_ebp , inc_esi , inc_edi , dec_eax , dec_ecx , dec_edx , dec_ebx , dec_esp , dec_ebp , dec_esi , dec_edi ,
push_eax , push_ecx , push_edx , push_ebx , push_esp , push_ebp , push_esi , push_edi , pop_eax , pop_ecx , pop_edx , pop_ebx , pop_esp , pop_ebp , pop_esi , pop_edi ,
pushad_ , popad_ , bound_ , arpl_ , PrefSEGFS , PrefSEGGS , PrefOpSize, PrefAdSize, push_Iv ,imul_GvEvIv, push_Ib ,imul_GvEvIb, insb_ , ins_ , outsb_ , outsw_ ,
jo_ , jno_ , jc_ , jnc_ , je_ , jne_ , jbe_ , jnbe_ , js_ , jns_ , jp_ , jnp_ , jl_ , jnl_ , jle_ , jnle_ ,
G1_EbIb , G1_EvIv , G1_EbIb2 , G1_EvIb , test_EbGb , test_EvGv , xchg_EbGb , xchg_EvGv , mov_EbGb , mov_EvGv , mov_GbEb , mov_GvEv , mov_EwSreg, lea_GvM , mov_SregEw, pop_Ev ,
nop_ , xchg_ecx , xchg_edx , xchg_ebx , xchg_esp , xchg_ebp , xchg_esi , xchg_edi , cwde_ , cdq_ , callf_ , wait_ , pushfd_ , popfd_ , sahf_ , lahf_ ,
mov_ALOb , mov_eAXOv , mov_ObAL , mov_OveAX , movs_ , movsw_ , cmpsb_ , cmps_ , test_ALIb ,test_eAX_Iv, stos_ , stosw_ , lodsb_ , lodsw_ , scasb_ , scas_ ,
mov_ALIb , mov_CLIb , mov_DLIb , mov_BLIb , mov_AHIb , mov_CHIb , mov_DHIb , mov_BHIb , mov_EAX , mov_ECX , mov_EDX , mov_EBX , mov_ESP , mov_EBP , mov_ESI , mov_EDI ,
G2_EbIb , G2_EvIb , retn_ , ret_ , les_GvM , lds_GvM , mov_EbIb , mov_EvIv , enter_ , leave_ , retf_Iw , retf_ , int3_ , int_ , into_ , iret_ ,
G2_Eb1 , G2_Ev1 , G2_EbCL , G2_EvCL , aam_ , aad_ , salc_ , xlat_ , D8_ , D9_ , DA_ , DB_ , DC_ , DD_ , DE_ , DF_ ,
loopne_ , loope_ , loop_ , jecxz_ , in_ALIb , in_eAX_Ib , out_IbAL , out_Ib_eAX, call_ , jmp_near , jmp_far , jmp_short , in_ALDX , in_eAX , out_DXAL , out_DXeAX ,
PrefLock , int1_ , PrefREPNE , PrefREPE , hlt_ , cmc_ , G3_Eb , G3_Ev , clc_ , stc_ , cli_ , sti_ , cld_ , std_ , G4_Eb , G5_Ev ,
};
/* =============================================================================== */
/* */
/* */
/* 2 BYTE_OPCODE MAP --> 0F xx */
/* */
/* */
/* =============================================================================== */
void (__bea_callspec__ *opcode_map2[])(PDISASM) = {
G6_ , G7_ , lar_GvEw , lsl_GvEw , FailDecode, syscall_ , clts_ , sysret_ , invd_ , wbinvd_ , FailDecode, ud2_ , FailDecode, nop_Ev , femms_ , FailDecode,
movups_VW , movups_WV , movlps_VM , movlps_MV , unpcklps_ , unpckhps_ , movhps_VM , movhps_MV , G16_ , hint_nop , hint_nop , hint_nop , hint_nop , hint_nop , hint_nop , nop_Ev ,
mov_RdCd , mov_RdDd , mov_CdRd , mov_DdRd , FailDecode, FailDecode, FailDecode, FailDecode, movaps_VW , movaps_WV , cvtpi2ps_ , movntps_ , cvttps2pi_, cvtps2pi_ , ucomiss_VW, comiss_VW ,
wrmsr_ , rdtsc_ , rdmsr_ , rdpmc_ , sysenter_ , sysexit_ , FailDecode, FailDecode,Esc_tableA4, FailDecode,Esc_tableA5, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode,
cmovo_ , cmovno_ , cmovb_ , cmovnb_ , cmove_ , cmovne_ , cmovbe_ , cmovnbe_ , cmovs_ , cmovns_ , cmovp_ , cmovnp_ , cmovl_ , cmovnl_ , cmovle_ , cmovnle_ ,
movmskps_ , sqrtps_VW , rsqrtps_ , rcpps_ , andps_VW , andnps_VW , orps_VW , xorps_VW , addps_VW , mulps_VW , cvtps2pd_ , cvtdq2ps_ , subps_VW , minps_VW , divps_VW , maxps_VW ,
punpcklbw_, punpcklwd_, punpckldq_, packsswb_ , pcmpgtb_ , pcmpgtw_ , pcmpgtd_ , packuswb_ , punpckhbw_, punpckhwd_, punpckhdq_, packssdw_ ,punpcklqdq_,punpckhqdq_, movd_PE , movq_PQ ,
pshufw_ , G12_ , G13_ , G14_ , pcmpeqb_ , pcmpeqw_ , pcmpeqd_ , emms_ , vmread_ , vmwrite_ , FailDecode, FailDecode, haddpd_VW , hsubpd_VW , movd_EP , movq_QP ,
jo_near , jno_near , jc_near , jnc_near , je_near , jne_near , jbe_near , ja_near , js_near , jns_near , jp_near , jnp_near , jl_near , jnl_near , jle_near , jnle_near ,
seto_ , setno_ , setb_ , setnb_ , sete_ , setne_ , setbe_ , setnbe_ , sets_ , setns_ , setp_ , setnp_ , setnge_ , setge_ , setle_ , setnle_ ,
push_fs , pop_fs , cpuid_ , bt_EvGv ,shld_EvGvIb,shld_EvGvCL, FailDecode, FailDecode, push_gs , pop_gs , rsm_ , bts_EvGv ,shrd_EvGvIb,shrd_EvGvCL, G15_ , imul_GvEv ,
cmpx_EbGb , cmpx_EvGv , lss_Mp , btr_EvGv , lfs_Mp , lgs_Mp , movzx_GvEb, movzx_GvEw, popcnt_ , ud2_ , G8_EvIb , btc_EvGv , bsf_GvEv , bsr_GvEv , movsx_GvEb, movsx_GvEw,
xadd_EbGb , xadd_EvGv , cmpps_VW , movnti_ , pinsrw_ , pextrw_ , shufps_ , G9_ , bswap_eax , bswap_ecx , bswap_edx , bswap_ebx , bswap_esp , bswap_ebp , bswap_esi , bswap_edi ,
addsubpd_ , psrlw_ , psrld_ , psrlq_ , paddq_ , pmullw_ , movq_WV , pmovmskb_ , psubusb_ , psubusw_ , pminub_ , pand_ , paddusb_ , paddusw_ , pmaxub_ , pandn_ ,
pavgb_ , psraw_ , psrad_ , pavgw_ , pmulhuw_ , pmulhw_ , cvtpd2dq_ , movntq_ , psubsb_ , psubsw_ , pminsw_ , por_ , paddsb_ , paddsw_ , pmaxsw_ , pxor_ ,
lddqu_ , psllw_ , pslld_ , psllq_ , pmuludq_ , pmaddwd_ , psadbw_ , maskmovq_ , psubb_ , psubw_ , psubd_ , psubq_ , paddb_ , paddw_ , paddd_ , FailDecode,
};
/* =============================================================================== */
/* */
/* */
/* 3 BYTE_OPCODE MAP --> 0F 38 xx */
/* */
/* */
/* =============================================================================== */
void (__bea_callspec__ *opcode_map3[])(PDISASM) = {
pshufb_ , phaddw_ , phaddd_ , phaddsw_ , pmaddubsw_, phsubw_ , phsubd_ , phsubsw_ , psignb_ , psignw_ , psignd_ , pmulhrsw_ , FailDecode, FailDecode, FailDecode, FailDecode,
pblendvb_ , FailDecode, FailDecode, FailDecode, blendvps_ , blendvpd_ , FailDecode, ptest_ , FailDecode, FailDecode, FailDecode, FailDecode, pabsb_ , pabsw_ , pabsd_ , FailDecode,
pmovsxbw_ , pmovsxbd_ , pmovsxbq_ , pmovsxwd_ , pmovsxwq_ , pmovsxdq_ , FailDecode, FailDecode, pmuldq_ , pcmpeqq_ , movntdqa_ , packusdw_ , FailDecode, FailDecode, FailDecode, FailDecode,
pmovzxbw_ , pmovzxbd_ , pmovzxbq_ , pmovzxwd_ , pmovzxwq_ , pmovzxdq_ , FailDecode, pcmpgtq_ , pminsb_ , pminsd_ , pminuw_ , pminud_ , pmaxsb_ , pmaxsd_ , pmaxuw_ , pmaxud_ ,
pmulld_ ,phminposuw_, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode,
FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode,
FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode,
FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode,
FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode,
FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode,
FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode,
FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode,
FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode,
FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, aesimc , aesenc , aesenclast, aesdec , aesdeclast,
FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode,
crc32_GvEb, crc32_GvEv, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode,
};
/* =============================================================================== */
/* */
/* */
/* 3 UInt8_OPCODE MAP --> 0F 3A xx */
/* */
/* */
/* =============================================================================== */
void (__bea_callspec__ *opcode_map4[])(PDISASM) = {
FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, roundps_ , roundpd_ , roundss_ , roundsd_ , blendps_ , blendpd_ , pblendw_ , palignr_ ,
FailDecode, FailDecode, FailDecode, FailDecode, pextrb_ , pextrw2_ , pextrd_ , extractps_, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode,
pinsrb_ , insertps_ , pinsrd_ , FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode,
FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode,
dpps_ , dppd_ , mpsadbw_ , FailDecode, pclmulqdq_, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode,
FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode,
pcmpestrm_, pcmpestri_, pcmpistrm_, pcmpistri_, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode,
FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode,
FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode,
FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode,
FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode,
FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode,
FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode,
FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, aeskeygen ,
FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode,
FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode, FailDecode,
};
void (__bea_callspec__ *ModRM_0[])(ARGTYPE*, PDISASM) = {
Addr_EAX,
Addr_ECX,
Addr_EDX,
Addr_EBX,
Addr_SIB,
Addr_disp32,
Addr_ESI,
Addr_EDI,
};
void (__bea_callspec__ *ModRM_1[])(ARGTYPE*, PDISASM) = {
Addr_EAX_disp8,
Addr_ECX_disp8,
Addr_EDX_disp8,
Addr_EBX_disp8,
Addr_SIB_disp8,
Addr_EBP_disp8,
Addr_ESI_disp8,
Addr_EDI_disp8,
};
void (__bea_callspec__ *ModRM_2[])(ARGTYPE*, PDISASM) = {
Addr_EAX_disp32,
Addr_ECX_disp32,
Addr_EDX_disp32,
Addr_EBX_disp32,
Addr_SIB_disp32,
Addr_EBP_disp32,
Addr_ESI_disp32,
Addr_EDI_disp32,
};
void (__bea_callspec__ *ModRM_3[])(ARGTYPE*, PDISASM) = {
_rEAX,
_rECX,
_rEDX,
_rEBX,
_rESP,
_rEBP,
_rESI,
_rEDI,
};
size_t (__bea_callspec__ *SIB[])(ARGTYPE*, size_t, PDISASM) = {
SIB_0,
SIB_1,
SIB_2,
SIB_3,
};

168
deps/beaengine-4.1/beaengineSources/Includes/instr_set/opcodes_AES.c vendored
View File

@ -1,168 +0,0 @@
/* Copyright 2006-2009, BeatriX
* File coded by BeatriX
*
* This file is part of BeaEngine.
*
* BeaEngine is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BeaEngine is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with BeaEngine. If not, see <http://www.gnu.org/licenses/>. */
/* ====================================================================
* 0x 0f 38 db
* ==================================================================== */
void __bea_callspec__ aesimc(PDISASM pMyDisasm)
{
/* ========== 0x66 */
if (GV.OperandSize == 16) {
GV.OperandSize = GV.OriginalOperandSize;
(*pMyDisasm).Prefix.OperandSize = MandatoryPrefix;
GV.MemDecoration = Arg2dqword;
(*pMyDisasm).Instruction.Category = AES_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "aesimc ");
#endif
GV.SSE_ = 1;
GxEx(pMyDisasm);
GV.SSE_ = 0;
}
else {
FailDecode(pMyDisasm);
}
}
/* ====================================================================
* 0x 0f 38 dc
* ==================================================================== */
void __bea_callspec__ aesenc(PDISASM pMyDisasm)
{
/* ========== 0x66 */
if (GV.OperandSize == 16) {
GV.OperandSize = GV.OriginalOperandSize;
(*pMyDisasm).Prefix.OperandSize = MandatoryPrefix;
GV.MemDecoration = Arg2dqword;
(*pMyDisasm).Instruction.Category = AES_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "aesenc ");
#endif
GV.SSE_ = 1;
GxEx(pMyDisasm);
GV.SSE_ = 0;
}
else {
FailDecode(pMyDisasm);
}
}
/* ====================================================================
* 0x 0f 38 dd
* ==================================================================== */
void __bea_callspec__ aesenclast(PDISASM pMyDisasm)
{
/* ========== 0x66 */
if (GV.OperandSize == 16) {
GV.OperandSize = GV.OriginalOperandSize;
(*pMyDisasm).Prefix.OperandSize = MandatoryPrefix;
GV.MemDecoration = Arg2dqword;
(*pMyDisasm).Instruction.Category = AES_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "aesenclast ");
#endif
GV.SSE_ = 1;
GxEx(pMyDisasm);
GV.SSE_ = 0;
}
else {
FailDecode(pMyDisasm);
}
}
/* ====================================================================
* 0x 0f 38 de
* ==================================================================== */
void __bea_callspec__ aesdec(PDISASM pMyDisasm)
{
/* ========== 0x66 */
if (GV.OperandSize == 16) {
GV.OperandSize = GV.OriginalOperandSize;
(*pMyDisasm).Prefix.OperandSize = MandatoryPrefix;
GV.MemDecoration = Arg2dqword;
(*pMyDisasm).Instruction.Category = AES_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "aesdec ");
#endif
GV.SSE_ = 1;
GxEx(pMyDisasm);
GV.SSE_ = 0;
}
else {
FailDecode(pMyDisasm);
}
}
/* ====================================================================
* 0x 0f 38 df
* ==================================================================== */
void __bea_callspec__ aesdeclast(PDISASM pMyDisasm)
{
/* ========== 0x66 */
if (GV.OperandSize == 16) {
GV.OperandSize = GV.OriginalOperandSize;
(*pMyDisasm).Prefix.OperandSize = MandatoryPrefix;
GV.MemDecoration = Arg2dqword;
(*pMyDisasm).Instruction.Category = AES_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "aesdeclast ");
#endif
GV.SSE_ = 1;
GxEx(pMyDisasm);
GV.SSE_ = 0;
}
else {
FailDecode(pMyDisasm);
}
}
/* ====================================================================
* 0x 0f 3a df
* ==================================================================== */
void __bea_callspec__ aeskeygen(PDISASM pMyDisasm)
{
/* ========== 0x66 */
if (GV.OperandSize == 16) {
GV.OperandSize = GV.OriginalOperandSize;
(*pMyDisasm).Prefix.OperandSize = MandatoryPrefix;
GV.MemDecoration = Arg2dqword;
(*pMyDisasm).Instruction.Category = AES_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "aeskeygenassist ");
#endif
GV.ImmediatSize = 8;
GV.SSE_ = 1;
GxEx(pMyDisasm);
GV.SSE_ = 0;
GV.EIP_++;
if (!Security(0, pMyDisasm)) return;
GV.third_arg = 1;
(*pMyDisasm).Instruction.Immediat = *((UInt8*)(UIntPtr) (GV.EIP_- 1));
#ifndef BEA_LIGHT_DISASSEMBLY
(void) CopyFormattedNumber(pMyDisasm, (char*) (*pMyDisasm).Argument3.ArgMnemonic, "%.2X",(Int64) *((UInt8*)(UIntPtr) (GV.EIP_- 1)));
#endif
(*pMyDisasm).Argument3.ArgType = CONSTANT_TYPE+ABSOLUTE_;
(*pMyDisasm).Argument3.ArgSize = 8;
}
else {
FailDecode(pMyDisasm);
}
}

6731
deps/beaengine-4.1/beaengineSources/Includes/instr_set/opcodes_A_M.c vendored
View File

File diff suppressed because it is too large Load Diff

74
deps/beaengine-4.1/beaengineSources/Includes/instr_set/opcodes_CLMUL.c vendored
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@ -1,74 +0,0 @@
/* Copyright 2006-2009, BeatriX
* File coded by BeatriX
*
* This file is part of BeaEngine.
*
* BeaEngine is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BeaEngine is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with BeaEngine. If not, see <http://www.gnu.org/licenses/>. */
/* ====================================================================
* 0x 0f 3a 44
* ==================================================================== */
void __bea_callspec__ pclmulqdq_(PDISASM pMyDisasm)
{
/* ========== 0x66 */
if (GV.OperandSize == 16) {
(*pMyDisasm).Prefix.OperandSize = MandatoryPrefix;
GV.MemDecoration = Arg2dqword;
(*pMyDisasm).Instruction.Category = CLMUL_INSTRUCTION;
GV.ImmediatSize = 8;
GV.SSE_ = 1;
GxEx(pMyDisasm);
GV.SSE_ = 0;
GV.EIP_++;
if (!Security(0, pMyDisasm)) return;
(*pMyDisasm).Instruction.Immediat = *((UInt8*)(UIntPtr) (GV.EIP_- 1));
if ((*pMyDisasm).Instruction.Immediat == 0) {
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "pclmullqlqdq ");
#endif
}
else if ((*pMyDisasm).Instruction.Immediat == 0x01 ) {
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "pclmulhqlqdq ");
#endif
}
else if ((*pMyDisasm).Instruction.Immediat == 0x10 ) {
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "pclmullqhqdq ");
#endif
}
else if ((*pMyDisasm).Instruction.Immediat == 0x011 ) {
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "pclmulhqhqdq ");
#endif
}
else {
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "pclmulqdq ");
#endif
GV.third_arg = 1;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) CopyFormattedNumber(pMyDisasm, (char*) (*pMyDisasm).Argument3.ArgMnemonic, "%.2X",(Int64) *((UInt8*)(UIntPtr) (GV.EIP_- 1)));
#endif
(*pMyDisasm).Argument3.ArgType = CONSTANT_TYPE+ABSOLUTE_;
(*pMyDisasm).Argument3.ArgSize = 8;
}
}
else {
FailDecode(pMyDisasm);
}
}

1785
deps/beaengine-4.1/beaengineSources/Includes/instr_set/opcodes_FPU.c vendored
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File diff suppressed because it is too large Load Diff

297
deps/beaengine-4.1/beaengineSources/Includes/instr_set/opcodes_Grp1.c vendored
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@ -1,297 +0,0 @@
/* Copyright 2006-2009, BeatriX
* File coded by BeatriX
*
* This file is part of BeaEngine.
*
* BeaEngine is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BeaEngine is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with BeaEngine. If not, see <http://www.gnu.org/licenses/>. */
/* ====================================================================
* 80h
* ==================================================================== */
void __bea_callspec__ G1_EbIb(PDISASM pMyDisasm)
{
GV.REGOPCODE = ((*((UInt8*)(UIntPtr) (GV.EIP_+1))) >> 3) & 0x7;
EbIb(pMyDisasm);
if (GV.REGOPCODE == 0) {
if ((*pMyDisasm).Prefix.LockPrefix == InvalidPrefix) {
(*pMyDisasm).Prefix.LockPrefix = InUsePrefix;
}
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+ARITHMETIC_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "add ");
#endif
FillFlags(pMyDisasm, 5);
}
else if (GV.REGOPCODE == 1) {
if ((*pMyDisasm).Prefix.LockPrefix == InvalidPrefix) {
(*pMyDisasm).Prefix.LockPrefix = InUsePrefix;
}
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+LOGICAL_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "or ");
#endif
FillFlags(pMyDisasm, 74);
}
else if (GV.REGOPCODE == 2) {
if ((*pMyDisasm).Prefix.LockPrefix == InvalidPrefix) {
(*pMyDisasm).Prefix.LockPrefix = InUsePrefix;
}
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+ARITHMETIC_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "adc ");
#endif
FillFlags(pMyDisasm, 4);
}
else if (GV.REGOPCODE == 3) {
if ((*pMyDisasm).Prefix.LockPrefix == InvalidPrefix) {
(*pMyDisasm).Prefix.LockPrefix = InUsePrefix;
}
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+ARITHMETIC_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "sbb ");
#endif
FillFlags(pMyDisasm, 93);
}
else if (GV.REGOPCODE == 4) {
if ((*pMyDisasm).Prefix.LockPrefix == InvalidPrefix) {
(*pMyDisasm).Prefix.LockPrefix = InUsePrefix;
}
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+LOGICAL_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "and ");
#endif
FillFlags(pMyDisasm, 6);
}
else if (GV.REGOPCODE == 5) {
if ((*pMyDisasm).Prefix.LockPrefix == InvalidPrefix) {
(*pMyDisasm).Prefix.LockPrefix = InUsePrefix;
}
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+ARITHMETIC_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "sub ");
#endif
FillFlags(pMyDisasm, 103);
}
else if (GV.REGOPCODE == 6) {
if ((*pMyDisasm).Prefix.LockPrefix == InvalidPrefix) {
(*pMyDisasm).Prefix.LockPrefix = InUsePrefix;
}
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+LOGICAL_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "xor ");
#endif
FillFlags(pMyDisasm, 113);
}
else if (GV.REGOPCODE == 7) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+ARITHMETIC_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "cmp ");
#endif
FillFlags(pMyDisasm, 20);
(*pMyDisasm).Argument1.AccessMode = READ;
}
}
/* ====================================================================
* 82h
* ==================================================================== */
void __bea_callspec__ G1_EbIb2(PDISASM pMyDisasm)
{
if (GV.Architecture == 64) {
FailDecode(pMyDisasm);
}
else {
G1_EbIb(pMyDisasm);
}
}
/* ====================================================================
* 81h
* ==================================================================== */
void __bea_callspec__ G1_EvIv(PDISASM pMyDisasm)
{
GV.REGOPCODE = ((*((UInt8*)(UIntPtr) (GV.EIP_+1))) >> 3) & 0x7;
EvIv(pMyDisasm);
if (GV.REGOPCODE == 0) {
if ((*pMyDisasm).Prefix.LockPrefix == InvalidPrefix) {
(*pMyDisasm).Prefix.LockPrefix = InUsePrefix;
}
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+ARITHMETIC_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "add ");
#endif
FillFlags(pMyDisasm, 5);
}
else if (GV.REGOPCODE == 1) {
if ((*pMyDisasm).Prefix.LockPrefix == InvalidPrefix) {
(*pMyDisasm).Prefix.LockPrefix = InUsePrefix;
}
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+LOGICAL_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "or ");
#endif
FillFlags(pMyDisasm, 74);
}
else if (GV.REGOPCODE == 2) {
if ((*pMyDisasm).Prefix.LockPrefix == InvalidPrefix) {
(*pMyDisasm).Prefix.LockPrefix = InUsePrefix;
}
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+ARITHMETIC_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "adc ");
#endif
FillFlags(pMyDisasm, 4);
}
else if (GV.REGOPCODE == 3) {
if ((*pMyDisasm).Prefix.LockPrefix == InvalidPrefix) {
(*pMyDisasm).Prefix.LockPrefix = InUsePrefix;
}
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+ARITHMETIC_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "sbb ");
#endif
FillFlags(pMyDisasm, 93);
}
else if (GV.REGOPCODE == 4) {
if ((*pMyDisasm).Prefix.LockPrefix == InvalidPrefix) {
(*pMyDisasm).Prefix.LockPrefix = InUsePrefix;
}
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+LOGICAL_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "and ");
#endif
FillFlags(pMyDisasm, 6);
}
else if (GV.REGOPCODE == 5) {
if ((*pMyDisasm).Prefix.LockPrefix == InvalidPrefix) {
(*pMyDisasm).Prefix.LockPrefix = InUsePrefix;
}
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+ARITHMETIC_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "sub ");
#endif
FillFlags(pMyDisasm, 103);
}
else if (GV.REGOPCODE == 6) {
if ((*pMyDisasm).Prefix.LockPrefix == InvalidPrefix) {
(*pMyDisasm).Prefix.LockPrefix = InUsePrefix;
}
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+LOGICAL_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "xor ");
#endif
FillFlags(pMyDisasm, 113);
}
else if (GV.REGOPCODE == 7) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+ARITHMETIC_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "cmp ");
#endif
FillFlags(pMyDisasm, 20);
(*pMyDisasm).Argument1.AccessMode = READ;
}
}
/* ====================================================================
* 83h
* ==================================================================== */
void __bea_callspec__ G1_EvIb(PDISASM pMyDisasm)
{
GV.REGOPCODE = ((*((UInt8*)(UIntPtr) (GV.EIP_+1))) >> 3) & 0x7;
EvIb(pMyDisasm);
if (GV.REGOPCODE == 0) {
if ((*pMyDisasm).Prefix.LockPrefix == InvalidPrefix) {
(*pMyDisasm).Prefix.LockPrefix = InUsePrefix;
}
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+ARITHMETIC_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "add ");
#endif
FillFlags(pMyDisasm, 5);
}
else if (GV.REGOPCODE == 1) {
if ((*pMyDisasm).Prefix.LockPrefix == InvalidPrefix) {
(*pMyDisasm).Prefix.LockPrefix = InUsePrefix;
}
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+LOGICAL_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "or ");
#endif
FillFlags(pMyDisasm, 74);
}
else if (GV.REGOPCODE == 2) {
if ((*pMyDisasm).Prefix.LockPrefix == InvalidPrefix) {
(*pMyDisasm).Prefix.LockPrefix = InUsePrefix;
}
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+ARITHMETIC_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "adc ");
#endif
FillFlags(pMyDisasm, 4);
}
else if (GV.REGOPCODE == 3) {
if ((*pMyDisasm).Prefix.LockPrefix == InvalidPrefix) {
(*pMyDisasm).Prefix.LockPrefix = InUsePrefix;
}
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+ARITHMETIC_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "sbb ");
#endif
FillFlags(pMyDisasm, 93);
}
else if (GV.REGOPCODE == 4) {
if ((*pMyDisasm).Prefix.LockPrefix == InvalidPrefix) {
(*pMyDisasm).Prefix.LockPrefix = InUsePrefix;
}
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+LOGICAL_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "and ");
#endif
FillFlags(pMyDisasm, 6);
}
else if (GV.REGOPCODE == 5) {
if ((*pMyDisasm).Prefix.LockPrefix == InvalidPrefix) {
(*pMyDisasm).Prefix.LockPrefix = InUsePrefix;
}
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+ARITHMETIC_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "sub ");
#endif
FillFlags(pMyDisasm, 103);
}
else if (GV.REGOPCODE == 6) {
if ((*pMyDisasm).Prefix.LockPrefix == InvalidPrefix) {
(*pMyDisasm).Prefix.LockPrefix = InUsePrefix;
}
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+LOGICAL_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "xor ");
#endif
FillFlags(pMyDisasm, 113);
}
else if (GV.REGOPCODE == 7) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+ARITHMETIC_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "cmp ");
#endif
FillFlags(pMyDisasm, 20);
(*pMyDisasm).Argument1.AccessMode = READ;
}
}

195
deps/beaengine-4.1/beaengineSources/Includes/instr_set/opcodes_Grp12.c vendored
View File

@ -1,195 +0,0 @@
/* Copyright 2006-2009, BeatriX
* File coded by BeatriX
*
* This file is part of BeaEngine.
*
* BeaEngine is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BeaEngine is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with BeaEngine. If not, see <http://www.gnu.org/licenses/>. */
/* ====================================================================
*
* ==================================================================== */
void __bea_callspec__ G12_(PDISASM pMyDisasm)
{
long MyNumber;
GV.REGOPCODE = ((*((UInt8*)(UIntPtr) (GV.EIP_+1))) >> 3) & 0x7;
if (GV.REGOPCODE == 2) {
if (GV.OperandSize == 16) {
(*pMyDisasm).Instruction.Category = SSE_INSTRUCTION+SHIFT_ROTATE;
GV.MemDecoration = Arg1dqword;
GV.ImmediatSize = 8;
GV.SSE_ = 1;
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
GV.SSE_ = 0;
if (GV.MOD_== 0x3) {
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "psrlw ");
#endif
}
else {
FailDecode(pMyDisasm);
}
GV.EIP_ += GV.DECALAGE_EIP+3;
if (!Security(0, pMyDisasm)) return;
MyNumber = *((UInt8*)(UIntPtr) (GV.EIP_-1));
#ifndef BEA_LIGHT_DISASSEMBLY
(void) CopyFormattedNumber(pMyDisasm, (char*) &(*pMyDisasm).Argument2.ArgMnemonic,"%.2X",(Int64) MyNumber);
#endif
(*pMyDisasm).Instruction.Immediat = MyNumber;
(*pMyDisasm).Argument2.ArgType = CONSTANT_TYPE+ABSOLUTE_;
(*pMyDisasm).Argument2.ArgSize = 8;
}
else {
(*pMyDisasm).Instruction.Category = MMX_INSTRUCTION+SHIFT_ROTATE;
GV.MemDecoration = Arg1qword;
GV.ImmediatSize = 8;
GV.MMX_ = 1;
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
GV.MMX_ = 0;
if (GV.MOD_== 0x3) {
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "psrlw ");
#endif
}
else {
FailDecode(pMyDisasm);
}
GV.EIP_ += GV.DECALAGE_EIP+3;
if (!Security(0, pMyDisasm)) return;
MyNumber = *((UInt8*)(UIntPtr) (GV.EIP_-1));
#ifndef BEA_LIGHT_DISASSEMBLY
(void) CopyFormattedNumber(pMyDisasm, (char*) &(*pMyDisasm).Argument2.ArgMnemonic,"%.2X",(Int64) MyNumber);
#endif
(*pMyDisasm).Instruction.Immediat = MyNumber;
(*pMyDisasm).Argument2.ArgType = CONSTANT_TYPE+ABSOLUTE_;
(*pMyDisasm).Argument2.ArgSize = 8;
}
}
else if (GV.REGOPCODE == 4) {
if (GV.OperandSize == 16) {
(*pMyDisasm).Instruction.Category = SSE_INSTRUCTION+SHIFT_ROTATE;
GV.MemDecoration = Arg1dqword;
GV.ImmediatSize = 8;
GV.SSE_ = 1;
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
GV.SSE_ = 0;
if (GV.MOD_== 0x3) {
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "psraw ");
#endif
}
else {
FailDecode(pMyDisasm);
}
GV.EIP_ += GV.DECALAGE_EIP+3;
if (!Security(0, pMyDisasm)) return;
MyNumber = *((UInt8*)(UIntPtr) (GV.EIP_-1));
#ifndef BEA_LIGHT_DISASSEMBLY
(void) CopyFormattedNumber(pMyDisasm, (char*) &(*pMyDisasm).Argument2.ArgMnemonic,"%.2X",(Int64) MyNumber);
#endif
(*pMyDisasm).Instruction.Immediat = MyNumber;
(*pMyDisasm).Argument2.ArgType = CONSTANT_TYPE+ABSOLUTE_;
(*pMyDisasm).Argument2.ArgSize = 8;
}
else {
(*pMyDisasm).Instruction.Category = MMX_INSTRUCTION+SHIFT_ROTATE;
GV.MemDecoration = Arg1qword;
GV.ImmediatSize = 8;
GV.MMX_ = 1;
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
GV.MMX_ = 0;
if (GV.MOD_== 0x3) {
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "psraw ");
#endif
}
else {
FailDecode(pMyDisasm);
}
GV.EIP_ += GV.DECALAGE_EIP+3;
if (!Security(0, pMyDisasm)) return;
MyNumber = *((UInt8*)(UIntPtr) (GV.EIP_-1));
#ifndef BEA_LIGHT_DISASSEMBLY
(void) CopyFormattedNumber(pMyDisasm, (char*) &(*pMyDisasm).Argument2.ArgMnemonic,"%.2X",(Int64) MyNumber);
#endif
(*pMyDisasm).Instruction.Immediat = MyNumber;
(*pMyDisasm).Argument2.ArgType = CONSTANT_TYPE+ABSOLUTE_;
(*pMyDisasm).Argument2.ArgSize = 8;
}
}
else if (GV.REGOPCODE == 6) {
if (GV.OperandSize == 16) {
(*pMyDisasm).Instruction.Category = SSE_INSTRUCTION+SHIFT_ROTATE;
GV.MemDecoration = Arg1dqword;
GV.ImmediatSize = 8;
GV.SSE_ = 1;
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
GV.SSE_ = 0;
if (GV.MOD_== 0x3) {
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "psllw ");
#endif
}
else {
FailDecode(pMyDisasm);
}
GV.EIP_ += GV.DECALAGE_EIP+3;
if (!Security(0, pMyDisasm)) return;
MyNumber = *((UInt8*)(UIntPtr) (GV.EIP_-1));
#ifndef BEA_LIGHT_DISASSEMBLY
(void) CopyFormattedNumber(pMyDisasm, (char*) &(*pMyDisasm).Argument2.ArgMnemonic,"%.2X",(Int64) MyNumber);
#endif
(*pMyDisasm).Instruction.Immediat = MyNumber;
(*pMyDisasm).Argument2.ArgType = CONSTANT_TYPE+ABSOLUTE_;
(*pMyDisasm).Argument2.ArgSize = 8;
}
else {
(*pMyDisasm).Instruction.Category = MMX_INSTRUCTION+SHIFT_ROTATE;
GV.MemDecoration = Arg1qword;
GV.ImmediatSize = 8;
GV.MMX_ = 1;
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
GV.MMX_ = 0;
if (GV.MOD_== 0x3) {
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "psllw ");
#endif
}
else {
FailDecode(pMyDisasm);
}
GV.EIP_ += GV.DECALAGE_EIP+3;
if (!Security(0, pMyDisasm)) return;
MyNumber = *((UInt8*)(UIntPtr) (GV.EIP_-1));
#ifndef BEA_LIGHT_DISASSEMBLY
(void) CopyFormattedNumber(pMyDisasm, (char*) &(*pMyDisasm).Argument2.ArgMnemonic,"%.2X",(Int64) MyNumber);
#endif
(*pMyDisasm).Instruction.Immediat = MyNumber;
(*pMyDisasm).Argument2.ArgType = CONSTANT_TYPE+ABSOLUTE_;
(*pMyDisasm).Argument2.ArgSize = 8;
}
}
else {
FailDecode(pMyDisasm);
}
}

194
deps/beaengine-4.1/beaengineSources/Includes/instr_set/opcodes_Grp13.c vendored
View File

@ -1,194 +0,0 @@
/* Copyright 2006-2009, BeatriX
* File coded by BeatriX
*
* This file is part of BeaEngine.
*
* BeaEngine is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BeaEngine is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with BeaEngine. If not, see <http://www.gnu.org/licenses/>. */
/* ====================================================================
*
* ==================================================================== */
void __bea_callspec__ G13_(PDISASM pMyDisasm)
{
long MyNumber;
GV.REGOPCODE = ((*((UInt8*)(UIntPtr) (GV.EIP_+1))) >> 3) & 0x7;
if (GV.REGOPCODE == 2) {
if (GV.OperandSize == 16) {
(*pMyDisasm).Instruction.Category = SSE_INSTRUCTION+SHIFT_ROTATE;
GV.MemDecoration = Arg1dqword;
GV.ImmediatSize = 8;
GV.SSE_ = 1;
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
GV.SSE_ = 0;
if (GV.MOD_== 0x3) {
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "psrld ");
#endif
}
else {
FailDecode(pMyDisasm);
}
GV.EIP_ += GV.DECALAGE_EIP+3;
if (!Security(0, pMyDisasm)) return;
MyNumber = *((UInt8*)(UIntPtr) (GV.EIP_-1));
#ifndef BEA_LIGHT_DISASSEMBLY
(void) CopyFormattedNumber(pMyDisasm, (char*) &(*pMyDisasm).Argument2.ArgMnemonic,"%.2X",(Int64) MyNumber);
#endif
(*pMyDisasm).Instruction.Immediat = MyNumber;
(*pMyDisasm).Argument2.ArgType = CONSTANT_TYPE+ABSOLUTE_;
(*pMyDisasm).Argument2.ArgSize = 8;
}
else {
(*pMyDisasm).Instruction.Category = MMX_INSTRUCTION+SHIFT_ROTATE;
GV.MemDecoration = Arg1qword;
GV.ImmediatSize = 8;
GV.MMX_ = 1;
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
GV.MMX_ = 0;
if (GV.MOD_== 0x3) {
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "psrld ");
#endif
}
else {
FailDecode(pMyDisasm);
}
GV.EIP_ += GV.DECALAGE_EIP+3;
if (!Security(0, pMyDisasm)) return;
MyNumber = *((UInt8*)(UIntPtr) (GV.EIP_-1));
#ifndef BEA_LIGHT_DISASSEMBLY
(void) CopyFormattedNumber(pMyDisasm, (char*) &(*pMyDisasm).Argument2.ArgMnemonic,"%.2X",(Int64) MyNumber);
#endif
(*pMyDisasm).Instruction.Immediat = MyNumber;
(*pMyDisasm).Argument2.ArgType = CONSTANT_TYPE+ABSOLUTE_;
(*pMyDisasm).Argument2.ArgSize = 8;
}
}
else if (GV.REGOPCODE == 4) {
if (GV.OperandSize == 16) {
(*pMyDisasm).Instruction.Category = SSE_INSTRUCTION+SHIFT_ROTATE;
GV.MemDecoration = Arg1dqword;
GV.ImmediatSize = 8;
GV.SSE_ = 1;
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
GV.SSE_ = 0;
if (GV.MOD_== 0x3) {
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "psrad ");
#endif
}
else {
FailDecode(pMyDisasm);
}
GV.EIP_ += GV.DECALAGE_EIP+3;
if (!Security(0, pMyDisasm)) return;
MyNumber = *((UInt8*)(UIntPtr) (GV.EIP_-1));
#ifndef BEA_LIGHT_DISASSEMBLY
(void) CopyFormattedNumber(pMyDisasm, (char*) &(*pMyDisasm).Argument2.ArgMnemonic,"%.2X",(Int64) MyNumber);
#endif
(*pMyDisasm).Instruction.Immediat = MyNumber;
(*pMyDisasm).Argument2.ArgType = CONSTANT_TYPE+ABSOLUTE_;
(*pMyDisasm).Argument2.ArgSize = 8;
}
else {
(*pMyDisasm).Instruction.Category = MMX_INSTRUCTION+SHIFT_ROTATE;
GV.MemDecoration = Arg1qword;
GV.ImmediatSize = 8;
GV.MMX_ = 1;
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
GV.MMX_ = 0;
if (GV.MOD_== 0x3) {
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "psrad ");
#endif
}
else {
FailDecode(pMyDisasm);
}
GV.EIP_ += GV.DECALAGE_EIP+3;
if (!Security(0, pMyDisasm)) return;
MyNumber = *((UInt8*)(UIntPtr) (GV.EIP_-1));
#ifndef BEA_LIGHT_DISASSEMBLY
(void) CopyFormattedNumber(pMyDisasm, (char*) &(*pMyDisasm).Argument2.ArgMnemonic,"%.2X",(Int64) MyNumber);
#endif
(*pMyDisasm).Instruction.Immediat = MyNumber;
(*pMyDisasm).Argument2.ArgType = CONSTANT_TYPE+ABSOLUTE_;
(*pMyDisasm).Argument2.ArgSize = 8;
}
}
else if (GV.REGOPCODE == 6) {
if (GV.OperandSize == 16) {
(*pMyDisasm).Instruction.Category = SSE_INSTRUCTION+SHIFT_ROTATE;
GV.MemDecoration = Arg1dqword;
GV.ImmediatSize = 8;
GV.SSE_ = 1;
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
GV.SSE_ = 0;
if (GV.MOD_== 0x3) {
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "pslld ");
#endif
}
else {
FailDecode(pMyDisasm);
}
GV.EIP_ += GV.DECALAGE_EIP+3;
if (!Security(0, pMyDisasm)) return;
MyNumber = *((UInt8*)(UIntPtr) (GV.EIP_-1));
#ifndef BEA_LIGHT_DISASSEMBLY
(void) CopyFormattedNumber(pMyDisasm, (char*) &(*pMyDisasm).Argument2.ArgMnemonic,"%.2X",(Int64) MyNumber);
#endif
(*pMyDisasm).Instruction.Immediat = MyNumber;
(*pMyDisasm).Argument2.ArgType = CONSTANT_TYPE+ABSOLUTE_;
(*pMyDisasm).Argument2.ArgSize = 8;
}
else {
(*pMyDisasm).Instruction.Category = MMX_INSTRUCTION+SHIFT_ROTATE;
GV.MemDecoration = Arg1qword;
GV.ImmediatSize = 8;
GV.MMX_ = 1;
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
GV.MMX_ = 0;
if (GV.MOD_== 0x3) {
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "pslld ");
#endif
}
else {
FailDecode(pMyDisasm);
}
GV.EIP_ += GV.DECALAGE_EIP+3;
if (!Security(0, pMyDisasm)) return;
MyNumber = *((UInt8*)(UIntPtr) (GV.EIP_-1));
#ifndef BEA_LIGHT_DISASSEMBLY
(void) CopyFormattedNumber(pMyDisasm, (char*) &(*pMyDisasm).Argument2.ArgMnemonic,"%.2X",(Int64) MyNumber);
#endif
(*pMyDisasm).Instruction.Immediat = MyNumber;
(*pMyDisasm).Argument2.ArgType = CONSTANT_TYPE+ABSOLUTE_;
(*pMyDisasm).Argument2.ArgSize = 8;
}
}
else {
FailDecode(pMyDisasm);
}
}

203
deps/beaengine-4.1/beaengineSources/Includes/instr_set/opcodes_Grp14.c vendored
View File

@ -1,203 +0,0 @@
/* Copyright 2006-2009, BeatriX
* File coded by BeatriX
*
* This file is part of BeaEngine.
*
* BeaEngine is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BeaEngine is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with BeaEngine. If not, see <http://www.gnu.org/licenses/>. */
/* ====================================================================
*
* ==================================================================== */
void __bea_callspec__ G14_(PDISASM pMyDisasm)
{
long MyNumber;
GV.REGOPCODE = ((*((UInt8*)(UIntPtr) (GV.EIP_+1))) >> 3) & 0x7;
if (GV.REGOPCODE == 2) {
if (GV.OperandSize == 16) {
(*pMyDisasm).Instruction.Category = SSE_INSTRUCTION+SHIFT_ROTATE;
GV.MemDecoration = Arg1dqword;
GV.ImmediatSize = 8;
GV.SSE_ = 1;
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
GV.SSE_ = 0;
if (GV.MOD_== 0x3) {
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "psrlq ");
#endif
}
else {
FailDecode(pMyDisasm);
}
GV.EIP_ += GV.DECALAGE_EIP+3;
if (!Security(0, pMyDisasm)) return;
MyNumber = *((UInt8*)(UIntPtr) (GV.EIP_-1));
#ifndef BEA_LIGHT_DISASSEMBLY
(void) CopyFormattedNumber(pMyDisasm, (char*) &(*pMyDisasm).Argument2.ArgMnemonic,"%.2X",(Int64) MyNumber);
#endif
(*pMyDisasm).Instruction.Immediat = MyNumber;
(*pMyDisasm).Argument2.ArgType = CONSTANT_TYPE+ABSOLUTE_;
(*pMyDisasm).Argument2.ArgSize = 8;
}
else {
(*pMyDisasm).Instruction.Category = MMX_INSTRUCTION+SHIFT_ROTATE;
GV.MemDecoration = Arg1qword;
GV.ImmediatSize = 8;
GV.MMX_ = 1;
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
GV.MMX_ = 0;
if (GV.MOD_== 0x3) {
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "psrlq ");
#endif
}
else {
FailDecode(pMyDisasm);
}
GV.EIP_ += GV.DECALAGE_EIP+3;
if (!Security(0, pMyDisasm)) return;
MyNumber = *((UInt8*)(UIntPtr) (GV.EIP_-1));
#ifndef BEA_LIGHT_DISASSEMBLY
(void) CopyFormattedNumber(pMyDisasm, (char*) &(*pMyDisasm).Argument2.ArgMnemonic,"%.2X",(Int64) MyNumber);
#endif
(*pMyDisasm).Instruction.Immediat = MyNumber;
(*pMyDisasm).Argument2.ArgType = CONSTANT_TYPE+ABSOLUTE_;
(*pMyDisasm).Argument2.ArgSize = 8;
}
}
else if (GV.REGOPCODE == 3) {
if (GV.OperandSize == 16) {
(*pMyDisasm).Instruction.Category = SSE_INSTRUCTION+SHIFT_ROTATE;
GV.MemDecoration = Arg1dqword;
GV.ImmediatSize = 8;
GV.SSE_ = 1;
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
GV.SSE_ = 0;
if (GV.MOD_== 0x3) {
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "psrldq ");
#endif
}
else {
FailDecode(pMyDisasm);
}
GV.EIP_ += GV.DECALAGE_EIP+3;
if (!Security(0, pMyDisasm)) return;
MyNumber = *((UInt8*)(UIntPtr) (GV.EIP_-1));
#ifndef BEA_LIGHT_DISASSEMBLY
(void) CopyFormattedNumber(pMyDisasm, (char*) &(*pMyDisasm).Argument2.ArgMnemonic,"%.2X",(Int64) MyNumber);
#endif
(*pMyDisasm).Instruction.Immediat = MyNumber;
(*pMyDisasm).Argument2.ArgType = CONSTANT_TYPE+ABSOLUTE_;
(*pMyDisasm).Argument2.ArgSize = 8;
}
else {
FailDecode(pMyDisasm);
}
}
else if (GV.REGOPCODE == 6) {
if (GV.OperandSize == 16) {
(*pMyDisasm).Instruction.Category = SSE_INSTRUCTION+SHIFT_ROTATE;
GV.MemDecoration = Arg1dqword;
GV.ImmediatSize = 8;
GV.SSE_ = 1;
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
GV.SSE_ = 0;
if (GV.MOD_== 0x3) {
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "psllq ");
#endif
}
else {
FailDecode(pMyDisasm);
}
GV.EIP_ += GV.DECALAGE_EIP+3;
if (!Security(0, pMyDisasm)) return;
MyNumber = *((UInt8*)(UIntPtr) (GV.EIP_-1));
#ifndef BEA_LIGHT_DISASSEMBLY
(void) CopyFormattedNumber(pMyDisasm, (char*) &(*pMyDisasm).Argument2.ArgMnemonic,"%.2X",(Int64) MyNumber);
#endif
(*pMyDisasm).Instruction.Immediat = MyNumber;
(*pMyDisasm).Argument2.ArgType = CONSTANT_TYPE+ABSOLUTE_;
(*pMyDisasm).Argument2.ArgSize = 8;
}
else {
(*pMyDisasm).Instruction.Category = MMX_INSTRUCTION+SHIFT_ROTATE;
GV.MemDecoration = Arg1qword;
GV.ImmediatSize = 8;
GV.MMX_ = 1;
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
GV.MMX_ = 0;
if (GV.MOD_== 0x3) {
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "psllq ");
#endif
}
else {
FailDecode(pMyDisasm);
}
GV.EIP_ += GV.DECALAGE_EIP+3;
if (!Security(0, pMyDisasm)) return;
MyNumber = *((UInt8*)(UIntPtr) (GV.EIP_-1));
#ifndef BEA_LIGHT_DISASSEMBLY
(void) CopyFormattedNumber(pMyDisasm, (char*) &(*pMyDisasm).Argument2.ArgMnemonic,"%.2X",(Int64) MyNumber);
#endif
(*pMyDisasm).Instruction.Immediat = MyNumber;
(*pMyDisasm).Argument2.ArgType = CONSTANT_TYPE+ABSOLUTE_;
(*pMyDisasm).Argument2.ArgSize = 8;
}
}
else if (GV.REGOPCODE == 7) {
if (GV.OperandSize == 16) {
(*pMyDisasm).Instruction.Category = SSE_INSTRUCTION+SHIFT_ROTATE;
GV.MemDecoration = Arg1dqword;
GV.ImmediatSize = 8;
GV.SSE_ = 1;
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
GV.SSE_ = 0;
if (GV.MOD_== 0x3) {
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "pslldq ");
#endif
}
else {
FailDecode(pMyDisasm);
}
GV.EIP_ += GV.DECALAGE_EIP+3;
if (!Security(0, pMyDisasm)) return;
MyNumber = *((UInt8*)(UIntPtr) (GV.EIP_-1));
#ifndef BEA_LIGHT_DISASSEMBLY
(void) CopyFormattedNumber(pMyDisasm, (char*) &(*pMyDisasm).Argument2.ArgMnemonic,"%.2X",(Int64) MyNumber);
#endif
(*pMyDisasm).Instruction.Immediat = MyNumber;
(*pMyDisasm).Argument2.ArgType = CONSTANT_TYPE+ABSOLUTE_;
(*pMyDisasm).Argument2.ArgSize = 8;
}
else {
FailDecode(pMyDisasm);
}
}
else {
FailDecode(pMyDisasm);
}
}

166
deps/beaengine-4.1/beaengineSources/Includes/instr_set/opcodes_Grp15.c vendored
View File

@ -1,166 +0,0 @@
/* Copyright 2006-2009, BeatriX
* File coded by BeatriX
*
* This file is part of BeaEngine.
*
* BeaEngine is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BeaEngine is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with BeaEngine. If not, see <http://www.gnu.org/licenses/>. */
/* ====================================================================
*
* ==================================================================== */
void __bea_callspec__ G15_(PDISASM pMyDisasm)
{
GV.REGOPCODE = ((*((UInt8*)(UIntPtr) (GV.EIP_+1))) >> 3) & 0x7;
if (GV.REGOPCODE == 0) {
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
if (GV.MOD_!= 0x3) {
GV.MemDecoration = Arg1multibytes;
(*pMyDisasm).Instruction.Category = FPU_INSTRUCTION+STATE_MANAGEMENT;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "fxsave ");
#endif
(*pMyDisasm).Argument1.ArgSize = 512;
(*pMyDisasm).Argument2.ArgType = REGISTER_TYPE+FPU_REG+MMX_REG+SSE_REG;
(*pMyDisasm).Argument2.ArgSize = 512;
}
else {
FailDecode(pMyDisasm);
}
}
else if (GV.REGOPCODE == 1) {
MOD_RM(&(*pMyDisasm).Argument2, pMyDisasm);
if (GV.MOD_!= 0x3) {
GV.MemDecoration = Arg2multibytes;
(*pMyDisasm).Instruction.Category = FPU_INSTRUCTION+STATE_MANAGEMENT;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "fxrstor ");
#endif
(*pMyDisasm).Argument2.ArgSize = 512;
(*pMyDisasm).Argument1.ArgType = REGISTER_TYPE+FPU_REG+MMX_REG+SSE_REG;
(*pMyDisasm).Argument1.ArgSize = 512;
}
else {
FailDecode(pMyDisasm);
}
}
else if (GV.REGOPCODE == 2) {
MOD_RM(&(*pMyDisasm).Argument2, pMyDisasm);
if (GV.MOD_!= 0x3) {
GV.MemDecoration = Arg2dword;
(*pMyDisasm).Instruction.Category = SSE_INSTRUCTION+STATE_MANAGEMENT;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "ldmxcsr ");
#endif
(*pMyDisasm).Argument1.ArgType = REGISTER_TYPE+SPECIAL_REG+REG1;
(*pMyDisasm).Argument1.ArgSize = 32;
}
else {
FailDecode(pMyDisasm);
}
}
else if (GV.REGOPCODE == 3) {
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
if (GV.MOD_!= 0x3) {
GV.MemDecoration = Arg1dword;
(*pMyDisasm).Instruction.Category = SSE_INSTRUCTION+STATE_MANAGEMENT;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "stmxcsr ");
#endif
(*pMyDisasm).Argument2.ArgType = REGISTER_TYPE+SPECIAL_REG+REG1;
(*pMyDisasm).Argument2.ArgSize = 32;
}
else {
FailDecode(pMyDisasm);
}
}
else if (GV.REGOPCODE == 4) {
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
if (GV.MOD_!= 0x3) {
GV.MemDecoration = Arg1multibytes;
(*pMyDisasm).Instruction.Category = FPU_INSTRUCTION+STATE_MANAGEMENT;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "xsave ");
#endif
(*pMyDisasm).Argument1.ArgSize = 512;
(*pMyDisasm).Argument2.ArgType = REGISTER_TYPE+FPU_REG+MMX_REG+SSE_REG;
(*pMyDisasm).Argument2.ArgSize = 512;
}
else {
FailDecode(pMyDisasm);
}
}
else if (GV.REGOPCODE == 5) {
GV.MOD_= ((*((UInt8*)(UIntPtr) (GV.EIP_+1))) >> 6) & 0x3;
if (GV.MOD_== 0x3) {
(*pMyDisasm).Instruction.Category = SSE2_INSTRUCTION+CACHEABILITY_CONTROL;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "lfence ");
#endif
}
else {
MOD_RM(&(*pMyDisasm).Argument2, pMyDisasm);
GV.MemDecoration = Arg2multibytes;
(*pMyDisasm).Instruction.Category = FPU_INSTRUCTION+STATE_MANAGEMENT;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "xrstor ");
#endif
(*pMyDisasm).Argument2.ArgSize = 512;
(*pMyDisasm).Argument1.ArgType = REGISTER_TYPE+FPU_REG+MMX_REG+SSE_REG;
(*pMyDisasm).Argument1.ArgSize = 512;
}
}
else if (GV.REGOPCODE == 6) {
GV.MOD_= ((*((UInt8*)(UIntPtr) (GV.EIP_+1))) >> 6) & 0x3;
if (GV.MOD_== 0x3) {
(*pMyDisasm).Instruction.Category = SSE2_INSTRUCTION+CACHEABILITY_CONTROL;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "mfence ");
#endif
}
else {
FailDecode(pMyDisasm);
}
}
else if (GV.REGOPCODE == 7) {
GV.MOD_= ((*((UInt8*)(UIntPtr) (GV.EIP_+1))) >> 6) & 0x3;
if (GV.MOD_== 0x3) {
(*pMyDisasm).Instruction.Category = SSE2_INSTRUCTION+CACHEABILITY_CONTROL;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "sfence ");
#endif
}
else {
GV.OperandSize = 8;
MOD_RM(&(*pMyDisasm).Argument2, pMyDisasm);
GV.OperandSize = 32;
GV.MemDecoration = Arg2byte;
(*pMyDisasm).Instruction.Category = SSE2_INSTRUCTION+CACHEABILITY_CONTROL;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "clflush ");
#endif
}
}
else {
FailDecode(pMyDisasm);
}
GV.EIP_+= GV.DECALAGE_EIP+2;
}

85
deps/beaengine-4.1/beaengineSources/Includes/instr_set/opcodes_Grp16.c vendored
View File

@ -1,85 +0,0 @@
/* Copyright 2006-2009, BeatriX
* File coded by BeatriX
*
* This file is part of BeaEngine.
*
* BeaEngine is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BeaEngine is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with BeaEngine. If not, see <http://www.gnu.org/licenses/>. */
/* ====================================================================
*
* ==================================================================== */
void __bea_callspec__ G16_(PDISASM pMyDisasm)
{
GV.REGOPCODE = ((*((UInt8*)(UIntPtr) (GV.EIP_+1))) >> 3) & 0x7;
if (GV.REGOPCODE == 0) {
MOD_RM(&(*pMyDisasm).Argument2, pMyDisasm);
if (GV.MOD_!= 0x3) {
GV.MemDecoration = Arg2byte;
(*pMyDisasm).Instruction.Category = SSE_INSTRUCTION+CACHEABILITY_CONTROL;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "prefetchNTA ");
#endif
}
else {
FailDecode(pMyDisasm);
}
}
else if (GV.REGOPCODE == 1) {
MOD_RM(&(*pMyDisasm).Argument2, pMyDisasm);
if (GV.MOD_!= 0x3) {
GV.MemDecoration = Arg2byte;
(*pMyDisasm).Instruction.Category = SSE_INSTRUCTION+CACHEABILITY_CONTROL;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "prefetchT0 ");
#endif
}
else {
FailDecode(pMyDisasm);
}
}
else if (GV.REGOPCODE == 2) {
MOD_RM(&(*pMyDisasm).Argument2, pMyDisasm);
if (GV.MOD_!= 0x3) {
GV.MemDecoration = Arg2byte;
(*pMyDisasm).Instruction.Category = SSE_INSTRUCTION+CACHEABILITY_CONTROL;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "prefetchT1 ");
#endif
}
else {
FailDecode(pMyDisasm);
}
}
else if (GV.REGOPCODE == 3) {
MOD_RM(&(*pMyDisasm).Argument2, pMyDisasm);
if (GV.MOD_!= 0x3) {
GV.MemDecoration = Arg2byte;
(*pMyDisasm).Instruction.Category = SSE_INSTRUCTION+CACHEABILITY_CONTROL;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "prefetchT2 ");
#endif
}
else {
FailDecode(pMyDisasm);
}
}
else {
FailDecode(pMyDisasm);
}
GV.EIP_+= GV.DECALAGE_EIP+2;
}

461
deps/beaengine-4.1/beaengineSources/Includes/instr_set/opcodes_Grp2.c vendored
View File

@ -1,461 +0,0 @@
/* Copyright 2006-2009, BeatriX
* File coded by BeatriX
*
* This file is part of BeaEngine.
*
* BeaEngine is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BeaEngine is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with BeaEngine. If not, see <http://www.gnu.org/licenses/>. */
/* ====================================================================
* 0c0h
* ==================================================================== */
void __bea_callspec__ G2_EbIb(PDISASM pMyDisasm)
{
GV.REGOPCODE = ((*((UInt8*)(UIntPtr) (GV.EIP_+1))) >> 3) & 0x7;
EbIb(pMyDisasm);
if (GV.REGOPCODE == 0) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "rol ");
#endif
FillFlags(pMyDisasm, 88);
}
else if (GV.REGOPCODE == 1) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "ror ");
#endif
FillFlags(pMyDisasm, 88);
}
else if (GV.REGOPCODE == 2) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "rcl ");
#endif
FillFlags(pMyDisasm, 81);
}
else if (GV.REGOPCODE == 3) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "rcr ");
#endif
FillFlags(pMyDisasm, 81);
}
else if (GV.REGOPCODE == 4) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "shl ");
#endif
FillFlags(pMyDisasm, 92);
}
else if (GV.REGOPCODE == 5) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "shr ");
#endif
FillFlags(pMyDisasm, 92);
}
else if (GV.REGOPCODE == 6) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "sal ");
#endif
FillFlags(pMyDisasm, 92);
}
else if (GV.REGOPCODE == 7) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "sar ");
#endif
FillFlags(pMyDisasm, 92);
}
}
/* ====================================================================
* 0c1h
* ==================================================================== */
void __bea_callspec__ G2_EvIb(PDISASM pMyDisasm)
{
GV.REGOPCODE = ((*((UInt8*)(UIntPtr) (GV.EIP_+1))) >> 3) & 0x7;
EvIb(pMyDisasm);
if (GV.REGOPCODE == 0) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "rol ");
#endif
FillFlags(pMyDisasm, 88);
}
else if (GV.REGOPCODE == 1) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "ror ");
#endif
FillFlags(pMyDisasm, 88);
}
else if (GV.REGOPCODE == 2) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "rcl ");
#endif
FillFlags(pMyDisasm, 81);
}
else if (GV.REGOPCODE == 3) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "rcr ");
#endif
FillFlags(pMyDisasm, 81);
}
else if (GV.REGOPCODE == 4) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "shl ");
#endif
FillFlags(pMyDisasm, 92);
}
else if (GV.REGOPCODE == 5) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "shr ");
#endif
FillFlags(pMyDisasm, 92);
}
else if (GV.REGOPCODE == 6) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "sal ");
#endif
FillFlags(pMyDisasm, 92);
}
else if (GV.REGOPCODE == 7) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "sar ");
#endif
FillFlags(pMyDisasm, 92);
}
}
/* ====================================================================
* 0d0h
* ==================================================================== */
void __bea_callspec__ G2_Eb1(PDISASM pMyDisasm)
{
GV.REGOPCODE = ((*((UInt8*)(UIntPtr) (GV.EIP_+1))) >> 3) & 0x7;
GV.MemDecoration = Arg1byte;
GV.OperandSize = 8;
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
GV.OperandSize = 32;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Argument2.ArgMnemonic, "1 ");
#endif
(*pMyDisasm).Argument2.ArgType = CONSTANT_TYPE+ABSOLUTE_;
(*pMyDisasm).Argument2.ArgSize = 8;
(*pMyDisasm).Instruction.Immediat = 1;
if (GV.REGOPCODE == 0) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "rol ");
#endif
FillFlags(pMyDisasm, 87);
}
else if (GV.REGOPCODE == 1) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "ror ");
#endif
FillFlags(pMyDisasm, 87);
}
else if (GV.REGOPCODE == 2) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "rcl ");
#endif
FillFlags(pMyDisasm, 80);
}
else if (GV.REGOPCODE == 3) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "rcr ");
#endif
FillFlags(pMyDisasm, 80);
}
else if (GV.REGOPCODE == 4) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "shl ");
#endif
FillFlags(pMyDisasm, 91);
}
else if (GV.REGOPCODE == 5) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "shr ");
#endif
FillFlags(pMyDisasm, 91);
}
else if (GV.REGOPCODE == 6) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "sal ");
#endif
FillFlags(pMyDisasm, 91);
}
else if (GV.REGOPCODE == 7) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "sar ");
#endif
FillFlags(pMyDisasm, 91);
}
GV.EIP_ += GV.DECALAGE_EIP+2;
}
/* ====================================================================
* 0d1h
* ==================================================================== */
void __bea_callspec__ G2_Ev1(PDISASM pMyDisasm)
{
GV.REGOPCODE = ((*((UInt8*)(UIntPtr) (GV.EIP_+1))) >> 3) & 0x7;
if (GV.OperandSize == 64) {
GV.MemDecoration = Arg1qword;
}
else if (GV.OperandSize == 32) {
GV.MemDecoration = Arg1dword;
}
else {
GV.MemDecoration = Arg1word;
}
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Argument2.ArgMnemonic, "1 ");
#endif
(*pMyDisasm).Argument2.ArgType = CONSTANT_TYPE+ABSOLUTE_;
(*pMyDisasm).Argument2.ArgSize = 8;
(*pMyDisasm).Instruction.Immediat = 1;
if (GV.REGOPCODE == 0) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "rol ");
#endif
FillFlags(pMyDisasm, 87);
}
else if (GV.REGOPCODE == 1) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "ror ");
#endif
FillFlags(pMyDisasm, 87);
}
else if (GV.REGOPCODE == 2) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "rcl ");
#endif
FillFlags(pMyDisasm, 80);
}
else if (GV.REGOPCODE == 3) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "rcr ");
#endif
FillFlags(pMyDisasm, 80);
}
else if (GV.REGOPCODE == 4) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "shl ");
#endif
FillFlags(pMyDisasm, 91);
}
else if (GV.REGOPCODE == 5) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "shr ");
#endif
FillFlags(pMyDisasm, 91);
}
else if (GV.REGOPCODE == 6) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "sal ");
#endif
FillFlags(pMyDisasm, 91);
}
else if (GV.REGOPCODE == 7) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "sar ");
#endif
FillFlags(pMyDisasm, 91);
}
GV.EIP_ += GV.DECALAGE_EIP+2;
}
/* ====================================================================
* 0d2h
* ==================================================================== */
void __bea_callspec__ G2_EbCL(PDISASM pMyDisasm)
{
GV.REGOPCODE = ((*((UInt8*)(UIntPtr) (GV.EIP_+1))) >> 3) & 0x7;
GV.MemDecoration = Arg1byte;
GV.OperandSize = 8;
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
GV.OperandSize = 32;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Argument2.ArgMnemonic, Registers8Bits[1]);
#endif
(*pMyDisasm).Argument2.ArgType = REGISTER_TYPE+GENERAL_REG+REG1;
(*pMyDisasm).Argument2.ArgSize = 8;
if (GV.REGOPCODE == 0) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "rol ");
#endif
FillFlags(pMyDisasm, 88);
}
else if (GV.REGOPCODE == 1) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "ror ");
#endif
FillFlags(pMyDisasm, 88);
}
else if (GV.REGOPCODE == 2) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "rcl ");
#endif
FillFlags(pMyDisasm, 81);
}
else if (GV.REGOPCODE == 3) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "rcr ");
#endif
FillFlags(pMyDisasm, 81);
}
else if (GV.REGOPCODE == 4) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "shl ");
#endif
FillFlags(pMyDisasm, 92);
}
else if (GV.REGOPCODE == 5) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "shr ");
#endif
FillFlags(pMyDisasm, 92);
}
else if (GV.REGOPCODE == 6) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "sal ");
#endif
FillFlags(pMyDisasm, 92);
}
else if (GV.REGOPCODE == 7) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "sar ");
#endif
FillFlags(pMyDisasm, 92);
}
GV.EIP_ += GV.DECALAGE_EIP+2;
}
/* ====================================================================
* 0d3h
* ==================================================================== */
void __bea_callspec__ G2_EvCL(PDISASM pMyDisasm)
{
GV.REGOPCODE = ((*((UInt8*)(UIntPtr) (GV.EIP_+1))) >> 3) & 0x7;
if (GV.OperandSize == 64) {
GV.MemDecoration = Arg1qword;
}
else if (GV.OperandSize == 32) {
GV.MemDecoration = Arg1dword;
}
else {
GV.MemDecoration = Arg1word;
}
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Argument2.ArgMnemonic, Registers8Bits[1]);
#endif
(*pMyDisasm).Argument2.ArgType = REGISTER_TYPE+GENERAL_REG+REG1;
(*pMyDisasm).Argument2.ArgSize = 8;
if (GV.REGOPCODE == 0) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "rol ");
#endif
FillFlags(pMyDisasm, 88);
}
else if (GV.REGOPCODE == 1) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "ror ");
#endif
FillFlags(pMyDisasm, 88);
}
else if (GV.REGOPCODE == 2) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "rcl ");
#endif
FillFlags(pMyDisasm, 81);
}
else if (GV.REGOPCODE == 3) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "rcr ");
#endif
FillFlags(pMyDisasm, 81);
}
else if (GV.REGOPCODE == 4) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "shl ");
#endif
FillFlags(pMyDisasm, 92);
}
else if (GV.REGOPCODE == 5) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "shr ");
#endif
FillFlags(pMyDisasm, 92);
}
else if (GV.REGOPCODE == 6) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "sal ");
#endif
FillFlags(pMyDisasm, 92);
}
else if (GV.REGOPCODE == 7) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+SHIFT_ROTATE;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "sar ");
#endif
FillFlags(pMyDisasm, 92);
}
GV.EIP_ += GV.DECALAGE_EIP+2;
}

257
deps/beaengine-4.1/beaengineSources/Includes/instr_set/opcodes_Grp3.c vendored
View File

@ -1,257 +0,0 @@
/* Copyright 2006-2009, BeatriX
* File coded by BeatriX
*
* This file is part of BeaEngine.
*
* BeaEngine is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BeaEngine is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with BeaEngine. If not, see <http://www.gnu.org/licenses/>. */
/* ====================================================================
* 0f6h
* ==================================================================== */
void __bea_callspec__ G3_Eb(PDISASM pMyDisasm)
{
GV.REGOPCODE = ((*((UInt8*)(UIntPtr) (GV.EIP_+1))) >> 3) & 0x7;
if (GV.REGOPCODE == 0) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+BIT_UInt8;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "test ");
#endif
EbIb(pMyDisasm);
(*pMyDisasm).Argument1.AccessMode = READ;
FillFlags(pMyDisasm, 104);
}
else if (GV.REGOPCODE == 1) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+BIT_UInt8;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "test ");
#endif
EbIb(pMyDisasm);
(*pMyDisasm).Argument1.AccessMode = READ;
FillFlags(pMyDisasm, 104);
}
else if (GV.REGOPCODE == 2) {
if ((*pMyDisasm).Prefix.LockPrefix == InvalidPrefix) {
(*pMyDisasm).Prefix.LockPrefix = InUsePrefix;
}
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+LOGICAL_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "not ");
#endif
Eb(pMyDisasm);
FillFlags(pMyDisasm, 73);
}
else if (GV.REGOPCODE == 3) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+ARITHMETIC_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "neg ");
#endif
Eb(pMyDisasm);
FillFlags(pMyDisasm, 71);
}
else if (GV.REGOPCODE == 4) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+ARITHMETIC_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "mul ");
#endif
GV.MemDecoration = Arg2byte;
GV.OperandSize = 8;
MOD_RM(&(*pMyDisasm).Argument2, pMyDisasm);
GV.OperandSize = 32;
GV.EIP_ += GV.DECALAGE_EIP+2;
(*pMyDisasm).Argument1.ArgType = REGISTER_TYPE+GENERAL_REG+REG0+REG2;
(*pMyDisasm).Argument1.ArgSize = 8;
(*pMyDisasm).Instruction.ImplicitModifiedRegs = REGISTER_TYPE+GENERAL_REG+REG0;
FillFlags(pMyDisasm, 70);
}
else if (GV.REGOPCODE == 5) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+ARITHMETIC_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "imul ");
#endif
GV.MemDecoration = Arg2byte;
GV.OperandSize = 8;
MOD_RM(&(*pMyDisasm).Argument2, pMyDisasm);
GV.OperandSize = 32;
GV.EIP_ += GV.DECALAGE_EIP+2;
(*pMyDisasm).Argument1.ArgType = REGISTER_TYPE+GENERAL_REG+REG0+REG2;
(*pMyDisasm).Argument1.ArgSize = 8;
FillFlags(pMyDisasm, 38);
}
else if (GV.REGOPCODE == 6) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+ARITHMETIC_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "div ");
#endif
GV.MemDecoration = Arg2byte;
GV.OperandSize = 8;
MOD_RM(&(*pMyDisasm).Argument2, pMyDisasm);
GV.OperandSize = 32;
GV.EIP_ += GV.DECALAGE_EIP+2;
(*pMyDisasm).Argument1.ArgType = REGISTER_TYPE+GENERAL_REG+REG0+REG2;
(*pMyDisasm).Argument1.ArgSize = 8;
FillFlags(pMyDisasm, 31);
}
else if (GV.REGOPCODE == 7) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+ARITHMETIC_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "idiv ");
#endif
GV.MemDecoration = Arg2byte;
GV.OperandSize = 8;
MOD_RM(&(*pMyDisasm).Argument2, pMyDisasm);
GV.OperandSize = 32;
GV.EIP_ += GV.DECALAGE_EIP+2;
(*pMyDisasm).Argument1.ArgType = REGISTER_TYPE+GENERAL_REG+REG0+REG2;
(*pMyDisasm).Argument1.ArgSize = 8;
(*pMyDisasm).Instruction.ImplicitModifiedRegs = REGISTER_TYPE+GENERAL_REG+REG0;
FillFlags(pMyDisasm, 37);
}
}
/* ====================================================================
* 0f7h
* ==================================================================== */
void __bea_callspec__ G3_Ev(PDISASM pMyDisasm)
{
GV.REGOPCODE = ((*((UInt8*)(UIntPtr) (GV.EIP_+1))) >> 3) & 0x7;
if (GV.REGOPCODE == 0) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+BIT_UInt8;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "test ");
#endif
EvIv(pMyDisasm);
(*pMyDisasm).Argument1.AccessMode = READ;
FillFlags(pMyDisasm, 104);
}
else if (GV.REGOPCODE == 1) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+BIT_UInt8;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "test ");
#endif
EvIv(pMyDisasm);
(*pMyDisasm).Argument1.AccessMode = READ;
FillFlags(pMyDisasm, 104);
}
else if (GV.REGOPCODE == 2) {
if ((*pMyDisasm).Prefix.LockPrefix == InvalidPrefix) {
(*pMyDisasm).Prefix.LockPrefix = InUsePrefix;
}
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+LOGICAL_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "not ");
#endif
Ev(pMyDisasm);
FillFlags(pMyDisasm, 73);
}
else if (GV.REGOPCODE == 3) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+ARITHMETIC_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "neg ");
#endif
Ev(pMyDisasm);
FillFlags(pMyDisasm, 71);
}
else if (GV.REGOPCODE == 4) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+ARITHMETIC_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "mul ");
#endif
if (GV.OperandSize == 64) {
GV.MemDecoration = Arg2qword;
(*pMyDisasm).Argument1.ArgSize = 64;
}
else if (GV.OperandSize == 32) {
GV.MemDecoration = Arg2dword;
(*pMyDisasm).Argument1.ArgSize = 32;
}
else {
GV.MemDecoration = Arg2word;
(*pMyDisasm).Argument1.ArgSize = 16;
}
MOD_RM(&(*pMyDisasm).Argument2, pMyDisasm);
GV.EIP_ += GV.DECALAGE_EIP+2;
(*pMyDisasm).Argument1.ArgType = REGISTER_TYPE+GENERAL_REG+REG0;
(*pMyDisasm).Instruction.ImplicitModifiedRegs = REGISTER_TYPE+GENERAL_REG+REG0+REG2;
FillFlags(pMyDisasm, 70);
}
else if (GV.REGOPCODE == 5) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+ARITHMETIC_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "imul ");
#endif
if (GV.OperandSize == 64) {
GV.MemDecoration = Arg2qword;
(*pMyDisasm).Argument1.ArgSize = 64;
}
else if (GV.OperandSize == 32) {
GV.MemDecoration = Arg2dword;
(*pMyDisasm).Argument1.ArgSize = 32;
}
else {
GV.MemDecoration = Arg2word;
(*pMyDisasm).Argument1.ArgSize = 16;
}
MOD_RM(&(*pMyDisasm).Argument2, pMyDisasm);
GV.EIP_ += GV.DECALAGE_EIP+2;
(*pMyDisasm).Argument1.ArgType = REGISTER_TYPE+GENERAL_REG+REG0;
(*pMyDisasm).Instruction.ImplicitModifiedRegs = REGISTER_TYPE+GENERAL_REG+REG0+REG2;
FillFlags(pMyDisasm, 38);
}
else if (GV.REGOPCODE == 6) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+ARITHMETIC_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "div ");
#endif
if (GV.OperandSize == 64) {
GV.MemDecoration = Arg2qword;
(*pMyDisasm).Argument1.ArgSize = 64;
}
else if (GV.OperandSize == 32) {
GV.MemDecoration = Arg2dword;
(*pMyDisasm).Argument1.ArgSize = 32;
}
else {
GV.MemDecoration = Arg2word;
(*pMyDisasm).Argument1.ArgSize = 16;
}
MOD_RM(&(*pMyDisasm).Argument2, pMyDisasm);
GV.EIP_ += GV.DECALAGE_EIP+2;
(*pMyDisasm).Argument1.ArgType = REGISTER_TYPE+GENERAL_REG+REG0+REG2;
(*pMyDisasm).Instruction.ImplicitModifiedRegs = REGISTER_TYPE+GENERAL_REG+REG0+REG2;
FillFlags(pMyDisasm, 31);
}
else if (GV.REGOPCODE == 7) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+ARITHMETIC_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "idiv ");
#endif
if (GV.OperandSize == 64) {
GV.MemDecoration = Arg2qword;
(*pMyDisasm).Argument1.ArgSize = 64;
}
else if (GV.OperandSize == 32) {
GV.MemDecoration = Arg2dword;
(*pMyDisasm).Argument1.ArgSize = 32;
}
else {
GV.MemDecoration = Arg2word;
(*pMyDisasm).Argument1.ArgSize = 16;
}
MOD_RM(&(*pMyDisasm).Argument2, pMyDisasm);
GV.EIP_ += GV.DECALAGE_EIP+2;
(*pMyDisasm).Argument1.ArgType = REGISTER_TYPE+GENERAL_REG+REG0+REG2;
(*pMyDisasm).Instruction.ImplicitModifiedRegs = REGISTER_TYPE+GENERAL_REG+REG0+REG2;
FillFlags(pMyDisasm, 37);
}
}

51
deps/beaengine-4.1/beaengineSources/Includes/instr_set/opcodes_Grp4.c vendored
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@ -1,51 +0,0 @@
/* Copyright 2006-2009, BeatriX
* File coded by BeatriX
*
* This file is part of BeaEngine.
*
* BeaEngine is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BeaEngine is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with BeaEngine. If not, see <http://www.gnu.org/licenses/>. */
/* ====================================================================
* 0feh
* ==================================================================== */
void __bea_callspec__ G4_Eb(PDISASM pMyDisasm)
{
GV.REGOPCODE = ((*((UInt8*)(UIntPtr) (GV.EIP_+1))) >> 3) & 0x7;
if (GV.REGOPCODE == 0) {
if ((*pMyDisasm).Prefix.LockPrefix == InvalidPrefix) {
(*pMyDisasm).Prefix.LockPrefix = InUsePrefix;
}
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+ARITHMETIC_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "inc ");
#endif
Eb(pMyDisasm);
FillFlags(pMyDisasm, 40);
}
else if (GV.REGOPCODE == 1) {
if ((*pMyDisasm).Prefix.LockPrefix == InvalidPrefix) {
(*pMyDisasm).Prefix.LockPrefix = InUsePrefix;
}
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+ARITHMETIC_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "dec ");
#endif
Eb(pMyDisasm);
FillFlags(pMyDisasm, 30);
}
else {
FailDecode(pMyDisasm);
}
}

153
deps/beaengine-4.1/beaengineSources/Includes/instr_set/opcodes_Grp5.c vendored
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@ -1,153 +0,0 @@
/* Copyright 2006-2009, BeatriX
* File coded by BeatriX
*
* This file is part of BeaEngine.
*
* BeaEngine is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BeaEngine is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with BeaEngine. If not, see <http://www.gnu.org/licenses/>. */
/* ====================================================================
* 0ffh
* ==================================================================== */
void __bea_callspec__ G5_Ev(PDISASM pMyDisasm)
{
GV.REGOPCODE = ((*((UInt8*)(UIntPtr) (GV.EIP_+1))) >> 3) & 0x7;
if (GV.REGOPCODE == 0) {
if ((*pMyDisasm).Prefix.LockPrefix == InvalidPrefix) {
(*pMyDisasm).Prefix.LockPrefix = InUsePrefix;
}
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+ARITHMETIC_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "inc ");
#endif
Ev(pMyDisasm);
FillFlags(pMyDisasm, 40);
}
else if (GV.REGOPCODE == 1) {
if ((*pMyDisasm).Prefix.LockPrefix == InvalidPrefix) {
(*pMyDisasm).Prefix.LockPrefix = InUsePrefix;
}
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+ARITHMETIC_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "dec ");
#endif
Ev(pMyDisasm);
FillFlags(pMyDisasm, 30);
}
else if (GV.REGOPCODE == 2) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+CONTROL_TRANSFER;
(*pMyDisasm).Instruction.BranchType = CallType;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "call ");
#endif
if (GV.Architecture == 64) {
GV.OperandSize = 64;
}
if (GV.OperandSize == 64) {
GV.MemDecoration = Arg1qword;
}
else if (GV.OperandSize == 32) {
GV.MemDecoration = Arg1dword;
}
else {
GV.MemDecoration = Arg1word;
}
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
GV.EIP_ += GV.DECALAGE_EIP+2;
(*pMyDisasm).Instruction.ImplicitModifiedRegs = GENERAL_REG+REG4;
}
else if (GV.REGOPCODE == 3) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+CONTROL_TRANSFER;
(*pMyDisasm).Instruction.BranchType = CallType;
if (GV.SYNTAX_ == ATSyntax) {
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "lcall ");
#endif
}
else {
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "call far ");
#endif
}
GV.MemDecoration = Arg1fword;
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
GV.EIP_ += GV.DECALAGE_EIP+2;
(*pMyDisasm).Instruction.ImplicitModifiedRegs = GENERAL_REG+REG4;
}
else if (GV.REGOPCODE == 4) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+CONTROL_TRANSFER;
(*pMyDisasm).Instruction.BranchType = JmpType;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "jmp ");
#endif
if (GV.Architecture == 64) {
GV.OperandSize = 64;
}
if (GV.OperandSize == 64) {
GV.MemDecoration = Arg1qword;
}
else if (GV.OperandSize == 32) {
GV.MemDecoration = Arg1dword;
}
else {
GV.MemDecoration = Arg1word;
}
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
GV.EIP_ += GV.DECALAGE_EIP+2;
}
else if (GV.REGOPCODE == 5) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+CONTROL_TRANSFER;
(*pMyDisasm).Instruction.BranchType = JmpType;
if (GV.SYNTAX_ == ATSyntax) {
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "ljmp ");
#endif
}
else {
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "jmp far ");
#endif
}
GV.MemDecoration = Arg1fword;
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
GV.EIP_ += GV.DECALAGE_EIP+2;
}
else if (GV.REGOPCODE == 6) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+DATA_TRANSFER;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "push ");
#endif
if (GV.Architecture == 64) {
GV.OperandSize = 64;
}
if (GV.OperandSize == 64) {
GV.MemDecoration = Arg2qword;
}
else if (GV.OperandSize == 32) {
GV.MemDecoration = Arg2dword;
}
else {
GV.MemDecoration = Arg2word;
}
MOD_RM(&(*pMyDisasm).Argument2, pMyDisasm);
GV.EIP_ += GV.DECALAGE_EIP+2;
(*pMyDisasm).Argument1.ArgType = MEMORY_TYPE;
(*pMyDisasm).Argument1.ArgSize = GV.OperandSize;
(*pMyDisasm).Argument1.Memory.BaseRegister = REG4;
(*pMyDisasm).Instruction.ImplicitModifiedRegs = GENERAL_REG+REG4;
}
else {
FailDecode(pMyDisasm);
}
}

117
deps/beaengine-4.1/beaengineSources/Includes/instr_set/opcodes_Grp6.c vendored
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@ -1,117 +0,0 @@
/* Copyright 2006-2009, BeatriX
* File coded by BeatriX
*
* This file is part of BeaEngine.
*
* BeaEngine is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BeaEngine is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with BeaEngine. If not, see <http://www.gnu.org/licenses/>. */
/* ====================================================================
* 0f00h
* ==================================================================== */
void __bea_callspec__ G6_(PDISASM pMyDisasm)
{
Int32 OperandSizeOld = 0;
(*pMyDisasm).Instruction.Category = SYSTEM_INSTRUCTION;
OperandSizeOld = GV.OperandSize;
GV.OperandSize = 16;
GV.REGOPCODE = ((*((UInt8*)(UIntPtr) (GV.EIP_+1))) >> 3) & 0x7;
GV.MOD_= ((*((UInt8*)(UIntPtr) (GV.EIP_+1))) >> 6) & 0x3;
if (GV.REGOPCODE == 0) {
if ((OperandSizeOld == 64) && (GV.MOD_== 0x3)) {
GV.OperandSize = OperandSizeOld;
}
else {
GV.MemDecoration = Arg1word;
}
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "sldt ");
#endif
(*pMyDisasm).Argument2.ArgType = REGISTER_TYPE+MEMORY_MANAGEMENT_REG+REG1;
(*pMyDisasm).Argument2.ArgSize = 32;
GV.OperandSize = OperandSizeOld;
GV.EIP_+= GV.DECALAGE_EIP+2;
}
else if (GV.REGOPCODE == 1) {
if ((OperandSizeOld == 64) && (GV.MOD_== 0x3)) {
GV.OperandSize = OperandSizeOld;
}
else {
GV.MemDecoration = Arg1word;
}
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "str ");
#endif
(*pMyDisasm).Argument2.ArgType = REGISTER_TYPE+MEMORY_MANAGEMENT_REG+REG3;
(*pMyDisasm).Argument2.ArgSize = 16;
GV.OperandSize = OperandSizeOld;
GV.EIP_+= GV.DECALAGE_EIP+2;
}
else if (GV.REGOPCODE == 2) {
GV.MemDecoration = Arg2word;
MOD_RM(&(*pMyDisasm).Argument2, pMyDisasm);
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "lldt ");
#endif
(*pMyDisasm).Argument1.ArgType = REGISTER_TYPE+MEMORY_MANAGEMENT_REG+REG1;
(*pMyDisasm).Argument1.ArgSize = 16;
GV.OperandSize = OperandSizeOld;
GV.EIP_+= GV.DECALAGE_EIP+2;
}
else if (GV.REGOPCODE == 3) {
GV.MemDecoration = Arg2word;
MOD_RM(&(*pMyDisasm).Argument2, pMyDisasm);
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "ltr ");
#endif
(*pMyDisasm).Argument1.ArgType = REGISTER_TYPE+MEMORY_MANAGEMENT_REG+REG3;
(*pMyDisasm).Argument1.ArgSize = 16;
GV.OperandSize = OperandSizeOld;
GV.EIP_+= GV.DECALAGE_EIP+2;
}
else if (GV.REGOPCODE == 4) {
GV.MemDecoration = Arg1word;
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "verr ");
#endif
(*pMyDisasm).Argument2.ArgType = REGISTER_TYPE+SPECIAL_REG+REG0;
(*pMyDisasm).Argument2.ArgSize = 16;
GV.OperandSize = OperandSizeOld;
GV.EIP_+= GV.DECALAGE_EIP+2;
}
else if (GV.REGOPCODE == 5) {
GV.MemDecoration = Arg1word;
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "verw ");
#endif
(*pMyDisasm).Argument2.ArgType = REGISTER_TYPE+SPECIAL_REG+REG0;
(*pMyDisasm).Argument2.ArgSize = 16;
GV.OperandSize = OperandSizeOld;
GV.EIP_+= GV.DECALAGE_EIP+2;
}
else if (GV.REGOPCODE == 6) {
FailDecode(pMyDisasm);
GV.OperandSize = OperandSizeOld;
}
else {
FailDecode(pMyDisasm);
GV.OperandSize = OperandSizeOld;
}
}

278
deps/beaengine-4.1/beaengineSources/Includes/instr_set/opcodes_Grp7.c vendored
View File

@ -1,278 +0,0 @@
/* Copyright 2006-2009, BeatriX
* File coded by BeatriX
*
* This file is part of BeaEngine.
*
* BeaEngine is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BeaEngine is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with BeaEngine. If not, see <http://www.gnu.org/licenses/>. */
/* ====================================================================
* 0f01h
* ==================================================================== */
void __bea_callspec__ G7_(PDISASM pMyDisasm)
{
(*pMyDisasm).Instruction.Category = SYSTEM_INSTRUCTION;
GV.REGOPCODE = ((*((UInt8*)(UIntPtr) (GV.EIP_+1))) >> 3) & 0x7;
GV.MOD_= ((*((UInt8*)(UIntPtr) (GV.EIP_+1))) >> 6) & 0x3;
GV.RM_ = (*((UInt8*)(UIntPtr) (GV.EIP_+1))) & 0x7;
if (GV.REGOPCODE == 0) {
if (GV.MOD_== 0x3) {
if (GV.RM_ == 0x1) {
(*pMyDisasm).Instruction.Category = VM_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "vmcall ");
#endif
GV.EIP_+= GV.DECALAGE_EIP+2;
}
else if (GV.RM_ == 0x2) {
(*pMyDisasm).Instruction.Category = VM_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "vmlaunch ");
#endif
GV.EIP_+= GV.DECALAGE_EIP+2;
}
else if (GV.RM_ == 0x3) {
(*pMyDisasm).Instruction.Category = VM_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "vmresume ");
#endif
GV.EIP_+= GV.DECALAGE_EIP+2;
}
else if (GV.RM_ == 0x4) {
(*pMyDisasm).Instruction.Category = VM_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "vmxoff ");
#endif
GV.EIP_+= GV.DECALAGE_EIP+2;
}
else {
FailDecode(pMyDisasm);
}
}
else {
GV.MemDecoration = Arg1fword;
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "sgdt ");
#endif
(*pMyDisasm).Argument2.ArgType = REGISTER_TYPE+MEMORY_MANAGEMENT_REG+REG0;
(*pMyDisasm).Argument2.ArgSize = 48;
GV.EIP_+= GV.DECALAGE_EIP+2;
}
}
else if (GV.REGOPCODE == 1) {
if (GV.MOD_== 0x3) {
if (GV.RM_ == 0x00) {
(*pMyDisasm).Instruction.Category = SSE3_INSTRUCTION+AGENT_SYNCHRONISATION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "monitor ");
#endif
GV.EIP_+= GV.DECALAGE_EIP+2;
}
else if (GV.RM_ == 0x01) {
(*pMyDisasm).Instruction.Category = SSE3_INSTRUCTION+AGENT_SYNCHRONISATION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "mwait ");
#endif
GV.EIP_+= GV.DECALAGE_EIP+2;
}
else {
FailDecode(pMyDisasm);
}
}
else {
GV.MemDecoration = Arg1fword;
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
(*pMyDisasm).Instruction.Category = SYSTEM_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "sidt ");
#endif
(*pMyDisasm).Argument2.ArgType = REGISTER_TYPE+MEMORY_MANAGEMENT_REG+REG2;
(*pMyDisasm).Argument2.ArgSize = 48;
GV.EIP_+= GV.DECALAGE_EIP+2;
}
}
else if (GV.REGOPCODE == 2) {
if (GV.MOD_== 0x3) {
if (GV.RM_ == 0x0) {
(*pMyDisasm).Instruction.Category = VM_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "xgetbv ");
#endif
GV.EIP_+= GV.DECALAGE_EIP+2;
}
else if (GV.RM_ == 0x1) {
(*pMyDisasm).Instruction.Category = VM_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "xsetbv ");
#endif
GV.EIP_+= GV.DECALAGE_EIP+2;
}
else {
FailDecode(pMyDisasm);
}
}
else {
GV.MemDecoration = Arg2fword;
MOD_RM(&(*pMyDisasm).Argument2, pMyDisasm);
(*pMyDisasm).Instruction.Category = SYSTEM_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "lgdt ");
#endif
(*pMyDisasm).Argument1.ArgType = REGISTER_TYPE+MEMORY_MANAGEMENT_REG+REG0;
(*pMyDisasm).Argument1.ArgSize = 48;
GV.EIP_+= GV.DECALAGE_EIP+2;
}
}
else if (GV.REGOPCODE == 3) {
if (GV.MOD_== 0x3) {
if (GV.RM_ == 0x0) {
(*pMyDisasm).Instruction.Category = VM_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "vmrun ");
#endif
GV.EIP_+= GV.DECALAGE_EIP+2;
}
else if (GV.RM_ == 0x1) {
(*pMyDisasm).Instruction.Category = VM_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "vmmcall ");
#endif
GV.EIP_+= GV.DECALAGE_EIP+2;
}
else if (GV.RM_ == 0x2) {
(*pMyDisasm).Instruction.Category = VM_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "vmload ");
#endif
GV.EIP_+= GV.DECALAGE_EIP+2;
}
else if (GV.RM_ == 0x3) {
(*pMyDisasm).Instruction.Category = VM_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "vmsave ");
#endif
GV.EIP_+= GV.DECALAGE_EIP+2;
}
else if (GV.RM_ == 0x4) {
(*pMyDisasm).Instruction.Category = VM_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "stgi ");
#endif
GV.EIP_+= GV.DECALAGE_EIP+2;
}
else if (GV.RM_ == 0x5) {
(*pMyDisasm).Instruction.Category = VM_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "clgi ");
#endif
GV.EIP_+= GV.DECALAGE_EIP+2;
}
else if (GV.RM_ == 0x6) {
(*pMyDisasm).Instruction.Category = VM_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "skinit ");
#endif
GV.EIP_+= GV.DECALAGE_EIP+2;
}
else if (GV.RM_ == 0x7) {
(*pMyDisasm).Instruction.Category = VM_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "invlpga ");
#endif
GV.EIP_+= GV.DECALAGE_EIP+2;
}
else {
FailDecode(pMyDisasm);
}
}
else {
GV.MemDecoration = Arg2fword;
MOD_RM(&(*pMyDisasm).Argument2, pMyDisasm);
(*pMyDisasm).Instruction.Category = SYSTEM_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "lidt ");
#endif
(*pMyDisasm).Argument1.ArgType = REGISTER_TYPE+MEMORY_MANAGEMENT_REG+REG2;
(*pMyDisasm).Argument1.ArgSize = 48;
GV.EIP_+= GV.DECALAGE_EIP+2;
}
}
else if (GV.REGOPCODE == 4) {
GV.MemDecoration = Arg2word;
MOD_RM(&(*pMyDisasm).Argument2, pMyDisasm);
(*pMyDisasm).Instruction.Category = SYSTEM_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "smsw ");
#endif
(*pMyDisasm).Argument1.ArgType = REGISTER_TYPE+CR_REG+REG0;
(*pMyDisasm).Argument1.ArgSize = 16;
GV.EIP_+= GV.DECALAGE_EIP+2;
}
else if (GV.REGOPCODE == 6) {
GV.MemDecoration = Arg1word;
MOD_RM(&(*pMyDisasm).Argument1, pMyDisasm);
(*pMyDisasm).Instruction.Category = SYSTEM_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "lmsw ");
#endif
(*pMyDisasm).Argument2.ArgType = REGISTER_TYPE+CR_REG+REG0;
(*pMyDisasm).Argument2.ArgSize = 16;
GV.EIP_+= GV.DECALAGE_EIP+2;
}
else if (GV.REGOPCODE == 7) {
if (GV.MOD_== 0x3) {
if (GV.Architecture == 64) {
if (GV.RM_ == 0x0) {
(*pMyDisasm).Instruction.Category = SYSTEM_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "swapgs ");
#endif
GV.EIP_+= GV.DECALAGE_EIP+2;
}
else {
FailDecode(pMyDisasm);
}
}
else {
if (GV.RM_ == 0x1) {
(*pMyDisasm).Instruction.Category = SYSTEM_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "rdtscp ");
#endif
GV.EIP_+= GV.DECALAGE_EIP+2;
}
else {
FailDecode(pMyDisasm);
}
}
}
else {
GV.MemDecoration = Arg2byte;
MOD_RM(&(*pMyDisasm).Argument2, pMyDisasm);
(*pMyDisasm).Instruction.Category = SYSTEM_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "invlpg ");
#endif
GV.EIP_+= GV.DECALAGE_EIP+2;
}
}
else {
FailDecode(pMyDisasm);
}
}

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deps/beaengine-4.1/beaengineSources/Includes/instr_set/opcodes_Grp8.c vendored
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@ -1,70 +0,0 @@
/* Copyright 2006-2009, BeatriX
* File coded by BeatriX
*
* This file is part of BeaEngine.
*
* BeaEngine is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BeaEngine is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with BeaEngine. If not, see <http://www.gnu.org/licenses/>. */
/* ====================================================================
* 0fbah
* ==================================================================== */
void __bea_callspec__ G8_EvIb(PDISASM pMyDisasm)
{
GV.REGOPCODE = ((*((UInt8*)(UIntPtr) (GV.EIP_+1))) >> 3) & 0x7;
EvIb(pMyDisasm);
if (GV.REGOPCODE == 4) {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+BIT_UInt8;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "bt ");
#endif
(*pMyDisasm).Argument1.AccessMode = READ;
FillFlags(pMyDisasm, 11);
}
else if (GV.REGOPCODE == 5) {
if ((*pMyDisasm).Prefix.LockPrefix == InvalidPrefix) {
(*pMyDisasm).Prefix.LockPrefix = InUsePrefix;
}
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+BIT_UInt8;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "bts ");
#endif
(*pMyDisasm).Argument1.AccessMode = READ;
FillFlags(pMyDisasm, 11);
}
else if (GV.REGOPCODE == 6) {
if ((*pMyDisasm).Prefix.LockPrefix == InvalidPrefix) {
(*pMyDisasm).Prefix.LockPrefix = InUsePrefix;
}
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+BIT_UInt8;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "btr ");
#endif
(*pMyDisasm).Argument1.AccessMode = READ;
FillFlags(pMyDisasm, 11);
}
else if (GV.REGOPCODE == 7) {
if ((*pMyDisasm).Prefix.LockPrefix == InvalidPrefix) {
(*pMyDisasm).Prefix.LockPrefix = InUsePrefix;
}
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+BIT_UInt8;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "btc ");
#endif
(*pMyDisasm).Argument1.AccessMode = READ;
FillFlags(pMyDisasm, 11);
}
else {
FailDecode(pMyDisasm);
}
}

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@ -1,84 +0,0 @@
/* Copyright 2006-2009, BeatriX
* File coded by BeatriX
*
* This file is part of BeaEngine.
*
* BeaEngine is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BeaEngine is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with BeaEngine. If not, see <http://www.gnu.org/licenses/>. */
/* ====================================================================
* 0fc7h
* ==================================================================== */
void __bea_callspec__ G9_(PDISASM pMyDisasm)
{
GV.REGOPCODE = ((*((UInt8*)(UIntPtr) (GV.EIP_+1))) >> 3) & 0x7;
GV.MemDecoration = Arg2qword;
MOD_RM(&(*pMyDisasm).Argument2, pMyDisasm);
if (GV.REGOPCODE == 1) {
if (GV.REX.W_ == 1) {
GV.MemDecoration = Arg2dqword;
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+DATA_TRANSFER;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "cmpxchg16b ");
#endif
(*pMyDisasm).Argument1.ArgType = REGISTER_TYPE+GENERAL_REG+REG0+REG2;
(*pMyDisasm).Argument1.ArgSize = 128;
(*pMyDisasm).Argument1.AccessMode = READ;
FillFlags(pMyDisasm, 23);
GV.EIP_ += GV.DECALAGE_EIP+2;
}
else {
(*pMyDisasm).Instruction.Category = GENERAL_PURPOSE_INSTRUCTION+DATA_TRANSFER;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "cmpxchg8b ");
#endif
(*pMyDisasm).Argument1.ArgType = REGISTER_TYPE+GENERAL_REG+REG0+REG2;
(*pMyDisasm).Argument1.ArgSize = 64;
(*pMyDisasm).Argument1.AccessMode = READ;
FillFlags(pMyDisasm, 23);
GV.EIP_ += GV.DECALAGE_EIP+2;
}
}
else if (GV.REGOPCODE == 6) {
(*pMyDisasm).Instruction.Category = VM_INSTRUCTION;
if (GV.OperandSize == 16) {
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "vmclear ");
#endif
}
else if (GV.PrefRepe == 1) {
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "vmxon ");
#endif
}
else {
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "vmptrld ");
#endif
}
GV.EIP_ += GV.DECALAGE_EIP+2;
}
else if (GV.REGOPCODE == 7) {
(*pMyDisasm).Instruction.Category = VM_INSTRUCTION;
#ifndef BEA_LIGHT_DISASSEMBLY
(void) strcpy ((*pMyDisasm).Instruction.Mnemonic, "vmptrst ");
#endif
GV.EIP_ += GV.DECALAGE_EIP+2;
}
else {
FailDecode(pMyDisasm);
}
}

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3692
deps/beaengine-4.1/beaengineSources/Includes/instr_set/opcodes_N_Z.c vendored
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deps/beaengine-4.1/beaengineSources/Includes/instr_set/opcodes_SSE.c vendored
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239
deps/beaengine-4.1/beaengineSources/Includes/instr_set/opcodes_prefixes.c vendored
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@ -1,239 +0,0 @@
/* Copyright 2006-2009, BeatriX
* File coded by BeatriX
*
* This file is part of BeaEngine.
*
* BeaEngine is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BeaEngine is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with BeaEngine. If not, see <http://www.gnu.org/licenses/>. */
/* ====================================================================
* Legacy Prefix F0h-Group 1
* ==================================================================== */
void __bea_callspec__ PrefLock(PDISASM pMyDisasm)
{
if (!Security(0, pMyDisasm)) return;
(*pMyDisasm).Prefix.LockPrefix = InvalidPrefix;
GV.EIP_++;
(*pMyDisasm).Prefix.Number++;
GV.NB_PREFIX++;
(*pMyDisasm).Instruction.Opcode = *((UInt8*) (UIntPtr)GV.EIP_);
(void) opcode_map1[*((UInt8*) (UIntPtr)GV.EIP_)](pMyDisasm);
GV.OperandSize = 32;
}
/* ====================================================================
* Legacy Prefix F2h-Group 1
* ==================================================================== */
void __bea_callspec__ PrefREPNE(PDISASM pMyDisasm)
{
if (!Security(0, pMyDisasm)) return;
(*pMyDisasm).Prefix.RepnePrefix = SuperfluousPrefix;
GV.EIP_++;
(*pMyDisasm).Prefix.Number++;
GV.NB_PREFIX++;
GV.PrefRepne = 1;
(*pMyDisasm).Instruction.Opcode = *((UInt8*) (UIntPtr)GV.EIP_);
(void) opcode_map1[*((UInt8*) (UIntPtr)GV.EIP_)](pMyDisasm);
GV.PrefRepne = 0;
}
/* ====================================================================
* Legacy Prefix F3h-Group 1
* ==================================================================== */
void __bea_callspec__ PrefREPE(PDISASM pMyDisasm)
{
if (!Security(0, pMyDisasm)) return;
(*pMyDisasm).Prefix.RepPrefix = SuperfluousPrefix;
GV.EIP_++;
(*pMyDisasm).Prefix.Number++;
GV.NB_PREFIX++;
GV.PrefRepe = 1;
(*pMyDisasm).Instruction.Opcode = *((UInt8*) (UIntPtr)GV.EIP_);
(void) opcode_map1[*((UInt8*) (UIntPtr)GV.EIP_)](pMyDisasm);
GV.PrefRepe = 0;
}
/* ====================================================================
* Legacy Prefix 2Eh-Group 2
* ==================================================================== */
void __bea_callspec__ PrefSEGCS(PDISASM pMyDisasm)
{
if (!Security(0, pMyDisasm)) return;
(*pMyDisasm).Prefix.CSPrefix = InUsePrefix;
GV.EIP_++;
(*pMyDisasm).Prefix.Number++;
GV.NB_PREFIX++;
(*pMyDisasm).Instruction.Opcode = *((UInt8*) (UIntPtr)GV.EIP_);
(void) opcode_map1[*((UInt8*) (UIntPtr)GV.EIP_)](pMyDisasm);
}
/* ====================================================================
* Legacy Prefix 3Eh-Group 2
* ==================================================================== */
void __bea_callspec__ PrefSEGDS(PDISASM pMyDisasm)
{
if (!Security(0, pMyDisasm)) return;
(*pMyDisasm).Prefix.DSPrefix = InUsePrefix;
GV.EIP_++;
(*pMyDisasm).Prefix.Number++;
GV.NB_PREFIX++;
(*pMyDisasm).Instruction.Opcode = *((UInt8*) (UIntPtr)GV.EIP_);
(void) opcode_map1[*((UInt8*) (UIntPtr)GV.EIP_)](pMyDisasm);
}
/* ====================================================================
* Legacy Prefix 26h-Group 2
* ==================================================================== */
void __bea_callspec__ PrefSEGES(PDISASM pMyDisasm)
{
if (!Security(0, pMyDisasm)) return;
(*pMyDisasm).Prefix.ESPrefix = InUsePrefix;
GV.EIP_++;
(*pMyDisasm).Prefix.Number++;
GV.NB_PREFIX++;
(*pMyDisasm).Instruction.Opcode = *((UInt8*) (UIntPtr)GV.EIP_);
(void) opcode_map1[*((UInt8*) (UIntPtr)GV.EIP_)](pMyDisasm);
}
/* ====================================================================
* Legacy Prefix 64h-Group 2
* ==================================================================== */
void __bea_callspec__ PrefSEGFS(PDISASM pMyDisasm)
{
if (!Security(0, pMyDisasm)) return;
(*pMyDisasm).Prefix.FSPrefix = InUsePrefix;
GV.EIP_++;
(*pMyDisasm).Prefix.Number++;
GV.NB_PREFIX++;
GV.SEGMENTFS = 1;
(*pMyDisasm).Instruction.Opcode = *((UInt8*) (UIntPtr)GV.EIP_);
(void) opcode_map1[*((UInt8*) (UIntPtr)GV.EIP_)](pMyDisasm);
}
/* ====================================================================
* Legacy Prefix 65h-Group 2
* ==================================================================== */
void __bea_callspec__ PrefSEGGS(PDISASM pMyDisasm)
{
if (!Security(0, pMyDisasm)) return;
(*pMyDisasm).Prefix.GSPrefix = InUsePrefix;
GV.EIP_++;
(*pMyDisasm).Prefix.Number++;
GV.NB_PREFIX++;
(*pMyDisasm).Instruction.Opcode = *((UInt8*) (UIntPtr)GV.EIP_);
(void) opcode_map1[*((UInt8*) (UIntPtr)GV.EIP_)](pMyDisasm);
}
/* ====================================================================
* Legacy Prefix 36h-Group 2
* ==================================================================== */
void __bea_callspec__ PrefSEGSS(PDISASM pMyDisasm)
{
if (!Security(0, pMyDisasm)) return;
(*pMyDisasm).Prefix.SSPrefix = InUsePrefix;
GV.EIP_++;
(*pMyDisasm).Prefix.Number++;
GV.NB_PREFIX++;
(*pMyDisasm).Instruction.Opcode = *((UInt8*) (UIntPtr)GV.EIP_);
(void) opcode_map1[*((UInt8*) (UIntPtr)GV.EIP_)](pMyDisasm);
}
/* ====================================================================
* Legacy Prefix 66h-Group 3
* ==================================================================== */
void __bea_callspec__ PrefOpSize(PDISASM pMyDisasm)
{
if (!Security(0, pMyDisasm)) return;
(*pMyDisasm).Prefix.OperandSize = InUsePrefix;
GV.EIP_++;
(*pMyDisasm).Prefix.Number++;
GV.NB_PREFIX++;
GV.OriginalOperandSize = GV.OperandSize; /* if GV.OperandSize is used as a mandatory prefix, keep the real operandsize value */
if (GV.Architecture == 16) {
GV.OperandSize = 32;
}
else {
if (GV.OperandSize != 64) {
GV.OperandSize = 16;
}
}
(*pMyDisasm).Instruction.Opcode = *((UInt8*) (UIntPtr)GV.EIP_);
(void) opcode_map1[*((UInt8*) (UIntPtr)GV.EIP_)](pMyDisasm);
if (GV.Architecture == 16) {
GV.OperandSize = 16;
}
else {
GV.OperandSize = 32;
}
}
/* ====================================================================
* Legacy Prefix 67h-Group 4
* ==================================================================== */
void __bea_callspec__ PrefAdSize(PDISASM pMyDisasm)
{
if (!Security(0, pMyDisasm)) return;
(*pMyDisasm).Prefix.AddressSize = InUsePrefix;
GV.EIP_++;
(*pMyDisasm).Prefix.Number++;
GV.NB_PREFIX++;
if (GV.Architecture == 16) {
GV.AddressSize = GV.AddressSize << 1;
}
else {
GV.AddressSize = GV.AddressSize >> 1;
}
(*pMyDisasm).Instruction.Opcode = *((UInt8*) (UIntPtr)GV.EIP_);
(void) opcode_map1[*((UInt8*) (UIntPtr)GV.EIP_)](pMyDisasm);
if (GV.Architecture == 16) {
GV.AddressSize = GV.AddressSize >> 1;
}
else {
GV.AddressSize = GV.AddressSize << 1;
}
}
/* ====================================================================
* Escape Prefix 0Fh-two bytes opcodes
* ==================================================================== */
void __bea_callspec__ Esc_2byte(PDISASM pMyDisasm)
{
if (!Security(0, pMyDisasm)) return;
GV.EIP_++;
(*pMyDisasm).Instruction.Opcode = *((UInt8*) (UIntPtr)GV.EIP_)+0x0F00;
(void) opcode_map2[*((UInt8*) (UIntPtr)GV.EIP_)](pMyDisasm);
}
/* ====================================================================
* Escape Prefix 0F38h-three bytes opcodes
* ==================================================================== */
void __bea_callspec__ Esc_tableA4(PDISASM pMyDisasm)
{
if (!Security(0, pMyDisasm)) return;
GV.EIP_++;
(*pMyDisasm).Instruction.Opcode = *((UInt8*) (UIntPtr)GV.EIP_)+0x0F3800;
(void) opcode_map3[*((UInt8*) (UIntPtr)GV.EIP_)](pMyDisasm);
}
/* ====================================================================
* Escape Prefix 0F3Ah-three bytes opcodes
* ==================================================================== */
void __bea_callspec__ Esc_tableA5(PDISASM pMyDisasm)
{
if (!Security(0, pMyDisasm)) return;
GV.EIP_++;
(*pMyDisasm).Instruction.Opcode = *((UInt8*) (UIntPtr)GV.EIP_)+0x0F3A00;
(void) opcode_map4[*((UInt8*) (UIntPtr)GV.EIP_)](pMyDisasm);
}

560
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@ -1,560 +0,0 @@
/* Copyright 2006-2009, BeatriX
* File coded by BeatriX
*
* This file is part of BeaEngine.
*
* BeaEngine is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BeaEngine is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with BeaEngine. If not, see <http://www.gnu.org/licenses/>. */
/* Define prefix GV aka GlobalVariable - used instead of global internal variables to make BeaEngine thread-safe */
#define GV (*pMyDisasm).Reserved_
/* Define constants to identify the position and type of decoration used in case of memory argument */
#define Arg1byte 1
#define Arg1word 2
#define Arg1dword 3
#define Arg1qword 4
#define Arg1multibytes 5
#define Arg1tbyte 6
#define Arg1fword 7
#define Arg1dqword 8
#define Arg2byte 101
#define Arg2word 102
#define Arg2dword 103
#define Arg2qword 104
#define Arg2multibytes 105
#define Arg2tbyte 106
#define Arg2fword 107
#define Arg2dqword 108
EFLStruct EFLAGS_TABLE[] = {
{UN_, UN_, UN_, MO_, UN_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 0-AAA */
{UN_, MO_, MO_, UN_, MO_, UN_, 0 , 0 , 0 , 0 , 0, 0}, /* 1-AAD */
{UN_, MO_, MO_, UN_, MO_, UN_, 0 , 0 , 0 , 0 , 0, 0}, /* 2-AAM */
{UN_, UN_, UN_, MO_, UN_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 3-AAS */
{MO_, MO_, MO_, MO_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 4-ADC */
{MO_, MO_, MO_, MO_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 5-ADD */
{RE_, MO_, MO_, UN_, MO_, RE_, 0 , 0 , 0 , 0 , 0, 0}, /* 6-AND */
{0 , 0 , MO_, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 7-ARPL */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 8-BOUND */
{UN_, UN_, MO_, UN_, UN_, UN_, 0 , 0 , 0 , 0 , 0, 0}, /* 9-BSF/BSR */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 10-BSWAP */
{UN_, UN_, UN_, UN_, UN_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 11-BT/BTS/BTR/BTC */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 12-CALL */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 13-CBW */
{0 , 0 , 0 , 0 , 0 , RE_, 0 , 0 , 0 , 0 , 0, 0}, /* 14-CLC */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , RE_, 0 , 0, 0}, /* 15-CLD */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , RE_, 0 , 0 , 0, 0}, /* 16-CLI */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 17-CLTS */
{0 , 0 , 0 , 0 , 0 , MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 18-CMC */
{TE_, TE_, TE_, 0 , TE_, TE_, 0 , 0 , 0 , 0 , 0, 0}, /* 19-CMOVcc */
{MO_, MO_, MO_, MO_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 20-CMP */
{MO_, MO_, MO_, MO_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 21-CMPS */
{MO_, MO_, MO_, MO_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 22-CMPXCHG */
{0 , 0 , MO_, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 23-CMPXCHGG8B */
{RE_, RE_, MO_, RE_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 24-COMSID */
{RE_, RE_, MO_, RE_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 25-COMISS */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 26-CPUID */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 27-CWD */
{UN_, MO_, MO_, MO_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 28-DAA */
{UN_, MO_, MO_, MO_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 29-DAS */
{MO_, MO_, MO_, MO_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 30-DEC */
{UN_, UN_, UN_, UN_, UN_, UN_, 0 , 0 , 0 , 0 , 0, 0}, /* 31-DIV */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 32-ENTER */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 33-ESC */
{0 , 0 , TE_, 0 , TE_, TE_, 0 , 0 , 0 , 0 , 0, 0}, /* 34-FCMOV */
{0 , 0 , MO_, 0 , MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 35-FCOMI FCOMIP FUCMI FUCMIP */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 36-HLT */
{UN_, UN_, UN_, UN_, UN_, UN_, 0 , 0 , 0 , 0 , 0, 0}, /* 37-IDIV */
{MO_, UN_, UN_, UN_, UN_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 38-IMUL */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 39-IN */
{MO_, MO_, MO_, MO_, MO_, 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 40-INC */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , TE_, 0 , 0, 0}, /* 41-INS */
{0 , 0 , 0 , 0 , 0 , 0 , RE_, 0 , 0 , RE_, 0, 0}, /* 42-INT */
{TE_, 0 , 0 , 0 , 0 , 0 , RE_, 0 , 0 , RE_, 0, 0}, /* 43-INTO */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 44-INVD */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 45-INVLPG */
{RE_, RE_, MO_, RE_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 46-UCOMSID */
{RE_, RE_, MO_, RE_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 47-UCOMISS */
{PR_, PR_, PR_, PR_, PR_, PR_, PR_, PR_, PR_, TE_, 0, 0}, /* 48-IRET */
{TE_, TE_, TE_, 0 , TE_, TE_, 0 , 0 , 0 , 0 , 0, 0}, /* 49-Jcc */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 50-JCXZ */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 51-JMP */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 52-LAHF */
{0 , 0 , MO_, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 53-LAR */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 54-LDS LES LSS LFS LGS */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 55-LEA */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 56-LEAVE */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 57-LGDT LIDT LLDT LMSW */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 58-LOCK */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , TE_, 0 , 0, 0}, /* 59-LODS */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 60-LOOP */
{0 , 0 , TE_, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 61-LOOPE LOOPNE */
{0 , 0 , MO_, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 62-LSL */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 63-LTR */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 64-MONITOR */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 65-MWAIT */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 66-MOV */
{UN_, UN_, UN_, UN_, UN_, UN_, 0 , 0 , 0 , 0 , 0, 0}, /* 67-MOV control, debug, test */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , TE_, 0 , 0, 0}, /* 68-MOVS */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 69-MOVSX MOVZX */
{MO_, UN_, UN_, UN_, UN_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 70-MUL */
{MO_, MO_, MO_, MO_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 71-NEG */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 72-NOP */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 73-NOT */
{RE_, MO_, MO_, UN_, MO_, RE_, 0 , 0 , 0 , 0 , 0, 0}, /* 74-OR */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 75-OUT */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , TE_, 0 , 0, 0}, /* 76-OUTS */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 77-POP POPA */
{PR_, PR_, PR_, PR_, PR_, PR_, PR_, PR_, PR_, PR_, 0, 0}, /* 78-POPF */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 79-PUSH PUSHA PUSHF */
{MO_, 0 , 0 , 0 , 0 , MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 80-RCL RCR 1 */
{UN_, 0 , 0 , 0 , 0 , MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 81-RCL RCR */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 82-RDMSR */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 83-RDPMC */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 84-RDTSC */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 85-REP REPE REPNE */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 86-RET */
{MO_, 0 , 0 , 0 , 0 , MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 87-ROL ROR 1 */
{UN_, 0 , 0 , 0 , 0 , MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 88-ROL ROR */
{MO_, MO_, MO_, MO_, MO_, MO_, MO_, MO_, MO_, MO_, MO_, 0}, /* 89-RSM */
{0 , PR_, PR_, PR_, PR_, PR_, 0 , 0 , 0 , 0 , 0, 0}, /* 90-SAHF */
{MO_, MO_, MO_, 0 , MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 91-SAL SAR SHL SHR 1 */
{0 , MO_, MO_, 0 , MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 92-SAL SAR SHL SHR */
{MO_, MO_, MO_, MO_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 93-SBB */
{MO_, MO_, MO_, MO_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 94-SCAS */
{TE_, TE_, TE_, 0 , TE_, TE_, 0 , 0 , 0 , 0 , 0, 0}, /* 95-SETcc */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 96-SGDT SIDT SLDT SMSW */
{UN_, MO_, MO_, UN_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 97-SHLD SHRD */
{0 , 0 , 0 , 0 , 0 , SE_, 0 , 0 , 0 , 0 , 0, 0}, /* 98-STC */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , SE_, 0 , 0, 0}, /* 99-STD */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , SE_, 0 , 0 , 0, 0}, /* 100-STI */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 101-STOS */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 102-STR */
{MO_, MO_, MO_, MO_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 103-SUB */
{RE_, MO_, MO_, UN_, MO_, RE_, 0 , 0 , 0 , 0 , 0, 0}, /* 104-TEST */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 105-UD2 */
{0 , 0 , MO_, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 106-VERR VERRW */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 107-WAIT */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 108-WBINVD */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 109-WRMSR */
{MO_, MO_, MO_, MO_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 110-XADD */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 111-XCHG */
{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 112-XLAT */
{RE_, MO_, MO_, UN_, MO_, RE_, 0 , 0 , 0 , 0 , 0, 0}, /* 113-XOR */
{RE_, RE_, MO_, RE_, RE_, RE_, 0 , 0 , 0 , 0 , 0, 0}, /* 114-POPCNT */
{TE_, TE_, TE_, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /*115 -jg jnle jng jle http://ref.x86asm.net/coder.html */
{TE_, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /*116 -jo jno http://ref.x86asm.net/coder.html */
{0 , 0 , 0 , 0 , 0 , TE_, 0 , 0 , 0 , 0 , 0, 0}, /*117 -jc jnc jb jnb jnae jae http://ref.x86asm.net/coder.html */
{0 , 0 , TE_, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /*118 -jz jnz je jne http://ref.x86asm.net/coder.html */
{0 , 0 , TE_, 0 , 0 , TE_, 0 , 0 , 0 , 0 , 0, 0}, /*119 -jbe jnbe jna ja http://ref.x86asm.net/coder.html */
{0 , TE_, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 120 - js jns http://ref.x86asm.net/coder.html */
{0 , 0 , 0 , 0 , TE_, 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 121 - jp jpe jnp jpo http://ref.x86asm.net/coder.html */
{TE_, TE_, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0} /* 122 - jl jnge jnl jge http://ref.x86asm.net/coder.html */
};
/* =====================================================
* To make a tabulation between mnemonic and first argument
* ===================================================== */
char space_tab[11][16] = {
" ",
" ",
" ",
" ",
" ",
" ",
" ",
" ",
" ",
" ",
" ",
};
/* =====================================================
* Segment registers
* ===================================================== */
char SegmentRegs[7][4] = {
"??:", /* +0 */
"es:", /* +1 */
"ds:", /* +2 */
"fs:", /* +3 */
"gs:", /* +4 */
"cs:", /* +5 */
"ss:", /* +6 */
};
/* =====================================================
* AT&T Suffixes
* ===================================================== */
char ATSuffixes[8][4] = {
"b ", /* GV.MemDecoration == 1 */
"w ", /* GV.MemDecoration == 2 */
"l ", /* GV.MemDecoration == 3 */
"q ", /* GV.MemDecoration == 4 */
" ", /* GV.MemDecoration == 5 (multibytes) */
"t ", /* GV.MemDecoration == 6 */
" ", /* GV.MemDecoration == 7 (fword) */
" ", /* GV.MemDecoration == 8 (dqword) */
};
/* =====================================================
* MASM Prefixes for MemoryType
* ===================================================== */
char MasmPrefixes[8][16] = {
"byte ptr ", /* GV.MemDecoration == 1 */
"word ptr ", /* GV.MemDecoration == 2 */
"dword ptr ", /* GV.MemDecoration == 3 */
"qword ptr ", /* GV.MemDecoration == 4 */
" ", /* GV.MemDecoration == 5 (multibytes) */
"tbyte ptr ", /* GV.MemDecoration == 6 */
"fword ptr ", /* GV.MemDecoration == 7 (fword) */
"dqword ptr ", /* GV.MemDecoration == 8 (dqword) */
};
/* =====================================================
* NASM Prefixes for MemoryType
* ===================================================== */
char NasmPrefixes[8][8] = {
"byte ", /* GV.MemDecoration == 1 */
"word ", /* GV.MemDecoration == 2 */
" ", /* GV.MemDecoration == 3 */
"qword ", /* GV.MemDecoration == 4 */
" ", /* GV.MemDecoration == 5 (multibytes) */
"tword ", /* GV.MemDecoration == 6 */
" ", /* GV.MemDecoration == 7 (fword) */
" ", /* GV.MemDecoration == 8 (dqword) */
};
/* =====================================================
* GOASM Prefixes for MemoryType
* ===================================================== */
char GoAsmPrefixes[8][4] = {
"b ", /* GV.MemDecoration == 1 */
"w ", /* GV.MemDecoration == 2 */
"d ", /* GV.MemDecoration == 3 */
"q ", /* GV.MemDecoration == 4 */
" ", /* GV.MemDecoration == 5 (multibytes) */
"t ", /* GV.MemDecoration == 6 */
" ", /* GV.MemDecoration == 7 (fword) */
" ", /* GV.MemDecoration == 8 (dqword) */
};
/* =====================================================
* Segment registers
* ===================================================== */
char RegistersSEG[16][8] = {
"es", /* +0 */
"cs", /* +1 */
"ss", /* +2 */
"ds", /* +3 */
"fs", /* +4 */
"gs", /* +5 */
"seg?",
"seg?",
"seg?",
"seg?",
"seg?",
"seg?",
"seg?",
"seg?",
"seg?",
"seg?",
};
/* =====================================================
* FPU Registers
* ===================================================== */
char RegistersFPU_Masm[8][8] = {
"st(0)", /* +0 */
"st(1)", /* +1 */
"st(2)", /* +2 */
"st(3)", /* +3 */
"st(4)", /* +4 */
"st(5)", /* +5 */
"st(6)", /* +6 */
"st(7)", /* +7 */
};
char RegistersFPU_Nasm[8][8] = {
"st0", /* +0 */
"st1", /* +1 */
"st2", /* +2 */
"st3", /* +3 */
"st4", /* +4 */
"st5", /* +5 */
"st6", /* +6 */
"st7", /* +7 */
};
/* =====================================================
* debug registers
* ===================================================== */
char RegistersDR[16][8] = {
"dr0", /* +0 */
"dr1", /* +1 */
"dr2", /* +2 */
"dr3", /* +3 */
"dr4", /* +4 */
"dr5", /* +5 */
"dr6", /* +6 */
"dr7", /* +7 */
"dr8", /* +8 */
"dr9", /* +9 */
"dr10", /* +10 */
"dr11", /* +11 */
"dr12", /* +12 */
"dr13", /* +13 */
"dr14", /* +14 */
"dr15", /* +15 */
};
/* =====================================================
* debug registers-AT&T syntax
* ===================================================== */
char RegistersDR_AT[16][8] = {
"db0", /* +0 */
"db1", /* +1 */
"db2", /* +2 */
"db3", /* +3 */
"db4", /* +4 */
"db5", /* +5 */
"db6", /* +6 */
"db7", /* +7 */
"db8", /* +8 */
"db9", /* +9 */
"db10", /* +10 */
"db11", /* +11 */
"db12", /* +12 */
"db13", /* +13 */
"db14", /* +14 */
"db15", /* +15 */
};
/* =====================================================
* control registers
* ===================================================== */
char RegistersCR[16][8] = {
"cr0", /* +0 */
"cr1", /* +1 */
"cr2", /* +2 */
"cr3", /* +3 */
"cr4", /* +4 */
"cr5", /* +5 */
"cr6", /* +6 */
"cr7", /* +7 */
"cr8", /* +8 */
"cr9", /* +9 */
"cr10", /* +10 */
"cr11", /* +11 */
"cr12", /* +12 */
"cr13", /* +13 */
"cr14", /* +14 */
"cr15", /* +15 */
};
/* =====================================================
* 64 bits registers
* ===================================================== */
char Registers64Bits[16][4] = {
"rax", /* +0 */
"rcx", /* +1 */
"rdx", /* +2 */
"rbx", /* +3 */
"rsp", /* +4 */
"rbp", /* +5 */
"rsi", /* +6 */
"rdi", /* +7 */
"r8", /* +8 */
"r9", /* +9 */
"r10", /* +10 */
"r11", /* +11 */
"r12", /* +12 */
"r13", /* +13 */
"r14", /* +14 */
"r15", /* +15 */
};
/* =====================================================
* 32 bits registers
* ===================================================== */
char Registers32Bits[16][8] = {
"eax",
"ecx",
"edx",
"ebx",
"esp",
"ebp",
"esi",
"edi",
"r8d",
"r9d",
"r10d",
"r11d",
"r12d",
"r13d",
"r14d",
"r15d",
};
/* =====================================================
* 16 bits registers
* ===================================================== */
char Registers16Bits[16][8] = {
"ax",
"cx",
"dx",
"bx",
"sp",
"bp",
"si",
"di",
"r8w",
"r9w",
"r10w",
"r11w",
"r12w",
"r13w",
"r14w",
"r15w",
};
/* =====================================================
* 8 bits registers
* ===================================================== */
char Registers8BitsLegacy[8][4] = {
"al",
"cl",
"dl",
"bl",
"ah",
"ch",
"dh",
"bh",
};
Int32 REGS8BITS[] = {
REG0,
REG1,
REG2,
REG3,
REG0,
REG1,
REG2,
REG3,
};
/* =====================================================
* 8 bits registers
* ===================================================== */
char Registers8Bits[16][8] = {
"al",
"cl",
"dl",
"bl",
"spl",
"bpl",
"sil",
"dil",
"r8L",
"r9L",
"r10L",
"r11L",
"r12L",
"r13L",
"r14L",
"r15L",
};
/* =====================================================
* MMX Registers
* ===================================================== */
char RegistersMMX[8][4] = {
"mm0",
"mm1",
"mm2",
"mm3",
"mm4",
"mm5",
"mm6",
"mm7",
};
/* =====================================================
* SSE Registers
* ===================================================== */
char RegistersSSE[16][8] = {
"xmm0",
"xmm1",
"xmm2",
"xmm3",
"xmm4",
"xmm5",
"xmm6",
"xmm7",
"xmm8", /* SSE3, SSSE3, SSE4 */
"xmm9", /* SSE3, SSSE3, SSE4 */
"xmm10", /* SSE3, SSSE3, SSE4 */
"xmm11", /* SSE3, SSSE3, SSE4 */
"xmm12", /* SSE3, SSSE3, SSE4 */
"xmm13", /* SSE3, SSSE3, SSE4 */
"xmm14", /* SSE3, SSSE3, SSE4 */
"xmm15", /* SSE3, SSSE3, SSE4 */
};
Int32 REGS[] = {
REG0, /* REG0 */
REG1, /* REG1 */
REG2, /* REG2 */
REG3, /* REG3 */
REG4, /* REG4 */
REG5, /* REG5 */
REG6, /* REG6 */
REG7, /* REG7 */
REG8, /* REG8 */
REG9, /* REG9 */
REG10, /* REG10 */
REG11, /* REG11 */
REG12, /* REG12 */
REG13, /* REG13 */
REG14, /* REG14 */
REG15, /* REG15 */
};
char BXSI_[] = "bx+si";
char BXDI_[] = "bx+di";
char BPSI_[] = "bp+si";
char BPDI_[] = "bp+di";

705
deps/beaengine-4.1/beaengineSources/Includes/protos.h vendored
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@ -1,705 +0,0 @@
/* Copyright 2006-2009, BeatriX
* File coded by BeatriX
*
* This file is part of BeaEngine.
*
* BeaEngine is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BeaEngine is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with BeaEngine. If not, see <http://www.gnu.org/licenses/>. */
/* ====================================== Routines_MODRM */
void __bea_callspec__ MOD_RM(ARGTYPE*, PDISASM);
void __bea_callspec__ Reg_Opcode(ARGTYPE*, PDISASM);
void __bea_callspec__ Addr_EAX(ARGTYPE*, PDISASM);
void __bea_callspec__ Addr_ECX(ARGTYPE*, PDISASM);
void __bea_callspec__ Addr_EDX(ARGTYPE*, PDISASM);
void __bea_callspec__ Addr_EBX(ARGTYPE*, PDISASM);
void __bea_callspec__ Addr_SIB(ARGTYPE*, PDISASM);
void __bea_callspec__ Addr_disp32(ARGTYPE*, PDISASM);
void __bea_callspec__ Addr_ESI(ARGTYPE*, PDISASM);
void __bea_callspec__ Addr_EDI(ARGTYPE*, PDISASM);
void __bea_callspec__ Addr_EAX_disp8(ARGTYPE*, PDISASM);
void __bea_callspec__ Addr_ECX_disp8(ARGTYPE*, PDISASM);
void __bea_callspec__ Addr_EDX_disp8(ARGTYPE*, PDISASM);
void __bea_callspec__ Addr_EBX_disp8(ARGTYPE*, PDISASM);
void __bea_callspec__ Addr_SIB_disp8(ARGTYPE*, PDISASM);
void __bea_callspec__ Addr_EBP_disp8(ARGTYPE*, PDISASM);
void __bea_callspec__ Addr_ESI_disp8(ARGTYPE*, PDISASM);
void __bea_callspec__ Addr_EDI_disp8(ARGTYPE*, PDISASM);
void __bea_callspec__ Addr_EAX_disp32(ARGTYPE*, PDISASM);
void __bea_callspec__ Addr_ECX_disp32(ARGTYPE*, PDISASM);
void __bea_callspec__ Addr_EDX_disp32(ARGTYPE*, PDISASM);
void __bea_callspec__ Addr_EBX_disp32(ARGTYPE*, PDISASM);
void __bea_callspec__ Addr_SIB_disp32(ARGTYPE*, PDISASM);
void __bea_callspec__ Addr_EBP_disp32(ARGTYPE*, PDISASM);
void __bea_callspec__ Addr_ESI_disp32(ARGTYPE*, PDISASM);
void __bea_callspec__ Addr_EDI_disp32(ARGTYPE*, PDISASM);
void __bea_callspec__ _rEAX(ARGTYPE*, PDISASM);
void __bea_callspec__ _rECX(ARGTYPE*, PDISASM);
void __bea_callspec__ _rEDX(ARGTYPE*, PDISASM);
void __bea_callspec__ _rEBX(ARGTYPE*, PDISASM);
void __bea_callspec__ _rESP(ARGTYPE*, PDISASM);
void __bea_callspec__ _rEBP(ARGTYPE*, PDISASM);
void __bea_callspec__ _rESI(ARGTYPE*, PDISASM);
void __bea_callspec__ _rEDI(ARGTYPE*, PDISASM);
size_t __bea_callspec__ SIB_0(ARGTYPE*, size_t, PDISASM);
size_t __bea_callspec__ SIB_1(ARGTYPE*, size_t, PDISASM);
size_t __bea_callspec__ SIB_2(ARGTYPE*, size_t, PDISASM);
size_t __bea_callspec__ SIB_3(ARGTYPE*, size_t, PDISASM);
/* ====================================== Routines_Disasm */
void __bea_callspec__ CompleteInstructionFields (PDISASM);
void __bea_callspec__ EbGb(PDISASM);
void __bea_callspec__ EvGv(PDISASM);
void __bea_callspec__ EvIb(PDISASM);
void __bea_callspec__ ExGx(PDISASM);
void __bea_callspec__ EvIv(PDISASM);
void __bea_callspec__ EbIb(PDISASM);
void __bea_callspec__ Eb(PDISASM);
void __bea_callspec__ Ev(PDISASM);
void __bea_callspec__ GvEv(PDISASM);
void __bea_callspec__ GvEb(PDISASM);
void __bea_callspec__ GxEx(PDISASM);
void __bea_callspec__ GvEw(PDISASM);
void __bea_callspec__ GbEb(PDISASM);
void __bea_callspec__ ALIb(PDISASM);
void __bea_callspec__ eAX_Iv(PDISASM);
int __bea_callspec__ AnalyzeOpcode (PDISASM);
int __bea_callspec__ Security(int, PDISASM);
void __bea_callspec__ CalculateRelativeAddress(UInt64 *, Int64, PDISASM);
size_t __bea_callspec__ CopyFormattedNumber(PDISASM, char*, const char*, Int64);
void __bea_callspec__ BuildCompleteInstruction(PDISASM);
void __bea_callspec__ BuildCompleteInstructionATSyntax(PDISASM);
int __bea_callspec__ InitVariables (PDISASM);
void __bea_callspec__ FillFlags(PDISASM, int);
void __bea_callspec__ FillSegmentsRegisters (PDISASM);
void __bea_callspec__ FixArgSizeForMemoryOperand (PDISASM);
void __bea_callspec__ FixREXPrefixes (PDISASM);
/* ====================================== opcodes_prefix */
void __bea_callspec__ PrefLock(PDISASM);
void __bea_callspec__ PrefREPNE(PDISASM);
void __bea_callspec__ PrefREPE(PDISASM);
void __bea_callspec__ PrefSEGCS(PDISASM);
void __bea_callspec__ PrefSEGDS(PDISASM);
void __bea_callspec__ PrefSEGES(PDISASM);
void __bea_callspec__ PrefSEGFS(PDISASM);
void __bea_callspec__ PrefSEGGS(PDISASM);
void __bea_callspec__ PrefSEGSS(PDISASM);
void __bea_callspec__ PrefOpSize(PDISASM);
void __bea_callspec__ PrefAdSize(PDISASM);
void __bea_callspec__ Esc_2byte(PDISASM);
void __bea_callspec__ Esc_tableA4(PDISASM);
void __bea_callspec__ Esc_tableA5(PDISASM);
/* ====================================== opcodes_A_M */
void __bea_callspec__ FailDecode(PDISASM);
void __bea_callspec__ aaa_(PDISASM);
void __bea_callspec__ aad_(PDISASM);
void __bea_callspec__ aas_(PDISASM);
void __bea_callspec__ aam_(PDISASM);
void __bea_callspec__ add_EbGb(PDISASM);
void __bea_callspec__ add_EvGv(PDISASM);
void __bea_callspec__ add_GbEb(PDISASM);
void __bea_callspec__ add_GvEv(PDISASM);
void __bea_callspec__ add_ALIb(PDISASM);
void __bea_callspec__ add_eAX_Iv(PDISASM);
void __bea_callspec__ adc_ALIb(PDISASM);
void __bea_callspec__ adc_eAX_Iv(PDISASM);
void __bea_callspec__ adc_EbGb(PDISASM);
void __bea_callspec__ adc_EvGv(PDISASM);
void __bea_callspec__ adc_GbEb(PDISASM);
void __bea_callspec__ adc_GvEv(PDISASM);
void __bea_callspec__ and_EbGb(PDISASM);
void __bea_callspec__ and_ALIb(PDISASM);
void __bea_callspec__ and_eAX_Iv(PDISASM);
void __bea_callspec__ and_EvGv(PDISASM);
void __bea_callspec__ and_GbEb(PDISASM);
void __bea_callspec__ and_GvEv(PDISASM);
void __bea_callspec__ arpl_(PDISASM);
void __bea_callspec__ bound_(PDISASM);
void __bea_callspec__ bswap_eax(PDISASM);
void __bea_callspec__ bswap_ebp(PDISASM);
void __bea_callspec__ bswap_ebx(PDISASM);
void __bea_callspec__ bswap_ecx(PDISASM);
void __bea_callspec__ bswap_edi(PDISASM);
void __bea_callspec__ bswap_edx(PDISASM);
void __bea_callspec__ bswap_esi(PDISASM);
void __bea_callspec__ bswap_esp(PDISASM);
void __bea_callspec__ bsf_GvEv(PDISASM);
void __bea_callspec__ bsr_GvEv(PDISASM);
void __bea_callspec__ btc_EvGv(PDISASM);
void __bea_callspec__ btr_EvGv(PDISASM);
void __bea_callspec__ bt_EvGv(PDISASM);
void __bea_callspec__ bts_EvGv(PDISASM);
void __bea_callspec__ callf_(PDISASM);
void __bea_callspec__ call_(PDISASM);
void __bea_callspec__ cdq_(PDISASM);
void __bea_callspec__ clts_(PDISASM);
void __bea_callspec__ cmc_(PDISASM);
void __bea_callspec__ cmovo_(PDISASM);
void __bea_callspec__ cmovno_(PDISASM);
void __bea_callspec__ cmovb_(PDISASM);
void __bea_callspec__ cmovnb_(PDISASM);
void __bea_callspec__ cmove_(PDISASM);
void __bea_callspec__ cmovne_(PDISASM);
void __bea_callspec__ cmovbe_(PDISASM);
void __bea_callspec__ cmovnbe_(PDISASM);
void __bea_callspec__ cmovs_(PDISASM);
void __bea_callspec__ cmovns_(PDISASM);
void __bea_callspec__ cmovp_(PDISASM);
void __bea_callspec__ cmovnp_(PDISASM);
void __bea_callspec__ cmovl_(PDISASM);
void __bea_callspec__ cmovnl_(PDISASM);
void __bea_callspec__ cmovle_(PDISASM);
void __bea_callspec__ cmovnle_(PDISASM);
void __bea_callspec__ cmpx_EbGb(PDISASM);
void __bea_callspec__ cmpx_EvGv(PDISASM);
void __bea_callspec__ cmp_EbGb(PDISASM);
void __bea_callspec__ cmp_EvGv(PDISASM);
void __bea_callspec__ cmp_GbEb(PDISASM);
void __bea_callspec__ cmp_GvEv(PDISASM);
void __bea_callspec__ cmp_ALIb(PDISASM);
void __bea_callspec__ cmp_eAX_Iv(PDISASM);
void __bea_callspec__ cmpsb_(PDISASM);
void __bea_callspec__ cmps_(PDISASM);
void __bea_callspec__ cwde_(PDISASM);
void __bea_callspec__ clc_(PDISASM);
void __bea_callspec__ cld_(PDISASM);
void __bea_callspec__ cli_(PDISASM);
void __bea_callspec__ cpuid_(PDISASM);
void __bea_callspec__ daa_(PDISASM);
void __bea_callspec__ das_(PDISASM);
void __bea_callspec__ dec_eax(PDISASM);
void __bea_callspec__ dec_ecx(PDISASM);
void __bea_callspec__ dec_edx(PDISASM);
void __bea_callspec__ dec_ebx(PDISASM);
void __bea_callspec__ dec_esp(PDISASM);
void __bea_callspec__ dec_ebp(PDISASM);
void __bea_callspec__ dec_esi(PDISASM);
void __bea_callspec__ dec_edi(PDISASM);
void __bea_callspec__ enter_(PDISASM);
void __bea_callspec__ femms_(PDISASM);
void __bea_callspec__ hlt_(PDISASM);
void __bea_callspec__ invd_(PDISASM);
void __bea_callspec__ inc_eax(PDISASM);
void __bea_callspec__ inc_ecx(PDISASM);
void __bea_callspec__ inc_edx(PDISASM);
void __bea_callspec__ inc_ebx(PDISASM);
void __bea_callspec__ inc_esp(PDISASM);
void __bea_callspec__ inc_ebp(PDISASM);
void __bea_callspec__ inc_esi(PDISASM);
void __bea_callspec__ inc_edi(PDISASM);
void __bea_callspec__ iret_(PDISASM);
void __bea_callspec__ in_ALDX(PDISASM);
void __bea_callspec__ in_ALIb(PDISASM);
void __bea_callspec__ in_eAX_Ib(PDISASM);
void __bea_callspec__ insb_(PDISASM);
void __bea_callspec__ ins_(PDISASM);
void __bea_callspec__ into_(PDISASM);
void __bea_callspec__ in_eAX(PDISASM);
void __bea_callspec__ int_(PDISASM);
void __bea_callspec__ int1_(PDISASM);
void __bea_callspec__ int3_(PDISASM);
void __bea_callspec__ imul_GvEvIv(PDISASM);
void __bea_callspec__ imul_GvEv(PDISASM);
void __bea_callspec__ imul_GvEvIb(PDISASM);
void __bea_callspec__ jo_(PDISASM);
void __bea_callspec__ jno_(PDISASM);
void __bea_callspec__ jc_(PDISASM);
void __bea_callspec__ jnc_(PDISASM);
void __bea_callspec__ je_(PDISASM);
void __bea_callspec__ jne_(PDISASM);
void __bea_callspec__ jbe_(PDISASM);
void __bea_callspec__ jnbe_(PDISASM);
void __bea_callspec__ js_(PDISASM);
void __bea_callspec__ jns_(PDISASM);
void __bea_callspec__ jp_(PDISASM);
void __bea_callspec__ jnp_(PDISASM);
void __bea_callspec__ jl_(PDISASM);
void __bea_callspec__ jnl_(PDISASM);
void __bea_callspec__ jle_(PDISASM);
void __bea_callspec__ jnle_(PDISASM);
void __bea_callspec__ jo_near(PDISASM);
void __bea_callspec__ jno_near(PDISASM);
void __bea_callspec__ jc_near(PDISASM);
void __bea_callspec__ jnc_near(PDISASM);
void __bea_callspec__ je_near(PDISASM);
void __bea_callspec__ jne_near(PDISASM);
void __bea_callspec__ jbe_near(PDISASM);
void __bea_callspec__ ja_near(PDISASM);
void __bea_callspec__ js_near(PDISASM);
void __bea_callspec__ jns_near(PDISASM);
void __bea_callspec__ jp_near(PDISASM);
void __bea_callspec__ jnp_near(PDISASM);
void __bea_callspec__ jl_near(PDISASM);
void __bea_callspec__ jnl_near(PDISASM);
void __bea_callspec__ jle_near(PDISASM);
void __bea_callspec__ jnle_near(PDISASM);
void __bea_callspec__ jecxz_(PDISASM);
void __bea_callspec__ jmp_near(PDISASM);
void __bea_callspec__ jmp_far(PDISASM);
void __bea_callspec__ jmp_short(PDISASM);
void __bea_callspec__ lahf_(PDISASM);
void __bea_callspec__ lar_GvEw(PDISASM);
void __bea_callspec__ lds_GvM(PDISASM);
void __bea_callspec__ leave_(PDISASM);
void __bea_callspec__ lea_GvM(PDISASM);
void __bea_callspec__ les_GvM(PDISASM);
void __bea_callspec__ lodsb_(PDISASM);
void __bea_callspec__ lodsw_(PDISASM);
void __bea_callspec__ loop_(PDISASM);
void __bea_callspec__ loope_(PDISASM);
void __bea_callspec__ loopne_(PDISASM);
void __bea_callspec__ lsl_GvEw(PDISASM);
void __bea_callspec__ lss_Mp(PDISASM);
void __bea_callspec__ lfs_Mp(PDISASM);
void __bea_callspec__ lgs_Mp(PDISASM);
void __bea_callspec__ mov_RdCd(PDISASM);
void __bea_callspec__ mov_RdDd(PDISASM);
void __bea_callspec__ mov_CdRd(PDISASM);
void __bea_callspec__ mov_DdRd(PDISASM);
void __bea_callspec__ mov_EbGb(PDISASM);
void __bea_callspec__ mov_EvGv(PDISASM);
void __bea_callspec__ mov_GbEb(PDISASM);
void __bea_callspec__ mov_GvEv(PDISASM);
void __bea_callspec__ mov_ALOb(PDISASM);
void __bea_callspec__ mov_eAXOv(PDISASM);
void __bea_callspec__ mov_ObAL(PDISASM);
void __bea_callspec__ mov_OveAX(PDISASM);
void __bea_callspec__ mov_ALIb(PDISASM);
void __bea_callspec__ mov_CLIb(PDISASM);
void __bea_callspec__ mov_DLIb(PDISASM);
void __bea_callspec__ mov_BLIb(PDISASM);
void __bea_callspec__ mov_AHIb(PDISASM);
void __bea_callspec__ mov_CHIb(PDISASM);
void __bea_callspec__ mov_DHIb(PDISASM);
void __bea_callspec__ mov_BHIb(PDISASM);
void __bea_callspec__ movs_(PDISASM);
void __bea_callspec__ movsw_(PDISASM);
void __bea_callspec__ movzx_GvEb(PDISASM);
void __bea_callspec__ movsx_GvEb(PDISASM);
void __bea_callspec__ movzx_GvEw(PDISASM);
void __bea_callspec__ movsx_GvEw(PDISASM);
void __bea_callspec__ mov_EAX(PDISASM);
void __bea_callspec__ mov_ECX(PDISASM);
void __bea_callspec__ mov_EDX(PDISASM);
void __bea_callspec__ mov_EBX(PDISASM);
void __bea_callspec__ mov_ESP(PDISASM);
void __bea_callspec__ mov_EBP(PDISASM);
void __bea_callspec__ mov_ESI(PDISASM);
void __bea_callspec__ mov_EDI(PDISASM);
void __bea_callspec__ mov_EbIb(PDISASM);
void __bea_callspec__ mov_EvIv(PDISASM);
void __bea_callspec__ mov_EwSreg(PDISASM);
void __bea_callspec__ mov_SregEw(PDISASM);
/* ====================================== opcodes_N_Z */
void __bea_callspec__ nop_(PDISASM);
void __bea_callspec__ nop_Ev(PDISASM);
void __bea_callspec__ hint_nop(PDISASM);
void __bea_callspec__ or_EbGb(PDISASM);
void __bea_callspec__ or_EvGv(PDISASM);
void __bea_callspec__ or_GbEb(PDISASM);
void __bea_callspec__ or_GvEv(PDISASM);
void __bea_callspec__ or_ALIb(PDISASM);
void __bea_callspec__ or_eAX_Iv(PDISASM);
void __bea_callspec__ outsb_(PDISASM);
void __bea_callspec__ outsw_(PDISASM);
void __bea_callspec__ out_IbAL(PDISASM);
void __bea_callspec__ out_Ib_eAX(PDISASM);
void __bea_callspec__ out_DXAL(PDISASM);
void __bea_callspec__ out_DXeAX(PDISASM);
void __bea_callspec__ pop_Ev(PDISASM);
void __bea_callspec__ pop_eax(PDISASM);
void __bea_callspec__ pop_ecx(PDISASM);
void __bea_callspec__ pop_edx(PDISASM);
void __bea_callspec__ pop_ebx(PDISASM);
void __bea_callspec__ pop_esp(PDISASM);
void __bea_callspec__ pop_ebp(PDISASM);
void __bea_callspec__ pop_esi(PDISASM);
void __bea_callspec__ pop_edi(PDISASM);
void __bea_callspec__ pop_ds(PDISASM);
void __bea_callspec__ pop_es(PDISASM);
void __bea_callspec__ pop_fs(PDISASM);
void __bea_callspec__ pop_gs(PDISASM);
void __bea_callspec__ pop_ss(PDISASM);
void __bea_callspec__ popfd_(PDISASM);
void __bea_callspec__ popad_(PDISASM);
void __bea_callspec__ push_eax(PDISASM);
void __bea_callspec__ push_ecx(PDISASM);
void __bea_callspec__ push_edx(PDISASM);
void __bea_callspec__ push_ebx(PDISASM);
void __bea_callspec__ push_esp(PDISASM);
void __bea_callspec__ push_ebp(PDISASM);
void __bea_callspec__ push_esi(PDISASM);
void __bea_callspec__ push_edi(PDISASM);
void __bea_callspec__ push_cs(PDISASM);
void __bea_callspec__ push_ds(PDISASM);
void __bea_callspec__ push_es(PDISASM);
void __bea_callspec__ push_fs(PDISASM);
void __bea_callspec__ push_gs(PDISASM);
void __bea_callspec__ push_ss(PDISASM);
void __bea_callspec__ pushfd_(PDISASM);
void __bea_callspec__ pushad_(PDISASM);
void __bea_callspec__ push_Iv(PDISASM);
void __bea_callspec__ push_Ib(PDISASM);
void __bea_callspec__ pushfd_(PDISASM);
void __bea_callspec__ pushad_(PDISASM);
void __bea_callspec__ retn_(PDISASM);
void __bea_callspec__ ret_(PDISASM);
void __bea_callspec__ retf_(PDISASM);
void __bea_callspec__ retf_Iw(PDISASM);
void __bea_callspec__ rdtsc_(PDISASM);
void __bea_callspec__ rdmsr_(PDISASM);
void __bea_callspec__ rdpmc_(PDISASM);
void __bea_callspec__ rsm_(PDISASM);
void __bea_callspec__ sysenter_(PDISASM);
void __bea_callspec__ sysexit_(PDISASM);
void __bea_callspec__ sahf_(PDISASM);
void __bea_callspec__ salc_(PDISASM);
void __bea_callspec__ scasb_(PDISASM);
void __bea_callspec__ scas_(PDISASM);
void __bea_callspec__ stc_(PDISASM);
void __bea_callspec__ sti_(PDISASM);
void __bea_callspec__ stos_(PDISASM);
void __bea_callspec__ stosw_(PDISASM);
void __bea_callspec__ syscall_(PDISASM);
void __bea_callspec__ sysret_(PDISASM);
void __bea_callspec__ sbb_EbGb(PDISASM);
void __bea_callspec__ sbb_EvGv(PDISASM);
void __bea_callspec__ sbb_GbEb(PDISASM);
void __bea_callspec__ sbb_GvEv(PDISASM);
void __bea_callspec__ sbb_ALIb(PDISASM);
void __bea_callspec__ sbb_eAX_Iv(PDISASM);
void __bea_callspec__ seto_(PDISASM);
void __bea_callspec__ setno_(PDISASM);
void __bea_callspec__ setb_(PDISASM);
void __bea_callspec__ setnb_(PDISASM);
void __bea_callspec__ sete_(PDISASM);
void __bea_callspec__ setne_(PDISASM);
void __bea_callspec__ setbe_(PDISASM);
void __bea_callspec__ setnbe_(PDISASM);
void __bea_callspec__ sets_(PDISASM);
void __bea_callspec__ setns_(PDISASM);
void __bea_callspec__ setp_(PDISASM);
void __bea_callspec__ setnp_(PDISASM);
void __bea_callspec__ setnge_(PDISASM);
void __bea_callspec__ setge_(PDISASM);
void __bea_callspec__ setle_(PDISASM);
void __bea_callspec__ setnle_(PDISASM);
void __bea_callspec__ shld_EvGvIb(PDISASM);
void __bea_callspec__ shld_EvGvCL(PDISASM);
void __bea_callspec__ shrd_EvGvIb(PDISASM);
void __bea_callspec__ shrd_EvGvCL(PDISASM);
void __bea_callspec__ std_(PDISASM);
void __bea_callspec__ sub_ALIb(PDISASM);
void __bea_callspec__ sub_eAX_Iv(PDISASM);
void __bea_callspec__ sub_EbGb(PDISASM);
void __bea_callspec__ sub_EvGv(PDISASM);
void __bea_callspec__ sub_GbEb(PDISASM);
void __bea_callspec__ sub_GvEv(PDISASM);
void __bea_callspec__ test_ALIb(PDISASM);
void __bea_callspec__ test_eAX_Iv(PDISASM);
void __bea_callspec__ test_EbGb(PDISASM);
void __bea_callspec__ test_EvGv(PDISASM);
void __bea_callspec__ test_GbEb(PDISASM);
void __bea_callspec__ test_GvEv(PDISASM);
void __bea_callspec__ ud2_(PDISASM);
void __bea_callspec__ vmread_(PDISASM);
void __bea_callspec__ vmwrite_(PDISASM);
void __bea_callspec__ wbinvd_(PDISASM);
void __bea_callspec__ wait_(PDISASM);
void __bea_callspec__ wrmsr_(PDISASM);
void __bea_callspec__ xadd_EbGb(PDISASM);
void __bea_callspec__ xadd_EvGv(PDISASM);
void __bea_callspec__ xchg_EbGb(PDISASM);
void __bea_callspec__ xchg_ebp(PDISASM);
void __bea_callspec__ xchg_ebx(PDISASM);
void __bea_callspec__ xchg_ecx(PDISASM);
void __bea_callspec__ xchg_edi(PDISASM);
void __bea_callspec__ xchg_edx(PDISASM);
void __bea_callspec__ xchg_esi(PDISASM);
void __bea_callspec__ xchg_esp(PDISASM);
void __bea_callspec__ xchg_EvGv(PDISASM);
void __bea_callspec__ xlat_(PDISASM);
void __bea_callspec__ xor_ALIb(PDISASM);
void __bea_callspec__ xor_eAX_Iv(PDISASM);
void __bea_callspec__ xor_EbGb(PDISASM);
void __bea_callspec__ xor_EvGv(PDISASM);
void __bea_callspec__ xor_GbEb(PDISASM);
void __bea_callspec__ xor_GvEv(PDISASM);
/* ====================================== opcodes_Grp1 */
void __bea_callspec__ G1_EbIb(PDISASM);
void __bea_callspec__ G1_EbIb2(PDISASM);
void __bea_callspec__ G1_EvIv(PDISASM);
void __bea_callspec__ G1_EvIb(PDISASM);
/* ====================================== opcodes_Grp2 */
void __bea_callspec__ G2_EbIb(PDISASM);
void __bea_callspec__ G2_EvIb(PDISASM);
void __bea_callspec__ G2_Ev1(PDISASM);
void __bea_callspec__ G2_Eb1(PDISASM);
void __bea_callspec__ G2_EbCL(PDISASM);
void __bea_callspec__ G2_EvCL(PDISASM);
/* ====================================== opcodes_Grp3 */
void __bea_callspec__ G3_Eb(PDISASM);
void __bea_callspec__ G3_Ev(PDISASM);
/* ====================================== opcodes_Grp4 */
void __bea_callspec__ G4_Eb(PDISASM);
/* ====================================== opcodes_Grp5 */
void __bea_callspec__ G5_Ev(PDISASM);
/* ====================================== opcodes_Grp6 */
void __bea_callspec__ G6_(PDISASM);
/* ====================================== opcodes_Grp7 */
void __bea_callspec__ G7_(PDISASM);
/* ====================================== opcodes_Grp8 */
void __bea_callspec__ G8_EvIb(PDISASM);
/* ====================================== opcodes_Grp9 */
void __bea_callspec__ G9_(PDISASM);
/* ====================================== opcodes_Grp12 */
void __bea_callspec__ G12_(PDISASM);
/* ====================================== opcodes_Grp13 */
void __bea_callspec__ G13_(PDISASM);
/* ====================================== opcodes_Grp14 */
void __bea_callspec__ G14_(PDISASM);
/* ====================================== opcodes_Grp15 */
void __bea_callspec__ G15_(PDISASM);
/* ====================================== opcodes_Grp16 */
void __bea_callspec__ G16_(PDISASM);
/* ====================================== opcodes_FPU */
void __bea_callspec__ D8_(PDISASM);
void __bea_callspec__ D9_(PDISASM);
void __bea_callspec__ DA_(PDISASM);
void __bea_callspec__ DB_(PDISASM);
void __bea_callspec__ DC_(PDISASM);
void __bea_callspec__ DD_(PDISASM);
void __bea_callspec__ DE_(PDISASM);
void __bea_callspec__ DF_(PDISASM);
/* ====================================== opcodes_MMX */
void __bea_callspec__ emms_(PDISASM);
void __bea_callspec__ movd_EP(PDISASM);
void __bea_callspec__ movd_PE(PDISASM);
void __bea_callspec__ movq_PQ(PDISASM);
void __bea_callspec__ movq_QP(PDISASM);
void __bea_callspec__ movq_WV(PDISASM);
void __bea_callspec__ pabsb_(PDISASM);
void __bea_callspec__ pabsd_(PDISASM);
void __bea_callspec__ pabsw_(PDISASM);
void __bea_callspec__ packssdw_(PDISASM);
void __bea_callspec__ packsswb_(PDISASM);
void __bea_callspec__ packuswb_(PDISASM);
void __bea_callspec__ paddb_(PDISASM);
void __bea_callspec__ paddd_(PDISASM);
void __bea_callspec__ paddsb_(PDISASM);
void __bea_callspec__ paddsw_(PDISASM);
void __bea_callspec__ paddusb_(PDISASM);
void __bea_callspec__ paddusw_(PDISASM);
void __bea_callspec__ paddw_(PDISASM);
void __bea_callspec__ pandn_(PDISASM);
void __bea_callspec__ pand_(PDISASM);
void __bea_callspec__ pcmpeqb_(PDISASM);
void __bea_callspec__ pcmpeqd_(PDISASM);
void __bea_callspec__ pcmpeqw_(PDISASM);
void __bea_callspec__ pcmpgtb_(PDISASM);
void __bea_callspec__ pcmpgtd_(PDISASM);
void __bea_callspec__ pcmpgtw_(PDISASM);
void __bea_callspec__ pmulhw_(PDISASM);
void __bea_callspec__ pmullw_(PDISASM);
void __bea_callspec__ pmaddwd_(PDISASM);
void __bea_callspec__ por_(PDISASM);
void __bea_callspec__ pslld_(PDISASM);
void __bea_callspec__ psllq_(PDISASM);
void __bea_callspec__ psllw_(PDISASM);
void __bea_callspec__ psrld_(PDISASM);
void __bea_callspec__ psrlq_(PDISASM);
void __bea_callspec__ psrlw_(PDISASM);
void __bea_callspec__ psrad_(PDISASM);
void __bea_callspec__ psraw_(PDISASM);
void __bea_callspec__ psubb_(PDISASM);
void __bea_callspec__ psubd_(PDISASM);
void __bea_callspec__ psubsb_(PDISASM);
void __bea_callspec__ psubsw_(PDISASM);
void __bea_callspec__ psubusb_(PDISASM);
void __bea_callspec__ psubusw_(PDISASM);
void __bea_callspec__ psubw_(PDISASM);
void __bea_callspec__ punpckhbw_(PDISASM);
void __bea_callspec__ punpckhdq_(PDISASM);
void __bea_callspec__ punpckhwd_(PDISASM);
void __bea_callspec__ punpcklbw_(PDISASM);
void __bea_callspec__ punpckldq_(PDISASM);
void __bea_callspec__ punpcklwd_(PDISASM);
void __bea_callspec__ pxor_(PDISASM);
/* ====================================== opcodes_SSE */
void __bea_callspec__ addps_VW(PDISASM);
void __bea_callspec__ addsubpd_(PDISASM);
void __bea_callspec__ andnps_VW(PDISASM);
void __bea_callspec__ andps_VW(PDISASM);
void __bea_callspec__ blendpd_(PDISASM);
void __bea_callspec__ blendps_(PDISASM);
void __bea_callspec__ blendvpd_(PDISASM);
void __bea_callspec__ blendvps_(PDISASM);
void __bea_callspec__ cmpps_VW(PDISASM);
void __bea_callspec__ crc32_GvEb(PDISASM);
void __bea_callspec__ crc32_GvEv(PDISASM);
void __bea_callspec__ comiss_VW(PDISASM);
void __bea_callspec__ cvtdq2ps_(PDISASM);
void __bea_callspec__ cvtpd2dq_(PDISASM);
void __bea_callspec__ cvtpi2ps_(PDISASM);
void __bea_callspec__ cvtps2pd_(PDISASM);
void __bea_callspec__ cvtps2pi_(PDISASM);
void __bea_callspec__ cvttps2pi_(PDISASM);
void __bea_callspec__ dppd_(PDISASM);
void __bea_callspec__ dpps_(PDISASM);
void __bea_callspec__ divps_VW(PDISASM);
void __bea_callspec__ extractps_(PDISASM);
void __bea_callspec__ haddpd_VW(PDISASM);
void __bea_callspec__ hsubpd_VW(PDISASM);
void __bea_callspec__ insertps_(PDISASM);
void __bea_callspec__ lddqu_(PDISASM);
void __bea_callspec__ maskmovq_(PDISASM);
void __bea_callspec__ maxps_VW(PDISASM);
void __bea_callspec__ minps_VW(PDISASM);
void __bea_callspec__ movaps_VW(PDISASM);
void __bea_callspec__ movaps_WV(PDISASM);
void __bea_callspec__ movhps_MV(PDISASM);
void __bea_callspec__ movhps_VM(PDISASM);
void __bea_callspec__ movlps_MV(PDISASM);
void __bea_callspec__ movlps_VM(PDISASM);
void __bea_callspec__ movmskps_(PDISASM);
void __bea_callspec__ movntdqa_(PDISASM);
void __bea_callspec__ movnti_(PDISASM);
void __bea_callspec__ movntps_(PDISASM);
void __bea_callspec__ movntq_(PDISASM);
void __bea_callspec__ movups_VW(PDISASM);
void __bea_callspec__ movups_WV(PDISASM);
void __bea_callspec__ mpsadbw_(PDISASM);
void __bea_callspec__ mulps_VW(PDISASM);
void __bea_callspec__ orps_VW(PDISASM);
void __bea_callspec__ packusdw_(PDISASM);
void __bea_callspec__ paddq_(PDISASM);
void __bea_callspec__ pavgb_(PDISASM);
void __bea_callspec__ pavgw_(PDISASM);
void __bea_callspec__ palignr_(PDISASM);
void __bea_callspec__ pblendvb_(PDISASM);
void __bea_callspec__ pblendw_(PDISASM);
void __bea_callspec__ pcmpeqq_(PDISASM);
void __bea_callspec__ pcmpestri_(PDISASM);
void __bea_callspec__ pcmpestrm_(PDISASM);
void __bea_callspec__ pcmpgtq_(PDISASM);
void __bea_callspec__ pcmpistri_(PDISASM);
void __bea_callspec__ pcmpistrm_(PDISASM);
void __bea_callspec__ pextrb_(PDISASM);
void __bea_callspec__ pextrd_(PDISASM);
void __bea_callspec__ pextrw2_(PDISASM);
void __bea_callspec__ pextrw_(PDISASM);
void __bea_callspec__ phaddd_(PDISASM);
void __bea_callspec__ phaddsw_(PDISASM);
void __bea_callspec__ phaddw_(PDISASM);
void __bea_callspec__ phminposuw_(PDISASM);
void __bea_callspec__ phsubd_(PDISASM);
void __bea_callspec__ phsubsw_(PDISASM);
void __bea_callspec__ phsubw_(PDISASM);
void __bea_callspec__ pinsrb_(PDISASM);
void __bea_callspec__ pinsrd_(PDISASM);
void __bea_callspec__ pinsrw_(PDISASM);
void __bea_callspec__ pmaxsb_(PDISASM);
void __bea_callspec__ pmaxsd_(PDISASM);
void __bea_callspec__ pmaxsw_(PDISASM);
void __bea_callspec__ pmaxub_(PDISASM);
void __bea_callspec__ pmaxud_(PDISASM);
void __bea_callspec__ pmaxuw_(PDISASM);
void __bea_callspec__ pminsb_(PDISASM);
void __bea_callspec__ pminsd_(PDISASM);
void __bea_callspec__ pminsw_(PDISASM);
void __bea_callspec__ pminub_(PDISASM);
void __bea_callspec__ pminud_(PDISASM);
void __bea_callspec__ pminuw_(PDISASM);
void __bea_callspec__ pmaddubsw_(PDISASM);
void __bea_callspec__ pmovmskb_(PDISASM);
void __bea_callspec__ pmovsxbd_(PDISASM);
void __bea_callspec__ pmovsxbq_(PDISASM);
void __bea_callspec__ pmovsxbw_(PDISASM);
void __bea_callspec__ pmovsxdq_(PDISASM);
void __bea_callspec__ pmovsxwd_(PDISASM);
void __bea_callspec__ pmovsxwq_(PDISASM);
void __bea_callspec__ pmovzxbd_(PDISASM);
void __bea_callspec__ pmovzxbq_(PDISASM);
void __bea_callspec__ pmovzxbw_(PDISASM);
void __bea_callspec__ pmovzxdq_(PDISASM);
void __bea_callspec__ pmovzxwd_(PDISASM);
void __bea_callspec__ pmovzxwq_(PDISASM);
void __bea_callspec__ pmuldq_(PDISASM);
void __bea_callspec__ pmulhrsw_(PDISASM);
void __bea_callspec__ pmulhuw_(PDISASM);
void __bea_callspec__ pmulhw_(PDISASM);
void __bea_callspec__ pmulld_(PDISASM);
void __bea_callspec__ pmullw_(PDISASM);
void __bea_callspec__ pmuludq_(PDISASM);
void __bea_callspec__ popcnt_(PDISASM);
void __bea_callspec__ psadbw_(PDISASM);
void __bea_callspec__ pshufb_(PDISASM);
void __bea_callspec__ pshufw_(PDISASM);
void __bea_callspec__ psignb_(PDISASM);
void __bea_callspec__ psignd_(PDISASM);
void __bea_callspec__ psignw_(PDISASM);
void __bea_callspec__ psubq_(PDISASM);
void __bea_callspec__ ptest_(PDISASM);
void __bea_callspec__ punpcklqdq_(PDISASM);
void __bea_callspec__ punpckhqdq_(PDISASM);
void __bea_callspec__ rcpps_(PDISASM);
void __bea_callspec__ roundpd_(PDISASM);
void __bea_callspec__ roundps_(PDISASM);
void __bea_callspec__ roundsd_(PDISASM);
void __bea_callspec__ roundss_(PDISASM);
void __bea_callspec__ rsqrtps_(PDISASM);
void __bea_callspec__ shufps_(PDISASM);
void __bea_callspec__ sqrtps_VW(PDISASM);
void __bea_callspec__ subps_VW(PDISASM);
void __bea_callspec__ ucomiss_VW(PDISASM);
void __bea_callspec__ unpckhps_(PDISASM);
void __bea_callspec__ unpcklps_(PDISASM);
void __bea_callspec__ xorps_VW(PDISASM);
/* ====================================== opcodes_AES */
void __bea_callspec__ aesimc(PDISASM);
void __bea_callspec__ aesdec(PDISASM);
void __bea_callspec__ aesdeclast(PDISASM);
void __bea_callspec__ aesenc(PDISASM);
void __bea_callspec__ aesenclast(PDISASM);
void __bea_callspec__ aeskeygen(PDISASM);
/* ====================================== opcodes_CLMUL */
void __bea_callspec__ pclmulqdq_(PDISASM);

30
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@ -1,30 +0,0 @@
; ========================================
;
; BeaEngine 4
;
; ========================================
1) LICENSE
==========
This software is distributed under the LGPL license.
See the COPYING and COPYING.LESSER files for more details.
2) ONLINE DOCUMENTATION
=======================
For online documentation, visit :
http://www.beaengine.org
3) AUTHOR, CONTRIBUTORS, BETA-TESTERS
==========================================
BeatriX - Author (France) : beaengine (at) gmail.com
Igor Gutnik - Developer (ported the project on linux)
Contributors :
andrewl, bax, William Pomian, Ange Albertini, Pyrae, Vincent Roy, Kharneth, Eedy, Neitsa, KumaT, Rafal Cyran, 29a metal, sessiondiy, Tim, vince, Igor Gutnik, ouadji, Helle, Baboon, pop9080, ktion23.

362
deps/beaengine-4.1/include/beaengine/BeaEngine.h vendored
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@ -1,362 +0,0 @@
#ifndef _BEA_ENGINE_
#define _BEA_ENGINE_
#if defined(__cplusplus) && defined(__BORLANDC__)
namespace BeaEngine {
#endif
#include <beaengine/macros.h>
#include <beaengine/export.h>
#include <beaengine/basic_types.h>
#if !defined(BEA_ENGINE_STATIC)
#if defined(BUILD_BEA_ENGINE_DLL)
#define BEA_API bea__api_export__
#else
#define BEA_API bea__api_import__
#endif
#else
#define BEA_API
#endif
#define INSTRUCT_LENGTH 64
#pragma pack(1)
typedef struct {
UInt8 W_;
UInt8 R_;
UInt8 X_;
UInt8 B_;
UInt8 state;
} REX_Struct ;
#pragma pack()
#pragma pack(1)
typedef struct {
int Number;
int NbUndefined;
UInt8 LockPrefix;
UInt8 OperandSize;
UInt8 AddressSize;
UInt8 RepnePrefix;
UInt8 RepPrefix;
UInt8 FSPrefix;
UInt8 SSPrefix;
UInt8 GSPrefix;
UInt8 ESPrefix;
UInt8 CSPrefix;
UInt8 DSPrefix;
UInt8 BranchTaken;
UInt8 BranchNotTaken;
REX_Struct REX;
char alignment[2];
} PREFIXINFO ;
#pragma pack()
#pragma pack(1)
typedef struct {
UInt8 OF_;
UInt8 SF_;
UInt8 ZF_;
UInt8 AF_;
UInt8 PF_;
UInt8 CF_;
UInt8 TF_;
UInt8 IF_;
UInt8 DF_;
UInt8 NT_;
UInt8 RF_;
UInt8 alignment;
} EFLStruct ;
#pragma pack()
#pragma pack(4)
typedef struct {
Int32 BaseRegister;
Int32 IndexRegister;
Int32 Scale;
Int64 Displacement;
} MEMORYTYPE ;
#pragma pack()
#pragma pack(1)
typedef struct {
Int32 Category;
Int32 Opcode;
char Mnemonic[16];
Int32 BranchType;
EFLStruct Flags;
UInt64 AddrValue;
Int64 Immediat;
UInt32 ImplicitModifiedRegs;
} INSTRTYPE;
#pragma pack()
#pragma pack(1)
typedef struct {
char ArgMnemonic[64];
Int32 ArgType;
Int32 ArgSize;
Int32 ArgPosition;
UInt32 AccessMode;
MEMORYTYPE Memory;
UInt32 SegmentReg;
} ARGTYPE;
#pragma pack()
/* reserved structure used for thread-safety */
/* unusable by customer */
#pragma pack(1)
typedef struct {
UIntPtr EIP_;
UInt64 EIP_VA;
UIntPtr EIP_REAL;
Int32 OriginalOperandSize;
Int32 OperandSize;
Int32 MemDecoration;
Int32 AddressSize;
Int32 MOD_;
Int32 RM_;
Int32 INDEX_;
Int32 SCALE_;
Int32 BASE_;
Int32 MMX_;
Int32 SSE_;
Int32 CR_;
Int32 DR_;
Int32 SEG_;
Int32 REGOPCODE;
UInt32 DECALAGE_EIP;
Int32 FORMATNUMBER;
Int32 SYNTAX_;
UInt64 EndOfBlock;
Int32 RelativeAddress;
UInt32 Architecture;
Int32 ImmediatSize;
Int32 NB_PREFIX;
Int32 PrefRepe;
Int32 PrefRepne;
UInt32 SEGMENTREGS;
UInt32 SEGMENTFS;
Int32 third_arg;
Int32 TAB_;
Int32 ERROR_OPCODE;
REX_Struct REX;
Int32 OutOfBlock;
} InternalDatas;
#pragma pack()
/* ************** main structure ************ */
#pragma pack(1)
typedef struct _Disasm {
UIntPtr EIP;
UInt64 VirtualAddr;
UInt32 SecurityBlock;
char CompleteInstr[INSTRUCT_LENGTH];
UInt32 Archi;
UInt64 Options;
INSTRTYPE Instruction;
ARGTYPE Argument1;
ARGTYPE Argument2;
ARGTYPE Argument3;
PREFIXINFO Prefix;
InternalDatas Reserved_;
} DISASM, *PDISASM, *LPDISASM;
#pragma pack()
#define ESReg 1
#define DSReg 2
#define FSReg 3
#define GSReg 4
#define CSReg 5
#define SSReg 6
#define InvalidPrefix 4
#define SuperfluousPrefix 2
#define NotUsedPrefix 0
#define MandatoryPrefix 8
#define InUsePrefix 1
#define LowPosition 0
#define HighPosition 1
enum INSTRUCTION_TYPE
{
GENERAL_PURPOSE_INSTRUCTION = 0x10000,
FPU_INSTRUCTION = 0x20000,
MMX_INSTRUCTION = 0x40000,
SSE_INSTRUCTION = 0x80000,
SSE2_INSTRUCTION = 0x100000,
SSE3_INSTRUCTION = 0x200000,
SSSE3_INSTRUCTION = 0x400000,
SSE41_INSTRUCTION = 0x800000,
SSE42_INSTRUCTION = 0x1000000,
SYSTEM_INSTRUCTION = 0x2000000,
VM_INSTRUCTION = 0x4000000,
UNDOCUMENTED_INSTRUCTION = 0x8000000,
AMD_INSTRUCTION = 0x10000000,
ILLEGAL_INSTRUCTION = 0x20000000,
AES_INSTRUCTION = 0x40000000,
CLMUL_INSTRUCTION = (int)0x80000000,
DATA_TRANSFER = 0x1,
ARITHMETIC_INSTRUCTION,
LOGICAL_INSTRUCTION,
SHIFT_ROTATE,
BIT_UInt8,
CONTROL_TRANSFER,
STRING_INSTRUCTION,
InOutINSTRUCTION,
ENTER_LEAVE_INSTRUCTION,
FLAG_CONTROL_INSTRUCTION,
SEGMENT_REGISTER,
MISCELLANEOUS_INSTRUCTION,
COMPARISON_INSTRUCTION,
LOGARITHMIC_INSTRUCTION,
TRIGONOMETRIC_INSTRUCTION,
UNSUPPORTED_INSTRUCTION,
LOAD_CONSTANTS,
FPUCONTROL,
STATE_MANAGEMENT,
CONVERSION_INSTRUCTION,
SHUFFLE_UNPACK,
PACKED_SINGLE_PRECISION,
SIMD128bits,
SIMD64bits,
CACHEABILITY_CONTROL,
FP_INTEGER_CONVERSION,
SPECIALIZED_128bits,
SIMD_FP_PACKED,
SIMD_FP_HORIZONTAL ,
AGENT_SYNCHRONISATION,
PACKED_ALIGN_RIGHT ,
PACKED_SIGN,
PACKED_BLENDING_INSTRUCTION,
PACKED_TEST,
PACKED_MINMAX,
HORIZONTAL_SEARCH,
PACKED_EQUALITY,
STREAMING_LOAD,
INSERTION_EXTRACTION,
DOT_PRODUCT,
SAD_INSTRUCTION,
ACCELERATOR_INSTRUCTION, /* crc32, popcnt (sse4.2) */
ROUND_INSTRUCTION
};
enum EFLAGS_STATES
{
TE_ = 1,
MO_ = 2,
RE_ = 4,
SE_ = 8,
UN_ = 0x10,
PR_ = 0x20
};
enum BRANCH_TYPE
{
JO = 1,
JC = 2,
JE = 3,
JA = 4,
JS = 5,
JP = 6,
JL = 7,
JG = 8,
JB = 2, // JC == JB
JECXZ = 10,
JmpType = 11,
CallType = 12,
RetType = 13,
JNO = -1,
JNC = -2,
JNE = -3,
JNA = -4,
JNS = -5,
JNP = -6,
JNL = -7,
JNG = -8,
JNB = -2 // JNC == JNB
};
enum ARGUMENTS_TYPE
{
NO_ARGUMENT = 0x10000000,
REGISTER_TYPE = 0x20000000,
MEMORY_TYPE = 0x40000000,
CONSTANT_TYPE = (int)0x80000000,
MMX_REG = 0x10000,
GENERAL_REG = 0x20000,
FPU_REG = 0x40000,
SSE_REG = 0x80000,
CR_REG = 0x100000,
DR_REG = 0x200000,
SPECIAL_REG = 0x400000,
MEMORY_MANAGEMENT_REG = 0x800000,
SEGMENT_REG = 0x1000000,
RELATIVE_ = 0x4000000,
ABSOLUTE_ = 0x8000000,
READ = 0x1,
WRITE = 0x2,
REG0 = 0x1,
REG1 = 0x2,
REG2 = 0x4,
REG3 = 0x8,
REG4 = 0x10,
REG5 = 0x20,
REG6 = 0x40,
REG7 = 0x80,
REG8 = 0x100,
REG9 = 0x200,
REG10 = 0x400,
REG11 = 0x800,
REG12 = 0x1000,
REG13 = 0x2000,
REG14 = 0x4000,
REG15 = 0x8000
};
enum SPECIAL_INFO
{
UNKNOWN_OPCODE = -1,
OUT_OF_BLOCK = 0,
/* === mask = 0xff */
NoTabulation = 0x00000000,
Tabulation = 0x00000001,
/* === mask = 0xff00 */
MasmSyntax = 0x00000000,
GoAsmSyntax = 0x00000100,
NasmSyntax = 0x00000200,
ATSyntax = 0x00000400,
/* === mask = 0xff0000 */
PrefixedNumeral = 0x00010000,
SuffixedNumeral = 0x00000000,
/* === mask = 0xff000000 */
ShowSegmentRegs = 0x01000000
};
#ifdef __cplusplus
extern "C"
#endif
BEA_API int __bea_callspec__ Disasm (LPDISASM pDisAsm);
BEA_API const__ char* __bea_callspec__ BeaEngineVersion (void);
BEA_API const__ char* __bea_callspec__ BeaEngineRevision (void);
#if defined(__cplusplus) && defined(__BORLANDC__)
};
using namespace BeaEngine;
#endif
#endif

272
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/**
* @file basic_types.h
* @author <igor.gutnik@gmail.com>
* @date Thu Dec 24 19:31:22 2009
*
* @brief Definitions of fixed-size integer types for various platforms
*
* This file is part of BeaEngine.
*
* BeaEngine is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BeaEngine is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with BeaEngine. If not, see <http://www.gnu.org/licenses/>. */
#ifndef __BEA_BASIC_TYPES_HPP__
#define __BEA_BASIC_TYPES_HPP__
#include <stddef.h>
#if defined(__GNUC__) || defined (__INTEL_COMPILER) || defined(__LCC__) || defined(__POCC__)
#include <stdint.h>
#endif
#if defined(_MSC_VER) && !defined(__BORLANDC__)
/*
* Windows/Visual C++
*/
typedef signed char Int8;
typedef unsigned char UInt8;
typedef signed short Int16;
typedef unsigned short UInt16;
typedef signed int Int32;
typedef unsigned int UInt32;
typedef signed __int64 Int64;
typedef unsigned __int64 UInt64;
#if defined(_WIN64)
#define BEA_PTR_IS_64_BIT 1
typedef signed __int64 IntPtr;
typedef unsigned __int64 UIntPtr;
#else
typedef signed long IntPtr;
typedef size_t UIntPtr;
#endif
#define BEA_HAVE_INT64 1
#elif defined(__POCC__)
/*
* PellesC
*/
typedef signed char Int8;
typedef unsigned char UInt8;
typedef signed short Int16;
typedef unsigned short UInt16;
typedef signed int Int32;
typedef unsigned int UInt32;
typedef signed long long Int64;
typedef unsigned long long UInt64;
#if defined(_WIN64)
#define BEA_PTR_IS_64_BIT 1
typedef signed long long IntPtr;
typedef unsigned long long UIntPtr;
#else
typedef signed long IntPtr;
typedef size_t UIntPtr;
#endif
#define BEA_HAVE_INT64 1
#elif defined(__GNUC__) || defined(__LCC__)
/*
* Unix/GCC
*/
typedef signed char Int8;
typedef unsigned char UInt8;
typedef signed short Int16;
typedef unsigned short UInt16;
typedef signed int Int32;
typedef unsigned int UInt32;
typedef intptr_t IntPtr;
typedef uintptr_t UIntPtr;
#if defined(__LP64__)
#define BEA_PTR_IS_64_BIT 1
#define BEA_LONG_IS_64_BIT 1
typedef signed long Int64;
typedef unsigned long UInt64;
#else
#if defined (__INTEL_COMPILER) || defined (__ICC) || defined (_ICC)
typedef __int64 Int64;
typedef unsigned __int64 UInt64;
#else
typedef signed long long Int64;
typedef unsigned long long UInt64;
#endif
#endif
#define BEA_HAVE_INT64 1
#elif defined(__DECCXX)
/*
* Compaq C++
*/
typedef signed char Int8;
typedef unsigned char UInt8;
typedef signed short Int16;
typedef unsigned short UInt16;
typedef signed int Int32;
typedef unsigned int UInt32;
typedef signed __int64 Int64;
typedef unsigned __int64 UInt64;
#if defined(__VMS)
#if defined(__32BITS)
typedef signed long IntPtr;
typedef unsigned long UIntPtr;
#else
typedef Int64 IntPtr;
typedef UInt64 UIntPtr;
#define BEA_PTR_IS_64_BIT 1
#endif
#else
typedef signed long IntPtr;
typedef unsigned long UIntPtr;
#define BEA_PTR_IS_64_BIT 1
#define BEA_LONG_IS_64_BIT 1
#endif
#define BEA_HAVE_INT64 1
#elif defined(__HP_aCC)
/*
* HP Ansi C++
*/
typedef signed char Int8;
typedef unsigned char UInt8;
typedef signed short Int16;
typedef unsigned short UInt16;
typedef signed int Int32;
typedef unsigned int UInt32;
typedef signed long IntPtr;
typedef unsigned long UIntPtr;
#if defined(__LP64__)
#define BEA_PTR_IS_64_BIT 1
#define BEA_LONG_IS_64_BIT 1
typedef signed long Int64;
typedef unsigned long UInt64;
#else
typedef signed long long Int64;
typedef unsigned long long UInt64;
#endif
#define BEA_HAVE_INT64 1
#elif defined(__SUNPRO_CC) || defined(__SUNPRO_C)
/*
* SUN Forte C++
*/
typedef signed char Int8;
typedef unsigned char UInt8;
typedef signed short Int16;
typedef unsigned short UInt16;
typedef signed int Int32;
typedef unsigned int UInt32;
typedef signed long IntPtr;
typedef unsigned long UIntPtr;
#if defined(__sparcv9)
#define BEA_PTR_IS_64_BIT 1
#define BEA_LONG_IS_64_BIT 1
typedef signed long Int64;
typedef unsigned long UInt64;
#else
typedef signed long long Int64;
typedef unsigned long long UInt64;
#endif
#define BEA_HAVE_INT64 1
#elif defined(__IBMCPP__)
/*
* IBM XL C++
*/
typedef signed char Int8;
typedef unsigned char UInt8;
typedef signed short Int16;
typedef unsigned short UInt16;
typedef signed int Int32;
typedef unsigned int UInt32;
typedef signed long IntPtr;
typedef unsigned long UIntPtr;
#if defined(__64BIT__)
#define BEA_PTR_IS_64_BIT 1
#define BEA_LONG_IS_64_BIT 1
typedef signed long Int64;
typedef unsigned long UInt64;
#else
typedef signed long long Int64;
typedef unsigned long long UInt64;
#endif
#define BEA_HAVE_INT64 1
#elif defined(__BORLANDC__)
/*
* Borland C/C++
*/
typedef signed char Int8;
typedef unsigned char UInt8;
typedef signed short Int16;
typedef unsigned short UInt16;
typedef signed int Int32;
typedef unsigned int UInt32;
typedef unsigned __int64 Int64;
typedef signed __int64 UInt64;
typedef signed long IntPtr;
typedef unsigned long UIntPtr;
#define BEA_HAVE_INT64 1
#elif defined(__WATCOMC__)
/*
* Watcom C/C++
*/
typedef signed char Int8;
typedef unsigned char UInt8;
typedef signed short Int16;
typedef unsigned short UInt16;
typedef signed int Int32;
typedef unsigned int UInt32;
typedef unsigned __int64 Int64;
typedef signed __int64 UInt64;
#define BEA_HAVE_INT64 1
typedef size_t UIntPtr;
#elif defined(__sgi)
/*
* MIPSpro C++
*/
typedef signed char Int8;
typedef unsigned char UInt8;
typedef signed short Int16;
typedef unsigned short UInt16;
typedef signed int Int32;
typedef unsigned int UInt32;
typedef signed long IntPtr;
typedef unsigned long UIntPtr;
#if _MIPS_SZLONG == 64
#define BEA_PTR_IS_64_BIT 1
#define BEA_LONG_IS_64_BIT 1
typedef signed long Int64;
typedef unsigned long UInt64;
#else
typedef signed long long Int64;
typedef unsigned long long UInt64;
#endif
#define BEA_HAVE_INT64 1
#endif
#if defined(_MSC_VER) || defined(__BORLANDC__)
#define W64LIT(x) x##ui64
#else
#define W64LIT(x) x##ULL
#endif
#ifndef C_STATIC_ASSERT
#define C_STATIC_ASSERT(tag_name, x) \
typedef int cache_static_assert_ ## tag_name[(x) * 2-1]
#endif
C_STATIC_ASSERT(sizeof_Int8 , (sizeof(Int8) == 1));
C_STATIC_ASSERT(sizeof_UInt8, (sizeof(UInt8) == 1));
C_STATIC_ASSERT(sizeof_Int16 , (sizeof(Int16) == 2));
C_STATIC_ASSERT(sizeof_UInt16, (sizeof(UInt16) == 2));
C_STATIC_ASSERT(sizeof_Int32 , (sizeof(Int32) == 4));
C_STATIC_ASSERT(sizeof_UInt32, (sizeof(UInt32) == 4));
C_STATIC_ASSERT(sizeof_Int64 , (sizeof(Int64) == 8));
C_STATIC_ASSERT(sizeof_UInt64, (sizeof(UInt64) == 8));
#endif

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/**
* @file export.h
* @author igor.gutnik@gmail.com
* @date Mon Sep 22 09:28:54 2008
*
* @brief This file sets things up for C dynamic library function definitions and
* static inlined functions
*
* This file is part of BeaEngine.
*
* BeaEngine is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BeaEngine is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with BeaEngine. If not, see <http://www.gnu.org/licenses/>. */
#ifndef __BEA_EXPORT_H__
#define __BEA_EXPORT_H__
/* Set up for C function definitions, even when using C++ */
#ifdef __cplusplus
#define CPP_VISIBLE_BEGIN extern "C" {
#define CPP_VISIBLE_END }
#else
#define CPP_VISIBLE_BEGIN
#define CPP_VISIBLE_END
#endif
#if defined(_MSC_VER)
#pragma warning( disable: 4251 )
#endif
/* Some compilers use a special export keyword */
#ifndef bea__api_export__
# if defined(__BEOS__)
# if defined(__GNUC__)
# define bea__api_export__ __declspec(dllexport)
# else
# define bea__api_export__ __declspec(export)
# endif
# elif defined(_WIN32) || defined(_WIN64)
# ifdef __BORLANDC__
# define bea__api_export__ __declspec(dllexport)
# define bea__api_import__ __declspec(dllimport)
# elif defined(__WATCOMC__)
# define bea__api_export__ __declspec(dllexport)
# define bea__api_import__
# else
# define bea__api_export__ __declspec(dllexport)
# define bea__api_import__ __declspec(dllimport)
# endif
# elif defined(__OS2__)
# ifdef __WATCOMC__
# define bea__api_export__ __declspec(dllexport)
# define bea__api_import__
# else
# define bea__api_export__
# define bea__api_import__
# endif
# else
# if defined(_WIN32) && defined(__GNUC__) && __GNUC__ >= 4
# define bea__api_export__ __attribubea__ ((visibility("default")))
# define bea__api_import__ __attribubea__ ((visibility("default")))
# else
# define bea__api_export__
# define bea__api_import__
# endif
# endif
#endif
/* Use C calling convention by default*/
#ifndef __bea_callspec__
#if defined(BEA_USE_STDCALL)
#if defined(__WIN32__) || defined(WIN32) || defined(_WIN32) || defined(_WIN64)
#if defined(__BORLANDC__) || defined(__WATCOMC__) || defined(_MSC_VER) || defined(__MINGW32__) || defined(__POCC__)
#define __bea_callspec__ __stdcall
#else
#define __bea_callspec__
#endif
#else
#ifdef __OS2__
#define __bea_callspec__ _System
#else
#define __bea_callspec__
#endif
#endif
#else
#define __bea_callspec__
#endif
#endif
#ifdef __SYMBIAN32__
# ifndef EKA2
# undef bea__api_export__
# undef bea__api_import__
# define bea__api_export__
# define bea__api_import__
# elif !defined(__WINS__)
# undef bea__api_export__
# undef bea__api_import__
# define bea__api_export__ __declspec(dllexport)
# define bea__api_import__ __declspec(dllexport)
# endif /* !EKA2 */
#endif /* __SYMBIAN32__ */
#if defined(__GNUC__) && (__GNUC__ > 2)
#define BEA_EXPECT_CONDITIONAL(c) (__builtin_expect((c), 1))
#define BEA_UNEXPECT_CONDITIONAL(c) (__builtin_expect((c), 0))
#else
#define BEA_EXPECT_CONDITIONAL(c) (c)
#define BEA_UNEXPECT_CONDITIONAL(c) (c)
#endif
/* Set up compiler-specific options for inlining functions */
#ifndef BEA_HAS_INLINE
#if defined(__GNUC__) || defined(__POCC__) || defined(__WATCOMC__) || defined(__SUNPRO_C)
#define BEA_HAS_INLINE
#else
/* Add any special compiler-specific cases here */
#if defined(_MSC_VER) || defined(__BORLANDC__) || \
defined(__DMC__) || defined(__SC__) || \
defined(__WATCOMC__) || defined(__LCC__) || \
defined(__DECC) || defined(__EABI__)
#ifndef __inline__
#define __inline__ __inline
#endif
#define BEA_HAS_INLINE
#else
#if !defined(__MRC__) && !defined(_SGI_SOURCE)
#ifndef __inline__
#define __inline__ inline
#endif
#define BEA_HAS_INLINE
#endif /* Not a funky compiler */
#endif /* Visual C++ */
#endif /* GNU C */
#endif /* CACHE_HAS_INLINE */
/* If inlining isn't supported, remove "__inline__", turning static
inlined functions into static functions (resulting in code bloat
in all files which include the offending header files)
*/
#ifndef BEA_HAS_INLINE
#define __inline__
#endif
/* fix a bug with gcc under windows */
#if defined(__WIN32__) || defined(WIN32) || defined(_WIN32) || defined(_WIN64)
#if defined(__MINGW32__)
#define const__
#else
#define const__ const
#endif
#else
#define const__ const
#endif
#endif

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deps/beaengine-4.1/include/beaengine/macros.h vendored
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@ -1,41 +0,0 @@
#ifndef __BEAENGINE_MACROS_H__
#define __BEAENGINE_MACROS_H__
/*
============================================================================
Compiler Silencing macros
Some compilers complain about parameters that are not used. This macro
should keep them quiet.
============================================================================
*/
# if defined (__GNUC__) && ((__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 2)))
# define BEA_UNUSED_ARG(a) (void) (a)
#elif defined (ghs) || defined (__GNUC__) || defined (__hpux) || defined (__sgi) || defined (__DECCXX) || defined (__rational__) || defined (__USLC__) || defined (BEA__RM544) || defined (__DCC__) || defined (__PGI) || defined (__TANDEM) || defined(__BORLANDC__)
/*
Some compilers complain about "statement with no effect" with (a).
This eliminates the warnings, and no code is generated for the null
conditional statement. Note, that may only be true if -O is enabled,
such as with GreenHills (ghs) 1.8.8.
*/
# define BEA_UNUSED_ARG(a) do {/* null */} while (&a == 0)
#elif defined (__DMC__)
#if defined(__cplusplus)
#define BEA_UNUSED_ID(identifier)
template <class T>
inline void BEA_UNUSED_ARG(const T& BEA_UNUSED_ID(t)) { }
#else
#define BEA_UNUSED_ARG(a)
#endif
#else /* ghs || __GNUC__ || ..... */
# define BEA_UNUSED_ARG(a) (a)
#endif /* ghs || __GNUC__ || ..... */
#if defined (_MSC_VER) || defined(__sgi) || defined (ghs) || defined (__DECCXX) || defined(__BORLANDC__) || defined (BEA_RM544) || defined (__USLC__) || defined (__DCC__) || defined (__PGI) || defined (__TANDEM) || (defined (__HP_aCC) && (__HP_aCC >= 60500))
# define BEA_NOTREACHED(a)
#else /* __sgi || ghs || ..... */
# define BEA_NOTREACHED(a) a
#endif /* __sgi || ghs || ..... */
#endif /* __BEAENGINE_MACROS_H__ */

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deps/beaengine-4.1/makeStaticLib64.bat vendored
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@ -1,28 +0,0 @@
@echo off
set INCLUDE=C:\Program Files\PellesC\Include\;C:\Program Files\PellesC\Include\Win\;
set LIB=C:\Program Files\PellesC\Lib\;C:\Program Files\PellesC\Lib\Win64\;
set name=BeaEngine
echo ____________________________________
echo *
echo * COMPILATION with POCC.EXE (Pelles C)
echo *
echo ____________________________________
pocc /Tamd64-coff /Ze /W2 /DBEA_ENGINE_STATIC beaengineSources/%name%.c
echo ____________________________________
echo *
echo * CREATE LIB with POLIB.EXE (Pelles C)
echo *
echo ____________________________________
"C:\Program Files\PellesC\Bin\PoLib" /MACHINE:X64 /out:%name%64.lib beaengineSources/%name%.obj
pause

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version: 3.0.4-{build}
os:
- Visual Studio 2015
before_build:
- call "C:\Program Files (x86)\Microsoft Visual Studio 14.0\VC\vcvarsall.bat" amd64
build_script:
- mkdir build
- cd build
- cmake -DCMAKE_BUILD_TYPE=RELEASE -G "NMake Makefiles" ..
- nmake

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# Object files
*.o
*.ko
# Gcc dependency-tracking files
*.d
# Libraries
*.lib
*.a
# Shared objects (inc. Windows DLLs)
*.dll
*.so
*.so.*
*.dylib
# Executables
*.exe
*.out
*.app
# python
bindings/python/build/
bindings/python/capstone.egg-info/
*.pyc
# java
bindings/java/capstone.jar
# ocaml
bindings/ocaml/*.cmi
bindings/ocaml/*.cmx
bindings/ocaml/*.cmxa
bindings/ocaml/*.mli
bindings/ocaml/test
bindings/ocaml/test_arm
bindings/ocaml/test_arm64
bindings/ocaml/test_mips
bindings/ocaml/test_x86
bindings/ocaml/test_detail
bindings/ocaml/test_ppc
bindings/ocaml/test_sparc
bindings/ocaml/test_systemz
bindings/ocaml/test_xcore
# test binaries
tests/test
tests/test_detail
tests/test_iter
tests/test_arm
tests/test_arm64
tests/test_mips
tests/test_x86
tests/test_ppc
tests/test_skipdata
tests/test_sparc
tests/test_systemz
tests/test_xcore
tests/*.static
tests/test_basic
tests/test_customized_mnem
# regress binaries
suite/regress/invalid_read_in_print_operand
# vim tmp file
*.swp
*~
capstone.pc
# local files
_*
# freebsd ports: generated file with "make makesum" command
packages/freebsd/ports/devel/capstone/distinfo
# VisualStudio
Debug/
Debug_WDK/
Release/
Release_WDK/
ipch/
*.sdf
*.opensdf
*.suo
*.user
*.VC.db
*.VC.opendb
# Xcode
xcode/Capstone.xcodeproj/xcuserdata
xcode/Capstone.xcodeproj/project.xcworkspace/xcuserdata
# suite/
test_arm_regression
test_arm_regression.o
fuzz_harness
test_iter_benchmark
*.s

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deps/capstone/.travis.yml vendored Normal file
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language: cpp
sudo: false
before_install:
- export LD_LIBRARY_PATH=`pwd`/tests/:$LD_LIBRARY_PATH
script:
- ./make.sh
- make check
- if [[ "$TRAVIS_OS_NAME" == "linux" ]]; then cp libcapstone.so bindings/python/; fi
- if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then cp libcapstone.dylib bindings/python/; fi
- cd bindings/python && make check
compiler:
- clang
- gcc
os:
- linux
- osx

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cmake_minimum_required(VERSION 2.6)
project(capstone)
set(VERSION_MAJOR 3)
set(VERSION_MINOR 0)
set(VERSION_PATCH 4)
# to configure the options specify them in in the command line or change them in the cmake UI.
# Don't edit the makefile!
option(CAPSTONE_BUILD_STATIC_RUNTIME "Embed static runtime" OFF)
option(CAPSTONE_BUILD_STATIC "Build static library" ON)
option(CAPSTONE_BUILD_SHARED "Build shared library" ON)
option(CAPSTONE_BUILD_DIET "Build diet library" OFF)
option(CAPSTONE_BUILD_TESTS "Build tests" ON)
option(CAPSTONE_USE_DEFAULT_ALLOC "Use default memory allocation functions" ON)
option(CAPSTONE_ARM_SUPPORT "ARM support" ON)
option(CAPSTONE_ARM64_SUPPORT "ARM64 support" ON)
option(CAPSTONE_MIPS_SUPPORT "MIPS support" ON)
option(CAPSTONE_PPC_SUPPORT "PowerPC support" ON)
option(CAPSTONE_SPARC_SUPPORT "Sparc support" ON)
option(CAPSTONE_SYSZ_SUPPORT "SystemZ support" ON)
option(CAPSTONE_XCORE_SUPPORT "XCore support" ON)
option(CAPSTONE_X86_SUPPORT "x86 support" ON)
option(CAPSTONE_X86_REDUCE "x86 with reduce instruction sets to minimize library" OFF)
option(CAPSTONE_X86_ATT_DISABLE "Disable x86 AT&T syntax" OFF)
option(CAPSTONE_OSXKERNEL_SUPPORT "Support to embed Capstone into OS X Kernel extensions" OFF)
if (CAPSTONE_BUILD_DIET)
add_definitions(-DCAPSTONE_DIET)
endif ()
if (CAPSTONE_USE_DEFAULT_ALLOC)
add_definitions(-DCAPSTONE_USE_SYS_DYN_MEM)
endif ()
if (CAPSTONE_X86_REDUCE)
add_definitions(-DCAPSTONE_X86_REDUCE)
endif ()
if (CAPSTONE_X86_ATT_DISABLE)
add_definitions(-DCAPSTONE_X86_ATT_DISABLE)
endif ()
## sources
set(SOURCES_ENGINE
cs.c
MCInst.c
MCInstrDesc.c
MCRegisterInfo.c
SStream.c
utils.c
)
set(HEADERS_ENGINE
include/capstone.h
utils.h
MCRegisterInfo.h
MCInst.h
MCInstrDesc.h
SStream.h
cs_priv.h
myinttypes.h
include/platform.h
)
set(HEADERS_COMMON
include/arm64.h
include/arm.h
include/capstone.h
include/mips.h
include/ppc.h
include/x86.h
include/sparc.h
include/systemz.h
include/xcore.h
include/platform.h
)
set(TEST_SOURCES test.c test_detail.c test_skipdata.c test_iter.c)
## architecture support
if (CAPSTONE_ARM_SUPPORT)
add_definitions(-DCAPSTONE_HAS_ARM)
set(SOURCES_ARM
arch/ARM/ARMDisassembler.c
arch/ARM/ARMInstPrinter.c
arch/ARM/ARMMapping.c
arch/ARM/ARMModule.c
)
set(HEADERS_ARM
arch/ARM/ARMAddressingModes.h
arch/ARM/ARMBaseInfo.h
arch/ARM/ARMDisassembler.h
arch/ARM/ARMGenAsmWriter.inc
arch/ARM/ARMGenDisassemblerTables.inc
arch/ARM/ARMGenInstrInfo.inc
arch/ARM/ARMGenRegisterInfo.inc
arch/ARM/ARMGenSubtargetInfo.inc
arch/ARM/ARMInstPrinter.h
arch/ARM/ARMMapping.h
)
set(TEST_SOURCES ${TEST_SOURCES} test_arm.c)
endif ()
if (CAPSTONE_ARM64_SUPPORT)
add_definitions(-DCAPSTONE_HAS_ARM64)
set(SOURCES_ARM64
arch/AArch64/AArch64BaseInfo.c
arch/AArch64/AArch64Disassembler.c
arch/AArch64/AArch64InstPrinter.c
arch/AArch64/AArch64Mapping.c
arch/AArch64/AArch64Module.c
)
set(HEADERS_ARM64
arch/AArch64/AArch64AddressingModes.h
arch/AArch64/AArch64BaseInfo.h
arch/AArch64/AArch64Disassembler.h
arch/AArch64/AArch64GenAsmWriter.inc
arch/AArch64/AArch64GenDisassemblerTables.inc
arch/AArch64/AArch64GenInstrInfo.inc
arch/AArch64/AArch64GenRegisterInfo.inc
arch/AArch64/AArch64GenSubtargetInfo.inc
arch/AArch64/AArch64InstPrinter.h
arch/AArch64/AArch64Mapping.h
)
set(TEST_SOURCES ${TEST_SOURCES} test_arm64.c)
endif ()
if (CAPSTONE_MIPS_SUPPORT)
add_definitions(-DCAPSTONE_HAS_MIPS)
set(SOURCES_MIPS
arch/Mips/MipsDisassembler.c
arch/Mips/MipsInstPrinter.c
arch/Mips/MipsMapping.c
arch/Mips/MipsModule.c
)
set(HEADERS_MIPS
arch/Mips/MipsDisassembler.h
arch/Mips/MipsGenAsmWriter.inc
arch/Mips/MipsGenDisassemblerTables.inc
arch/Mips/MipsGenInstrInfo.inc
arch/Mips/MipsGenRegisterInfo.inc
arch/Mips/MipsGenSubtargetInfo.inc
arch/Mips/MipsInstPrinter.h
arch/Mips/MipsMapping.h
)
set(TEST_SOURCES ${TEST_SOURCES} test_mips.c)
endif ()
if (CAPSTONE_PPC_SUPPORT)
add_definitions(-DCAPSTONE_HAS_POWERPC)
set(SOURCES_PPC
arch/PowerPC/PPCDisassembler.c
arch/PowerPC/PPCInstPrinter.c
arch/PowerPC/PPCMapping.c
arch/PowerPC/PPCModule.c
)
set(HEADERS_PPC
arch/PowerPC/PPCDisassembler.h
arch/PowerPC/PPCGenAsmWriter.inc
arch/PowerPC/PPCGenDisassemblerTables.inc
arch/PowerPC/PPCGenInstrInfo.inc
arch/PowerPC/PPCGenRegisterInfo.inc
arch/PowerPC/PPCGenSubtargetInfo.inc
arch/PowerPC/PPCInstPrinter.h
arch/PowerPC/PPCMapping.h
arch/PowerPC/PPCPredicates.h
)
set(TEST_SOURCES ${TEST_SOURCES} test_ppc.c)
endif ()
if (CAPSTONE_X86_SUPPORT)
add_definitions(-DCAPSTONE_HAS_X86)
set(SOURCES_X86
arch/X86/X86Disassembler.c
arch/X86/X86DisassemblerDecoder.c
arch/X86/X86IntelInstPrinter.c
arch/X86/X86Mapping.c
arch/X86/X86Module.c
)
set(HEADERS_X86
arch/X86/X86BaseInfo.h
arch/X86/X86Disassembler.h
arch/X86/X86DisassemblerDecoder.h
arch/X86/X86DisassemblerDecoderCommon.h
arch/X86/X86GenAsmWriter.inc
arch/X86/X86GenAsmWriter1.inc
arch/X86/X86GenAsmWriter1_reduce.inc
arch/X86/X86GenAsmWriter_reduce.inc
arch/X86/X86GenDisassemblerTables.inc
arch/X86/X86GenDisassemblerTables_reduce.inc
arch/X86/X86GenInstrInfo.inc
arch/X86/X86GenInstrInfo_reduce.inc
arch/X86/X86GenRegisterInfo.inc
arch/X86/X86InstPrinter.h
arch/X86/X86Mapping.h
)
if (NOT CAPSTONE_BUILD_DIET)
set(SOURCES_X86 ${SOURCES_X86} arch/X86/X86ATTInstPrinter.c)
endif ()
set(TEST_SOURCES ${TEST_SOURCES} test_x86.c)
endif ()
if (CAPSTONE_SPARC_SUPPORT)
add_definitions(-DCAPSTONE_HAS_SPARC)
set(SOURCES_SPARC
arch/Sparc/SparcDisassembler.c
arch/Sparc/SparcInstPrinter.c
arch/Sparc/SparcMapping.c
arch/Sparc/SparcModule.c
)
set(HEADERS_SPARC
arch/Sparc/Sparc.h
arch/Sparc/SparcDisassembler.h
arch/Sparc/SparcGenAsmWriter.inc
arch/Sparc/SparcGenDisassemblerTables.inc
arch/Sparc/SparcGenInstrInfo.inc
arch/Sparc/SparcGenRegisterInfo.inc
arch/Sparc/SparcGenSubtargetInfo.inc
arch/Sparc/SparcInstPrinter.h
arch/Sparc/SparcMapping.h
)
set(TEST_SOURCES ${TEST_SOURCES} test_sparc.c)
endif ()
if (CAPSTONE_SYSZ_SUPPORT)
add_definitions(-DCAPSTONE_HAS_SYSZ)
set(SOURCES_SYSZ
arch/SystemZ/SystemZDisassembler.c
arch/SystemZ/SystemZInstPrinter.c
arch/SystemZ/SystemZMapping.c
arch/SystemZ/SystemZModule.c
arch/SystemZ/SystemZMCTargetDesc.c
)
set(HEADERS_SYSZ
arch/SystemZ/SystemZDisassembler.h
arch/SystemZ/SystemZGenAsmWriter.inc
arch/SystemZ/SystemZGenDisassemblerTables.inc
arch/SystemZ/SystemZGenInstrInfo.inc
arch/SystemZ/SystemZGenRegisterInfo.inc
arch/SystemZ/SystemZGenSubtargetInfo.inc
arch/SystemZ/SystemZInstPrinter.h
arch/SystemZ/SystemZMCTargetDesc.h
arch/SystemZ/SystemZMapping.h
)
set(TEST_SOURCES ${TEST_SOURCES} test_systemz.c)
endif ()
if (CAPSTONE_XCORE_SUPPORT)
add_definitions(-DCAPSTONE_HAS_XCORE)
set(SOURCES_XCORE
arch/XCore/XCoreDisassembler.c
arch/XCore/XCoreInstPrinter.c
arch/XCore/XCoreMapping.c
arch/XCore/XCoreModule.c
)
set(HEADERS_XCORE
arch/XCore/XCoreDisassembler.h
arch/XCore/XCoreGenAsmWriter.inc
arch/XCore/XCoreGenDisassemblerTables.inc
arch/XCore/XCoreGenInstrInfo.inc
arch/XCore/XCoreGenRegisterInfo.inc
arch/XCore/XCoreInstPrinter.h
arch/XCore/XCoreMapping.h
)
set(TEST_SOURCES ${TEST_SOURCES} test_xcore.c)
endif ()
if (CAPSTONE_OSXKERNEL_SUPPORT)
add_definitions(-DCAPSTONE_HAS_OSXKERNEL)
endif ()
set(ALL_SOURCES
${SOURCES_ENGINE}
${SOURCES_ARM}
${SOURCES_ARM64}
${SOURCES_MIPS}
${SOURCES_PPC}
${SOURCES_X86}
${SOURCES_SPARC}
${SOURCES_SYSZ}
${SOURCES_XCORE}
)
set(ALL_HEADERS
${HEADERS_COMMON}
${HEADERS_ENGINE}
${HEADERS_ARM}
${HEADERS_ARM64}
${HEADERS_MIPS}
${HEADERS_PPC}
${HEADERS_X86}
${HEADERS_SPARC}
${HEADERS_SYSZ}
${HEADERS_XCORE}
)
include_directories("${PROJECT_SOURCE_DIR}/include")
## properties
# version info
set_property(GLOBAL PROPERTY VERSION ${VERSION_MAJOR}.${VERSION_MINOR}.${VERSION_PATCH})
set_property(GLOBAL PROPERTY SOVERSION SOVERSION ${VERSION_MAJOR})
## targets
if (CAPSTONE_BUILD_STATIC)
add_library(capstone-static STATIC ${ALL_SOURCES} ${ALL_HEADERS})
set_property(TARGET capstone-static PROPERTY OUTPUT_NAME capstone)
set(default-target capstone-static)
endif ()
# Force static runtime libraries
if (CAPSTONE_BUILD_STATIC_RUNTIME)
FOREACH(flag
CMAKE_C_FLAGS_RELEASE CMAKE_C_FLAGS_RELWITHDEBINFO
CMAKE_C_FLAGS_DEBUG CMAKE_C_FLAGS_DEBUG_INIT
CMAKE_CXX_FLAGS_RELEASE CMAKE_CXX_FLAGS_RELWITHDEBINFO
CMAKE_CXX_FLAGS_DEBUG CMAKE_CXX_FLAGS_DEBUG_INIT)
STRING(REPLACE "/MD" "/MT" "${flag}" "${${flag}}")
SET("${flag}" "${${flag}} /EHsc")
ENDFOREACH()
endif ()
if (CAPSTONE_BUILD_SHARED)
add_library(capstone-shared SHARED ${ALL_SOURCES} ${ALL_HEADERS})
set_property(TARGET capstone-shared PROPERTY OUTPUT_NAME capstone)
set_property(TARGET capstone-shared PROPERTY COMPILE_FLAGS -DCAPSTONE_SHARED)
if (MSVC)
set_target_properties(capstone-shared PROPERTIES IMPORT_SUFFIX _dll.lib)
endif ()
if(NOT DEFINED default-target) # honor `capstone-static` for tests first.
set(default-target capstone-shared)
add_definitions(-DCAPSTONE_SHARED)
endif ()
endif ()
if (CAPSTONE_BUILD_TESTS)
foreach (TSRC ${TEST_SOURCES})
STRING(REGEX REPLACE ".c$" "" TBIN ${TSRC})
add_executable(${TBIN} "tests/${TSRC}")
target_link_libraries(${TBIN} ${default-target})
endforeach ()
if (CAPSTONE_ARM_SUPPORT)
set(ARM_REGRESS_TEST test_arm_regression.c)
STRING(REGEX REPLACE ".c$" "" ARM_REGRESS_BIN ${ARM_REGRESS_TEST})
add_executable(${ARM_REGRESS_BIN} "suite/arm/${ARM_REGRESS_TEST}")
target_link_libraries(${ARM_REGRESS_BIN} ${default-target})
endif()
endif ()
source_group("Source\\Engine" FILES ${SOURCES_ENGINE})
source_group("Source\\ARM" FILES ${SOURCES_ARM})
source_group("Source\\ARM64" FILES ${SOURCES_ARM64})
source_group("Source\\Mips" FILES ${SOURCES_MIPS})
source_group("Source\\PowerPC" FILES ${SOURCES_PPC})
source_group("Source\\Sparc" FILES ${SOURCES_SPARC})
source_group("Source\\SystemZ" FILES ${SOURCES_SYSZ})
source_group("Source\\X86" FILES ${SOURCES_X86})
source_group("Source\\XCore" FILES ${SOURCES_XCORE})
source_group("Include\\Common" FILES ${HEADERS_COMMON})
source_group("Include\\Engine" FILES ${HEADERS_ENGINE})
source_group("Include\\ARM" FILES ${HEADERS_ARM})
source_group("Include\\ARM64" FILES ${HEADERS_ARM64})
source_group("Include\\Mips" FILES ${HEADERS_MIPS})
source_group("Include\\PowerPC" FILES ${HEADERS_PPC})
source_group("Include\\Sparc" FILES ${HEADERS_SPARC})
source_group("Include\\SystemZ" FILES ${HEADERS_SYSZ})
source_group("Include\\X86" FILES ${HEADERS_X86})
source_group("Include\\XCore" FILES ${HEADERS_XCORE})
## installation
install(FILES ${HEADERS_COMMON} DESTINATION include/capstone)
if (CAPSTONE_BUILD_STATIC)
install(TARGETS capstone-static
RUNTIME DESTINATION bin
LIBRARY DESTINATION lib
ARCHIVE DESTINATION lib)
endif ()
if (CAPSTONE_BUILD_SHARED)
install(TARGETS capstone-shared
RUNTIME DESTINATION bin
LIBRARY DESTINATION lib
ARCHIVE DESTINATION lib)
endif ()

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This documentation explains how to compile, install & run Capstone on MacOSX,
Linux, *BSD & Solaris. We also show steps to cross-compile for Microsoft Windows.
To natively compile for Windows using Microsoft Visual Studio, see COMPILE_MSVC.TXT.
To compile using CMake, see COMPILE_CMAKE.TXT.
To compile using XCode on MacOSX, see xcode/README.md.
*-*-*-*-*-*
Capstone requires no prerequisite packages, so it is easy to compile & install.
(0) Tailor Capstone to your need.
Out of 8 archtitectures supported by Capstone (Arm, Arm64, Mips, PPC, Sparc,
SystemZ, XCore & X86), if you just need several selected archs, choose which
ones you want to compile in by editing "config.mk" before going to next steps.
By default, all 8 architectures are compiled.
The other way of customize Capstone without having to edit config.mk is to
pass the desired options on the commandline to ./make.sh. Currently,
Capstone supports 5 options, as followings.
- CAPSTONE_ARCHS: specify list of architectures to compiled in.
- CAPSTONE_USE_SYS_DYN_MEM: change this if you have your own dynamic memory management.
- CAPSTONE_DIET: use this to make the output binaries more compact.
- CAPSTONE_X86_REDUCE: another option to make X86 binary smaller.
- CAPSTONE_X86_ATT_DISABLE: disables AT&T syntax on x86.
- CAPSTONE_STATIC: build static library.
- CAPSTONE_SHARED: build dynamic (shared) library.
By default, Capstone uses system dynamic memory management, both DIET and X86_REDUCE
modes are disable, and builds all the static & shared libraries.
To avoid editing config.mk for these customization, we can pass their values to
make.sh, as followings.
$ CAPSTONE_ARCHS="arm aarch64 x86" CAPSTONE_USE_SYS_DYN_MEM=no CAPSTONE_DIET=yes CAPSTONE_X86_REDUCE=yes ./make.sh
NOTE: on commandline, put these values in front of ./make.sh, not after it.
For each option, refer to docs/README for more details.
(1) Compile from source
On *nix (such as MacOSX, Linux, *BSD, Solaris):
- To compile for current platform, run:
$ ./make.sh
- On 64-bit OS, run the command below to cross-compile Capstone for 32-bit binary:
$ ./make.sh nix32
(2) Install Capstone on *nix
To install Capstone, run:
$ sudo ./make.sh install
For FreeBSD/OpenBSD, where sudo is unavailable, run:
$ su; ./make.sh install
Users are then required to enter root password to copy Capstone into machine
system directories.
Afterwards, run ./tests/test* to see the tests disassembling sample code.
NOTE: The core framework installed by "./make.sh install" consist of
following files:
/usr/include/capstone/capstone.h
/usr/include/capstone/x86.h
/usr/include/capstone/arm.h
/usr/include/capstone/arm64.h
/usr/include/capstone/mips.h
/usr/include/capstone/ppc.h
/usr/include/capstone/sparc.h
/usr/include/capstone/systemz.h
/usr/include/capstone/xcore.h
/usr/include/capstone/platform.h
/usr/lib/libcapstone.so (for Linux/*nix), or /usr/lib/libcapstone.dylib (OSX)
/usr/lib/libcapstone.a
(3) Cross-compile for Windows from *nix
To cross-compile for Windows, Linux & gcc-mingw-w64-i686 (and also gcc-mingw-w64-x86-64
for 64-bit binaries) are required.
- To cross-compile Windows 32-bit binary, simply run:
$ ./make.sh cross-win32
- To cross-compile Windows 64-bit binary, run:
$ ./make.sh cross-win64
Resulted files libcapstone.dll, libcapstone.dll.a & tests/test*.exe can then
be used on Windows machine.
(4) Cross-compile for iOS from Mac OSX.
To cross-compile for iOS (iPhone/iPad/iPod), Mac OSX with XCode installed is required.
- To cross-compile for ArmV7 (iPod 4, iPad 1/2/3, iPhone4, iPhone4S), run:
$ ./make.sh ios_armv7
- To cross-compile for ArmV7s (iPad 4, iPhone 5C, iPad mini), run:
$ ./make.sh ios_armv7s
- To cross-compile for Arm64 (iPhone 5S, iPad mini Retina, iPad Air), run:
$ ./make.sh ios_arm64
- To cross-compile for all iDevices (armv7 + armv7s + arm64), run:
$ ./make.sh ios
Resulted files libcapstone.dylib, libcapstone.a & tests/test* can then
be used on iOS devices.
(5) Cross-compile for Android
To cross-compile for Android (smartphone/tablet), Android NDK is required.
NOTE: Only ARM and ARM64 are currently supported.
$ NDK=/android/android-ndk-r10e ./make.sh cross-android arm
or
$ NDK=/android/android-ndk-r10e ./make.sh cross-android arm64
Resulted files libcapstone.so, libcapstone.a & tests/test* can then
be used on Android devices.
(6) Compile on Windows with Cygwin
To compile under Cygwin gcc-mingw-w64-i686 or x86_64-w64-mingw32 run:
- To compile Windows 32-bit binary under Cygwin, run:
$ ./make.sh cygwin-mingw32
- To compile Windows 64-bit binary under Cygwin, run:
$ ./make.sh cygwin-mingw64
Resulted files libcapstone.dll, libcapstone.dll.a & tests/test*.exe can then
be used on Windows machine.
(7) By default, "cc" (default C compiler on the system) is used as compiler.
- To use "clang" compiler instead, run the command below:
$ ./make.sh clang
- To use "gcc" compiler instead, run:
$ ./make.sh gcc
(8) To uninstall Capstone, run the command below:
$ sudo ./make.sh uninstall
(9) Language bindings
So far, Python, Ocaml & Java are supported by bindings in the main code.
Look for the bindings under directory bindings/, and refer to README file
of corresponding languages.
Community also provide bindings for C#, Go, Ruby, NodeJS, C++ & Vala. Links to
these can be found at address http://capstone-engine.org/download.html

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This documentation explains how to compile Capstone with CMake, focus on
using Microsoft Visual C as the compiler.
To compile Capstone on *nix, see COMPILE.TXT.
To compile Capstone on Windows using Visual Studio, see COMPILE_MSVC.TXT.
*-*-*-*-*-*
This documentation requires CMake & Windows SDK or MS Visual Studio installed on
your machine.
Get CMake for free from http://www.cmake.org.
(0) Tailor Capstone to your need.
Out of 8 archtitectures supported by Capstone (Arm, Arm64, Mips, PPC, Sparc,
SystemZ, X86 & XCore), if you just need several selected archs, run "cmake"
with the unwanted archs disabled (set to 0) as followings.
- CAPSTONE_ARM_SUPPORT: support ARM. Run cmake with -DCAPSTONE_ARM_SUPPORT=0 to remove ARM.
- CAPSTONE_ARM64_SUPPORT: support ARM64. Run cmake with -DCAPSTONE_ARM64_SUPPORT=0 to remove ARM64.
- CAPSTONE_MIPS_SUPPORT: support Mips. Run cmake with -DCAPSTONE_MIPS_SUPPORT=0 to remove Mips.
- CAPSTONE_PPC_SUPPORT: support PPC. Run cmake with -DCAPSTONE_PPC_SUPPORT=0 to remove PPC.
- CAPSTONE_SPARC_SUPPORT: support Sparc. Run cmake with -DCAPSTONE_SPARC_SUPPORT=0 to remove Sparc.
- CAPSTONE_SYSZ_SUPPORT: support SystemZ. Run cmake with -DCAPSTONE_SYSZ_SUPPORT=0 to remove SystemZ.
- CAPSTONE_XCORE_SUPPORT: support XCore. Run cmake with -DCAPSTONE_XCORE_SUPPORT=0 to remove XCore.
- CAPSTONE_X86_SUPPORT: support X86. Run cmake with -DCAPSTONE_X86_SUPPORT=0 to remove X86.
By default, all 8 architectures are compiled in.
Besides, Capstone also allows some more customization via following macros.
- CAPSTONE_USE_SYS_DYN_MEM: change this to OFF to use your own dynamic memory management.
- CAPSTONE_BUILD_DIET: change this to ON to make the binaries more compact.
- CAPSTONE_X86_REDUCE: change this to ON to make X86 binary smaller.
- CAPSTONE_X86_ATT_DISABLE: change this to ON to disable AT&T syntax on x86.
By default, Capstone use system dynamic memory management, and both DIET and X86_REDUCE
modes are disabled. To use your own memory allocations, turn ON both DIET &
X86_REDUCE, run "cmake" with: -DCAPSTONE_USE_SYS_DYN_MEM=0 -DCAPSTONE_BUILD_DIET=1 -DCAPSTONE_X86_REDUCE=1
For each option, refer to docs/README for more details.
(1) CMake allows you to generate different generators to build Capstone. Below is
some examples on how to build Capstone on Windows with CMake.
(*) To build Capstone using Nmake of Windows SDK, do:
mkdir build
cd build
cmake -DCMAKE_BUILD_TYPE=RELEASE -G "NMake Makefiles" ..
nmake
After this, find the samples test*.exe, libcapstone_static.lib & libcapstone.dll
in the same directory.
(*) To build Capstone using Visual Studio, choose the generator accordingly to the
version of Visual Studio on your machine. For example, with Visual Studio 2013, do:
mkdir build
cd build
cmake -G "Visual Studio 12" ..
After this, find capstone.sln in the same directory. Open it with Visual Studio
and build the solution including libraries & all test as usual.
(2) You can make sure the prior steps successfully worked by launching one of the
testing binary (test*.exe).

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This documentation explains how to compile Capstone on Windows using
Microsoft Visual Studio version 2010 or newer.
To compile Capstone on *nix, see COMPILE.TXT
To compile Capstone with CMake, see COMPILE_CMAKE.TXT
*-*-*-*-*-*
Capstone requires no prerequisite packages, so it is easy to compile & install.
Open the Visual Studio solution "msvc/capstone.sln" and follow the instructions
below.
NOTE: This requires Visual Studio 2010 or newer versions.
(0) Tailor Capstone to your need.
Out of 8 archtitectures supported by Capstone (Arm, Arm64, Mips, PPC, Sparc,
SystemZ, X86 & XCore), if you just need several selected archs, choose the ones
you want to compile in by opening Visual Studio solution "msvc\capstone.sln",
then directly editing the projects "capstone_static" & "capstone_dll" for static
and dynamic libraries, respectively. This must be done before going to the
next steps.
In VisualStudio interface, modify the preprocessor definitions via
"Project Properties" -> "Configuration Propertis" -> "C/C++" -> "Preprocessor"
to customize Capstone library, as followings.
- CAPSTONE_HAS_ARM: support ARM. Delete this to remove ARM support.
- CAPSTONE_HAS_ARM64: support ARM64. Delete this to remove ARM64 support.
- CAPSTONE_HAS_MIPS: support Mips. Delete this to remove Mips support.
- CAPSTONE_HAS_PPC: support PPC. Delete this to remove PPC support.
- CAPSTONE_HAS_SPARC: support Sparc. Delete this to remove Sparc support.
- CAPSTONE_HAS_SYSZ: support SystemZ. Delete this to remove SystemZ support.
- CAPSTONE_HAS_X86: support X86. Delete this to remove X86 support.
- CAPSTONE_HAS_XCORE: support XCore. Delete this to remove XCore support.
By default, all 8 architectures are compiled in.
Besides, Capstone also allows some more customization via following macros.
- CAPSTONE_USE_SYS_DYN_MEM: delete this to use your own dynamic memory management.
- CAPSTONE_DIET_NO: rename this to "CAPSTONE_DIET" to make the binaries more compact.
- CAPSTONE_X86_REDUCE_NO: rename this to "CAPSTONE_X86_REDUCE" to make X86 binary smaller.
- CAPSTONE_X86_ATT_DISABLE_NO: rename this to "CAPSTONE_X86_ATT_DISABLE" to disable
AT&T syntax on x86.
By default, Capstone use system dynamic memory management, and both DIET and X86_REDUCE
modes are disable.
For each option, refer to docs/README for more details.
(1) Compile from source on Windows with Visual Studio
- Choose the configuration and the platform you want: Release/Debug & Win32/Win64.
- Build only the libraries, or the libraries along with all the tests.
(2) You can make sure the prior steps successfully worked by launching one of the
testing binary (test*.exe).

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This file credits all the contributors of the Capstone engine project.
Key developers
==============
1. Nguyen Anh Quynh <aquynh -at- gmail.com>
- Core engine
- Bindings: Python, Ruby, OCaml, Java, C#
2. Tan Sheng Di <shengdi -at- coseinc.com>
- Bindings: Ruby
3. Ben Nagy <ben -at- coseinc.com>
- Bindings: Ruby, Go
4. Dang Hoang Vu <dang.hvu -at- gmail.com>
- Bindings: Java
Beta testers (in random order)
==============================
Pancake
Van Hauser
FX of Phenoelit
The Grugq, The Grugq <-- our hero for submitting the first ever patch!
Isaac Dawson, Veracode Inc
Patroklos Argyroudis, Census Inc. (http://census-labs.com)
Attila Suszter
Le Dinh Long
Nicolas Ruff
Gunther
Alex Ionescu, Winsider Seminars & Solutions Inc.
Snare
Daniel Godas-Lopez
Joshua J. Drake
Edgar Barbosa
Ralf-Philipp Weinmann
Hugo Fortier
Joxean Koret
Bruce Dang
Andrew Dunham
Contributors (in no particular order)
=====================================
(Please let us know if you want to have your name here)
Ole André Vadla Ravnås (author of the 100th Pull-Request in our Github repo, thanks!)
Axel "0vercl0k" Souchet (@0vercl0k) & Alex Ionescu: port to MSVC.
Daniel Pistelli: Cmake support.
Peter Hlavaty: integrate Capstone for Windows kernel drivers.
Guillaume Jeanne: Ocaml binding.
Martin Tofall, Obsidium Software: Optimize X86 performance & size.
David Martínez Moreno & Hilko Bengen: Debian package.
Félix Cloutier: Xcode project.
Benoit Lecocq: OpenBSD package.
Christophe Avoinne (Hlide): Improve memory management for better performance.
Michael Cohen & Nguyen Tan Cong: Python module installer.
Adel Gadllah, Francisco Alonso & Stefan Cornelius: RPM package.
Felix Gröbert (Google): fuzz testing harness.
Xipiter LLC: Capstone logo redesigned.
Satoshi Tanda: Support Windows kernel driver.

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This file details the changelog of Capstone.
---------------------------------
Version 3.0.4: July 15th, 2015
[ Library ]
- Improve cross-compile for Android using Android NDK.
- Support cross-compile for AArch64 Android (with Linux GCC).
- Removed osxkernel_inttypes.h that is incompatible with BSD license.
- Make it possible to compile with CC having a space inside (like "ccache gcc").
[ X86 ]
- Fix a null pointer dereference bug on handling code with special prefixes.
- Properly handle AL/AX/EAX operand for OUT instruction in AT&T syntax.
- Print immediate operand in positive form in some algorithm instructions.
- Properly decode some SSE instructions.
[ PowerPC ]
- Fixed a memory corruption bug.
- Fixed a memory corruption bug for the engine built in DIET mode.
[ Mips ]
- Fixed instruction ID of SUBU instruction.
- Fixed a memory corruption bug.
[ Arm ]
- Fixed a memory corruption bug on IT instruction.
[ XCore ]
- Fixed a memory corruption bug when instruction has a memory operand.
[ Python ]
- Support Virtualenv.
- setup.py supports option --user if not in a virtualenv to allow for local usage.
- Properly handle the destruction of Cs object in the case the shared library
was already unloaded.
---------------------------------
Version 3.0.3: May 08th, 2015
[ Library ]
- Support to embed into Mac OS X kernel extensions.
- Now it is possible to compile Capstone with older C compilers, such as
GCC 4.8 on Ubuntu 12.04.
- Add "test_iter" to MSVC project.
[ X86 ]
- All shifted instructions SHL, SHR, SAL, SAR, RCL, RCR, ROL & ROR now support
$1 as first operand in *AT&T* syntax (so we have "rcll $1, %edx" instead of
"rcll %edx").
- CMPXCHG16B is a valid instruction with LOCK prefix.
- Fixed a segfault on the input of 0xF3.
[ Arm ]
- BLX instruction modifies PC & LR registers.
[ Sparc ]
- Improved displacement decoding for sparc banching instructions.
[ Python binding ]
- Fix for Cython so it can properly initialize.
- X86Op.avx_zero_mask now has c_bool type, but not c_uint8 type.
- Properly support compile with Cygwin & install binding (setup.py).
---------------------------------
Version 3.0.2: March 11th, 2015
[ Library ]
- On *nix, only export symbols that are part of the API (instead of all
the internal symbols).
[ X86 ]
- Do not consider 0xF2 as REPNE prefix if it is a part of instruction encoding.
- Fix implicit registers read/written & instruction groups of some instructions.
- More flexible on the order of prefixes, so better handle some tricky
instructions.
- REPNE prefix can go with STOS & MOVS instructions.
- Fix a compilation bug for X86_REDUCE mode.
- Fix operand size of instructions with operand PTR []
[ Arm ]
- Fix a bug where arm_op_mem.disp is wrongly calculated (in DETAIL mode).
- Fix a bug on handling the If-Then block.
[ Mips ]
- Sanity check for the input size for MIPS64 mode.
[ MSVC ]
- Compile capstone.dll with static runtime MSVCR built in.
[ Python binding ]
- Fix a compiling issue of Cython binding with gcc 4.9.
---------------------------------
Version 3.0.1: February 03rd, 2015
[ X86 ]
- Properly handle LOCK, REP, REPE & REPNE prefixes.
- Handle undocumented immediates for SSE's (V)CMPPS/PD/SS/SD instructions.
- Print LJUMP/LCALL without * as prefix for Intel syntax.
- Handle REX prefix properly for segment/MMX related instructions (x86_64).
- Instruction with length > 15 is consider invalid.
- Handle some tricky encodings for instructions MOVSXD, FXCH, FCOM, FCOMP,
FSTP, FSTPNCE, NOP.
- Handle some tricky code for some X86_64 instructions with REX prefix.
- Add missing operands in detail mode for PUSH , POP , IN/OUT reg, reg
- MOV32ms & MOV32sm should reference word rather than dword.
[ Arm64 ]
- BL & BLR instructions do not read SP register.
- Print absolute (rather than relative) address for instructions B, BL,
CBNZ, ADR.
[ Arm ]
- Instructions ADC & SBC do not update flags.
- BL & BLX do not read SP, but PC register.
- Alias LDR instruction with operands [sp], 4 to POP.
- Print immediate operand of MVN instruction in positive hexadecimal form.
[ PowerPC ]
- Fix some compilation bugs when DIET mode is enable.
- Populate SLWI/SRWI instruction details with SH operand.
[ Python binding ]
- Fix a Cython bug when CsInsn.bytes returns a shorten array of bytes.
- Fixed a memory leak for Cython disasm functions when we immaturely quit
the enumeration of disassembled instructions.
- Fix a NULL memory access issue when SKIPDATA & Detail modes are enable
at the same time.
- Fix a memory leaking bug when when we stop enumeration over the disassembled
instructions prematurely.
- Export generic operand types & groups (CS_OP_xxx & CS_GRP_xxx).
---------------------------------
Version 3.0: November 19th, 2014
[ API ]
- New API: cs_disasm_iter & cs_malloc. See docs/README for tutorials.
- Renamed cs_disasm_ex to cs_disasm (cs_disasm_ex is still supported, but
marked obsolete to be removed in future)
- Support SKIPDATA mode, so Capstone can jump over unknown data and keep going
from the next legitimate instruction. See docs/README for tutorials.
- More details provided in cs_detail struct for all architectures.
- API version was bumped to 3.0.
[ Bindings ]
- Python binding supports Python3 (besides Python2).
- Support Ocaml binding.
- Java: add close() method to be used to deinitialize a Capstone object when
no longer use it.
[ Architectures ]
- New architectures: Sparc, SystemZ & XCore.
- Important bugfixes for Arm, Arm64, Mips, PowerPC & X86.
- Support more instructions for Arm, Arm64, Mips, PowerPC & X86.
- Always expose absolute addresses rather than relative addresses (Arm, Arm64,
Mips, PPC, Sparc, X86).
- Use common instruction operand types REG, IMM, MEM & FP across all
architectures (to enable cross-architecture analysis).
- Use common instruction group types across all architectures (to enable
cross-architecture analysis).
[ X86 ]
- X86 engine is mature & handles all the malware tricks (that we are aware of).
- Added a lot of new instructions (such as AVX512, 3DNow, etc).
- Add prefix symbols X86_PREFIX_REP/REPNE/LOCK/CS/DS/SS/FS/GS/ES/OPSIZE/ADDRSIZE.
- Print immediate in positive form & hexadecimal for AND/OR/XOR instructions.
- More friendly disassembly for JMP16i (in the form segment:offset)
[ Mips ]
- Engine added supports for new hardware modes: Mips32R6 (CS_MODE_MIPS32R6) &
MipsGP64 (CS_MODE_MIPSGP64).
- Removed the ABI-only mode CS_MODE_N64.
- New modes CS_MODE_MIPS32 & CS_MODE_MIPS64 (to use instead of CS_MODE_32 &
CS_MODE_64).
[ ARM ]
- Support new mode CS_MODE_V8 for Armv8 A32 encodings.
- Print immediate in positive form & hexadecimal for AND/ORR/EOR/BIC instructions
[ ARM64 ]
- Print immediate in hexadecimal for AND/ORR/EOR/TST instructions.
[ PowerPC ]
- Do not print a dot in front of absolute address.
[ Other features ]
- Support for Microsoft Visual Studio (so enable Windows native compilation).
- Support CMake compilation.
- Cross-compile for Android.
- Build libraries/tests using XCode project
- Much faster, while consuming less memory for all architectures.
---------------------------------
Version 2.1.2: April 3rd, 2014
This is a stable release to fix some bugs deep in the core. There is no update
to any architectures or bindings, so bindings version 2.1 can be used with this
version 2.1.2 just fine.
[ Core changes]
- Support cross-compilation for all iDevices (iPhone/iPad/iPod).
- X86: do not print memory offset in negative form.
- Fix a bug in X86 when Capstone cannot handle short instruction.
- Print negative number above -9 without prefix 0x (arm64, mips, arm).
- Correct the SONAME setup for library versioning (Linux, *BSD, Solaris).
- Set library versioning for dylib of OSX.
---------------------------------
Version 2.1.1: March 13th, 2014
This is a stable release to fix some bugs deep in the core. There is no update
to any architectures or bindings, so bindings version 2.1 can be used with this
version 2.1.1 just fine.
[ Core changes]
- Fix a buffer overflow bug in Thumb mode (ARM). Some special input can
trigger this flaw.
- Fix a crash issue when embedding Capstone into OSX kernel. This should
also enable Capstone to be embedded into other systems with limited stack
memory size such as Linux kernel or some firmwares.
- Use a proper SONAME for library versioning (Linux).
---------------------------------
Version 2.1: March 5th, 2014
[ API changes ]
- API version has been bumped to 2.1.
- Change prototype of cs_close() to be able to invalidate closed handle.
See http://capstone-engine.org/version_2.1_API.html for more information.
- Extend cs_support() to handle more query types, not only about supported
architectures. This change is backward compatible, however, so existent code
do not need to be modified to support this.
- New query type CS_SUPPORT_DIET for cs_support() to ask about diet status of
the engine.
- New error code CS_ERR_DIET to report errors about newly added diet mode.
- New error code CS_ERR_VERSION to report issue of incompatible versions between
bindings & core engine.
[ Core changes ]
- On memory usage, Capstone uses about 40% less memory, while still faster
than version 2.0.
- All architectures are much smaller: binaries size reduce at least 30%.
Especially, X86-only binary reduces from 1.9MB to just 720KB.
- Support "diet" mode, in which engine size is further reduced (by around 40%)
for embedding purpose. The price to pay is that we have to sacrifice some
non-critical data fields. See http://capstone-engine.org/diet.html for more
details.
[ Architectures ]
- Update all 5 architectures to fix bugs.
- PowerPC:
- New instructions: FMR & MSYNC.
- Mips:
- New instruction: DLSA
- X86:
- Properly handle AVX-512 instructions.
- New instructions: PSETPM, SALC, INT1, GETSEC.
- Fix some memory leaking issues in case of prefixed instructions such
as LOCK, REP, REPNE.
[ Python binding ]
- Verify the core version at initialization time. Refuse to run if its version
is different from the core's version.
- New API disasm_lite() added to Cs class. This light API only returns tuples of
(address, size, mnemonic, op_str), rather than list of CsInsn objects. This
improves performance by around 30% in some benchmarks.
- New API version_bind() returns binding's version, which might differ from
the core's API version if the binding is out-of-date.
- New API debug() returns information on Cython support, diet status & archs
compiled in.
- Fixed some memory leaking bugs for Cython binding.
- Fix a bug crashing Cython code when accessing @regs_read/regs_write/groups.
- Support diet mode.
[ Java binding ]
- Fix some memory leaking bugs.
- New API version() returns combined version.
- Support diet mode.
- Better support for detail option.
[ Miscellaneous ]
- make.sh now can uninstall the core engine. This is done with:
$ sudo ./make.sh uninstall
----------------------------------
Version 2.0: January 22nd, 2014
Release 2.0 deprecates verison 1.0 and brings a lot of crucial changes.
[ API changes ]
- API version has been bumped to 2.0 (see cs_version() API)
- New API cs_strerror(errno) returns a string describing error code given
in its only argument.
- cs_version() now returns combined version encoding both major & minor versions.
- New option CS_OPT_MODE allows to change engine’s mode at run-time with
cs_option().
- New option CS_OPT_MEM allows to specify user-defined functions for dynamically
memory management used internally by Capstone. This is useful to embed Capstone
into special environments such as kernel or firware.
- New API cs_support() can be used to check if this lib supports a particular
architecture (this is necessary since we now allow to choose which architectures
to compile in).
- The detail option is OFF by default now. To get detail information, it should be
explicitly turned ON. The details then can be accessed using cs_insn.detail
pointer (to newly added structure cs_detail)
[ Core changes ]
- On memory usage, Capstone uses much less memory, but a lot faster now.
- User now can choose which architectures to be supported by modifying config.mk
before compiling/installing.
[ Architectures ]
- Arm
- Support Big-Endian mode (besides Little-Endian mode).
- Support friendly register, so instead of output sub "r12,r11,0x14",
we have "sub ip,fp,0x14".
- Arm64: support Big-Endian mode (besides Little-Endian mode).
- PowerPC: newly added.
- Mips: support friendly register, so instead of output "srl $2,$1,0x1f",
we have "srl $v0,$at,0x1f".
- X86: bug fixes.
[ Python binding ]
- Python binding is vastly improved in performance: around 3 ~ 4 times faster
than in 1.0.
- Cython support has been added, which can further speed up over the default
pure Python binding (up to 30% in some cases)
- Function cs_disasm_quick() & Cs.disasm() now use generator (rather than a list)
to return succesfully disassembled instructions. This improves the performance
and reduces memory usage.
[ Java binding ]
- Better performance & bug fixes.
[ Miscellaneous ]
- Fixed some installation issues with Gentoo Linux.
- Capstone now can easily compile/install on all *nix, including Linux, OSX,
{Net, Free, Open}BSD & Solaris.
----------------------------------
[Version 1.0]: December 18th, 2013
- Initial public release.

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Capstone source is organized as followings.
. <- core engine + README + COMPILE.TXT etc
├── arch <- code handling disasm engine for each arch
│   ├── AArch64 <- ARM64 (aka ARMv8) engine
│   ├── ARM <- ARM engine
│   ├── Mips <- Mips engine
│   ├── PowerPC <- PowerPC engine
│   ├── Sparc <- Sparc engine
│   ├── SystemZ <- SystemZ engine
│   ├── X86 <- X86 engine
│   └── XCore <- XCore engine
├── bindings <- all bindings are under this dir
│   ├── java <- Java bindings + test code
│   ├── ocaml <- Ocaml bindings + test code
│   └── python <- Python bindings + test code
├── contrib <- Code contributed by community to help Capstone integration
├── docs <- Documentation
├── include <- API headers in C language (*.h)
├── msvc <- Microsoft Visual Studio support (for Windows compile)
├── packages <- Packages for Linux/OSX/BSD.
├── suite <- Development test tools - for Capstone developers only
├── tests <- Test code (in C language)
└── xcode <- Xcode support (for MacOSX compile)
Follow instructions in COMPILE.TXT for how to compile and run test code.
Note: if you find some strange bugs, it is recommended to firstly clean
the code and try to recompile/reinstall again. This can be done with:
$ ./make.sh
$ sudo ./make.sh install
At the same time, for Java/Ocaml/Python bindings, be sure to always use
the bindings coming with the core to avoid potential incompatility issue
with older versions.
See bindings/<language>/README for detail instructions on how to compile &
install the bindings.

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//===- llvm/Support/LEB128.h - [SU]LEB128 utility functions -----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file declares some utility functions for encoding SLEB128 and
// ULEB128 values.
//
//===----------------------------------------------------------------------===//
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
#ifndef CS_LLVM_SUPPORT_LEB128_H
#define CS_LLVM_SUPPORT_LEB128_H
#include <stdint.h>
/// Utility function to decode a ULEB128 value.
static inline uint64_t decodeULEB128(const uint8_t *p, unsigned *n)
{
const uint8_t *orig_p = p;
uint64_t Value = 0;
unsigned Shift = 0;
do {
Value += (*p & 0x7f) << Shift;
Shift += 7;
} while (*p++ >= 128);
if (n)
*n = (unsigned)(p - orig_p);
return Value;
}
#endif // LLVM_SYSTEM_LEB128_H

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This is the software license for Capstone disassembly framework.
Capstone has been designed & implemented by Nguyen Anh Quynh <aquynh@gmail.com>
See http://www.capstone-engine.org for further information.
Copyright (c) 2013, COSEINC.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
* Neither the name of the developer(s) nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.

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==============================================================================
LLVM Release License
==============================================================================
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2013 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
==============================================================================
Copyrights and Licenses for Third Party Software Distributed with LLVM:
==============================================================================
The LLVM software contains code written by third parties. Such software will
have its own individual LICENSE.TXT file in the directory in which it appears.
This file will describe the copyrights, license, and restrictions which apply
to that code.
The disclaimer of warranty in the University of Illinois Open Source License
applies to all code in the LLVM Distribution, and nothing in any of the
other licenses gives permission to use the names of the LLVM Team or the
University of Illinois to endorse or promote products derived from this
Software.
The following pieces of software have additional or alternate copyrights,
licenses, and/or restrictions:
Program Directory
------- ---------
Autoconf llvm/autoconf
llvm/projects/ModuleMaker/autoconf
llvm/projects/sample/autoconf
Google Test llvm/utils/unittest/googletest
OpenBSD regex llvm/lib/Support/{reg*, COPYRIGHT.regex}
pyyaml tests llvm/test/YAMLParser/{*.data, LICENSE.TXT}
ARM contributions llvm/lib/Target/ARM/LICENSE.TXT
md5 contributions llvm/lib/Support/MD5.cpp llvm/include/llvm/Support/MD5.h

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/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
#ifndef CS_MCDISASSEMBLER_H
#define CS_MCDISASSEMBLER_H
typedef enum DecodeStatus {
MCDisassembler_Fail = 0,
MCDisassembler_SoftFail = 1,
MCDisassembler_Success = 3,
} DecodeStatus;
#endif

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//===-- llvm/MC/MCFixedLenDisassembler.h - Decoder driver -------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
// Fixed length disassembler decoder state machine driver.
//===----------------------------------------------------------------------===//
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
#ifndef CS_LLVM_MC_MCFIXEDLENDISASSEMBLER_H
#define CS_LLVM_MC_MCFIXEDLENDISASSEMBLER_H
// Disassembler state machine opcodes.
enum DecoderOps {
MCD_OPC_ExtractField = 1, // OPC_ExtractField(uint8_t Start, uint8_t Len)
MCD_OPC_FilterValue, // OPC_FilterValue(uleb128 Val, uint16_t NumToSkip)
MCD_OPC_CheckField, // OPC_CheckField(uint8_t Start, uint8_t Len,
// uleb128 Val, uint16_t NumToSkip)
MCD_OPC_CheckPredicate, // OPC_CheckPredicate(uleb128 PIdx, uint16_t NumToSkip)
MCD_OPC_Decode, // OPC_Decode(uleb128 Opcode, uleb128 DIdx)
MCD_OPC_SoftFail, // OPC_SoftFail(uleb128 PMask, uleb128 NMask)
MCD_OPC_Fail // OPC_Fail()
};
#endif

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/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
#if defined(CAPSTONE_HAS_OSXKERNEL)
#include <libkern/libkern.h>
#else
#include <stdio.h>
#include <stdlib.h>
#endif
#include <string.h>
#include "MCInst.h"
#include "utils.h"
#define MCINST_CACHE (ARR_SIZE(mcInst->Operands) - 1)
void MCInst_Init(MCInst *inst)
{
inst->OpcodePub = 0;
inst->size = 0;
inst->has_imm = false;
inst->op1_size = 0;
inst->writeback = false;
}
void MCInst_clear(MCInst *inst)
{
inst->size = 0;
}
// do not free @Op
void MCInst_insert0(MCInst *inst, int index, MCOperand *Op)
{
int i;
for(i = inst->size; i > index; i--)
//memcpy(&(inst->Operands[i]), &(inst->Operands[i-1]), sizeof(MCOperand));
inst->Operands[i] = inst->Operands[i-1];
inst->Operands[index] = *Op;
inst->size++;
}
void MCInst_setOpcode(MCInst *inst, unsigned Op)
{
inst->Opcode = Op;
}
void MCInst_setOpcodePub(MCInst *inst, unsigned Op)
{
inst->OpcodePub = Op;
}
unsigned MCInst_getOpcode(const MCInst *inst)
{
return inst->Opcode;
}
unsigned MCInst_getOpcodePub(const MCInst *inst)
{
return inst->OpcodePub;
}
MCOperand *MCInst_getOperand(MCInst *inst, unsigned i)
{
return &inst->Operands[i];
}
unsigned MCInst_getNumOperands(const MCInst *inst)
{
return inst->size;
}
// This addOperand2 function doesnt free Op
void MCInst_addOperand2(MCInst *inst, MCOperand *Op)
{
inst->Operands[inst->size] = *Op;
inst->size++;
}
void MCOperand_Init(MCOperand *op)
{
op->Kind = kInvalid;
op->FPImmVal = 0.0;
}
bool MCOperand_isValid(const MCOperand *op)
{
return op->Kind != kInvalid;
}
bool MCOperand_isReg(const MCOperand *op)
{
return op->Kind == kRegister;
}
bool MCOperand_isImm(const MCOperand *op)
{
return op->Kind == kImmediate;
}
bool MCOperand_isFPImm(const MCOperand *op)
{
return op->Kind == kFPImmediate;
}
/// getReg - Returns the register number.
unsigned MCOperand_getReg(const MCOperand *op)
{
return op->RegVal;
}
/// setReg - Set the register number.
void MCOperand_setReg(MCOperand *op, unsigned Reg)
{
op->RegVal = Reg;
}
int64_t MCOperand_getImm(MCOperand *op)
{
return op->ImmVal;
}
void MCOperand_setImm(MCOperand *op, int64_t Val)
{
op->ImmVal = Val;
}
double MCOperand_getFPImm(const MCOperand *op)
{
return op->FPImmVal;
}
void MCOperand_setFPImm(MCOperand *op, double Val)
{
op->FPImmVal = Val;
}
MCOperand *MCOperand_CreateReg1(MCInst *mcInst, unsigned Reg)
{
MCOperand *op = &(mcInst->Operands[MCINST_CACHE]);
op->Kind = kRegister;
op->RegVal = Reg;
return op;
}
void MCOperand_CreateReg0(MCInst *mcInst, unsigned Reg)
{
MCOperand *op = &(mcInst->Operands[mcInst->size]);
mcInst->size++;
op->Kind = kRegister;
op->RegVal = Reg;
}
MCOperand *MCOperand_CreateImm1(MCInst *mcInst, int64_t Val)
{
MCOperand *op = &(mcInst->Operands[MCINST_CACHE]);
op->Kind = kImmediate;
op->ImmVal = Val;
return op;
}
void MCOperand_CreateImm0(MCInst *mcInst, int64_t Val)
{
MCOperand *op = &(mcInst->Operands[mcInst->size]);
mcInst->size++;
op->Kind = kImmediate;
op->ImmVal = Val;
}

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//===-- llvm/MC/MCInst.h - MCInst class -------------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the declaration of the MCInst and MCOperand classes, which
// is the basic representation used to represent low-level machine code
// instructions.
//
//===----------------------------------------------------------------------===//
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
#ifndef CS_MCINST_H
#define CS_MCINST_H
#include <stdint.h>
#include "include/capstone.h"
typedef struct MCInst MCInst;
typedef struct cs_struct cs_struct;
typedef struct MCOperand MCOperand;
/// MCOperand - Instances of this class represent operands of the MCInst class.
/// This is a simple discriminated union.
struct MCOperand {
enum {
kInvalid = 0, ///< Uninitialized.
kRegister, ///< Register operand.
kImmediate, ///< Immediate operand.
kFPImmediate, ///< Floating-point immediate operand.
} MachineOperandType;
unsigned char Kind;
union {
unsigned RegVal;
int64_t ImmVal;
double FPImmVal;
};
};
bool MCOperand_isValid(const MCOperand *op);
bool MCOperand_isReg(const MCOperand *op);
bool MCOperand_isImm(const MCOperand *op);
bool MCOperand_isFPImm(const MCOperand *op);
bool MCOperand_isInst(const MCOperand *op);
/// getReg - Returns the register number.
unsigned MCOperand_getReg(const MCOperand *op);
/// setReg - Set the register number.
void MCOperand_setReg(MCOperand *op, unsigned Reg);
int64_t MCOperand_getImm(MCOperand *op);
void MCOperand_setImm(MCOperand *op, int64_t Val);
double MCOperand_getFPImm(const MCOperand *op);
void MCOperand_setFPImm(MCOperand *op, double Val);
const MCInst *MCOperand_getInst(const MCOperand *op);
void MCOperand_setInst(MCOperand *op, const MCInst *Val);
// create Reg operand in the next slot
void MCOperand_CreateReg0(MCInst *inst, unsigned Reg);
// create Reg operand use the last-unused slot
MCOperand *MCOperand_CreateReg1(MCInst *inst, unsigned Reg);
// create Imm operand in the next slot
void MCOperand_CreateImm0(MCInst *inst, int64_t Val);
// create Imm operand in the last-unused slot
MCOperand *MCOperand_CreateImm1(MCInst *inst, int64_t Val);
/// MCInst - Instances of this class represent a single low-level machine
/// instruction.
struct MCInst {
unsigned OpcodePub;
uint8_t size; // number of operands
bool has_imm; // indicate this instruction has an X86_OP_IMM operand - used for ATT syntax
uint8_t op1_size; // size of 1st operand - for X86 Intel syntax
unsigned Opcode;
MCOperand Operands[48];
cs_insn *flat_insn; // insn to be exposed to public
uint64_t address; // address of this insn
cs_struct *csh; // save the main csh
uint8_t x86opsize; // opsize for [mem] operand
// (Optional) instruction prefix, which can be up to 4 bytes.
// A prefix byte gets value 0 when irrelevant.
// This is copied from cs_x86 struct
uint8_t x86_prefix[4];
uint8_t imm_size; // immediate size for X86_OP_IMM operand
bool writeback; // writeback for ARM
};
void MCInst_Init(MCInst *inst);
void MCInst_clear(MCInst *inst);
// do not free operand after inserting
void MCInst_insert0(MCInst *inst, int index, MCOperand *Op);
void MCInst_setOpcode(MCInst *inst, unsigned Op);
unsigned MCInst_getOpcode(const MCInst*);
void MCInst_setOpcodePub(MCInst *inst, unsigned Op);
unsigned MCInst_getOpcodePub(const MCInst*);
MCOperand *MCInst_getOperand(MCInst *inst, unsigned i);
unsigned MCInst_getNumOperands(const MCInst *inst);
// This addOperand2 function doesnt free Op
void MCInst_addOperand2(MCInst *inst, MCOperand *Op);
#endif

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/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
#include "MCInstrDesc.h"
/// isPredicate - Set if this is one of the operands that made up of
/// the predicate operand that controls an isPredicable() instruction.
bool MCOperandInfo_isPredicate(MCOperandInfo *m)
{
return m->Flags & (1 << MCOI_Predicate);
}
/// isOptionalDef - Set if this operand is a optional def.
///
bool MCOperandInfo_isOptionalDef(MCOperandInfo *m)
{
return m->Flags & (1 << MCOI_OptionalDef);
}

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//===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file defines the MCOperandInfo and MCInstrDesc classes, which
// are used to describe target instructions and their operands.
//
//===----------------------------------------------------------------------===//
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
#ifndef CS_LLVM_MC_MCINSTRDESC_H
#define CS_LLVM_MC_MCINSTRDESC_H
#include <stdint.h>
#include "include/platform.h"
//===----------------------------------------------------------------------===//
// Machine Operand Flags and Description
//===----------------------------------------------------------------------===//
// Operand constraints
enum MCOI_OperandConstraint {
MCOI_TIED_TO = 0, // Must be allocated the same register as.
MCOI_EARLY_CLOBBER // Operand is an early clobber register operand
};
/// OperandFlags - These are flags set on operands, but should be considered
/// private, all access should go through the MCOperandInfo accessors.
/// See the accessors for a description of what these are.
enum MCOI_OperandFlags {
MCOI_LookupPtrRegClass = 0,
MCOI_Predicate,
MCOI_OptionalDef
};
/// Operand Type - Operands are tagged with one of the values of this enum.
enum MCOI_OperandType {
MCOI_OPERAND_UNKNOWN,
MCOI_OPERAND_IMMEDIATE,
MCOI_OPERAND_REGISTER,
MCOI_OPERAND_MEMORY,
MCOI_OPERAND_PCREL
};
/// MCOperandInfo - This holds information about one operand of a machine
/// instruction, indicating the register class for register operands, etc.
///
typedef struct MCOperandInfo {
/// RegClass - This specifies the register class enumeration of the operand
/// if the operand is a register. If isLookupPtrRegClass is set, then this is
/// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
/// get a dynamic register class.
int16_t RegClass;
/// Flags - These are flags from the MCOI::OperandFlags enum.
uint8_t Flags;
/// OperandType - Information about the type of the operand.
uint8_t OperandType;
/// Lower 16 bits are used to specify which constraints are set. The higher 16
/// bits are used to specify the value of constraints (4 bits each).
uint32_t Constraints;
/// Currently no other information.
} MCOperandInfo;
//===----------------------------------------------------------------------===//
// Machine Instruction Flags and Description
//===----------------------------------------------------------------------===//
/// MCInstrDesc flags - These should be considered private to the
/// implementation of the MCInstrDesc class. Clients should use the predicate
/// methods on MCInstrDesc, not use these directly. These all correspond to
/// bitfields in the MCInstrDesc::Flags field.
enum {
MCID_Variadic = 0,
MCID_HasOptionalDef,
MCID_Pseudo,
MCID_Return,
MCID_Call,
MCID_Barrier,
MCID_Terminator,
MCID_Branch,
MCID_IndirectBranch,
MCID_Compare,
MCID_MoveImm,
MCID_Bitcast,
MCID_Select,
MCID_DelaySlot,
MCID_FoldableAsLoad,
MCID_MayLoad,
MCID_MayStore,
MCID_Predicable,
MCID_NotDuplicable,
MCID_UnmodeledSideEffects,
MCID_Commutable,
MCID_ConvertibleTo3Addr,
MCID_UsesCustomInserter,
MCID_HasPostISelHook,
MCID_Rematerializable,
MCID_CheapAsAMove,
MCID_ExtraSrcRegAllocReq,
MCID_ExtraDefRegAllocReq,
MCID_RegSequence,
};
/// MCInstrDesc - Describe properties that are true of each instruction in the
/// target description file. This captures information about side effects,
/// register use and many other things. There is one instance of this struct
/// for each target instruction class, and the MachineInstr class points to
/// this struct directly to describe itself.
typedef struct MCInstrDesc {
unsigned short Opcode; // The opcode number
unsigned char NumOperands; // Num of args (may be more if variable_ops)
unsigned char NumDefs; // Num of args that are definitions
unsigned short SchedClass; // enum identifying instr sched class
unsigned char Size; // Number of bytes in encoding.
unsigned Flags; // Flags identifying machine instr class
uint64_t TSFlags; // Target Specific Flag values
char ImplicitUses; // Registers implicitly read by this instr
char ImplicitDefs; // Registers implicitly defined by this instr
MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
uint64_t DeprecatedFeatureMask;// Feature bits that this is deprecated on, if any
// A complex method to determine is a certain is deprecated or not, and return
// the reason for deprecation.
//bool (*ComplexDeprecationInfo)(MCInst &, MCSubtargetInfo &, std::string &);
unsigned char ComplexDeprecationInfo; // dummy field, just to satisfy initializer
} MCInstrDesc;
bool MCOperandInfo_isPredicate(MCOperandInfo *m);
bool MCOperandInfo_isOptionalDef(MCOperandInfo *m);
#endif

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//=== MC/MCRegisterInfo.cpp - Target Register Description -------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file implements MCRegisterInfo functions.
//
//===----------------------------------------------------------------------===//
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
#include "MCRegisterInfo.h"
/// DiffListIterator - Base iterator class that can traverse the
/// differentially encoded register and regunit lists in DiffLists.
/// Don't use this class directly, use one of the specialized sub-classes
/// defined below.
typedef struct DiffListIterator {
uint16_t Val;
MCPhysReg *List;
} DiffListIterator;
void MCRegisterInfo_InitMCRegisterInfo(MCRegisterInfo *RI,
MCRegisterDesc *D, unsigned NR,
unsigned RA, unsigned PC,
MCRegisterClass *C, unsigned NC,
uint16_t (*RURoots)[2], unsigned NRU,
MCPhysReg *DL,
char *Strings,
uint16_t *SubIndices, unsigned NumIndices,
uint16_t *RET)
{
RI->Desc = D;
RI->NumRegs = NR;
RI->RAReg = RA;
RI->PCReg = PC;
RI->Classes = C;
RI->DiffLists = DL;
RI->RegStrings = Strings;
RI->NumClasses = NC;
RI->RegUnitRoots = RURoots;
RI->NumRegUnits = NRU;
RI->SubRegIndices = SubIndices;
RI->NumSubRegIndices = NumIndices;
RI->RegEncodingTable = RET;
}
static void DiffListIterator_init(DiffListIterator *d, MCPhysReg InitVal, MCPhysReg *DiffList)
{
d->Val = InitVal;
d->List = DiffList;
}
static uint16_t DiffListIterator_getVal(DiffListIterator *d)
{
return d->Val;
}
static bool DiffListIterator_next(DiffListIterator *d)
{
MCPhysReg D;
if (d->List == 0)
return false;
D = *d->List;
d->List++;
d->Val += D;
if (!D)
d->List = 0;
return (D != 0);
}
static bool DiffListIterator_isValid(DiffListIterator *d)
{
return (d->List != 0);
}
unsigned MCRegisterInfo_getMatchingSuperReg(MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, MCRegisterClass *RC)
{
DiffListIterator iter;
if (Reg >= RI->NumRegs) {
return 0;
}
DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SuperRegs);
DiffListIterator_next(&iter);
while(DiffListIterator_isValid(&iter)) {
uint16_t val = DiffListIterator_getVal(&iter);
if (MCRegisterClass_contains(RC, val) && Reg == MCRegisterInfo_getSubReg(RI, val, SubIdx))
return val;
DiffListIterator_next(&iter);
}
return 0;
}
unsigned MCRegisterInfo_getSubReg(MCRegisterInfo *RI, unsigned Reg, unsigned Idx)
{
DiffListIterator iter;
uint16_t *SRI = RI->SubRegIndices + RI->Desc[Reg].SubRegIndices;
DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SubRegs);
DiffListIterator_next(&iter);
while(DiffListIterator_isValid(&iter)) {
if (*SRI == Idx)
return DiffListIterator_getVal(&iter);
DiffListIterator_next(&iter);
++SRI;
}
return 0;
}
MCRegisterClass* MCRegisterInfo_getRegClass(MCRegisterInfo *RI, unsigned i)
{
//assert(i < getNumRegClasses() && "Register Class ID out of range");
if (i >= RI->NumClasses)
return 0;
return &(RI->Classes[i]);
}
bool MCRegisterClass_contains(MCRegisterClass *c, unsigned Reg)
{
unsigned InByte = Reg % 8;
unsigned Byte = Reg / 8;
if (Byte >= c->RegSetSize)
return false;
return (c->RegSet[Byte] & (1 << InByte)) != 0;
}

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//=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file describes an abstract interface used to get information about a
// target machines register file. This information is used for a variety of
// purposed, especially register allocation.
//
//===----------------------------------------------------------------------===//
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
#ifndef CS_LLVM_MC_MCREGISTERINFO_H
#define CS_LLVM_MC_MCREGISTERINFO_H
#include <stdint.h>
#include "include/platform.h"
/// An unsigned integer type large enough to represent all physical registers,
/// but not necessarily virtual registers.
typedef uint16_t MCPhysReg;
typedef MCPhysReg* iterator;
typedef struct MCRegisterClass {
char *Name;
iterator RegsBegin;
uint8_t *RegSet;
uint16_t RegsSize;
uint16_t RegSetSize;
uint16_t ID;
uint16_t RegSize, Alignment; // Size & Alignment of register in bytes
int8_t CopyCost;
bool Allocatable;
} MCRegisterClass;
/// MCRegisterDesc - This record contains information about a particular
/// register. The SubRegs field is a zero terminated array of registers that
/// are sub-registers of the specific register, e.g. AL, AH are sub-registers
/// of AX. The SuperRegs field is a zero terminated array of registers that are
/// super-registers of the specific register, e.g. RAX, EAX, are
/// super-registers of AX.
///
typedef struct MCRegisterDesc {
uint32_t Name; // Printable name for the reg (for debugging)
uint32_t SubRegs; // Sub-register set, described above
uint32_t SuperRegs; // Super-register set, described above
// Offset into MCRI::SubRegIndices of a list of sub-register indices for each
// sub-register in SubRegs.
uint32_t SubRegIndices;
// RegUnits - Points to the list of register units. The low 4 bits holds the
// Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator.
uint32_t RegUnits;
} MCRegisterDesc;
/// MCRegisterInfo base class - We assume that the target defines a static
/// array of MCRegisterDesc objects that represent all of the machine
/// registers that the target has. As such, we simply have to track a pointer
/// to this array so that we can turn register number into a register
/// descriptor.
///
/// Note this class is designed to be a base class of TargetRegisterInfo, which
/// is the interface used by codegen. However, specific targets *should never*
/// specialize this class. MCRegisterInfo should only contain getters to access
/// TableGen generated physical register data. It must not be extended with
/// virtual methods.
///
typedef struct MCRegisterInfo {
MCRegisterDesc *Desc; // Pointer to the descriptor array
unsigned NumRegs; // Number of entries in the array
unsigned RAReg; // Return address register
unsigned PCReg; // Program counter register
MCRegisterClass *Classes; // Pointer to the regclass array
unsigned NumClasses; // Number of entries in the array
unsigned NumRegUnits; // Number of regunits.
uint16_t (*RegUnitRoots)[2]; // Pointer to regunit root table.
MCPhysReg *DiffLists; // Pointer to the difflists array
char *RegStrings; // Pointer to the string table.
uint16_t *SubRegIndices; // Pointer to the subreg lookup
// array.
unsigned NumSubRegIndices; // Number of subreg indices.
uint16_t *RegEncodingTable; // Pointer to array of register
// encodings.
} MCRegisterInfo;
void MCRegisterInfo_InitMCRegisterInfo(MCRegisterInfo *RI,
MCRegisterDesc *D, unsigned NR, unsigned RA,
unsigned PC,
MCRegisterClass *C, unsigned NC,
uint16_t (*RURoots)[2],
unsigned NRU,
MCPhysReg *DL,
char *Strings,
uint16_t *SubIndices,
unsigned NumIndices,
uint16_t *RET);
unsigned MCRegisterInfo_getMatchingSuperReg(MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, MCRegisterClass *RC);
unsigned MCRegisterInfo_getSubReg(MCRegisterInfo *RI, unsigned Reg, unsigned Idx);
MCRegisterClass* MCRegisterInfo_getRegClass(MCRegisterInfo *RI, unsigned i);
bool MCRegisterClass_contains(MCRegisterClass *c, unsigned Reg);
#endif

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//===-- llvm/Support/MathExtras.h - Useful math functions -------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains some functions that are useful for math stuff.
//
//===----------------------------------------------------------------------===//
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
#ifndef CS_LLVM_SUPPORT_MATHEXTRAS_H
#define CS_LLVM_SUPPORT_MATHEXTRAS_H
#include <stdint.h>
#ifdef _MSC_VER
# include <intrin.h>
#endif
#ifndef __cplusplus
#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)
#define inline /* inline */
#endif
#endif
// NOTE: The following support functions use the _32/_64 extensions instead of
// type overloading so that signed and unsigned integers can be used without
// ambiguity.
/// Hi_32 - This function returns the high 32 bits of a 64 bit value.
static inline uint32_t Hi_32(uint64_t Value) {
return (uint32_t)(Value >> 32);
}
/// Lo_32 - This function returns the low 32 bits of a 64 bit value.
static inline uint32_t Lo_32(uint64_t Value) {
return (uint32_t)(Value);
}
/// isUIntN - Checks if an unsigned integer fits into the given (dynamic)
/// bit width.
static inline bool isUIntN(unsigned N, uint64_t x) {
return x == (x & (~0ULL >> (64 - N)));
}
/// isIntN - Checks if an signed integer fits into the given (dynamic)
/// bit width.
//static inline bool isIntN(unsigned N, int64_t x) {
// return N >= 64 || (-(INT64_C(1)<<(N-1)) <= x && x < (INT64_C(1)<<(N-1)));
//}
/// isMask_32 - This function returns true if the argument is a sequence of ones
/// starting at the least significant bit with the remainder zero (32 bit
/// version). Ex. isMask_32(0x0000FFFFU) == true.
static inline bool isMask_32(uint32_t Value) {
return Value && ((Value + 1) & Value) == 0;
}
/// isMask_64 - This function returns true if the argument is a sequence of ones
/// starting at the least significant bit with the remainder zero (64 bit
/// version).
static inline bool isMask_64(uint64_t Value) {
return Value && ((Value + 1) & Value) == 0;
}
/// isShiftedMask_32 - This function returns true if the argument contains a
/// sequence of ones with the remainder zero (32 bit version.)
/// Ex. isShiftedMask_32(0x0000FF00U) == true.
static inline bool isShiftedMask_32(uint32_t Value) {
return isMask_32((Value - 1) | Value);
}
/// isShiftedMask_64 - This function returns true if the argument contains a
/// sequence of ones with the remainder zero (64 bit version.)
static inline bool isShiftedMask_64(uint64_t Value) {
return isMask_64((Value - 1) | Value);
}
/// isPowerOf2_32 - This function returns true if the argument is a power of
/// two > 0. Ex. isPowerOf2_32(0x00100000U) == true (32 bit edition.)
static inline bool isPowerOf2_32(uint32_t Value) {
return Value && !(Value & (Value - 1));
}
/// CountLeadingZeros_32 - this function performs the platform optimal form of
/// counting the number of zeros from the most significant bit to the first one
/// bit. Ex. CountLeadingZeros_32(0x00F000FF) == 8.
/// Returns 32 if the word is zero.
static inline unsigned CountLeadingZeros_32(uint32_t Value) {
unsigned Count; // result
#if __GNUC__ >= 4
// PowerPC is defined for __builtin_clz(0)
#if !defined(__ppc__) && !defined(__ppc64__)
if (!Value) return 32;
#endif
Count = __builtin_clz(Value);
#else
unsigned Shift;
if (!Value) return 32;
Count = 0;
// bisection method for count leading zeros
for (Shift = 32 >> 1; Shift; Shift >>= 1) {
uint32_t Tmp = Value >> Shift;
if (Tmp) {
Value = Tmp;
} else {
Count |= Shift;
}
}
#endif
return Count;
}
/// CountLeadingOnes_32 - this function performs the operation of
/// counting the number of ones from the most significant bit to the first zero
/// bit. Ex. CountLeadingOnes_32(0xFF0FFF00) == 8.
/// Returns 32 if the word is all ones.
static inline unsigned CountLeadingOnes_32(uint32_t Value) {
return CountLeadingZeros_32(~Value);
}
/// CountLeadingZeros_64 - This function performs the platform optimal form
/// of counting the number of zeros from the most significant bit to the first
/// one bit (64 bit edition.)
/// Returns 64 if the word is zero.
static inline unsigned CountLeadingZeros_64(uint64_t Value) {
unsigned Count; // result
#if __GNUC__ >= 4
// PowerPC is defined for __builtin_clzll(0)
#if !defined(__ppc__) && !defined(__ppc64__)
if (!Value) return 64;
#endif
Count = __builtin_clzll(Value);
#else
#ifndef _MSC_VER
unsigned Shift;
if (sizeof(long) == sizeof(int64_t))
{
if (!Value) return 64;
Count = 0;
// bisection method for count leading zeros
for (Shift = 64 >> 1; Shift; Shift >>= 1) {
uint64_t Tmp = Value >> Shift;
if (Tmp) {
Value = Tmp;
} else {
Count |= Shift;
}
}
}
else
#endif
{
// get hi portion
uint32_t Hi = Hi_32(Value);
// if some bits in hi portion
if (Hi) {
// leading zeros in hi portion plus all bits in lo portion
Count = CountLeadingZeros_32(Hi);
} else {
// get lo portion
uint32_t Lo = Lo_32(Value);
// same as 32 bit value
Count = CountLeadingZeros_32(Lo)+32;
}
}
#endif
return Count;
}
/// CountLeadingOnes_64 - This function performs the operation
/// of counting the number of ones from the most significant bit to the first
/// zero bit (64 bit edition.)
/// Returns 64 if the word is all ones.
static inline unsigned CountLeadingOnes_64(uint64_t Value) {
return CountLeadingZeros_64(~Value);
}
/// CountTrailingZeros_32 - this function performs the platform optimal form of
/// counting the number of zeros from the least significant bit to the first one
/// bit. Ex. CountTrailingZeros_32(0xFF00FF00) == 8.
/// Returns 32 if the word is zero.
static inline unsigned CountTrailingZeros_32(uint32_t Value) {
#if __GNUC__ >= 4
return Value ? __builtin_ctz(Value) : 32;
#else
static const unsigned Mod37BitPosition[] = {
32, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13,
4, 7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9,
5, 20, 8, 19, 18
};
// Replace "-Value" by "1+~Value" in the following commented code to avoid
// MSVC warning C4146
// return Mod37BitPosition[(-Value & Value) % 37];
return Mod37BitPosition[((1 + ~Value) & Value) % 37];
#endif
}
/// CountTrailingOnes_32 - this function performs the operation of
/// counting the number of ones from the least significant bit to the first zero
/// bit. Ex. CountTrailingOnes_32(0x00FF00FF) == 8.
/// Returns 32 if the word is all ones.
static inline unsigned CountTrailingOnes_32(uint32_t Value) {
return CountTrailingZeros_32(~Value);
}
/// CountTrailingZeros_64 - This function performs the platform optimal form
/// of counting the number of zeros from the least significant bit to the first
/// one bit (64 bit edition.)
/// Returns 64 if the word is zero.
static inline unsigned CountTrailingZeros_64(uint64_t Value) {
#if __GNUC__ >= 4
return Value ? __builtin_ctzll(Value) : 64;
#else
static const unsigned Mod67Position[] = {
64, 0, 1, 39, 2, 15, 40, 23, 3, 12, 16, 59, 41, 19, 24, 54,
4, 64, 13, 10, 17, 62, 60, 28, 42, 30, 20, 51, 25, 44, 55,
47, 5, 32, 65, 38, 14, 22, 11, 58, 18, 53, 63, 9, 61, 27,
29, 50, 43, 46, 31, 37, 21, 57, 52, 8, 26, 49, 45, 36, 56,
7, 48, 35, 6, 34, 33, 0
};
// Replace "-Value" by "1+~Value" in the following commented code to avoid
// MSVC warning C4146
// return Mod67Position[(-Value & Value) % 67];
return Mod67Position[((1 + ~Value) & Value) % 67];
#endif
}
/// CountTrailingOnes_64 - This function performs the operation
/// of counting the number of ones from the least significant bit to the first
/// zero bit (64 bit edition.)
/// Returns 64 if the word is all ones.
static inline unsigned CountTrailingOnes_64(uint64_t Value) {
return CountTrailingZeros_64(~Value);
}
/// CountPopulation_32 - this function counts the number of set bits in a value.
/// Ex. CountPopulation(0xF000F000) = 8
/// Returns 0 if the word is zero.
static inline unsigned CountPopulation_32(uint32_t Value) {
#if __GNUC__ >= 4
return __builtin_popcount(Value);
#else
uint32_t v = Value - ((Value >> 1) & 0x55555555);
v = (v & 0x33333333) + ((v >> 2) & 0x33333333);
return (((v + (v >> 4)) & 0xF0F0F0F) * 0x1010101) >> 24;
#endif
}
/// CountPopulation_64 - this function counts the number of set bits in a value,
/// (64 bit edition.)
static inline unsigned CountPopulation_64(uint64_t Value) {
#if __GNUC__ >= 4
return __builtin_popcountll(Value);
#else
uint64_t v = Value - ((Value >> 1) & 0x5555555555555555ULL);
v = (v & 0x3333333333333333ULL) + ((v >> 2) & 0x3333333333333333ULL);
v = (v + (v >> 4)) & 0x0F0F0F0F0F0F0F0FULL;
return (uint64_t)((v * 0x0101010101010101ULL) >> 56);
#endif
}
/// Log2_32 - This function returns the floor log base 2 of the specified value,
/// -1 if the value is zero. (32 bit edition.)
/// Ex. Log2_32(32) == 5, Log2_32(1) == 0, Log2_32(0) == -1, Log2_32(6) == 2
static inline unsigned Log2_32(uint32_t Value) {
return 31 - CountLeadingZeros_32(Value);
}
/// Log2_64 - This function returns the floor log base 2 of the specified value,
/// -1 if the value is zero. (64 bit edition.)
static inline unsigned Log2_64(uint64_t Value) {
return 63 - CountLeadingZeros_64(Value);
}
/// Log2_32_Ceil - This function returns the ceil log base 2 of the specified
/// value, 32 if the value is zero. (32 bit edition).
/// Ex. Log2_32_Ceil(32) == 5, Log2_32_Ceil(1) == 0, Log2_32_Ceil(6) == 3
static inline unsigned Log2_32_Ceil(uint32_t Value) {
return 32-CountLeadingZeros_32(Value-1);
}
/// Log2_64_Ceil - This function returns the ceil log base 2 of the specified
/// value, 64 if the value is zero. (64 bit edition.)
static inline unsigned Log2_64_Ceil(uint64_t Value) {
return 64-CountLeadingZeros_64(Value-1);
}
/// GreatestCommonDivisor64 - Return the greatest common divisor of the two
/// values using Euclid's algorithm.
static inline uint64_t GreatestCommonDivisor64(uint64_t A, uint64_t B) {
while (B) {
uint64_t T = B;
B = A % B;
A = T;
}
return A;
}
/// BitsToDouble - This function takes a 64-bit integer and returns the bit
/// equivalent double.
static inline double BitsToDouble(uint64_t Bits) {
union {
uint64_t L;
double D;
} T;
T.L = Bits;
return T.D;
}
/// BitsToFloat - This function takes a 32-bit integer and returns the bit
/// equivalent float.
static inline float BitsToFloat(uint32_t Bits) {
union {
uint32_t I;
float F;
} T;
T.I = Bits;
return T.F;
}
/// DoubleToBits - This function takes a double and returns the bit
/// equivalent 64-bit integer. Note that copying doubles around
/// changes the bits of NaNs on some hosts, notably x86, so this
/// routine cannot be used if these bits are needed.
static inline uint64_t DoubleToBits(double Double) {
union {
uint64_t L;
double D;
} T;
T.D = Double;
return T.L;
}
/// FloatToBits - This function takes a float and returns the bit
/// equivalent 32-bit integer. Note that copying floats around
/// changes the bits of NaNs on some hosts, notably x86, so this
/// routine cannot be used if these bits are needed.
static inline uint32_t FloatToBits(float Float) {
union {
uint32_t I;
float F;
} T;
T.F = Float;
return T.I;
}
/// MinAlign - A and B are either alignments or offsets. Return the minimum
/// alignment that may be assumed after adding the two together.
static inline uint64_t MinAlign(uint64_t A, uint64_t B) {
// The largest power of 2 that divides both A and B.
//
// Replace "-Value" by "1+~Value" in the following commented code to avoid
// MSVC warning C4146
// return (A | B) & -(A | B);
return (A | B) & (1 + ~(A | B));
}
/// NextPowerOf2 - Returns the next power of two (in 64-bits)
/// that is strictly greater than A. Returns zero on overflow.
static inline uint64_t NextPowerOf2(uint64_t A) {
A |= (A >> 1);
A |= (A >> 2);
A |= (A >> 4);
A |= (A >> 8);
A |= (A >> 16);
A |= (A >> 32);
return A + 1;
}
/// Returns the next integer (mod 2**64) that is greater than or equal to
/// \p Value and is a multiple of \p Align. \p Align must be non-zero.
///
/// Examples:
/// \code
/// RoundUpToAlignment(5, 8) = 8
/// RoundUpToAlignment(17, 8) = 24
/// RoundUpToAlignment(~0LL, 8) = 0
/// \endcode
static inline uint64_t RoundUpToAlignment(uint64_t Value, uint64_t Align) {
return ((Value + Align - 1) / Align) * Align;
}
/// Returns the offset to the next integer (mod 2**64) that is greater than
/// or equal to \p Value and is a multiple of \p Align. \p Align must be
/// non-zero.
static inline uint64_t OffsetToAlignment(uint64_t Value, uint64_t Align) {
return RoundUpToAlignment(Value, Align) - Value;
}
/// abs64 - absolute value of a 64-bit int. Not all environments support
/// "abs" on whatever their name for the 64-bit int type is. The absolute
/// value of the largest negative number is undefined, as with "abs".
static inline int64_t abs64(int64_t x) {
return (x < 0) ? -x : x;
}
/// \brief Sign extend number in the bottom B bits of X to a 32-bit int.
/// Requires 0 < B <= 32.
static inline int32_t SignExtend32(uint32_t X, unsigned B) {
return (int32_t)(X << (32 - B)) >> (32 - B);
}
/// \brief Sign extend number in the bottom B bits of X to a 64-bit int.
/// Requires 0 < B <= 64.
static inline int64_t SignExtend64(uint64_t X, unsigned B) {
return (int64_t)(X << (64 - B)) >> (64 - B);
}
/// \brief Count number of 0's from the most significant bit to the least
/// stopping at the first 1.
///
/// Only unsigned integral types are allowed.
///
/// \param ZB the behavior on an input of 0. Only ZB_Width and ZB_Undefined are
/// valid arguments.
static inline unsigned int countLeadingZeros(int x)
{
unsigned count = 0;
int i;
const unsigned bits = sizeof(x) * 8;
for (i = bits; --i; ) {
if (x < 0) break;
count++;
x <<= 1;
}
return count;
}
#endif

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Capstone is a disassembly framework with the target of becoming the ultimate
disasm engine for binary analysis and reversing in the security community.
Created by Nguyen Anh Quynh, then developed and maintained by a small community,
Capstone offers some unparalleled features:
- Support multiple hardware architectures: ARM, ARM64 (ARMv8), Mips, PPC, Sparc,
SystemZ, XCore and X86 (including X86_64).
- Having clean/simple/lightweight/intuitive architecture-neutral API.
- Provide details on disassembled instruction (called “decomposer” by others).
- Provide semantics of the disassembled instruction, such as list of implicit
registers read & written.
- Implemented in pure C language, with lightweight bindings for Haskell, Perl, Python,
Ruby, C#, NodeJS, Java, GO, C++, OCaml, Lua, Rust, Delphi, Free Pascal & Vala
ready either in main code, or provided externally by the community).
- Native support for all popular platforms: Windows, Mac OSX, iOS, Android,
Linux, *BSD, Solaris, etc.
- Thread-safe by design.
- Special support for embedding into firmware or OS kernel.
- High performance & suitable for malware analysis (capable of handling various
X86 malware tricks).
- Distributed under the open source BSD license.
Further information is available at http://www.capstone-engine.org
[Compile]
See COMPILE.TXT file for how to compile and install Capstone.
[Documentation]
See docs/README for how to customize & program your own tools with Capstone.
[Hack]
See HACK.TXT file for the structure of the source code.
[License]
This project is released under the BSD license. If you redistribute the binary
or source code of Capstone, please attach file LICENSE.TXT with your products.

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/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
#include <stdint.h>
#include <stdarg.h>
#if defined(CAPSTONE_HAS_OSXKERNEL)
#include <libkern/libkern.h>
#else
#include <stdio.h>
#endif
#include <string.h>
#include "SStream.h"
#include "cs_priv.h"
#include "myinttypes.h"
#include "utils.h"
#ifdef _MSC_VER
#pragma warning(disable: 4996) // disable MSVC's warning on strcpy()
#endif
void SStream_Init(SStream *ss)
{
ss->index = 0;
ss->buffer[0] = '\0';
}
void SStream_concat0(SStream *ss, char *s)
{
#ifndef CAPSTONE_DIET
unsigned int len = (unsigned int) strlen(s);
memcpy(ss->buffer + ss->index, s, len);
ss->index += len;
ss->buffer[ss->index] = '\0';
#endif
}
void SStream_concat(SStream *ss, const char *fmt, ...)
{
#ifndef CAPSTONE_DIET
va_list ap;
int ret;
va_start(ap, fmt);
ret = cs_vsnprintf(ss->buffer + ss->index, sizeof(ss->buffer) - (ss->index + 1), fmt, ap);
va_end(ap);
ss->index += ret;
#endif
}
// print number with prefix #
void printInt64Bang(SStream *O, int64_t val)
{
if (val >= 0) {
if (val > HEX_THRESHOLD)
SStream_concat(O, "#0x%"PRIx64, val);
else
SStream_concat(O, "#%"PRIu64, val);
} else {
if (val <- HEX_THRESHOLD)
SStream_concat(O, "#-0x%"PRIx64, -val);
else
SStream_concat(O, "#-%"PRIu64, -val);
}
}
void printUInt64Bang(SStream *O, uint64_t val)
{
if (val > HEX_THRESHOLD)
SStream_concat(O, "#0x%"PRIx64, val);
else
SStream_concat(O, "#%"PRIu64, val);
}
// print number
void printInt64(SStream *O, int64_t val)
{
if (val >= 0) {
if (val > HEX_THRESHOLD)
SStream_concat(O, "0x%"PRIx64, val);
else
SStream_concat(O, "%"PRIu64, val);
} else {
if (val <- HEX_THRESHOLD)
SStream_concat(O, "-0x%"PRIx64, -val);
else
SStream_concat(O, "-%"PRIu64, -val);
}
}
// print number in decimal mode
void printInt32BangDec(SStream *O, int32_t val)
{
if (val >= 0)
SStream_concat(O, "#%u", val);
else
SStream_concat(O, "#-%u", -val);
}
void printInt32Bang(SStream *O, int32_t val)
{
if (val >= 0) {
if (val > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", val);
else
SStream_concat(O, "#%u", val);
} else {
if (val <- HEX_THRESHOLD)
SStream_concat(O, "#-0x%x", -val);
else
SStream_concat(O, "#-%u", -val);
}
}
void printInt32(SStream *O, int32_t val)
{
if (val >= 0) {
if (val > HEX_THRESHOLD)
SStream_concat(O, "0x%x", val);
else
SStream_concat(O, "%u", val);
} else {
if (val <- HEX_THRESHOLD)
SStream_concat(O, "-0x%x", -val);
else
SStream_concat(O, "-%u", -val);
}
}
void printUInt32Bang(SStream *O, uint32_t val)
{
if (val > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", val);
else
SStream_concat(O, "#%u", val);
}
void printUInt32(SStream *O, uint32_t val)
{
if (val > HEX_THRESHOLD)
SStream_concat(O, "0x%x", val);
else
SStream_concat(O, "%u", val);
}
/*
int main()
{
SStream ss;
int64_t i;
SStream_Init(&ss);
SStream_concat(&ss, "hello ");
SStream_concat(&ss, "%d - 0x%x", 200, 16);
i = 123;
SStream_concat(&ss, " + %ld", i);
SStream_concat(&ss, "%s", "haaaaa");
printf("%s\n", ss.buffer);
return 0;
}
*/

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/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
#ifndef CS_SSTREAM_H_
#define CS_SSTREAM_H_
typedef struct SStream {
char buffer[512];
int index;
} SStream;
void SStream_Init(SStream *ss);
void SStream_concat(SStream *ss, const char *fmt, ...);
void SStream_concat0(SStream *ss, char *s);
void printInt64Bang(SStream *O, int64_t val);
void printUInt64Bang(SStream *O, uint64_t val);
void printInt64(SStream *O, int64_t val);
void printInt32Bang(SStream *O, int32_t val);
void printInt32(SStream *O, int32_t val);
void printUInt32Bang(SStream *O, uint32_t val);
void printUInt32(SStream *O, uint32_t val);
// print number in decimal mode
void printInt32BangDec(SStream *O, int32_t val);
#endif

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Issues to be solved in next versions
[Core]
- X86 can already handle all the malware tricks we are aware of. If you find
any such instruction sequence that Capstone disassembles wrongly or fails
completely, please report. Fixing this issue is always the top priority of
our project.
- More optimization for better performance.
[Bindings]
- OCaml binding is working, but still needs to support the core API better.

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//===- AArch64AddressingModes.h - AArch64 Addressing Modes ------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the AArch64 addressing mode implementation stuff.
//
//===----------------------------------------------------------------------===//
#ifndef CS_AARCH64_ADDRESSINGMODES_H
#define CS_AARCH64_ADDRESSINGMODES_H
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014 */
#include "../../MathExtras.h"
/// AArch64_AM - AArch64 Addressing Mode Stuff
//===----------------------------------------------------------------------===//
// Shifts
//
typedef enum AArch64_AM_ShiftExtendType {
AArch64_AM_InvalidShiftExtend = -1,
AArch64_AM_LSL = 0,
AArch64_AM_LSR,
AArch64_AM_ASR,
AArch64_AM_ROR,
AArch64_AM_MSL,
AArch64_AM_UXTB,
AArch64_AM_UXTH,
AArch64_AM_UXTW,
AArch64_AM_UXTX,
AArch64_AM_SXTB,
AArch64_AM_SXTH,
AArch64_AM_SXTW,
AArch64_AM_SXTX,
} AArch64_AM_ShiftExtendType;
/// getShiftName - Get the string encoding for the shift type.
static inline const char *AArch64_AM_getShiftExtendName(AArch64_AM_ShiftExtendType ST)
{
switch (ST) {
default: return NULL; // never reach
case AArch64_AM_LSL: return "lsl";
case AArch64_AM_LSR: return "lsr";
case AArch64_AM_ASR: return "asr";
case AArch64_AM_ROR: return "ror";
case AArch64_AM_MSL: return "msl";
case AArch64_AM_UXTB: return "uxtb";
case AArch64_AM_UXTH: return "uxth";
case AArch64_AM_UXTW: return "uxtw";
case AArch64_AM_UXTX: return "uxtx";
case AArch64_AM_SXTB: return "sxtb";
case AArch64_AM_SXTH: return "sxth";
case AArch64_AM_SXTW: return "sxtw";
case AArch64_AM_SXTX: return "sxtx";
}
}
/// getShiftType - Extract the shift type.
static inline AArch64_AM_ShiftExtendType AArch64_AM_getShiftType(unsigned Imm)
{
switch ((Imm >> 6) & 0x7) {
default: return AArch64_AM_InvalidShiftExtend;
case 0: return AArch64_AM_LSL;
case 1: return AArch64_AM_LSR;
case 2: return AArch64_AM_ASR;
case 3: return AArch64_AM_ROR;
case 4: return AArch64_AM_MSL;
}
}
/// getShiftValue - Extract the shift value.
static inline unsigned AArch64_AM_getShiftValue(unsigned Imm)
{
return Imm & 0x3f;
}
//===----------------------------------------------------------------------===//
// Extends
//
/// getArithShiftValue - get the arithmetic shift value.
static inline unsigned AArch64_AM_getArithShiftValue(unsigned Imm)
{
return Imm & 0x7;
}
/// getExtendType - Extract the extend type for operands of arithmetic ops.
static inline AArch64_AM_ShiftExtendType AArch64_AM_getExtendType(unsigned Imm)
{
// assert((Imm & 0x7) == Imm && "invalid immediate!");
switch (Imm) {
default: // llvm_unreachable("Compiler bug!");
case 0: return AArch64_AM_UXTB;
case 1: return AArch64_AM_UXTH;
case 2: return AArch64_AM_UXTW;
case 3: return AArch64_AM_UXTX;
case 4: return AArch64_AM_SXTB;
case 5: return AArch64_AM_SXTH;
case 6: return AArch64_AM_SXTW;
case 7: return AArch64_AM_SXTX;
}
}
static inline AArch64_AM_ShiftExtendType AArch64_AM_getArithExtendType(unsigned Imm)
{
return AArch64_AM_getExtendType((Imm >> 3) & 0x7);
}
static inline uint64_t ror(uint64_t elt, unsigned size)
{
return ((elt & 1) << (size-1)) | (elt >> 1);
}
/// decodeLogicalImmediate - Decode a logical immediate value in the form
/// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the
/// integer value it represents with regSize bits.
static inline uint64_t AArch64_AM_decodeLogicalImmediate(uint64_t val, unsigned regSize)
{
// Extract the N, imms, and immr fields.
unsigned N = (val >> 12) & 1;
unsigned immr = (val >> 6) & 0x3f;
unsigned imms = val & 0x3f;
unsigned i;
// assert((regSize == 64 || N == 0) && "undefined logical immediate encoding");
int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
// assert(len >= 0 && "undefined logical immediate encoding");
unsigned size = (1 << len);
unsigned R = immr & (size - 1);
unsigned S = imms & (size - 1);
// assert(S != size - 1 && "undefined logical immediate encoding");
uint64_t pattern = (1ULL << (S + 1)) - 1;
for (i = 0; i < R; ++i)
pattern = ror(pattern, size);
// Replicate the pattern to fill the regSize.
while (size != regSize) {
pattern |= (pattern << size);
size *= 2;
}
return pattern;
}
/// isValidDecodeLogicalImmediate - Check to see if the logical immediate value
/// in the form "N:immr:imms" (where the immr and imms fields are each 6 bits)
/// is a valid encoding for an integer value with regSize bits.
static inline bool AArch64_AM_isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize)
{
unsigned size;
unsigned S;
int len;
// Extract the N and imms fields needed for checking.
unsigned N = (val >> 12) & 1;
unsigned imms = val & 0x3f;
if (regSize == 32 && N != 0) // undefined logical immediate encoding
return false;
len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
if (len < 0) // undefined logical immediate encoding
return false;
size = (1 << len);
S = imms & (size - 1);
if (S == size - 1) // undefined logical immediate encoding
return false;
return true;
}
//===----------------------------------------------------------------------===//
// Floating-point Immediates
//
static inline float AArch64_AM_getFPImmFloat(unsigned Imm)
{
// We expect an 8-bit binary encoding of a floating-point number here.
union {
uint32_t I;
float F;
} FPUnion;
uint8_t Sign = (Imm >> 7) & 0x1;
uint8_t Exp = (Imm >> 4) & 0x7;
uint8_t Mantissa = Imm & 0xf;
// 8-bit FP iEEEE Float Encoding
// abcd efgh aBbbbbbc defgh000 00000000 00000000
//
// where B = NOT(b);
FPUnion.I = 0;
FPUnion.I |= Sign << 31;
FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
FPUnion.I |= (Exp & 0x3) << 23;
FPUnion.I |= Mantissa << 19;
return FPUnion.F;
}
//===--------------------------------------------------------------------===//
// AdvSIMD Modified Immediates
//===--------------------------------------------------------------------===//
static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType10(uint8_t Imm)
{
uint64_t EncVal = 0;
if (Imm & 0x80) EncVal |= 0xff00000000000000ULL;
if (Imm & 0x40) EncVal |= 0x00ff000000000000ULL;
if (Imm & 0x20) EncVal |= 0x0000ff0000000000ULL;
if (Imm & 0x10) EncVal |= 0x000000ff00000000ULL;
if (Imm & 0x08) EncVal |= 0x00000000ff000000ULL;
if (Imm & 0x04) EncVal |= 0x0000000000ff0000ULL;
if (Imm & 0x02) EncVal |= 0x000000000000ff00ULL;
if (Imm & 0x01) EncVal |= 0x00000000000000ffULL;
return EncVal;
}
#endif

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//===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file provides basic encoding and assembly information for AArch64.
//
//===----------------------------------------------------------------------===//
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
#ifdef CAPSTONE_HAS_ARM64
#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)
#pragma warning(disable:4996)
#endif
#include "../../utils.h"
#include <stdio.h>
#include <stdlib.h>
#include "AArch64BaseInfo.h"
char *A64NamedImmMapper_toString(A64NamedImmMapper *N, uint32_t Value, bool *Valid)
{
unsigned i;
for (i = 0; i < N->NumPairs; ++i) {
if (N->Pairs[i].Value == Value) {
*Valid = true;
return N->Pairs[i].Name;
}
}
*Valid = false;
return 0;
}
// compare s1 with lower(s2)
// return true if s1 == lower(f2), and false otherwise
static bool compare_lower_str(char *s1, char *s2)
{
bool res;
char *lower = cs_strdup(s2), *c;
for (c = lower; *c; c++)
*c = (char)tolower((int) *c);
res = (strcmp(s1, lower) == 0);
cs_mem_free(lower);
return res;
}
uint32_t A64NamedImmMapper_fromString(A64NamedImmMapper *N, char *Name, bool *Valid)
{
unsigned i;
for (i = 0; i < N->NumPairs; ++i) {
if (compare_lower_str(N->Pairs[i].Name, Name)) {
*Valid = true;
return N->Pairs[i].Value;
}
}
*Valid = false;
return (uint32_t)-1;
}
bool A64NamedImmMapper_validImm(A64NamedImmMapper *N, uint32_t Value)
{
return Value < N->TooBigImm;
}
// return a string representing the number X
// NOTE: caller must free() the result itself to avoid memory leak
static char *utostr(uint64_t X, bool isNeg)
{
char Buffer[22];
char *BufPtr = Buffer+21;
char *result;
Buffer[21] = '\0';
if (X == 0) *--BufPtr = '0'; // Handle special case...
while (X) {
*--BufPtr = X % 10 + '0';
X /= 10;
}
if (isNeg) *--BufPtr = '-'; // Add negative sign...
result = cs_strdup(BufPtr);
return result;
}
static A64NamedImmMapper_Mapping SysRegPairs[] = {
{"osdtrrx_el1", A64SysReg_OSDTRRX_EL1},
{"osdtrtx_el1", A64SysReg_OSDTRTX_EL1},
{"teecr32_el1", A64SysReg_TEECR32_EL1},
{"mdccint_el1", A64SysReg_MDCCINT_EL1},
{"mdscr_el1", A64SysReg_MDSCR_EL1},
{"dbgdtr_el0", A64SysReg_DBGDTR_EL0},
{"oseccr_el1", A64SysReg_OSECCR_EL1},
{"dbgvcr32_el2", A64SysReg_DBGVCR32_EL2},
{"dbgbvr0_el1", A64SysReg_DBGBVR0_EL1},
{"dbgbvr1_el1", A64SysReg_DBGBVR1_EL1},
{"dbgbvr2_el1", A64SysReg_DBGBVR2_EL1},
{"dbgbvr3_el1", A64SysReg_DBGBVR3_EL1},
{"dbgbvr4_el1", A64SysReg_DBGBVR4_EL1},
{"dbgbvr5_el1", A64SysReg_DBGBVR5_EL1},
{"dbgbvr6_el1", A64SysReg_DBGBVR6_EL1},
{"dbgbvr7_el1", A64SysReg_DBGBVR7_EL1},
{"dbgbvr8_el1", A64SysReg_DBGBVR8_EL1},
{"dbgbvr9_el1", A64SysReg_DBGBVR9_EL1},
{"dbgbvr10_el1", A64SysReg_DBGBVR10_EL1},
{"dbgbvr11_el1", A64SysReg_DBGBVR11_EL1},
{"dbgbvr12_el1", A64SysReg_DBGBVR12_EL1},
{"dbgbvr13_el1", A64SysReg_DBGBVR13_EL1},
{"dbgbvr14_el1", A64SysReg_DBGBVR14_EL1},
{"dbgbvr15_el1", A64SysReg_DBGBVR15_EL1},
{"dbgbcr0_el1", A64SysReg_DBGBCR0_EL1},
{"dbgbcr1_el1", A64SysReg_DBGBCR1_EL1},
{"dbgbcr2_el1", A64SysReg_DBGBCR2_EL1},
{"dbgbcr3_el1", A64SysReg_DBGBCR3_EL1},
{"dbgbcr4_el1", A64SysReg_DBGBCR4_EL1},
{"dbgbcr5_el1", A64SysReg_DBGBCR5_EL1},
{"dbgbcr6_el1", A64SysReg_DBGBCR6_EL1},
{"dbgbcr7_el1", A64SysReg_DBGBCR7_EL1},
{"dbgbcr8_el1", A64SysReg_DBGBCR8_EL1},
{"dbgbcr9_el1", A64SysReg_DBGBCR9_EL1},
{"dbgbcr10_el1", A64SysReg_DBGBCR10_EL1},
{"dbgbcr11_el1", A64SysReg_DBGBCR11_EL1},
{"dbgbcr12_el1", A64SysReg_DBGBCR12_EL1},
{"dbgbcr13_el1", A64SysReg_DBGBCR13_EL1},
{"dbgbcr14_el1", A64SysReg_DBGBCR14_EL1},
{"dbgbcr15_el1", A64SysReg_DBGBCR15_EL1},
{"dbgwvr0_el1", A64SysReg_DBGWVR0_EL1},
{"dbgwvr1_el1", A64SysReg_DBGWVR1_EL1},
{"dbgwvr2_el1", A64SysReg_DBGWVR2_EL1},
{"dbgwvr3_el1", A64SysReg_DBGWVR3_EL1},
{"dbgwvr4_el1", A64SysReg_DBGWVR4_EL1},
{"dbgwvr5_el1", A64SysReg_DBGWVR5_EL1},
{"dbgwvr6_el1", A64SysReg_DBGWVR6_EL1},
{"dbgwvr7_el1", A64SysReg_DBGWVR7_EL1},
{"dbgwvr8_el1", A64SysReg_DBGWVR8_EL1},
{"dbgwvr9_el1", A64SysReg_DBGWVR9_EL1},
{"dbgwvr10_el1", A64SysReg_DBGWVR10_EL1},
{"dbgwvr11_el1", A64SysReg_DBGWVR11_EL1},
{"dbgwvr12_el1", A64SysReg_DBGWVR12_EL1},
{"dbgwvr13_el1", A64SysReg_DBGWVR13_EL1},
{"dbgwvr14_el1", A64SysReg_DBGWVR14_EL1},
{"dbgwvr15_el1", A64SysReg_DBGWVR15_EL1},
{"dbgwcr0_el1", A64SysReg_DBGWCR0_EL1},
{"dbgwcr1_el1", A64SysReg_DBGWCR1_EL1},
{"dbgwcr2_el1", A64SysReg_DBGWCR2_EL1},
{"dbgwcr3_el1", A64SysReg_DBGWCR3_EL1},
{"dbgwcr4_el1", A64SysReg_DBGWCR4_EL1},
{"dbgwcr5_el1", A64SysReg_DBGWCR5_EL1},
{"dbgwcr6_el1", A64SysReg_DBGWCR6_EL1},
{"dbgwcr7_el1", A64SysReg_DBGWCR7_EL1},
{"dbgwcr8_el1", A64SysReg_DBGWCR8_EL1},
{"dbgwcr9_el1", A64SysReg_DBGWCR9_EL1},
{"dbgwcr10_el1", A64SysReg_DBGWCR10_EL1},
{"dbgwcr11_el1", A64SysReg_DBGWCR11_EL1},
{"dbgwcr12_el1", A64SysReg_DBGWCR12_EL1},
{"dbgwcr13_el1", A64SysReg_DBGWCR13_EL1},
{"dbgwcr14_el1", A64SysReg_DBGWCR14_EL1},
{"dbgwcr15_el1", A64SysReg_DBGWCR15_EL1},
{"teehbr32_el1", A64SysReg_TEEHBR32_EL1},
{"osdlr_el1", A64SysReg_OSDLR_EL1},
{"dbgprcr_el1", A64SysReg_DBGPRCR_EL1},
{"dbgclaimset_el1", A64SysReg_DBGCLAIMSET_EL1},
{"dbgclaimclr_el1", A64SysReg_DBGCLAIMCLR_EL1},
{"csselr_el1", A64SysReg_CSSELR_EL1},
{"vpidr_el2", A64SysReg_VPIDR_EL2},
{"vmpidr_el2", A64SysReg_VMPIDR_EL2},
{"sctlr_el1", A64SysReg_SCTLR_EL1},
{"sctlr_el2", A64SysReg_SCTLR_EL2},
{"sctlr_el3", A64SysReg_SCTLR_EL3},
{"actlr_el1", A64SysReg_ACTLR_EL1},
{"actlr_el2", A64SysReg_ACTLR_EL2},
{"actlr_el3", A64SysReg_ACTLR_EL3},
{"cpacr_el1", A64SysReg_CPACR_EL1},
{"hcr_el2", A64SysReg_HCR_EL2},
{"scr_el3", A64SysReg_SCR_EL3},
{"mdcr_el2", A64SysReg_MDCR_EL2},
{"sder32_el3", A64SysReg_SDER32_EL3},
{"cptr_el2", A64SysReg_CPTR_EL2},
{"cptr_el3", A64SysReg_CPTR_EL3},
{"hstr_el2", A64SysReg_HSTR_EL2},
{"hacr_el2", A64SysReg_HACR_EL2},
{"mdcr_el3", A64SysReg_MDCR_EL3},
{"ttbr0_el1", A64SysReg_TTBR0_EL1},
{"ttbr0_el2", A64SysReg_TTBR0_EL2},
{"ttbr0_el3", A64SysReg_TTBR0_EL3},
{"ttbr1_el1", A64SysReg_TTBR1_EL1},
{"tcr_el1", A64SysReg_TCR_EL1},
{"tcr_el2", A64SysReg_TCR_EL2},
{"tcr_el3", A64SysReg_TCR_EL3},
{"vttbr_el2", A64SysReg_VTTBR_EL2},
{"vtcr_el2", A64SysReg_VTCR_EL2},
{"dacr32_el2", A64SysReg_DACR32_EL2},
{"spsr_el1", A64SysReg_SPSR_EL1},
{"spsr_el2", A64SysReg_SPSR_EL2},
{"spsr_el3", A64SysReg_SPSR_EL3},
{"elr_el1", A64SysReg_ELR_EL1},
{"elr_el2", A64SysReg_ELR_EL2},
{"elr_el3", A64SysReg_ELR_EL3},
{"sp_el0", A64SysReg_SP_EL0},
{"sp_el1", A64SysReg_SP_EL1},
{"sp_el2", A64SysReg_SP_EL2},
{"spsel", A64SysReg_SPSel},
{"nzcv", A64SysReg_NZCV},
{"daif", A64SysReg_DAIF},
{"currentel", A64SysReg_CurrentEL},
{"spsr_irq", A64SysReg_SPSR_irq},
{"spsr_abt", A64SysReg_SPSR_abt},
{"spsr_und", A64SysReg_SPSR_und},
{"spsr_fiq", A64SysReg_SPSR_fiq},
{"fpcr", A64SysReg_FPCR},
{"fpsr", A64SysReg_FPSR},
{"dspsr_el0", A64SysReg_DSPSR_EL0},
{"dlr_el0", A64SysReg_DLR_EL0},
{"ifsr32_el2", A64SysReg_IFSR32_EL2},
{"afsr0_el1", A64SysReg_AFSR0_EL1},
{"afsr0_el2", A64SysReg_AFSR0_EL2},
{"afsr0_el3", A64SysReg_AFSR0_EL3},
{"afsr1_el1", A64SysReg_AFSR1_EL1},
{"afsr1_el2", A64SysReg_AFSR1_EL2},
{"afsr1_el3", A64SysReg_AFSR1_EL3},
{"esr_el1", A64SysReg_ESR_EL1},
{"esr_el2", A64SysReg_ESR_EL2},
{"esr_el3", A64SysReg_ESR_EL3},
{"fpexc32_el2", A64SysReg_FPEXC32_EL2},
{"far_el1", A64SysReg_FAR_EL1},
{"far_el2", A64SysReg_FAR_EL2},
{"far_el3", A64SysReg_FAR_EL3},
{"hpfar_el2", A64SysReg_HPFAR_EL2},
{"par_el1", A64SysReg_PAR_EL1},
{"pmcr_el0", A64SysReg_PMCR_EL0},
{"pmcntenset_el0", A64SysReg_PMCNTENSET_EL0},
{"pmcntenclr_el0", A64SysReg_PMCNTENCLR_EL0},
{"pmovsclr_el0", A64SysReg_PMOVSCLR_EL0},
{"pmselr_el0", A64SysReg_PMSELR_EL0},
{"pmccntr_el0", A64SysReg_PMCCNTR_EL0},
{"pmxevtyper_el0", A64SysReg_PMXEVTYPER_EL0},
{"pmxevcntr_el0", A64SysReg_PMXEVCNTR_EL0},
{"pmuserenr_el0", A64SysReg_PMUSERENR_EL0},
{"pmintenset_el1", A64SysReg_PMINTENSET_EL1},
{"pmintenclr_el1", A64SysReg_PMINTENCLR_EL1},
{"pmovsset_el0", A64SysReg_PMOVSSET_EL0},
{"mair_el1", A64SysReg_MAIR_EL1},
{"mair_el2", A64SysReg_MAIR_EL2},
{"mair_el3", A64SysReg_MAIR_EL3},
{"amair_el1", A64SysReg_AMAIR_EL1},
{"amair_el2", A64SysReg_AMAIR_EL2},
{"amair_el3", A64SysReg_AMAIR_EL3},
{"vbar_el1", A64SysReg_VBAR_EL1},
{"vbar_el2", A64SysReg_VBAR_EL2},
{"vbar_el3", A64SysReg_VBAR_EL3},
{"rmr_el1", A64SysReg_RMR_EL1},
{"rmr_el2", A64SysReg_RMR_EL2},
{"rmr_el3", A64SysReg_RMR_EL3},
{"contextidr_el1", A64SysReg_CONTEXTIDR_EL1},
{"tpidr_el0", A64SysReg_TPIDR_EL0},
{"tpidr_el2", A64SysReg_TPIDR_EL2},
{"tpidr_el3", A64SysReg_TPIDR_EL3},
{"tpidrro_el0", A64SysReg_TPIDRRO_EL0},
{"tpidr_el1", A64SysReg_TPIDR_EL1},
{"cntfrq_el0", A64SysReg_CNTFRQ_EL0},
{"cntvoff_el2", A64SysReg_CNTVOFF_EL2},
{"cntkctl_el1", A64SysReg_CNTKCTL_EL1},
{"cnthctl_el2", A64SysReg_CNTHCTL_EL2},
{"cntp_tval_el0", A64SysReg_CNTP_TVAL_EL0},
{"cnthp_tval_el2", A64SysReg_CNTHP_TVAL_EL2},
{"cntps_tval_el1", A64SysReg_CNTPS_TVAL_EL1},
{"cntp_ctl_el0", A64SysReg_CNTP_CTL_EL0},
{"cnthp_ctl_el2", A64SysReg_CNTHP_CTL_EL2},
{"cntps_ctl_el1", A64SysReg_CNTPS_CTL_EL1},
{"cntp_cval_el0", A64SysReg_CNTP_CVAL_EL0},
{"cnthp_cval_el2", A64SysReg_CNTHP_CVAL_EL2},
{"cntps_cval_el1", A64SysReg_CNTPS_CVAL_EL1},
{"cntv_tval_el0", A64SysReg_CNTV_TVAL_EL0},
{"cntv_ctl_el0", A64SysReg_CNTV_CTL_EL0},
{"cntv_cval_el0", A64SysReg_CNTV_CVAL_EL0},
{"pmevcntr0_el0", A64SysReg_PMEVCNTR0_EL0},
{"pmevcntr1_el0", A64SysReg_PMEVCNTR1_EL0},
{"pmevcntr2_el0", A64SysReg_PMEVCNTR2_EL0},
{"pmevcntr3_el0", A64SysReg_PMEVCNTR3_EL0},
{"pmevcntr4_el0", A64SysReg_PMEVCNTR4_EL0},
{"pmevcntr5_el0", A64SysReg_PMEVCNTR5_EL0},
{"pmevcntr6_el0", A64SysReg_PMEVCNTR6_EL0},
{"pmevcntr7_el0", A64SysReg_PMEVCNTR7_EL0},
{"pmevcntr8_el0", A64SysReg_PMEVCNTR8_EL0},
{"pmevcntr9_el0", A64SysReg_PMEVCNTR9_EL0},
{"pmevcntr10_el0", A64SysReg_PMEVCNTR10_EL0},
{"pmevcntr11_el0", A64SysReg_PMEVCNTR11_EL0},
{"pmevcntr12_el0", A64SysReg_PMEVCNTR12_EL0},
{"pmevcntr13_el0", A64SysReg_PMEVCNTR13_EL0},
{"pmevcntr14_el0", A64SysReg_PMEVCNTR14_EL0},
{"pmevcntr15_el0", A64SysReg_PMEVCNTR15_EL0},
{"pmevcntr16_el0", A64SysReg_PMEVCNTR16_EL0},
{"pmevcntr17_el0", A64SysReg_PMEVCNTR17_EL0},
{"pmevcntr18_el0", A64SysReg_PMEVCNTR18_EL0},
{"pmevcntr19_el0", A64SysReg_PMEVCNTR19_EL0},
{"pmevcntr20_el0", A64SysReg_PMEVCNTR20_EL0},
{"pmevcntr21_el0", A64SysReg_PMEVCNTR21_EL0},
{"pmevcntr22_el0", A64SysReg_PMEVCNTR22_EL0},
{"pmevcntr23_el0", A64SysReg_PMEVCNTR23_EL0},
{"pmevcntr24_el0", A64SysReg_PMEVCNTR24_EL0},
{"pmevcntr25_el0", A64SysReg_PMEVCNTR25_EL0},
{"pmevcntr26_el0", A64SysReg_PMEVCNTR26_EL0},
{"pmevcntr27_el0", A64SysReg_PMEVCNTR27_EL0},
{"pmevcntr28_el0", A64SysReg_PMEVCNTR28_EL0},
{"pmevcntr29_el0", A64SysReg_PMEVCNTR29_EL0},
{"pmevcntr30_el0", A64SysReg_PMEVCNTR30_EL0},
{"pmccfiltr_el0", A64SysReg_PMCCFILTR_EL0},
{"pmevtyper0_el0", A64SysReg_PMEVTYPER0_EL0},
{"pmevtyper1_el0", A64SysReg_PMEVTYPER1_EL0},
{"pmevtyper2_el0", A64SysReg_PMEVTYPER2_EL0},
{"pmevtyper3_el0", A64SysReg_PMEVTYPER3_EL0},
{"pmevtyper4_el0", A64SysReg_PMEVTYPER4_EL0},
{"pmevtyper5_el0", A64SysReg_PMEVTYPER5_EL0},
{"pmevtyper6_el0", A64SysReg_PMEVTYPER6_EL0},
{"pmevtyper7_el0", A64SysReg_PMEVTYPER7_EL0},
{"pmevtyper8_el0", A64SysReg_PMEVTYPER8_EL0},
{"pmevtyper9_el0", A64SysReg_PMEVTYPER9_EL0},
{"pmevtyper10_el0", A64SysReg_PMEVTYPER10_EL0},
{"pmevtyper11_el0", A64SysReg_PMEVTYPER11_EL0},
{"pmevtyper12_el0", A64SysReg_PMEVTYPER12_EL0},
{"pmevtyper13_el0", A64SysReg_PMEVTYPER13_EL0},
{"pmevtyper14_el0", A64SysReg_PMEVTYPER14_EL0},
{"pmevtyper15_el0", A64SysReg_PMEVTYPER15_EL0},
{"pmevtyper16_el0", A64SysReg_PMEVTYPER16_EL0},
{"pmevtyper17_el0", A64SysReg_PMEVTYPER17_EL0},
{"pmevtyper18_el0", A64SysReg_PMEVTYPER18_EL0},
{"pmevtyper19_el0", A64SysReg_PMEVTYPER19_EL0},
{"pmevtyper20_el0", A64SysReg_PMEVTYPER20_EL0},
{"pmevtyper21_el0", A64SysReg_PMEVTYPER21_EL0},
{"pmevtyper22_el0", A64SysReg_PMEVTYPER22_EL0},
{"pmevtyper23_el0", A64SysReg_PMEVTYPER23_EL0},
{"pmevtyper24_el0", A64SysReg_PMEVTYPER24_EL0},
{"pmevtyper25_el0", A64SysReg_PMEVTYPER25_EL0},
{"pmevtyper26_el0", A64SysReg_PMEVTYPER26_EL0},
{"pmevtyper27_el0", A64SysReg_PMEVTYPER27_EL0},
{"pmevtyper28_el0", A64SysReg_PMEVTYPER28_EL0},
{"pmevtyper29_el0", A64SysReg_PMEVTYPER29_EL0},
{"pmevtyper30_el0", A64SysReg_PMEVTYPER30_EL0},
// Trace registers
{"trcprgctlr", A64SysReg_TRCPRGCTLR},
{"trcprocselr", A64SysReg_TRCPROCSELR},
{"trcconfigr", A64SysReg_TRCCONFIGR},
{"trcauxctlr", A64SysReg_TRCAUXCTLR},
{"trceventctl0r", A64SysReg_TRCEVENTCTL0R},
{"trceventctl1r", A64SysReg_TRCEVENTCTL1R},
{"trcstallctlr", A64SysReg_TRCSTALLCTLR},
{"trctsctlr", A64SysReg_TRCTSCTLR},
{"trcsyncpr", A64SysReg_TRCSYNCPR},
{"trcccctlr", A64SysReg_TRCCCCTLR},
{"trcbbctlr", A64SysReg_TRCBBCTLR},
{"trctraceidr", A64SysReg_TRCTRACEIDR},
{"trcqctlr", A64SysReg_TRCQCTLR},
{"trcvictlr", A64SysReg_TRCVICTLR},
{"trcviiectlr", A64SysReg_TRCVIIECTLR},
{"trcvissctlr", A64SysReg_TRCVISSCTLR},
{"trcvipcssctlr", A64SysReg_TRCVIPCSSCTLR},
{"trcvdctlr", A64SysReg_TRCVDCTLR},
{"trcvdsacctlr", A64SysReg_TRCVDSACCTLR},
{"trcvdarcctlr", A64SysReg_TRCVDARCCTLR},
{"trcseqevr0", A64SysReg_TRCSEQEVR0},
{"trcseqevr1", A64SysReg_TRCSEQEVR1},
{"trcseqevr2", A64SysReg_TRCSEQEVR2},
{"trcseqrstevr", A64SysReg_TRCSEQRSTEVR},
{"trcseqstr", A64SysReg_TRCSEQSTR},
{"trcextinselr", A64SysReg_TRCEXTINSELR},
{"trccntrldvr0", A64SysReg_TRCCNTRLDVR0},
{"trccntrldvr1", A64SysReg_TRCCNTRLDVR1},
{"trccntrldvr2", A64SysReg_TRCCNTRLDVR2},
{"trccntrldvr3", A64SysReg_TRCCNTRLDVR3},
{"trccntctlr0", A64SysReg_TRCCNTCTLR0},
{"trccntctlr1", A64SysReg_TRCCNTCTLR1},
{"trccntctlr2", A64SysReg_TRCCNTCTLR2},
{"trccntctlr3", A64SysReg_TRCCNTCTLR3},
{"trccntvr0", A64SysReg_TRCCNTVR0},
{"trccntvr1", A64SysReg_TRCCNTVR1},
{"trccntvr2", A64SysReg_TRCCNTVR2},
{"trccntvr3", A64SysReg_TRCCNTVR3},
{"trcimspec0", A64SysReg_TRCIMSPEC0},
{"trcimspec1", A64SysReg_TRCIMSPEC1},
{"trcimspec2", A64SysReg_TRCIMSPEC2},
{"trcimspec3", A64SysReg_TRCIMSPEC3},
{"trcimspec4", A64SysReg_TRCIMSPEC4},
{"trcimspec5", A64SysReg_TRCIMSPEC5},
{"trcimspec6", A64SysReg_TRCIMSPEC6},
{"trcimspec7", A64SysReg_TRCIMSPEC7},
{"trcrsctlr2", A64SysReg_TRCRSCTLR2},
{"trcrsctlr3", A64SysReg_TRCRSCTLR3},
{"trcrsctlr4", A64SysReg_TRCRSCTLR4},
{"trcrsctlr5", A64SysReg_TRCRSCTLR5},
{"trcrsctlr6", A64SysReg_TRCRSCTLR6},
{"trcrsctlr7", A64SysReg_TRCRSCTLR7},
{"trcrsctlr8", A64SysReg_TRCRSCTLR8},
{"trcrsctlr9", A64SysReg_TRCRSCTLR9},
{"trcrsctlr10", A64SysReg_TRCRSCTLR10},
{"trcrsctlr11", A64SysReg_TRCRSCTLR11},
{"trcrsctlr12", A64SysReg_TRCRSCTLR12},
{"trcrsctlr13", A64SysReg_TRCRSCTLR13},
{"trcrsctlr14", A64SysReg_TRCRSCTLR14},
{"trcrsctlr15", A64SysReg_TRCRSCTLR15},
{"trcrsctlr16", A64SysReg_TRCRSCTLR16},
{"trcrsctlr17", A64SysReg_TRCRSCTLR17},
{"trcrsctlr18", A64SysReg_TRCRSCTLR18},
{"trcrsctlr19", A64SysReg_TRCRSCTLR19},
{"trcrsctlr20", A64SysReg_TRCRSCTLR20},
{"trcrsctlr21", A64SysReg_TRCRSCTLR21},
{"trcrsctlr22", A64SysReg_TRCRSCTLR22},
{"trcrsctlr23", A64SysReg_TRCRSCTLR23},
{"trcrsctlr24", A64SysReg_TRCRSCTLR24},
{"trcrsctlr25", A64SysReg_TRCRSCTLR25},
{"trcrsctlr26", A64SysReg_TRCRSCTLR26},
{"trcrsctlr27", A64SysReg_TRCRSCTLR27},
{"trcrsctlr28", A64SysReg_TRCRSCTLR28},
{"trcrsctlr29", A64SysReg_TRCRSCTLR29},
{"trcrsctlr30", A64SysReg_TRCRSCTLR30},
{"trcrsctlr31", A64SysReg_TRCRSCTLR31},
{"trcssccr0", A64SysReg_TRCSSCCR0},
{"trcssccr1", A64SysReg_TRCSSCCR1},
{"trcssccr2", A64SysReg_TRCSSCCR2},
{"trcssccr3", A64SysReg_TRCSSCCR3},
{"trcssccr4", A64SysReg_TRCSSCCR4},
{"trcssccr5", A64SysReg_TRCSSCCR5},
{"trcssccr6", A64SysReg_TRCSSCCR6},
{"trcssccr7", A64SysReg_TRCSSCCR7},
{"trcsscsr0", A64SysReg_TRCSSCSR0},
{"trcsscsr1", A64SysReg_TRCSSCSR1},
{"trcsscsr2", A64SysReg_TRCSSCSR2},
{"trcsscsr3", A64SysReg_TRCSSCSR3},
{"trcsscsr4", A64SysReg_TRCSSCSR4},
{"trcsscsr5", A64SysReg_TRCSSCSR5},
{"trcsscsr6", A64SysReg_TRCSSCSR6},
{"trcsscsr7", A64SysReg_TRCSSCSR7},
{"trcsspcicr0", A64SysReg_TRCSSPCICR0},
{"trcsspcicr1", A64SysReg_TRCSSPCICR1},
{"trcsspcicr2", A64SysReg_TRCSSPCICR2},
{"trcsspcicr3", A64SysReg_TRCSSPCICR3},
{"trcsspcicr4", A64SysReg_TRCSSPCICR4},
{"trcsspcicr5", A64SysReg_TRCSSPCICR5},
{"trcsspcicr6", A64SysReg_TRCSSPCICR6},
{"trcsspcicr7", A64SysReg_TRCSSPCICR7},
{"trcpdcr", A64SysReg_TRCPDCR},
{"trcacvr0", A64SysReg_TRCACVR0},
{"trcacvr1", A64SysReg_TRCACVR1},
{"trcacvr2", A64SysReg_TRCACVR2},
{"trcacvr3", A64SysReg_TRCACVR3},
{"trcacvr4", A64SysReg_TRCACVR4},
{"trcacvr5", A64SysReg_TRCACVR5},
{"trcacvr6", A64SysReg_TRCACVR6},
{"trcacvr7", A64SysReg_TRCACVR7},
{"trcacvr8", A64SysReg_TRCACVR8},
{"trcacvr9", A64SysReg_TRCACVR9},
{"trcacvr10", A64SysReg_TRCACVR10},
{"trcacvr11", A64SysReg_TRCACVR11},
{"trcacvr12", A64SysReg_TRCACVR12},
{"trcacvr13", A64SysReg_TRCACVR13},
{"trcacvr14", A64SysReg_TRCACVR14},
{"trcacvr15", A64SysReg_TRCACVR15},
{"trcacatr0", A64SysReg_TRCACATR0},
{"trcacatr1", A64SysReg_TRCACATR1},
{"trcacatr2", A64SysReg_TRCACATR2},
{"trcacatr3", A64SysReg_TRCACATR3},
{"trcacatr4", A64SysReg_TRCACATR4},
{"trcacatr5", A64SysReg_TRCACATR5},
{"trcacatr6", A64SysReg_TRCACATR6},
{"trcacatr7", A64SysReg_TRCACATR7},
{"trcacatr8", A64SysReg_TRCACATR8},
{"trcacatr9", A64SysReg_TRCACATR9},
{"trcacatr10", A64SysReg_TRCACATR10},
{"trcacatr11", A64SysReg_TRCACATR11},
{"trcacatr12", A64SysReg_TRCACATR12},
{"trcacatr13", A64SysReg_TRCACATR13},
{"trcacatr14", A64SysReg_TRCACATR14},
{"trcacatr15", A64SysReg_TRCACATR15},
{"trcdvcvr0", A64SysReg_TRCDVCVR0},
{"trcdvcvr1", A64SysReg_TRCDVCVR1},
{"trcdvcvr2", A64SysReg_TRCDVCVR2},
{"trcdvcvr3", A64SysReg_TRCDVCVR3},
{"trcdvcvr4", A64SysReg_TRCDVCVR4},
{"trcdvcvr5", A64SysReg_TRCDVCVR5},
{"trcdvcvr6", A64SysReg_TRCDVCVR6},
{"trcdvcvr7", A64SysReg_TRCDVCVR7},
{"trcdvcmr0", A64SysReg_TRCDVCMR0},
{"trcdvcmr1", A64SysReg_TRCDVCMR1},
{"trcdvcmr2", A64SysReg_TRCDVCMR2},
{"trcdvcmr3", A64SysReg_TRCDVCMR3},
{"trcdvcmr4", A64SysReg_TRCDVCMR4},
{"trcdvcmr5", A64SysReg_TRCDVCMR5},
{"trcdvcmr6", A64SysReg_TRCDVCMR6},
{"trcdvcmr7", A64SysReg_TRCDVCMR7},
{"trccidcvr0", A64SysReg_TRCCIDCVR0},
{"trccidcvr1", A64SysReg_TRCCIDCVR1},
{"trccidcvr2", A64SysReg_TRCCIDCVR2},
{"trccidcvr3", A64SysReg_TRCCIDCVR3},
{"trccidcvr4", A64SysReg_TRCCIDCVR4},
{"trccidcvr5", A64SysReg_TRCCIDCVR5},
{"trccidcvr6", A64SysReg_TRCCIDCVR6},
{"trccidcvr7", A64SysReg_TRCCIDCVR7},
{"trcvmidcvr0", A64SysReg_TRCVMIDCVR0},
{"trcvmidcvr1", A64SysReg_TRCVMIDCVR1},
{"trcvmidcvr2", A64SysReg_TRCVMIDCVR2},
{"trcvmidcvr3", A64SysReg_TRCVMIDCVR3},
{"trcvmidcvr4", A64SysReg_TRCVMIDCVR4},
{"trcvmidcvr5", A64SysReg_TRCVMIDCVR5},
{"trcvmidcvr6", A64SysReg_TRCVMIDCVR6},
{"trcvmidcvr7", A64SysReg_TRCVMIDCVR7},
{"trccidcctlr0", A64SysReg_TRCCIDCCTLR0},
{"trccidcctlr1", A64SysReg_TRCCIDCCTLR1},
{"trcvmidcctlr0", A64SysReg_TRCVMIDCCTLR0},
{"trcvmidcctlr1", A64SysReg_TRCVMIDCCTLR1},
{"trcitctrl", A64SysReg_TRCITCTRL},
{"trcclaimset", A64SysReg_TRCCLAIMSET},
{"trcclaimclr", A64SysReg_TRCCLAIMCLR},
// GICv3 registers
{"icc_bpr1_el1", A64SysReg_ICC_BPR1_EL1},
{"icc_bpr0_el1", A64SysReg_ICC_BPR0_EL1},
{"icc_pmr_el1", A64SysReg_ICC_PMR_EL1},
{"icc_ctlr_el1", A64SysReg_ICC_CTLR_EL1},
{"icc_ctlr_el3", A64SysReg_ICC_CTLR_EL3},
{"icc_sre_el1", A64SysReg_ICC_SRE_EL1},
{"icc_sre_el2", A64SysReg_ICC_SRE_EL2},
{"icc_sre_el3", A64SysReg_ICC_SRE_EL3},
{"icc_igrpen0_el1", A64SysReg_ICC_IGRPEN0_EL1},
{"icc_igrpen1_el1", A64SysReg_ICC_IGRPEN1_EL1},
{"icc_igrpen1_el3", A64SysReg_ICC_IGRPEN1_EL3},
{"icc_seien_el1", A64SysReg_ICC_SEIEN_EL1},
{"icc_ap0r0_el1", A64SysReg_ICC_AP0R0_EL1},
{"icc_ap0r1_el1", A64SysReg_ICC_AP0R1_EL1},
{"icc_ap0r2_el1", A64SysReg_ICC_AP0R2_EL1},
{"icc_ap0r3_el1", A64SysReg_ICC_AP0R3_EL1},
{"icc_ap1r0_el1", A64SysReg_ICC_AP1R0_EL1},
{"icc_ap1r1_el1", A64SysReg_ICC_AP1R1_EL1},
{"icc_ap1r2_el1", A64SysReg_ICC_AP1R2_EL1},
{"icc_ap1r3_el1", A64SysReg_ICC_AP1R3_EL1},
{"ich_ap0r0_el2", A64SysReg_ICH_AP0R0_EL2},
{"ich_ap0r1_el2", A64SysReg_ICH_AP0R1_EL2},
{"ich_ap0r2_el2", A64SysReg_ICH_AP0R2_EL2},
{"ich_ap0r3_el2", A64SysReg_ICH_AP0R3_EL2},
{"ich_ap1r0_el2", A64SysReg_ICH_AP1R0_EL2},
{"ich_ap1r1_el2", A64SysReg_ICH_AP1R1_EL2},
{"ich_ap1r2_el2", A64SysReg_ICH_AP1R2_EL2},
{"ich_ap1r3_el2", A64SysReg_ICH_AP1R3_EL2},
{"ich_hcr_el2", A64SysReg_ICH_HCR_EL2},
{"ich_misr_el2", A64SysReg_ICH_MISR_EL2},
{"ich_vmcr_el2", A64SysReg_ICH_VMCR_EL2},
{"ich_vseir_el2", A64SysReg_ICH_VSEIR_EL2},
{"ich_lr0_el2", A64SysReg_ICH_LR0_EL2},
{"ich_lr1_el2", A64SysReg_ICH_LR1_EL2},
{"ich_lr2_el2", A64SysReg_ICH_LR2_EL2},
{"ich_lr3_el2", A64SysReg_ICH_LR3_EL2},
{"ich_lr4_el2", A64SysReg_ICH_LR4_EL2},
{"ich_lr5_el2", A64SysReg_ICH_LR5_EL2},
{"ich_lr6_el2", A64SysReg_ICH_LR6_EL2},
{"ich_lr7_el2", A64SysReg_ICH_LR7_EL2},
{"ich_lr8_el2", A64SysReg_ICH_LR8_EL2},
{"ich_lr9_el2", A64SysReg_ICH_LR9_EL2},
{"ich_lr10_el2", A64SysReg_ICH_LR10_EL2},
{"ich_lr11_el2", A64SysReg_ICH_LR11_EL2},
{"ich_lr12_el2", A64SysReg_ICH_LR12_EL2},
{"ich_lr13_el2", A64SysReg_ICH_LR13_EL2},
{"ich_lr14_el2", A64SysReg_ICH_LR14_EL2},
{"ich_lr15_el2", A64SysReg_ICH_LR15_EL2}
};
static A64NamedImmMapper_Mapping CycloneSysRegPairs[] = {
{"cpm_ioacc_ctl_el3", A64SysReg_CPM_IOACC_CTL_EL3}
};
// result must be a big enough buffer: 128 bytes is more than enough
void A64SysRegMapper_toString(A64SysRegMapper *S, uint32_t Bits, bool *Valid, char *result)
{
int dummy;
uint32_t Op0, Op1, CRn, CRm, Op2;
char *Op1S, *CRnS, *CRmS, *Op2S;
unsigned i;
// First search the registers shared by all
for (i = 0; i < ARR_SIZE(SysRegPairs); ++i) {
if (SysRegPairs[i].Value == Bits) {
*Valid = true;
strcpy(result, SysRegPairs[i].Name);
return;
}
}
// Next search for target specific registers
// if (FeatureBits & AArch64_ProcCyclone) {
if (true) {
for (i = 0; i < ARR_SIZE(CycloneSysRegPairs); ++i) {
if (CycloneSysRegPairs[i].Value == Bits) {
*Valid = true;
strcpy(result, CycloneSysRegPairs[i].Name);
return;
}
}
}
// Now try the instruction-specific registers (either read-only or
// write-only).
for (i = 0; i < S->NumInstPairs; ++i) {
if (S->InstPairs[i].Value == Bits) {
*Valid = true;
strcpy(result, S->InstPairs[i].Name);
return;
}
}
Op0 = (Bits >> 14) & 0x3;
Op1 = (Bits >> 11) & 0x7;
CRn = (Bits >> 7) & 0xf;
CRm = (Bits >> 3) & 0xf;
Op2 = Bits & 0x7;
// Only combinations matching: 11 xxx 1x11 xxxx xxx are valid for a generic
// name.
if (Op0 != 3 || (CRn != 11 && CRn != 15)) {
*Valid = false;
return;
}
//assert(Op0 == 3 && (CRn == 11 || CRn == 15) && "Invalid generic sysreg");
*Valid = true;
Op1S = utostr(Op1, false);
CRnS = utostr(CRn, false);
CRmS = utostr(CRm, false);
Op2S = utostr(Op2, false);
//printf("Op1S: %s, CRnS: %s, CRmS: %s, Op2S: %s\n", Op1S, CRnS, CRmS, Op2S);
dummy = cs_snprintf(result, 128, "s3_%s_c%s_c%s_%s", Op1S, CRnS, CRmS, Op2S);
(void)dummy;
cs_mem_free(Op1S);
cs_mem_free(CRnS);
cs_mem_free(CRmS);
cs_mem_free(Op2S);
}
static A64NamedImmMapper_Mapping TLBIPairs[] = {
{"ipas2e1is", A64TLBI_IPAS2E1IS},
{"ipas2le1is", A64TLBI_IPAS2LE1IS},
{"vmalle1is", A64TLBI_VMALLE1IS},
{"alle2is", A64TLBI_ALLE2IS},
{"alle3is", A64TLBI_ALLE3IS},
{"vae1is", A64TLBI_VAE1IS},
{"vae2is", A64TLBI_VAE2IS},
{"vae3is", A64TLBI_VAE3IS},
{"aside1is", A64TLBI_ASIDE1IS},
{"vaae1is", A64TLBI_VAAE1IS},
{"alle1is", A64TLBI_ALLE1IS},
{"vale1is", A64TLBI_VALE1IS},
{"vale2is", A64TLBI_VALE2IS},
{"vale3is", A64TLBI_VALE3IS},
{"vmalls12e1is", A64TLBI_VMALLS12E1IS},
{"vaale1is", A64TLBI_VAALE1IS},
{"ipas2e1", A64TLBI_IPAS2E1},
{"ipas2le1", A64TLBI_IPAS2LE1},
{"vmalle1", A64TLBI_VMALLE1},
{"alle2", A64TLBI_ALLE2},
{"alle3", A64TLBI_ALLE3},
{"vae1", A64TLBI_VAE1},
{"vae2", A64TLBI_VAE2},
{"vae3", A64TLBI_VAE3},
{"aside1", A64TLBI_ASIDE1},
{"vaae1", A64TLBI_VAAE1},
{"alle1", A64TLBI_ALLE1},
{"vale1", A64TLBI_VALE1},
{"vale2", A64TLBI_VALE2},
{"vale3", A64TLBI_VALE3},
{"vmalls12e1", A64TLBI_VMALLS12E1},
{"vaale1", A64TLBI_VAALE1}
};
A64NamedImmMapper A64TLBI_TLBIMapper = {
TLBIPairs,
ARR_SIZE(TLBIPairs),
0,
};
static A64NamedImmMapper_Mapping ATPairs[] = {
{"s1e1r", A64AT_S1E1R},
{"s1e2r", A64AT_S1E2R},
{"s1e3r", A64AT_S1E3R},
{"s1e1w", A64AT_S1E1W},
{"s1e2w", A64AT_S1E2W},
{"s1e3w", A64AT_S1E3W},
{"s1e0r", A64AT_S1E0R},
{"s1e0w", A64AT_S1E0W},
{"s12e1r", A64AT_S12E1R},
{"s12e1w", A64AT_S12E1W},
{"s12e0r", A64AT_S12E0R},
{"s12e0w", A64AT_S12E0W},
};
A64NamedImmMapper A64AT_ATMapper = {
ATPairs,
ARR_SIZE(ATPairs),
0,
};
static A64NamedImmMapper_Mapping DBarrierPairs[] = {
{"oshld", A64DB_OSHLD},
{"oshst", A64DB_OSHST},
{"osh", A64DB_OSH},
{"nshld", A64DB_NSHLD},
{"nshst", A64DB_NSHST},
{"nsh", A64DB_NSH},
{"ishld", A64DB_ISHLD},
{"ishst", A64DB_ISHST},
{"ish", A64DB_ISH},
{"ld", A64DB_LD},
{"st", A64DB_ST},
{"sy", A64DB_SY}
};
A64NamedImmMapper A64DB_DBarrierMapper = {
DBarrierPairs,
ARR_SIZE(DBarrierPairs),
16,
};
static A64NamedImmMapper_Mapping DCPairs[] = {
{"zva", A64DC_ZVA},
{"ivac", A64DC_IVAC},
{"isw", A64DC_ISW},
{"cvac", A64DC_CVAC},
{"csw", A64DC_CSW},
{"cvau", A64DC_CVAU},
{"civac", A64DC_CIVAC},
{"cisw", A64DC_CISW}
};
A64NamedImmMapper A64DC_DCMapper = {
DCPairs,
ARR_SIZE(DCPairs),
0,
};
static A64NamedImmMapper_Mapping ICPairs[] = {
{"ialluis", A64IC_IALLUIS},
{"iallu", A64IC_IALLU},
{"ivau", A64IC_IVAU}
};
A64NamedImmMapper A64IC_ICMapper = {
ICPairs,
ARR_SIZE(ICPairs),
0,
};
static A64NamedImmMapper_Mapping ISBPairs[] = {
{"sy", A64DB_SY},
};
A64NamedImmMapper A64ISB_ISBMapper = {
ISBPairs,
ARR_SIZE(ISBPairs),
16,
};
static A64NamedImmMapper_Mapping PRFMPairs[] = {
{"pldl1keep", A64PRFM_PLDL1KEEP},
{"pldl1strm", A64PRFM_PLDL1STRM},
{"pldl2keep", A64PRFM_PLDL2KEEP},
{"pldl2strm", A64PRFM_PLDL2STRM},
{"pldl3keep", A64PRFM_PLDL3KEEP},
{"pldl3strm", A64PRFM_PLDL3STRM},
{"plil1keep", A64PRFM_PLIL1KEEP},
{"plil1strm", A64PRFM_PLIL1STRM},
{"plil2keep", A64PRFM_PLIL2KEEP},
{"plil2strm", A64PRFM_PLIL2STRM},
{"plil3keep", A64PRFM_PLIL3KEEP},
{"plil3strm", A64PRFM_PLIL3STRM},
{"pstl1keep", A64PRFM_PSTL1KEEP},
{"pstl1strm", A64PRFM_PSTL1STRM},
{"pstl2keep", A64PRFM_PSTL2KEEP},
{"pstl2strm", A64PRFM_PSTL2STRM},
{"pstl3keep", A64PRFM_PSTL3KEEP},
{"pstl3strm", A64PRFM_PSTL3STRM}
};
A64NamedImmMapper A64PRFM_PRFMMapper = {
PRFMPairs,
ARR_SIZE(PRFMPairs),
32,
};
static A64NamedImmMapper_Mapping PStatePairs[] = {
{"spsel", A64PState_SPSel},
{"daifset", A64PState_DAIFSet},
{"daifclr", A64PState_DAIFClr}
};
A64NamedImmMapper A64PState_PStateMapper = {
PStatePairs,
ARR_SIZE(PStatePairs),
0,
};
static A64NamedImmMapper_Mapping MRSPairs[] = {
{"mdccsr_el0", A64SysReg_MDCCSR_EL0},
{"dbgdtrrx_el0", A64SysReg_DBGDTRRX_EL0},
{"mdrar_el1", A64SysReg_MDRAR_EL1},
{"oslsr_el1", A64SysReg_OSLSR_EL1},
{"dbgauthstatus_el1", A64SysReg_DBGAUTHSTATUS_EL1},
{"pmceid0_el0", A64SysReg_PMCEID0_EL0},
{"pmceid1_el0", A64SysReg_PMCEID1_EL0},
{"midr_el1", A64SysReg_MIDR_EL1},
{"ccsidr_el1", A64SysReg_CCSIDR_EL1},
{"clidr_el1", A64SysReg_CLIDR_EL1},
{"ctr_el0", A64SysReg_CTR_EL0},
{"mpidr_el1", A64SysReg_MPIDR_EL1},
{"revidr_el1", A64SysReg_REVIDR_EL1},
{"aidr_el1", A64SysReg_AIDR_EL1},
{"dczid_el0", A64SysReg_DCZID_EL0},
{"id_pfr0_el1", A64SysReg_ID_PFR0_EL1},
{"id_pfr1_el1", A64SysReg_ID_PFR1_EL1},
{"id_dfr0_el1", A64SysReg_ID_DFR0_EL1},
{"id_afr0_el1", A64SysReg_ID_AFR0_EL1},
{"id_mmfr0_el1", A64SysReg_ID_MMFR0_EL1},
{"id_mmfr1_el1", A64SysReg_ID_MMFR1_EL1},
{"id_mmfr2_el1", A64SysReg_ID_MMFR2_EL1},
{"id_mmfr3_el1", A64SysReg_ID_MMFR3_EL1},
{"id_isar0_el1", A64SysReg_ID_ISAR0_EL1},
{"id_isar1_el1", A64SysReg_ID_ISAR1_EL1},
{"id_isar2_el1", A64SysReg_ID_ISAR2_EL1},
{"id_isar3_el1", A64SysReg_ID_ISAR3_EL1},
{"id_isar4_el1", A64SysReg_ID_ISAR4_EL1},
{"id_isar5_el1", A64SysReg_ID_ISAR5_EL1},
{"id_aa64pfr0_el1", A64SysReg_ID_A64PFR0_EL1},
{"id_aa64pfr1_el1", A64SysReg_ID_A64PFR1_EL1},
{"id_aa64dfr0_el1", A64SysReg_ID_A64DFR0_EL1},
{"id_aa64dfr1_el1", A64SysReg_ID_A64DFR1_EL1},
{"id_aa64afr0_el1", A64SysReg_ID_A64AFR0_EL1},
{"id_aa64afr1_el1", A64SysReg_ID_A64AFR1_EL1},
{"id_aa64isar0_el1", A64SysReg_ID_A64ISAR0_EL1},
{"id_aa64isar1_el1", A64SysReg_ID_A64ISAR1_EL1},
{"id_aa64mmfr0_el1", A64SysReg_ID_A64MMFR0_EL1},
{"id_aa64mmfr1_el1", A64SysReg_ID_A64MMFR1_EL1},
{"mvfr0_el1", A64SysReg_MVFR0_EL1},
{"mvfr1_el1", A64SysReg_MVFR1_EL1},
{"mvfr2_el1", A64SysReg_MVFR2_EL1},
{"rvbar_el1", A64SysReg_RVBAR_EL1},
{"rvbar_el2", A64SysReg_RVBAR_EL2},
{"rvbar_el3", A64SysReg_RVBAR_EL3},
{"isr_el1", A64SysReg_ISR_EL1},
{"cntpct_el0", A64SysReg_CNTPCT_EL0},
{"cntvct_el0", A64SysReg_CNTVCT_EL0},
// Trace registers
{"trcstatr", A64SysReg_TRCSTATR},
{"trcidr8", A64SysReg_TRCIDR8},
{"trcidr9", A64SysReg_TRCIDR9},
{"trcidr10", A64SysReg_TRCIDR10},
{"trcidr11", A64SysReg_TRCIDR11},
{"trcidr12", A64SysReg_TRCIDR12},
{"trcidr13", A64SysReg_TRCIDR13},
{"trcidr0", A64SysReg_TRCIDR0},
{"trcidr1", A64SysReg_TRCIDR1},
{"trcidr2", A64SysReg_TRCIDR2},
{"trcidr3", A64SysReg_TRCIDR3},
{"trcidr4", A64SysReg_TRCIDR4},
{"trcidr5", A64SysReg_TRCIDR5},
{"trcidr6", A64SysReg_TRCIDR6},
{"trcidr7", A64SysReg_TRCIDR7},
{"trcoslsr", A64SysReg_TRCOSLSR},
{"trcpdsr", A64SysReg_TRCPDSR},
{"trcdevaff0", A64SysReg_TRCDEVAFF0},
{"trcdevaff1", A64SysReg_TRCDEVAFF1},
{"trclsr", A64SysReg_TRCLSR},
{"trcauthstatus", A64SysReg_TRCAUTHSTATUS},
{"trcdevarch", A64SysReg_TRCDEVARCH},
{"trcdevid", A64SysReg_TRCDEVID},
{"trcdevtype", A64SysReg_TRCDEVTYPE},
{"trcpidr4", A64SysReg_TRCPIDR4},
{"trcpidr5", A64SysReg_TRCPIDR5},
{"trcpidr6", A64SysReg_TRCPIDR6},
{"trcpidr7", A64SysReg_TRCPIDR7},
{"trcpidr0", A64SysReg_TRCPIDR0},
{"trcpidr1", A64SysReg_TRCPIDR1},
{"trcpidr2", A64SysReg_TRCPIDR2},
{"trcpidr3", A64SysReg_TRCPIDR3},
{"trccidr0", A64SysReg_TRCCIDR0},
{"trccidr1", A64SysReg_TRCCIDR1},
{"trccidr2", A64SysReg_TRCCIDR2},
{"trccidr3", A64SysReg_TRCCIDR3},
// GICv3 registers
{"icc_iar1_el1", A64SysReg_ICC_IAR1_EL1},
{"icc_iar0_el1", A64SysReg_ICC_IAR0_EL1},
{"icc_hppir1_el1", A64SysReg_ICC_HPPIR1_EL1},
{"icc_hppir0_el1", A64SysReg_ICC_HPPIR0_EL1},
{"icc_rpr_el1", A64SysReg_ICC_RPR_EL1},
{"ich_vtr_el2", A64SysReg_ICH_VTR_EL2},
{"ich_eisr_el2", A64SysReg_ICH_EISR_EL2},
{"ich_elsr_el2", A64SysReg_ICH_ELSR_EL2}
};
A64SysRegMapper AArch64_MRSMapper = {
NULL,
MRSPairs,
ARR_SIZE(MRSPairs),
};
static A64NamedImmMapper_Mapping MSRPairs[] = {
{"dbgdtrtx_el0", A64SysReg_DBGDTRTX_EL0},
{"oslar_el1", A64SysReg_OSLAR_EL1},
{"pmswinc_el0", A64SysReg_PMSWINC_EL0},
// Trace registers
{"trcoslar", A64SysReg_TRCOSLAR},
{"trclar", A64SysReg_TRCLAR},
// GICv3 registers
{"icc_eoir1_el1", A64SysReg_ICC_EOIR1_EL1},
{"icc_eoir0_el1", A64SysReg_ICC_EOIR0_EL1},
{"icc_dir_el1", A64SysReg_ICC_DIR_EL1},
{"icc_sgi1r_el1", A64SysReg_ICC_SGI1R_EL1},
{"icc_asgi1r_el1", A64SysReg_ICC_ASGI1R_EL1},
{"icc_sgi0r_el1", A64SysReg_ICC_SGI0R_EL1}
};
A64SysRegMapper AArch64_MSRMapper = {
NULL,
MSRPairs,
ARR_SIZE(MSRPairs),
};
#endif

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@ -0,0 +1,959 @@
//===-- AArch64BaseInfo.h - Top level definitions for AArch64- --*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains small standalone helper functions and enum definitions for
// the AArch64 target useful for the compiler back-end and the MC libraries.
// As such, it deliberately does not include references to LLVM core
// code gen types, passes, etc..
//
//===----------------------------------------------------------------------===//
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
#ifndef CS_LLVM_AARCH64_BASEINFO_H
#define CS_LLVM_AARCH64_BASEINFO_H
#include <ctype.h>
#include <stdint.h>
#include <string.h>
#ifndef __cplusplus
#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)
#define inline /* inline */
#endif
#endif
inline static unsigned getWRegFromXReg(unsigned Reg)
{
switch (Reg) {
case ARM64_REG_X0: return ARM64_REG_W0;
case ARM64_REG_X1: return ARM64_REG_W1;
case ARM64_REG_X2: return ARM64_REG_W2;
case ARM64_REG_X3: return ARM64_REG_W3;
case ARM64_REG_X4: return ARM64_REG_W4;
case ARM64_REG_X5: return ARM64_REG_W5;
case ARM64_REG_X6: return ARM64_REG_W6;
case ARM64_REG_X7: return ARM64_REG_W7;
case ARM64_REG_X8: return ARM64_REG_W8;
case ARM64_REG_X9: return ARM64_REG_W9;
case ARM64_REG_X10: return ARM64_REG_W10;
case ARM64_REG_X11: return ARM64_REG_W11;
case ARM64_REG_X12: return ARM64_REG_W12;
case ARM64_REG_X13: return ARM64_REG_W13;
case ARM64_REG_X14: return ARM64_REG_W14;
case ARM64_REG_X15: return ARM64_REG_W15;
case ARM64_REG_X16: return ARM64_REG_W16;
case ARM64_REG_X17: return ARM64_REG_W17;
case ARM64_REG_X18: return ARM64_REG_W18;
case ARM64_REG_X19: return ARM64_REG_W19;
case ARM64_REG_X20: return ARM64_REG_W20;
case ARM64_REG_X21: return ARM64_REG_W21;
case ARM64_REG_X22: return ARM64_REG_W22;
case ARM64_REG_X23: return ARM64_REG_W23;
case ARM64_REG_X24: return ARM64_REG_W24;
case ARM64_REG_X25: return ARM64_REG_W25;
case ARM64_REG_X26: return ARM64_REG_W26;
case ARM64_REG_X27: return ARM64_REG_W27;
case ARM64_REG_X28: return ARM64_REG_W28;
case ARM64_REG_FP: return ARM64_REG_W29;
case ARM64_REG_LR: return ARM64_REG_W30;
case ARM64_REG_SP: return ARM64_REG_WSP;
case ARM64_REG_XZR: return ARM64_REG_WZR;
}
// For anything else, return it unchanged.
return Reg;
}
// // Enums corresponding to AArch64 condition codes
// The CondCodes constants map directly to the 4-bit encoding of the
// condition field for predicated instructions.
typedef enum A64CC_CondCode { // Meaning (integer) Meaning (floating-point)
A64CC_EQ = 0, // Equal Equal
A64CC_NE, // Not equal Not equal, or unordered
A64CC_HS, // Unsigned higher or same >, ==, or unordered
A64CC_LO, // Unsigned lower or same Less than
A64CC_MI, // Minus, negative Less than
A64CC_PL, // Plus, positive or zero >, ==, or unordered
A64CC_VS, // Overflow Unordered
A64CC_VC, // No overflow Ordered
A64CC_HI, // Unsigned higher Greater than, or unordered
A64CC_LS, // Unsigned lower or same Less than or equal
A64CC_GE, // Greater than or equal Greater than or equal
A64CC_LT, // Less than Less than, or unordered
A64CC_GT, // Signed greater than Greater than
A64CC_LE, // Signed less than or equal <, ==, or unordered
A64CC_AL, // Always (unconditional) Always (unconditional)
A64CC_NV, // Always (unconditional) Always (unconditional)
// Note the NV exists purely to disassemble 0b1111. Execution is "always".
A64CC_Invalid
} A64CC_CondCode;
inline static char *getCondCodeName(A64CC_CondCode CC)
{
switch (CC) {
default: return NULL; // never reach
case A64CC_EQ: return "eq";
case A64CC_NE: return "ne";
case A64CC_HS: return "hs";
case A64CC_LO: return "lo";
case A64CC_MI: return "mi";
case A64CC_PL: return "pl";
case A64CC_VS: return "vs";
case A64CC_VC: return "vc";
case A64CC_HI: return "hi";
case A64CC_LS: return "ls";
case A64CC_GE: return "ge";
case A64CC_LT: return "lt";
case A64CC_GT: return "gt";
case A64CC_LE: return "le";
case A64CC_AL: return "al";
case A64CC_NV: return "nv";
}
}
inline static A64CC_CondCode getInvertedCondCode(A64CC_CondCode Code)
{
// To reverse a condition it's necessary to only invert the low bit:
return (A64CC_CondCode)((unsigned)Code ^ 0x1);
}
/// Instances of this class can perform bidirectional mapping from random
/// identifier strings to operand encodings. For example "MSR" takes a named
/// system-register which must be encoded somehow and decoded for printing. This
/// central location means that the information for those transformations is not
/// duplicated and remains in sync.
///
/// FIXME: currently the algorithm is a completely unoptimised linear
/// search. Obviously this could be improved, but we would probably want to work
/// out just how often these instructions are emitted before working on it. It
/// might even be optimal to just reorder the tables for the common instructions
/// rather than changing the algorithm.
typedef struct A64NamedImmMapper_Mapping {
char *Name;
uint32_t Value;
} A64NamedImmMapper_Mapping;
typedef struct A64NamedImmMapper {
A64NamedImmMapper_Mapping *Pairs;
size_t NumPairs;
uint32_t TooBigImm;
} A64NamedImmMapper;
typedef struct A64SysRegMapper {
A64NamedImmMapper_Mapping *SysRegPairs;
A64NamedImmMapper_Mapping *InstPairs;
size_t NumInstPairs;
} A64SysRegMapper;
extern A64SysRegMapper AArch64_MSRMapper;
extern A64SysRegMapper AArch64_MRSMapper;
extern A64NamedImmMapper A64DB_DBarrierMapper;
extern A64NamedImmMapper A64AT_ATMapper;
extern A64NamedImmMapper A64DC_DCMapper;
extern A64NamedImmMapper A64IC_ICMapper;
extern A64NamedImmMapper A64ISB_ISBMapper;
extern A64NamedImmMapper A64PRFM_PRFMMapper;
extern A64NamedImmMapper A64PState_PStateMapper;
extern A64NamedImmMapper A64TLBI_TLBIMapper;
enum {
A64AT_Invalid = -1, // Op0 Op1 CRn CRm Op2
A64AT_S1E1R = 0x43c0, // 01 000 0111 1000 000
A64AT_S1E2R = 0x63c0, // 01 100 0111 1000 000
A64AT_S1E3R = 0x73c0, // 01 110 0111 1000 000
A64AT_S1E1W = 0x43c1, // 01 000 0111 1000 001
A64AT_S1E2W = 0x63c1, // 01 100 0111 1000 001
A64AT_S1E3W = 0x73c1, // 01 110 0111 1000 001
A64AT_S1E0R = 0x43c2, // 01 000 0111 1000 010
A64AT_S1E0W = 0x43c3, // 01 000 0111 1000 011
A64AT_S12E1R = 0x63c4, // 01 100 0111 1000 100
A64AT_S12E1W = 0x63c5, // 01 100 0111 1000 101
A64AT_S12E0R = 0x63c6, // 01 100 0111 1000 110
A64AT_S12E0W = 0x63c7 // 01 100 0111 1000 111
};
enum A64DBValues {
A64DB_Invalid = -1,
A64DB_OSHLD = 0x1,
A64DB_OSHST = 0x2,
A64DB_OSH = 0x3,
A64DB_NSHLD = 0x5,
A64DB_NSHST = 0x6,
A64DB_NSH = 0x7,
A64DB_ISHLD = 0x9,
A64DB_ISHST = 0xa,
A64DB_ISH = 0xb,
A64DB_LD = 0xd,
A64DB_ST = 0xe,
A64DB_SY = 0xf
};
enum A64DCValues {
A64DC_Invalid = -1, // Op1 CRn CRm Op2
A64DC_ZVA = 0x5ba1, // 01 011 0111 0100 001
A64DC_IVAC = 0x43b1, // 01 000 0111 0110 001
A64DC_ISW = 0x43b2, // 01 000 0111 0110 010
A64DC_CVAC = 0x5bd1, // 01 011 0111 1010 001
A64DC_CSW = 0x43d2, // 01 000 0111 1010 010
A64DC_CVAU = 0x5bd9, // 01 011 0111 1011 001
A64DC_CIVAC = 0x5bf1, // 01 011 0111 1110 001
A64DC_CISW = 0x43f2 // 01 000 0111 1110 010
};
enum A64ICValues {
A64IC_Invalid = -1, // Op1 CRn CRm Op2
A64IC_IALLUIS = 0x0388, // 000 0111 0001 000
A64IC_IALLU = 0x03a8, // 000 0111 0101 000
A64IC_IVAU = 0x1ba9 // 011 0111 0101 001
};
enum A64ISBValues {
A64ISB_Invalid = -1,
A64ISB_SY = 0xf
};
enum A64PRFMValues {
A64PRFM_Invalid = -1,
A64PRFM_PLDL1KEEP = 0x00,
A64PRFM_PLDL1STRM = 0x01,
A64PRFM_PLDL2KEEP = 0x02,
A64PRFM_PLDL2STRM = 0x03,
A64PRFM_PLDL3KEEP = 0x04,
A64PRFM_PLDL3STRM = 0x05,
A64PRFM_PLIL1KEEP = 0x08,
A64PRFM_PLIL1STRM = 0x09,
A64PRFM_PLIL2KEEP = 0x0a,
A64PRFM_PLIL2STRM = 0x0b,
A64PRFM_PLIL3KEEP = 0x0c,
A64PRFM_PLIL3STRM = 0x0d,
A64PRFM_PSTL1KEEP = 0x10,
A64PRFM_PSTL1STRM = 0x11,
A64PRFM_PSTL2KEEP = 0x12,
A64PRFM_PSTL2STRM = 0x13,
A64PRFM_PSTL3KEEP = 0x14,
A64PRFM_PSTL3STRM = 0x15
};
enum A64PStateValues {
A64PState_Invalid = -1,
A64PState_SPSel = 0x05,
A64PState_DAIFSet = 0x1e,
A64PState_DAIFClr = 0x1f
};
typedef enum A64SE_ShiftExtSpecifiers {
A64SE_Invalid = -1,
A64SE_LSL,
A64SE_MSL,
A64SE_LSR,
A64SE_ASR,
A64SE_ROR,
A64SE_UXTB,
A64SE_UXTH,
A64SE_UXTW,
A64SE_UXTX,
A64SE_SXTB,
A64SE_SXTH,
A64SE_SXTW,
A64SE_SXTX
} A64SE_ShiftExtSpecifiers;
typedef enum A64Layout_VectorLayout {
A64Layout_Invalid = -1,
A64Layout_VL_8B,
A64Layout_VL_4H,
A64Layout_VL_2S,
A64Layout_VL_1D,
A64Layout_VL_16B,
A64Layout_VL_8H,
A64Layout_VL_4S,
A64Layout_VL_2D,
// Bare layout for the 128-bit vector
// (only show ".b", ".h", ".s", ".d" without vector number)
A64Layout_VL_B,
A64Layout_VL_H,
A64Layout_VL_S,
A64Layout_VL_D
} A64Layout_VectorLayout;
inline static char *A64VectorLayoutToString(A64Layout_VectorLayout Layout)
{
switch (Layout) {
case A64Layout_VL_8B: return ".8b";
case A64Layout_VL_4H: return ".4h";
case A64Layout_VL_2S: return ".2s";
case A64Layout_VL_1D: return ".1d";
case A64Layout_VL_16B: return ".16b";
case A64Layout_VL_8H: return ".8h";
case A64Layout_VL_4S: return ".4s";
case A64Layout_VL_2D: return ".2d";
case A64Layout_VL_B: return ".b";
case A64Layout_VL_H: return ".h";
case A64Layout_VL_S: return ".s";
case A64Layout_VL_D: return ".d";
default: return NULL; // never reach
}
}
enum A64SysRegROValues {
A64SysReg_MDCCSR_EL0 = 0x9808, // 10 011 0000 0001 000
A64SysReg_DBGDTRRX_EL0 = 0x9828, // 10 011 0000 0101 000
A64SysReg_MDRAR_EL1 = 0x8080, // 10 000 0001 0000 000
A64SysReg_OSLSR_EL1 = 0x808c, // 10 000 0001 0001 100
A64SysReg_DBGAUTHSTATUS_EL1 = 0x83f6, // 10 000 0111 1110 110
A64SysReg_PMCEID0_EL0 = 0xdce6, // 11 011 1001 1100 110
A64SysReg_PMCEID1_EL0 = 0xdce7, // 11 011 1001 1100 111
A64SysReg_MIDR_EL1 = 0xc000, // 11 000 0000 0000 000
A64SysReg_CCSIDR_EL1 = 0xc800, // 11 001 0000 0000 000
A64SysReg_CLIDR_EL1 = 0xc801, // 11 001 0000 0000 001
A64SysReg_CTR_EL0 = 0xd801, // 11 011 0000 0000 001
A64SysReg_MPIDR_EL1 = 0xc005, // 11 000 0000 0000 101
A64SysReg_REVIDR_EL1 = 0xc006, // 11 000 0000 0000 110
A64SysReg_AIDR_EL1 = 0xc807, // 11 001 0000 0000 111
A64SysReg_DCZID_EL0 = 0xd807, // 11 011 0000 0000 111
A64SysReg_ID_PFR0_EL1 = 0xc008, // 11 000 0000 0001 000
A64SysReg_ID_PFR1_EL1 = 0xc009, // 11 000 0000 0001 001
A64SysReg_ID_DFR0_EL1 = 0xc00a, // 11 000 0000 0001 010
A64SysReg_ID_AFR0_EL1 = 0xc00b, // 11 000 0000 0001 011
A64SysReg_ID_MMFR0_EL1 = 0xc00c, // 11 000 0000 0001 100
A64SysReg_ID_MMFR1_EL1 = 0xc00d, // 11 000 0000 0001 101
A64SysReg_ID_MMFR2_EL1 = 0xc00e, // 11 000 0000 0001 110
A64SysReg_ID_MMFR3_EL1 = 0xc00f, // 11 000 0000 0001 111
A64SysReg_ID_ISAR0_EL1 = 0xc010, // 11 000 0000 0010 000
A64SysReg_ID_ISAR1_EL1 = 0xc011, // 11 000 0000 0010 001
A64SysReg_ID_ISAR2_EL1 = 0xc012, // 11 000 0000 0010 010
A64SysReg_ID_ISAR3_EL1 = 0xc013, // 11 000 0000 0010 011
A64SysReg_ID_ISAR4_EL1 = 0xc014, // 11 000 0000 0010 100
A64SysReg_ID_ISAR5_EL1 = 0xc015, // 11 000 0000 0010 101
A64SysReg_ID_A64PFR0_EL1 = 0xc020, // 11 000 0000 0100 000
A64SysReg_ID_A64PFR1_EL1 = 0xc021, // 11 000 0000 0100 001
A64SysReg_ID_A64DFR0_EL1 = 0xc028, // 11 000 0000 0101 000
A64SysReg_ID_A64DFR1_EL1 = 0xc029, // 11 000 0000 0101 001
A64SysReg_ID_A64AFR0_EL1 = 0xc02c, // 11 000 0000 0101 100
A64SysReg_ID_A64AFR1_EL1 = 0xc02d, // 11 000 0000 0101 101
A64SysReg_ID_A64ISAR0_EL1 = 0xc030, // 11 000 0000 0110 000
A64SysReg_ID_A64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001
A64SysReg_ID_A64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000
A64SysReg_ID_A64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001
A64SysReg_MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000
A64SysReg_MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001
A64SysReg_MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010
A64SysReg_RVBAR_EL1 = 0xc601, // 11 000 1100 0000 001
A64SysReg_RVBAR_EL2 = 0xe601, // 11 100 1100 0000 001
A64SysReg_RVBAR_EL3 = 0xf601, // 11 110 1100 0000 001
A64SysReg_ISR_EL1 = 0xc608, // 11 000 1100 0001 000
A64SysReg_CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001
A64SysReg_CNTVCT_EL0 = 0xdf02, // 11 011 1110 0000 010
// Trace registers
A64SysReg_TRCSTATR = 0x8818, // 10 001 0000 0011 000
A64SysReg_TRCIDR8 = 0x8806, // 10 001 0000 0000 110
A64SysReg_TRCIDR9 = 0x880e, // 10 001 0000 0001 110
A64SysReg_TRCIDR10 = 0x8816, // 10 001 0000 0010 110
A64SysReg_TRCIDR11 = 0x881e, // 10 001 0000 0011 110
A64SysReg_TRCIDR12 = 0x8826, // 10 001 0000 0100 110
A64SysReg_TRCIDR13 = 0x882e, // 10 001 0000 0101 110
A64SysReg_TRCIDR0 = 0x8847, // 10 001 0000 1000 111
A64SysReg_TRCIDR1 = 0x884f, // 10 001 0000 1001 111
A64SysReg_TRCIDR2 = 0x8857, // 10 001 0000 1010 111
A64SysReg_TRCIDR3 = 0x885f, // 10 001 0000 1011 111
A64SysReg_TRCIDR4 = 0x8867, // 10 001 0000 1100 111
A64SysReg_TRCIDR5 = 0x886f, // 10 001 0000 1101 111
A64SysReg_TRCIDR6 = 0x8877, // 10 001 0000 1110 111
A64SysReg_TRCIDR7 = 0x887f, // 10 001 0000 1111 111
A64SysReg_TRCOSLSR = 0x888c, // 10 001 0001 0001 100
A64SysReg_TRCPDSR = 0x88ac, // 10 001 0001 0101 100
A64SysReg_TRCDEVAFF0 = 0x8bd6, // 10 001 0111 1010 110
A64SysReg_TRCDEVAFF1 = 0x8bde, // 10 001 0111 1011 110
A64SysReg_TRCLSR = 0x8bee, // 10 001 0111 1101 110
A64SysReg_TRCAUTHSTATUS = 0x8bf6, // 10 001 0111 1110 110
A64SysReg_TRCDEVARCH = 0x8bfe, // 10 001 0111 1111 110
A64SysReg_TRCDEVID = 0x8b97, // 10 001 0111 0010 111
A64SysReg_TRCDEVTYPE = 0x8b9f, // 10 001 0111 0011 111
A64SysReg_TRCPIDR4 = 0x8ba7, // 10 001 0111 0100 111
A64SysReg_TRCPIDR5 = 0x8baf, // 10 001 0111 0101 111
A64SysReg_TRCPIDR6 = 0x8bb7, // 10 001 0111 0110 111
A64SysReg_TRCPIDR7 = 0x8bbf, // 10 001 0111 0111 111
A64SysReg_TRCPIDR0 = 0x8bc7, // 10 001 0111 1000 111
A64SysReg_TRCPIDR1 = 0x8bcf, // 10 001 0111 1001 111
A64SysReg_TRCPIDR2 = 0x8bd7, // 10 001 0111 1010 111
A64SysReg_TRCPIDR3 = 0x8bdf, // 10 001 0111 1011 111
A64SysReg_TRCCIDR0 = 0x8be7, // 10 001 0111 1100 111
A64SysReg_TRCCIDR1 = 0x8bef, // 10 001 0111 1101 111
A64SysReg_TRCCIDR2 = 0x8bf7, // 10 001 0111 1110 111
A64SysReg_TRCCIDR3 = 0x8bff, // 10 001 0111 1111 111
// GICv3 registers
A64SysReg_ICC_IAR1_EL1 = 0xc660, // 11 000 1100 1100 000
A64SysReg_ICC_IAR0_EL1 = 0xc640, // 11 000 1100 1000 000
A64SysReg_ICC_HPPIR1_EL1 = 0xc662, // 11 000 1100 1100 010
A64SysReg_ICC_HPPIR0_EL1 = 0xc642, // 11 000 1100 1000 010
A64SysReg_ICC_RPR_EL1 = 0xc65b, // 11 000 1100 1011 011
A64SysReg_ICH_VTR_EL2 = 0xe659, // 11 100 1100 1011 001
A64SysReg_ICH_EISR_EL2 = 0xe65b, // 11 100 1100 1011 011
A64SysReg_ICH_ELSR_EL2 = 0xe65d // 11 100 1100 1011 101
};
enum A64SysRegWOValues {
A64SysReg_DBGDTRTX_EL0 = 0x9828, // 10 011 0000 0101 000
A64SysReg_OSLAR_EL1 = 0x8084, // 10 000 0001 0000 100
A64SysReg_PMSWINC_EL0 = 0xdce4, // 11 011 1001 1100 100
// Trace Registers
A64SysReg_TRCOSLAR = 0x8884, // 10 001 0001 0000 100
A64SysReg_TRCLAR = 0x8be6, // 10 001 0111 1100 110
// GICv3 registers
A64SysReg_ICC_EOIR1_EL1 = 0xc661, // 11 000 1100 1100 001
A64SysReg_ICC_EOIR0_EL1 = 0xc641, // 11 000 1100 1000 001
A64SysReg_ICC_DIR_EL1 = 0xc659, // 11 000 1100 1011 001
A64SysReg_ICC_SGI1R_EL1 = 0xc65d, // 11 000 1100 1011 101
A64SysReg_ICC_ASGI1R_EL1 = 0xc65e, // 11 000 1100 1011 110
A64SysReg_ICC_SGI0R_EL1 = 0xc65f // 11 000 1100 1011 111
};
enum A64SysRegValues {
A64SysReg_Invalid = -1, // Op0 Op1 CRn CRm Op2
A64SysReg_OSDTRRX_EL1 = 0x8002, // 10 000 0000 0000 010
A64SysReg_OSDTRTX_EL1 = 0x801a, // 10 000 0000 0011 010
A64SysReg_TEECR32_EL1 = 0x9000, // 10 010 0000 0000 000
A64SysReg_MDCCINT_EL1 = 0x8010, // 10 000 0000 0010 000
A64SysReg_MDSCR_EL1 = 0x8012, // 10 000 0000 0010 010
A64SysReg_DBGDTR_EL0 = 0x9820, // 10 011 0000 0100 000
A64SysReg_OSECCR_EL1 = 0x8032, // 10 000 0000 0110 010
A64SysReg_DBGVCR32_EL2 = 0xa038, // 10 100 0000 0111 000
A64SysReg_DBGBVR0_EL1 = 0x8004, // 10 000 0000 0000 100
A64SysReg_DBGBVR1_EL1 = 0x800c, // 10 000 0000 0001 100
A64SysReg_DBGBVR2_EL1 = 0x8014, // 10 000 0000 0010 100
A64SysReg_DBGBVR3_EL1 = 0x801c, // 10 000 0000 0011 100
A64SysReg_DBGBVR4_EL1 = 0x8024, // 10 000 0000 0100 100
A64SysReg_DBGBVR5_EL1 = 0x802c, // 10 000 0000 0101 100
A64SysReg_DBGBVR6_EL1 = 0x8034, // 10 000 0000 0110 100
A64SysReg_DBGBVR7_EL1 = 0x803c, // 10 000 0000 0111 100
A64SysReg_DBGBVR8_EL1 = 0x8044, // 10 000 0000 1000 100
A64SysReg_DBGBVR9_EL1 = 0x804c, // 10 000 0000 1001 100
A64SysReg_DBGBVR10_EL1 = 0x8054, // 10 000 0000 1010 100
A64SysReg_DBGBVR11_EL1 = 0x805c, // 10 000 0000 1011 100
A64SysReg_DBGBVR12_EL1 = 0x8064, // 10 000 0000 1100 100
A64SysReg_DBGBVR13_EL1 = 0x806c, // 10 000 0000 1101 100
A64SysReg_DBGBVR14_EL1 = 0x8074, // 10 000 0000 1110 100
A64SysReg_DBGBVR15_EL1 = 0x807c, // 10 000 0000 1111 100
A64SysReg_DBGBCR0_EL1 = 0x8005, // 10 000 0000 0000 101
A64SysReg_DBGBCR1_EL1 = 0x800d, // 10 000 0000 0001 101
A64SysReg_DBGBCR2_EL1 = 0x8015, // 10 000 0000 0010 101
A64SysReg_DBGBCR3_EL1 = 0x801d, // 10 000 0000 0011 101
A64SysReg_DBGBCR4_EL1 = 0x8025, // 10 000 0000 0100 101
A64SysReg_DBGBCR5_EL1 = 0x802d, // 10 000 0000 0101 101
A64SysReg_DBGBCR6_EL1 = 0x8035, // 10 000 0000 0110 101
A64SysReg_DBGBCR7_EL1 = 0x803d, // 10 000 0000 0111 101
A64SysReg_DBGBCR8_EL1 = 0x8045, // 10 000 0000 1000 101
A64SysReg_DBGBCR9_EL1 = 0x804d, // 10 000 0000 1001 101
A64SysReg_DBGBCR10_EL1 = 0x8055, // 10 000 0000 1010 101
A64SysReg_DBGBCR11_EL1 = 0x805d, // 10 000 0000 1011 101
A64SysReg_DBGBCR12_EL1 = 0x8065, // 10 000 0000 1100 101
A64SysReg_DBGBCR13_EL1 = 0x806d, // 10 000 0000 1101 101
A64SysReg_DBGBCR14_EL1 = 0x8075, // 10 000 0000 1110 101
A64SysReg_DBGBCR15_EL1 = 0x807d, // 10 000 0000 1111 101
A64SysReg_DBGWVR0_EL1 = 0x8006, // 10 000 0000 0000 110
A64SysReg_DBGWVR1_EL1 = 0x800e, // 10 000 0000 0001 110
A64SysReg_DBGWVR2_EL1 = 0x8016, // 10 000 0000 0010 110
A64SysReg_DBGWVR3_EL1 = 0x801e, // 10 000 0000 0011 110
A64SysReg_DBGWVR4_EL1 = 0x8026, // 10 000 0000 0100 110
A64SysReg_DBGWVR5_EL1 = 0x802e, // 10 000 0000 0101 110
A64SysReg_DBGWVR6_EL1 = 0x8036, // 10 000 0000 0110 110
A64SysReg_DBGWVR7_EL1 = 0x803e, // 10 000 0000 0111 110
A64SysReg_DBGWVR8_EL1 = 0x8046, // 10 000 0000 1000 110
A64SysReg_DBGWVR9_EL1 = 0x804e, // 10 000 0000 1001 110
A64SysReg_DBGWVR10_EL1 = 0x8056, // 10 000 0000 1010 110
A64SysReg_DBGWVR11_EL1 = 0x805e, // 10 000 0000 1011 110
A64SysReg_DBGWVR12_EL1 = 0x8066, // 10 000 0000 1100 110
A64SysReg_DBGWVR13_EL1 = 0x806e, // 10 000 0000 1101 110
A64SysReg_DBGWVR14_EL1 = 0x8076, // 10 000 0000 1110 110
A64SysReg_DBGWVR15_EL1 = 0x807e, // 10 000 0000 1111 110
A64SysReg_DBGWCR0_EL1 = 0x8007, // 10 000 0000 0000 111
A64SysReg_DBGWCR1_EL1 = 0x800f, // 10 000 0000 0001 111
A64SysReg_DBGWCR2_EL1 = 0x8017, // 10 000 0000 0010 111
A64SysReg_DBGWCR3_EL1 = 0x801f, // 10 000 0000 0011 111
A64SysReg_DBGWCR4_EL1 = 0x8027, // 10 000 0000 0100 111
A64SysReg_DBGWCR5_EL1 = 0x802f, // 10 000 0000 0101 111
A64SysReg_DBGWCR6_EL1 = 0x8037, // 10 000 0000 0110 111
A64SysReg_DBGWCR7_EL1 = 0x803f, // 10 000 0000 0111 111
A64SysReg_DBGWCR8_EL1 = 0x8047, // 10 000 0000 1000 111
A64SysReg_DBGWCR9_EL1 = 0x804f, // 10 000 0000 1001 111
A64SysReg_DBGWCR10_EL1 = 0x8057, // 10 000 0000 1010 111
A64SysReg_DBGWCR11_EL1 = 0x805f, // 10 000 0000 1011 111
A64SysReg_DBGWCR12_EL1 = 0x8067, // 10 000 0000 1100 111
A64SysReg_DBGWCR13_EL1 = 0x806f, // 10 000 0000 1101 111
A64SysReg_DBGWCR14_EL1 = 0x8077, // 10 000 0000 1110 111
A64SysReg_DBGWCR15_EL1 = 0x807f, // 10 000 0000 1111 111
A64SysReg_TEEHBR32_EL1 = 0x9080, // 10 010 0001 0000 000
A64SysReg_OSDLR_EL1 = 0x809c, // 10 000 0001 0011 100
A64SysReg_DBGPRCR_EL1 = 0x80a4, // 10 000 0001 0100 100
A64SysReg_DBGCLAIMSET_EL1 = 0x83c6, // 10 000 0111 1000 110
A64SysReg_DBGCLAIMCLR_EL1 = 0x83ce, // 10 000 0111 1001 110
A64SysReg_CSSELR_EL1 = 0xd000, // 11 010 0000 0000 000
A64SysReg_VPIDR_EL2 = 0xe000, // 11 100 0000 0000 000
A64SysReg_VMPIDR_EL2 = 0xe005, // 11 100 0000 0000 101
A64SysReg_CPACR_EL1 = 0xc082, // 11 000 0001 0000 010
A64SysReg_SCTLR_EL1 = 0xc080, // 11 000 0001 0000 000
A64SysReg_SCTLR_EL2 = 0xe080, // 11 100 0001 0000 000
A64SysReg_SCTLR_EL3 = 0xf080, // 11 110 0001 0000 000
A64SysReg_ACTLR_EL1 = 0xc081, // 11 000 0001 0000 001
A64SysReg_ACTLR_EL2 = 0xe081, // 11 100 0001 0000 001
A64SysReg_ACTLR_EL3 = 0xf081, // 11 110 0001 0000 001
A64SysReg_HCR_EL2 = 0xe088, // 11 100 0001 0001 000
A64SysReg_SCR_EL3 = 0xf088, // 11 110 0001 0001 000
A64SysReg_MDCR_EL2 = 0xe089, // 11 100 0001 0001 001
A64SysReg_SDER32_EL3 = 0xf089, // 11 110 0001 0001 001
A64SysReg_CPTR_EL2 = 0xe08a, // 11 100 0001 0001 010
A64SysReg_CPTR_EL3 = 0xf08a, // 11 110 0001 0001 010
A64SysReg_HSTR_EL2 = 0xe08b, // 11 100 0001 0001 011
A64SysReg_HACR_EL2 = 0xe08f, // 11 100 0001 0001 111
A64SysReg_MDCR_EL3 = 0xf099, // 11 110 0001 0011 001
A64SysReg_TTBR0_EL1 = 0xc100, // 11 000 0010 0000 000
A64SysReg_TTBR0_EL2 = 0xe100, // 11 100 0010 0000 000
A64SysReg_TTBR0_EL3 = 0xf100, // 11 110 0010 0000 000
A64SysReg_TTBR1_EL1 = 0xc101, // 11 000 0010 0000 001
A64SysReg_TCR_EL1 = 0xc102, // 11 000 0010 0000 010
A64SysReg_TCR_EL2 = 0xe102, // 11 100 0010 0000 010
A64SysReg_TCR_EL3 = 0xf102, // 11 110 0010 0000 010
A64SysReg_VTTBR_EL2 = 0xe108, // 11 100 0010 0001 000
A64SysReg_VTCR_EL2 = 0xe10a, // 11 100 0010 0001 010
A64SysReg_DACR32_EL2 = 0xe180, // 11 100 0011 0000 000
A64SysReg_SPSR_EL1 = 0xc200, // 11 000 0100 0000 000
A64SysReg_SPSR_EL2 = 0xe200, // 11 100 0100 0000 000
A64SysReg_SPSR_EL3 = 0xf200, // 11 110 0100 0000 000
A64SysReg_ELR_EL1 = 0xc201, // 11 000 0100 0000 001
A64SysReg_ELR_EL2 = 0xe201, // 11 100 0100 0000 001
A64SysReg_ELR_EL3 = 0xf201, // 11 110 0100 0000 001
A64SysReg_SP_EL0 = 0xc208, // 11 000 0100 0001 000
A64SysReg_SP_EL1 = 0xe208, // 11 100 0100 0001 000
A64SysReg_SP_EL2 = 0xf208, // 11 110 0100 0001 000
A64SysReg_SPSel = 0xc210, // 11 000 0100 0010 000
A64SysReg_NZCV = 0xda10, // 11 011 0100 0010 000
A64SysReg_DAIF = 0xda11, // 11 011 0100 0010 001
A64SysReg_CurrentEL = 0xc212, // 11 000 0100 0010 010
A64SysReg_SPSR_irq = 0xe218, // 11 100 0100 0011 000
A64SysReg_SPSR_abt = 0xe219, // 11 100 0100 0011 001
A64SysReg_SPSR_und = 0xe21a, // 11 100 0100 0011 010
A64SysReg_SPSR_fiq = 0xe21b, // 11 100 0100 0011 011
A64SysReg_FPCR = 0xda20, // 11 011 0100 0100 000
A64SysReg_FPSR = 0xda21, // 11 011 0100 0100 001
A64SysReg_DSPSR_EL0 = 0xda28, // 11 011 0100 0101 000
A64SysReg_DLR_EL0 = 0xda29, // 11 011 0100 0101 001
A64SysReg_IFSR32_EL2 = 0xe281, // 11 100 0101 0000 001
A64SysReg_AFSR0_EL1 = 0xc288, // 11 000 0101 0001 000
A64SysReg_AFSR0_EL2 = 0xe288, // 11 100 0101 0001 000
A64SysReg_AFSR0_EL3 = 0xf288, // 11 110 0101 0001 000
A64SysReg_AFSR1_EL1 = 0xc289, // 11 000 0101 0001 001
A64SysReg_AFSR1_EL2 = 0xe289, // 11 100 0101 0001 001
A64SysReg_AFSR1_EL3 = 0xf289, // 11 110 0101 0001 001
A64SysReg_ESR_EL1 = 0xc290, // 11 000 0101 0010 000
A64SysReg_ESR_EL2 = 0xe290, // 11 100 0101 0010 000
A64SysReg_ESR_EL3 = 0xf290, // 11 110 0101 0010 000
A64SysReg_FPEXC32_EL2 = 0xe298, // 11 100 0101 0011 000
A64SysReg_FAR_EL1 = 0xc300, // 11 000 0110 0000 000
A64SysReg_FAR_EL2 = 0xe300, // 11 100 0110 0000 000
A64SysReg_FAR_EL3 = 0xf300, // 11 110 0110 0000 000
A64SysReg_HPFAR_EL2 = 0xe304, // 11 100 0110 0000 100
A64SysReg_PAR_EL1 = 0xc3a0, // 11 000 0111 0100 000
A64SysReg_PMCR_EL0 = 0xdce0, // 11 011 1001 1100 000
A64SysReg_PMCNTENSET_EL0 = 0xdce1, // 11 011 1001 1100 001
A64SysReg_PMCNTENCLR_EL0 = 0xdce2, // 11 011 1001 1100 010
A64SysReg_PMOVSCLR_EL0 = 0xdce3, // 11 011 1001 1100 011
A64SysReg_PMSELR_EL0 = 0xdce5, // 11 011 1001 1100 101
A64SysReg_PMCCNTR_EL0 = 0xdce8, // 11 011 1001 1101 000
A64SysReg_PMXEVTYPER_EL0 = 0xdce9, // 11 011 1001 1101 001
A64SysReg_PMXEVCNTR_EL0 = 0xdcea, // 11 011 1001 1101 010
A64SysReg_PMUSERENR_EL0 = 0xdcf0, // 11 011 1001 1110 000
A64SysReg_PMINTENSET_EL1 = 0xc4f1, // 11 000 1001 1110 001
A64SysReg_PMINTENCLR_EL1 = 0xc4f2, // 11 000 1001 1110 010
A64SysReg_PMOVSSET_EL0 = 0xdcf3, // 11 011 1001 1110 011
A64SysReg_MAIR_EL1 = 0xc510, // 11 000 1010 0010 000
A64SysReg_MAIR_EL2 = 0xe510, // 11 100 1010 0010 000
A64SysReg_MAIR_EL3 = 0xf510, // 11 110 1010 0010 000
A64SysReg_AMAIR_EL1 = 0xc518, // 11 000 1010 0011 000
A64SysReg_AMAIR_EL2 = 0xe518, // 11 100 1010 0011 000
A64SysReg_AMAIR_EL3 = 0xf518, // 11 110 1010 0011 000
A64SysReg_VBAR_EL1 = 0xc600, // 11 000 1100 0000 000
A64SysReg_VBAR_EL2 = 0xe600, // 11 100 1100 0000 000
A64SysReg_VBAR_EL3 = 0xf600, // 11 110 1100 0000 000
A64SysReg_RMR_EL1 = 0xc602, // 11 000 1100 0000 010
A64SysReg_RMR_EL2 = 0xe602, // 11 100 1100 0000 010
A64SysReg_RMR_EL3 = 0xf602, // 11 110 1100 0000 010
A64SysReg_CONTEXTIDR_EL1 = 0xc681, // 11 000 1101 0000 001
A64SysReg_TPIDR_EL0 = 0xde82, // 11 011 1101 0000 010
A64SysReg_TPIDR_EL2 = 0xe682, // 11 100 1101 0000 010
A64SysReg_TPIDR_EL3 = 0xf682, // 11 110 1101 0000 010
A64SysReg_TPIDRRO_EL0 = 0xde83, // 11 011 1101 0000 011
A64SysReg_TPIDR_EL1 = 0xc684, // 11 000 1101 0000 100
A64SysReg_CNTFRQ_EL0 = 0xdf00, // 11 011 1110 0000 000
A64SysReg_CNTVOFF_EL2 = 0xe703, // 11 100 1110 0000 011
A64SysReg_CNTKCTL_EL1 = 0xc708, // 11 000 1110 0001 000
A64SysReg_CNTHCTL_EL2 = 0xe708, // 11 100 1110 0001 000
A64SysReg_CNTP_TVAL_EL0 = 0xdf10, // 11 011 1110 0010 000
A64SysReg_CNTHP_TVAL_EL2 = 0xe710, // 11 100 1110 0010 000
A64SysReg_CNTPS_TVAL_EL1 = 0xff10, // 11 111 1110 0010 000
A64SysReg_CNTP_CTL_EL0 = 0xdf11, // 11 011 1110 0010 001
A64SysReg_CNTHP_CTL_EL2 = 0xe711, // 11 100 1110 0010 001
A64SysReg_CNTPS_CTL_EL1 = 0xff11, // 11 111 1110 0010 001
A64SysReg_CNTP_CVAL_EL0 = 0xdf12, // 11 011 1110 0010 010
A64SysReg_CNTHP_CVAL_EL2 = 0xe712, // 11 100 1110 0010 010
A64SysReg_CNTPS_CVAL_EL1 = 0xff12, // 11 111 1110 0010 010
A64SysReg_CNTV_TVAL_EL0 = 0xdf18, // 11 011 1110 0011 000
A64SysReg_CNTV_CTL_EL0 = 0xdf19, // 11 011 1110 0011 001
A64SysReg_CNTV_CVAL_EL0 = 0xdf1a, // 11 011 1110 0011 010
A64SysReg_PMEVCNTR0_EL0 = 0xdf40, // 11 011 1110 1000 000
A64SysReg_PMEVCNTR1_EL0 = 0xdf41, // 11 011 1110 1000 001
A64SysReg_PMEVCNTR2_EL0 = 0xdf42, // 11 011 1110 1000 010
A64SysReg_PMEVCNTR3_EL0 = 0xdf43, // 11 011 1110 1000 011
A64SysReg_PMEVCNTR4_EL0 = 0xdf44, // 11 011 1110 1000 100
A64SysReg_PMEVCNTR5_EL0 = 0xdf45, // 11 011 1110 1000 101
A64SysReg_PMEVCNTR6_EL0 = 0xdf46, // 11 011 1110 1000 110
A64SysReg_PMEVCNTR7_EL0 = 0xdf47, // 11 011 1110 1000 111
A64SysReg_PMEVCNTR8_EL0 = 0xdf48, // 11 011 1110 1001 000
A64SysReg_PMEVCNTR9_EL0 = 0xdf49, // 11 011 1110 1001 001
A64SysReg_PMEVCNTR10_EL0 = 0xdf4a, // 11 011 1110 1001 010
A64SysReg_PMEVCNTR11_EL0 = 0xdf4b, // 11 011 1110 1001 011
A64SysReg_PMEVCNTR12_EL0 = 0xdf4c, // 11 011 1110 1001 100
A64SysReg_PMEVCNTR13_EL0 = 0xdf4d, // 11 011 1110 1001 101
A64SysReg_PMEVCNTR14_EL0 = 0xdf4e, // 11 011 1110 1001 110
A64SysReg_PMEVCNTR15_EL0 = 0xdf4f, // 11 011 1110 1001 111
A64SysReg_PMEVCNTR16_EL0 = 0xdf50, // 11 011 1110 1010 000
A64SysReg_PMEVCNTR17_EL0 = 0xdf51, // 11 011 1110 1010 001
A64SysReg_PMEVCNTR18_EL0 = 0xdf52, // 11 011 1110 1010 010
A64SysReg_PMEVCNTR19_EL0 = 0xdf53, // 11 011 1110 1010 011
A64SysReg_PMEVCNTR20_EL0 = 0xdf54, // 11 011 1110 1010 100
A64SysReg_PMEVCNTR21_EL0 = 0xdf55, // 11 011 1110 1010 101
A64SysReg_PMEVCNTR22_EL0 = 0xdf56, // 11 011 1110 1010 110
A64SysReg_PMEVCNTR23_EL0 = 0xdf57, // 11 011 1110 1010 111
A64SysReg_PMEVCNTR24_EL0 = 0xdf58, // 11 011 1110 1011 000
A64SysReg_PMEVCNTR25_EL0 = 0xdf59, // 11 011 1110 1011 001
A64SysReg_PMEVCNTR26_EL0 = 0xdf5a, // 11 011 1110 1011 010
A64SysReg_PMEVCNTR27_EL0 = 0xdf5b, // 11 011 1110 1011 011
A64SysReg_PMEVCNTR28_EL0 = 0xdf5c, // 11 011 1110 1011 100
A64SysReg_PMEVCNTR29_EL0 = 0xdf5d, // 11 011 1110 1011 101
A64SysReg_PMEVCNTR30_EL0 = 0xdf5e, // 11 011 1110 1011 110
A64SysReg_PMCCFILTR_EL0 = 0xdf7f, // 11 011 1110 1111 111
A64SysReg_PMEVTYPER0_EL0 = 0xdf60, // 11 011 1110 1100 000
A64SysReg_PMEVTYPER1_EL0 = 0xdf61, // 11 011 1110 1100 001
A64SysReg_PMEVTYPER2_EL0 = 0xdf62, // 11 011 1110 1100 010
A64SysReg_PMEVTYPER3_EL0 = 0xdf63, // 11 011 1110 1100 011
A64SysReg_PMEVTYPER4_EL0 = 0xdf64, // 11 011 1110 1100 100
A64SysReg_PMEVTYPER5_EL0 = 0xdf65, // 11 011 1110 1100 101
A64SysReg_PMEVTYPER6_EL0 = 0xdf66, // 11 011 1110 1100 110
A64SysReg_PMEVTYPER7_EL0 = 0xdf67, // 11 011 1110 1100 111
A64SysReg_PMEVTYPER8_EL0 = 0xdf68, // 11 011 1110 1101 000
A64SysReg_PMEVTYPER9_EL0 = 0xdf69, // 11 011 1110 1101 001
A64SysReg_PMEVTYPER10_EL0 = 0xdf6a, // 11 011 1110 1101 010
A64SysReg_PMEVTYPER11_EL0 = 0xdf6b, // 11 011 1110 1101 011
A64SysReg_PMEVTYPER12_EL0 = 0xdf6c, // 11 011 1110 1101 100
A64SysReg_PMEVTYPER13_EL0 = 0xdf6d, // 11 011 1110 1101 101
A64SysReg_PMEVTYPER14_EL0 = 0xdf6e, // 11 011 1110 1101 110
A64SysReg_PMEVTYPER15_EL0 = 0xdf6f, // 11 011 1110 1101 111
A64SysReg_PMEVTYPER16_EL0 = 0xdf70, // 11 011 1110 1110 000
A64SysReg_PMEVTYPER17_EL0 = 0xdf71, // 11 011 1110 1110 001
A64SysReg_PMEVTYPER18_EL0 = 0xdf72, // 11 011 1110 1110 010
A64SysReg_PMEVTYPER19_EL0 = 0xdf73, // 11 011 1110 1110 011
A64SysReg_PMEVTYPER20_EL0 = 0xdf74, // 11 011 1110 1110 100
A64SysReg_PMEVTYPER21_EL0 = 0xdf75, // 11 011 1110 1110 101
A64SysReg_PMEVTYPER22_EL0 = 0xdf76, // 11 011 1110 1110 110
A64SysReg_PMEVTYPER23_EL0 = 0xdf77, // 11 011 1110 1110 111
A64SysReg_PMEVTYPER24_EL0 = 0xdf78, // 11 011 1110 1111 000
A64SysReg_PMEVTYPER25_EL0 = 0xdf79, // 11 011 1110 1111 001
A64SysReg_PMEVTYPER26_EL0 = 0xdf7a, // 11 011 1110 1111 010
A64SysReg_PMEVTYPER27_EL0 = 0xdf7b, // 11 011 1110 1111 011
A64SysReg_PMEVTYPER28_EL0 = 0xdf7c, // 11 011 1110 1111 100
A64SysReg_PMEVTYPER29_EL0 = 0xdf7d, // 11 011 1110 1111 101
A64SysReg_PMEVTYPER30_EL0 = 0xdf7e, // 11 011 1110 1111 110
// Trace registers
A64SysReg_TRCPRGCTLR = 0x8808, // 10 001 0000 0001 000
A64SysReg_TRCPROCSELR = 0x8810, // 10 001 0000 0010 000
A64SysReg_TRCCONFIGR = 0x8820, // 10 001 0000 0100 000
A64SysReg_TRCAUXCTLR = 0x8830, // 10 001 0000 0110 000
A64SysReg_TRCEVENTCTL0R = 0x8840, // 10 001 0000 1000 000
A64SysReg_TRCEVENTCTL1R = 0x8848, // 10 001 0000 1001 000
A64SysReg_TRCSTALLCTLR = 0x8858, // 10 001 0000 1011 000
A64SysReg_TRCTSCTLR = 0x8860, // 10 001 0000 1100 000
A64SysReg_TRCSYNCPR = 0x8868, // 10 001 0000 1101 000
A64SysReg_TRCCCCTLR = 0x8870, // 10 001 0000 1110 000
A64SysReg_TRCBBCTLR = 0x8878, // 10 001 0000 1111 000
A64SysReg_TRCTRACEIDR = 0x8801, // 10 001 0000 0000 001
A64SysReg_TRCQCTLR = 0x8809, // 10 001 0000 0001 001
A64SysReg_TRCVICTLR = 0x8802, // 10 001 0000 0000 010
A64SysReg_TRCVIIECTLR = 0x880a, // 10 001 0000 0001 010
A64SysReg_TRCVISSCTLR = 0x8812, // 10 001 0000 0010 010
A64SysReg_TRCVIPCSSCTLR = 0x881a, // 10 001 0000 0011 010
A64SysReg_TRCVDCTLR = 0x8842, // 10 001 0000 1000 010
A64SysReg_TRCVDSACCTLR = 0x884a, // 10 001 0000 1001 010
A64SysReg_TRCVDARCCTLR = 0x8852, // 10 001 0000 1010 010
A64SysReg_TRCSEQEVR0 = 0x8804, // 10 001 0000 0000 100
A64SysReg_TRCSEQEVR1 = 0x880c, // 10 001 0000 0001 100
A64SysReg_TRCSEQEVR2 = 0x8814, // 10 001 0000 0010 100
A64SysReg_TRCSEQRSTEVR = 0x8834, // 10 001 0000 0110 100
A64SysReg_TRCSEQSTR = 0x883c, // 10 001 0000 0111 100
A64SysReg_TRCEXTINSELR = 0x8844, // 10 001 0000 1000 100
A64SysReg_TRCCNTRLDVR0 = 0x8805, // 10 001 0000 0000 101
A64SysReg_TRCCNTRLDVR1 = 0x880d, // 10 001 0000 0001 101
A64SysReg_TRCCNTRLDVR2 = 0x8815, // 10 001 0000 0010 101
A64SysReg_TRCCNTRLDVR3 = 0x881d, // 10 001 0000 0011 101
A64SysReg_TRCCNTCTLR0 = 0x8825, // 10 001 0000 0100 101
A64SysReg_TRCCNTCTLR1 = 0x882d, // 10 001 0000 0101 101
A64SysReg_TRCCNTCTLR2 = 0x8835, // 10 001 0000 0110 101
A64SysReg_TRCCNTCTLR3 = 0x883d, // 10 001 0000 0111 101
A64SysReg_TRCCNTVR0 = 0x8845, // 10 001 0000 1000 101
A64SysReg_TRCCNTVR1 = 0x884d, // 10 001 0000 1001 101
A64SysReg_TRCCNTVR2 = 0x8855, // 10 001 0000 1010 101
A64SysReg_TRCCNTVR3 = 0x885d, // 10 001 0000 1011 101
A64SysReg_TRCIMSPEC0 = 0x8807, // 10 001 0000 0000 111
A64SysReg_TRCIMSPEC1 = 0x880f, // 10 001 0000 0001 111
A64SysReg_TRCIMSPEC2 = 0x8817, // 10 001 0000 0010 111
A64SysReg_TRCIMSPEC3 = 0x881f, // 10 001 0000 0011 111
A64SysReg_TRCIMSPEC4 = 0x8827, // 10 001 0000 0100 111
A64SysReg_TRCIMSPEC5 = 0x882f, // 10 001 0000 0101 111
A64SysReg_TRCIMSPEC6 = 0x8837, // 10 001 0000 0110 111
A64SysReg_TRCIMSPEC7 = 0x883f, // 10 001 0000 0111 111
A64SysReg_TRCRSCTLR2 = 0x8890, // 10 001 0001 0010 000
A64SysReg_TRCRSCTLR3 = 0x8898, // 10 001 0001 0011 000
A64SysReg_TRCRSCTLR4 = 0x88a0, // 10 001 0001 0100 000
A64SysReg_TRCRSCTLR5 = 0x88a8, // 10 001 0001 0101 000
A64SysReg_TRCRSCTLR6 = 0x88b0, // 10 001 0001 0110 000
A64SysReg_TRCRSCTLR7 = 0x88b8, // 10 001 0001 0111 000
A64SysReg_TRCRSCTLR8 = 0x88c0, // 10 001 0001 1000 000
A64SysReg_TRCRSCTLR9 = 0x88c8, // 10 001 0001 1001 000
A64SysReg_TRCRSCTLR10 = 0x88d0, // 10 001 0001 1010 000
A64SysReg_TRCRSCTLR11 = 0x88d8, // 10 001 0001 1011 000
A64SysReg_TRCRSCTLR12 = 0x88e0, // 10 001 0001 1100 000
A64SysReg_TRCRSCTLR13 = 0x88e8, // 10 001 0001 1101 000
A64SysReg_TRCRSCTLR14 = 0x88f0, // 10 001 0001 1110 000
A64SysReg_TRCRSCTLR15 = 0x88f8, // 10 001 0001 1111 000
A64SysReg_TRCRSCTLR16 = 0x8881, // 10 001 0001 0000 001
A64SysReg_TRCRSCTLR17 = 0x8889, // 10 001 0001 0001 001
A64SysReg_TRCRSCTLR18 = 0x8891, // 10 001 0001 0010 001
A64SysReg_TRCRSCTLR19 = 0x8899, // 10 001 0001 0011 001
A64SysReg_TRCRSCTLR20 = 0x88a1, // 10 001 0001 0100 001
A64SysReg_TRCRSCTLR21 = 0x88a9, // 10 001 0001 0101 001
A64SysReg_TRCRSCTLR22 = 0x88b1, // 10 001 0001 0110 001
A64SysReg_TRCRSCTLR23 = 0x88b9, // 10 001 0001 0111 001
A64SysReg_TRCRSCTLR24 = 0x88c1, // 10 001 0001 1000 001
A64SysReg_TRCRSCTLR25 = 0x88c9, // 10 001 0001 1001 001
A64SysReg_TRCRSCTLR26 = 0x88d1, // 10 001 0001 1010 001
A64SysReg_TRCRSCTLR27 = 0x88d9, // 10 001 0001 1011 001
A64SysReg_TRCRSCTLR28 = 0x88e1, // 10 001 0001 1100 001
A64SysReg_TRCRSCTLR29 = 0x88e9, // 10 001 0001 1101 001
A64SysReg_TRCRSCTLR30 = 0x88f1, // 10 001 0001 1110 001
A64SysReg_TRCRSCTLR31 = 0x88f9, // 10 001 0001 1111 001
A64SysReg_TRCSSCCR0 = 0x8882, // 10 001 0001 0000 010
A64SysReg_TRCSSCCR1 = 0x888a, // 10 001 0001 0001 010
A64SysReg_TRCSSCCR2 = 0x8892, // 10 001 0001 0010 010
A64SysReg_TRCSSCCR3 = 0x889a, // 10 001 0001 0011 010
A64SysReg_TRCSSCCR4 = 0x88a2, // 10 001 0001 0100 010
A64SysReg_TRCSSCCR5 = 0x88aa, // 10 001 0001 0101 010
A64SysReg_TRCSSCCR6 = 0x88b2, // 10 001 0001 0110 010
A64SysReg_TRCSSCCR7 = 0x88ba, // 10 001 0001 0111 010
A64SysReg_TRCSSCSR0 = 0x88c2, // 10 001 0001 1000 010
A64SysReg_TRCSSCSR1 = 0x88ca, // 10 001 0001 1001 010
A64SysReg_TRCSSCSR2 = 0x88d2, // 10 001 0001 1010 010
A64SysReg_TRCSSCSR3 = 0x88da, // 10 001 0001 1011 010
A64SysReg_TRCSSCSR4 = 0x88e2, // 10 001 0001 1100 010
A64SysReg_TRCSSCSR5 = 0x88ea, // 10 001 0001 1101 010
A64SysReg_TRCSSCSR6 = 0x88f2, // 10 001 0001 1110 010
A64SysReg_TRCSSCSR7 = 0x88fa, // 10 001 0001 1111 010
A64SysReg_TRCSSPCICR0 = 0x8883, // 10 001 0001 0000 011
A64SysReg_TRCSSPCICR1 = 0x888b, // 10 001 0001 0001 011
A64SysReg_TRCSSPCICR2 = 0x8893, // 10 001 0001 0010 011
A64SysReg_TRCSSPCICR3 = 0x889b, // 10 001 0001 0011 011
A64SysReg_TRCSSPCICR4 = 0x88a3, // 10 001 0001 0100 011
A64SysReg_TRCSSPCICR5 = 0x88ab, // 10 001 0001 0101 011
A64SysReg_TRCSSPCICR6 = 0x88b3, // 10 001 0001 0110 011
A64SysReg_TRCSSPCICR7 = 0x88bb, // 10 001 0001 0111 011
A64SysReg_TRCPDCR = 0x88a4, // 10 001 0001 0100 100
A64SysReg_TRCACVR0 = 0x8900, // 10 001 0010 0000 000
A64SysReg_TRCACVR1 = 0x8910, // 10 001 0010 0010 000
A64SysReg_TRCACVR2 = 0x8920, // 10 001 0010 0100 000
A64SysReg_TRCACVR3 = 0x8930, // 10 001 0010 0110 000
A64SysReg_TRCACVR4 = 0x8940, // 10 001 0010 1000 000
A64SysReg_TRCACVR5 = 0x8950, // 10 001 0010 1010 000
A64SysReg_TRCACVR6 = 0x8960, // 10 001 0010 1100 000
A64SysReg_TRCACVR7 = 0x8970, // 10 001 0010 1110 000
A64SysReg_TRCACVR8 = 0x8901, // 10 001 0010 0000 001
A64SysReg_TRCACVR9 = 0x8911, // 10 001 0010 0010 001
A64SysReg_TRCACVR10 = 0x8921, // 10 001 0010 0100 001
A64SysReg_TRCACVR11 = 0x8931, // 10 001 0010 0110 001
A64SysReg_TRCACVR12 = 0x8941, // 10 001 0010 1000 001
A64SysReg_TRCACVR13 = 0x8951, // 10 001 0010 1010 001
A64SysReg_TRCACVR14 = 0x8961, // 10 001 0010 1100 001
A64SysReg_TRCACVR15 = 0x8971, // 10 001 0010 1110 001
A64SysReg_TRCACATR0 = 0x8902, // 10 001 0010 0000 010
A64SysReg_TRCACATR1 = 0x8912, // 10 001 0010 0010 010
A64SysReg_TRCACATR2 = 0x8922, // 10 001 0010 0100 010
A64SysReg_TRCACATR3 = 0x8932, // 10 001 0010 0110 010
A64SysReg_TRCACATR4 = 0x8942, // 10 001 0010 1000 010
A64SysReg_TRCACATR5 = 0x8952, // 10 001 0010 1010 010
A64SysReg_TRCACATR6 = 0x8962, // 10 001 0010 1100 010
A64SysReg_TRCACATR7 = 0x8972, // 10 001 0010 1110 010
A64SysReg_TRCACATR8 = 0x8903, // 10 001 0010 0000 011
A64SysReg_TRCACATR9 = 0x8913, // 10 001 0010 0010 011
A64SysReg_TRCACATR10 = 0x8923, // 10 001 0010 0100 011
A64SysReg_TRCACATR11 = 0x8933, // 10 001 0010 0110 011
A64SysReg_TRCACATR12 = 0x8943, // 10 001 0010 1000 011
A64SysReg_TRCACATR13 = 0x8953, // 10 001 0010 1010 011
A64SysReg_TRCACATR14 = 0x8963, // 10 001 0010 1100 011
A64SysReg_TRCACATR15 = 0x8973, // 10 001 0010 1110 011
A64SysReg_TRCDVCVR0 = 0x8904, // 10 001 0010 0000 100
A64SysReg_TRCDVCVR1 = 0x8924, // 10 001 0010 0100 100
A64SysReg_TRCDVCVR2 = 0x8944, // 10 001 0010 1000 100
A64SysReg_TRCDVCVR3 = 0x8964, // 10 001 0010 1100 100
A64SysReg_TRCDVCVR4 = 0x8905, // 10 001 0010 0000 101
A64SysReg_TRCDVCVR5 = 0x8925, // 10 001 0010 0100 101
A64SysReg_TRCDVCVR6 = 0x8945, // 10 001 0010 1000 101
A64SysReg_TRCDVCVR7 = 0x8965, // 10 001 0010 1100 101
A64SysReg_TRCDVCMR0 = 0x8906, // 10 001 0010 0000 110
A64SysReg_TRCDVCMR1 = 0x8926, // 10 001 0010 0100 110
A64SysReg_TRCDVCMR2 = 0x8946, // 10 001 0010 1000 110
A64SysReg_TRCDVCMR3 = 0x8966, // 10 001 0010 1100 110
A64SysReg_TRCDVCMR4 = 0x8907, // 10 001 0010 0000 111
A64SysReg_TRCDVCMR5 = 0x8927, // 10 001 0010 0100 111
A64SysReg_TRCDVCMR6 = 0x8947, // 10 001 0010 1000 111
A64SysReg_TRCDVCMR7 = 0x8967, // 10 001 0010 1100 111
A64SysReg_TRCCIDCVR0 = 0x8980, // 10 001 0011 0000 000
A64SysReg_TRCCIDCVR1 = 0x8990, // 10 001 0011 0010 000
A64SysReg_TRCCIDCVR2 = 0x89a0, // 10 001 0011 0100 000
A64SysReg_TRCCIDCVR3 = 0x89b0, // 10 001 0011 0110 000
A64SysReg_TRCCIDCVR4 = 0x89c0, // 10 001 0011 1000 000
A64SysReg_TRCCIDCVR5 = 0x89d0, // 10 001 0011 1010 000
A64SysReg_TRCCIDCVR6 = 0x89e0, // 10 001 0011 1100 000
A64SysReg_TRCCIDCVR7 = 0x89f0, // 10 001 0011 1110 000
A64SysReg_TRCVMIDCVR0 = 0x8981, // 10 001 0011 0000 001
A64SysReg_TRCVMIDCVR1 = 0x8991, // 10 001 0011 0010 001
A64SysReg_TRCVMIDCVR2 = 0x89a1, // 10 001 0011 0100 001
A64SysReg_TRCVMIDCVR3 = 0x89b1, // 10 001 0011 0110 001
A64SysReg_TRCVMIDCVR4 = 0x89c1, // 10 001 0011 1000 001
A64SysReg_TRCVMIDCVR5 = 0x89d1, // 10 001 0011 1010 001
A64SysReg_TRCVMIDCVR6 = 0x89e1, // 10 001 0011 1100 001
A64SysReg_TRCVMIDCVR7 = 0x89f1, // 10 001 0011 1110 001
A64SysReg_TRCCIDCCTLR0 = 0x8982, // 10 001 0011 0000 010
A64SysReg_TRCCIDCCTLR1 = 0x898a, // 10 001 0011 0001 010
A64SysReg_TRCVMIDCCTLR0 = 0x8992, // 10 001 0011 0010 010
A64SysReg_TRCVMIDCCTLR1 = 0x899a, // 10 001 0011 0011 010
A64SysReg_TRCITCTRL = 0x8b84, // 10 001 0111 0000 100
A64SysReg_TRCCLAIMSET = 0x8bc6, // 10 001 0111 1000 110
A64SysReg_TRCCLAIMCLR = 0x8bce, // 10 001 0111 1001 110
// GICv3 registers
A64SysReg_ICC_BPR1_EL1 = 0xc663, // 11 000 1100 1100 011
A64SysReg_ICC_BPR0_EL1 = 0xc643, // 11 000 1100 1000 011
A64SysReg_ICC_PMR_EL1 = 0xc230, // 11 000 0100 0110 000
A64SysReg_ICC_CTLR_EL1 = 0xc664, // 11 000 1100 1100 100
A64SysReg_ICC_CTLR_EL3 = 0xf664, // 11 110 1100 1100 100
A64SysReg_ICC_SRE_EL1 = 0xc665, // 11 000 1100 1100 101
A64SysReg_ICC_SRE_EL2 = 0xe64d, // 11 100 1100 1001 101
A64SysReg_ICC_SRE_EL3 = 0xf665, // 11 110 1100 1100 101
A64SysReg_ICC_IGRPEN0_EL1 = 0xc666, // 11 000 1100 1100 110
A64SysReg_ICC_IGRPEN1_EL1 = 0xc667, // 11 000 1100 1100 111
A64SysReg_ICC_IGRPEN1_EL3 = 0xf667, // 11 110 1100 1100 111
A64SysReg_ICC_SEIEN_EL1 = 0xc668, // 11 000 1100 1101 000
A64SysReg_ICC_AP0R0_EL1 = 0xc644, // 11 000 1100 1000 100
A64SysReg_ICC_AP0R1_EL1 = 0xc645, // 11 000 1100 1000 101
A64SysReg_ICC_AP0R2_EL1 = 0xc646, // 11 000 1100 1000 110
A64SysReg_ICC_AP0R3_EL1 = 0xc647, // 11 000 1100 1000 111
A64SysReg_ICC_AP1R0_EL1 = 0xc648, // 11 000 1100 1001 000
A64SysReg_ICC_AP1R1_EL1 = 0xc649, // 11 000 1100 1001 001
A64SysReg_ICC_AP1R2_EL1 = 0xc64a, // 11 000 1100 1001 010
A64SysReg_ICC_AP1R3_EL1 = 0xc64b, // 11 000 1100 1001 011
A64SysReg_ICH_AP0R0_EL2 = 0xe640, // 11 100 1100 1000 000
A64SysReg_ICH_AP0R1_EL2 = 0xe641, // 11 100 1100 1000 001
A64SysReg_ICH_AP0R2_EL2 = 0xe642, // 11 100 1100 1000 010
A64SysReg_ICH_AP0R3_EL2 = 0xe643, // 11 100 1100 1000 011
A64SysReg_ICH_AP1R0_EL2 = 0xe648, // 11 100 1100 1001 000
A64SysReg_ICH_AP1R1_EL2 = 0xe649, // 11 100 1100 1001 001
A64SysReg_ICH_AP1R2_EL2 = 0xe64a, // 11 100 1100 1001 010
A64SysReg_ICH_AP1R3_EL2 = 0xe64b, // 11 100 1100 1001 011
A64SysReg_ICH_HCR_EL2 = 0xe658, // 11 100 1100 1011 000
A64SysReg_ICH_MISR_EL2 = 0xe65a, // 11 100 1100 1011 010
A64SysReg_ICH_VMCR_EL2 = 0xe65f, // 11 100 1100 1011 111
A64SysReg_ICH_VSEIR_EL2 = 0xe64c, // 11 100 1100 1001 100
A64SysReg_ICH_LR0_EL2 = 0xe660, // 11 100 1100 1100 000
A64SysReg_ICH_LR1_EL2 = 0xe661, // 11 100 1100 1100 001
A64SysReg_ICH_LR2_EL2 = 0xe662, // 11 100 1100 1100 010
A64SysReg_ICH_LR3_EL2 = 0xe663, // 11 100 1100 1100 011
A64SysReg_ICH_LR4_EL2 = 0xe664, // 11 100 1100 1100 100
A64SysReg_ICH_LR5_EL2 = 0xe665, // 11 100 1100 1100 101
A64SysReg_ICH_LR6_EL2 = 0xe666, // 11 100 1100 1100 110
A64SysReg_ICH_LR7_EL2 = 0xe667, // 11 100 1100 1100 111
A64SysReg_ICH_LR8_EL2 = 0xe668, // 11 100 1100 1101 000
A64SysReg_ICH_LR9_EL2 = 0xe669, // 11 100 1100 1101 001
A64SysReg_ICH_LR10_EL2 = 0xe66a, // 11 100 1100 1101 010
A64SysReg_ICH_LR11_EL2 = 0xe66b, // 11 100 1100 1101 011
A64SysReg_ICH_LR12_EL2 = 0xe66c, // 11 100 1100 1101 100
A64SysReg_ICH_LR13_EL2 = 0xe66d, // 11 100 1100 1101 101
A64SysReg_ICH_LR14_EL2 = 0xe66e, // 11 100 1100 1101 110
A64SysReg_ICH_LR15_EL2 = 0xe66f // 11 100 1100 1101 111
};
// Cyclone specific system registers
enum A64CycloneSysRegValues {
A64SysReg_CPM_IOACC_CTL_EL3 = 0xff90
};
enum A64TLBIValues {
A64TLBI_Invalid = -1, // Op0 Op1 CRn CRm Op2
A64TLBI_IPAS2E1IS = 0x6401, // 01 100 1000 0000 001
A64TLBI_IPAS2LE1IS = 0x6405, // 01 100 1000 0000 101
A64TLBI_VMALLE1IS = 0x4418, // 01 000 1000 0011 000
A64TLBI_ALLE2IS = 0x6418, // 01 100 1000 0011 000
A64TLBI_ALLE3IS = 0x7418, // 01 110 1000 0011 000
A64TLBI_VAE1IS = 0x4419, // 01 000 1000 0011 001
A64TLBI_VAE2IS = 0x6419, // 01 100 1000 0011 001
A64TLBI_VAE3IS = 0x7419, // 01 110 1000 0011 001
A64TLBI_ASIDE1IS = 0x441a, // 01 000 1000 0011 010
A64TLBI_VAAE1IS = 0x441b, // 01 000 1000 0011 011
A64TLBI_ALLE1IS = 0x641c, // 01 100 1000 0011 100
A64TLBI_VALE1IS = 0x441d, // 01 000 1000 0011 101
A64TLBI_VALE2IS = 0x641d, // 01 100 1000 0011 101
A64TLBI_VALE3IS = 0x741d, // 01 110 1000 0011 101
A64TLBI_VMALLS12E1IS = 0x641e, // 01 100 1000 0011 110
A64TLBI_VAALE1IS = 0x441f, // 01 000 1000 0011 111
A64TLBI_IPAS2E1 = 0x6421, // 01 100 1000 0100 001
A64TLBI_IPAS2LE1 = 0x6425, // 01 100 1000 0100 101
A64TLBI_VMALLE1 = 0x4438, // 01 000 1000 0111 000
A64TLBI_ALLE2 = 0x6438, // 01 100 1000 0111 000
A64TLBI_ALLE3 = 0x7438, // 01 110 1000 0111 000
A64TLBI_VAE1 = 0x4439, // 01 000 1000 0111 001
A64TLBI_VAE2 = 0x6439, // 01 100 1000 0111 001
A64TLBI_VAE3 = 0x7439, // 01 110 1000 0111 001
A64TLBI_ASIDE1 = 0x443a, // 01 000 1000 0111 010
A64TLBI_VAAE1 = 0x443b, // 01 000 1000 0111 011
A64TLBI_ALLE1 = 0x643c, // 01 100 1000 0111 100
A64TLBI_VALE1 = 0x443d, // 01 000 1000 0111 101
A64TLBI_VALE2 = 0x643d, // 01 100 1000 0111 101
A64TLBI_VALE3 = 0x743d, // 01 110 1000 0111 101
A64TLBI_VMALLS12E1 = 0x643e, // 01 100 1000 0111 110
A64TLBI_VAALE1 = 0x443f // 01 000 1000 0111 111
};
bool A64Imms_isLogicalImmBits(unsigned RegWidth, uint32_t Bits, uint64_t *Imm);
char *A64NamedImmMapper_toString(A64NamedImmMapper *N, uint32_t Value, bool *Valid);
uint32_t A64NamedImmMapper_fromString(A64NamedImmMapper *N, char *Name, bool *Valid);
bool A64NamedImmMapper_validImm(A64NamedImmMapper *N, uint32_t Value);
void A64SysRegMapper_toString(A64SysRegMapper *S, uint32_t Bits, bool *Valid, char *result);
#endif

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/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
#ifndef CS_AARCH64_DISASSEMBLER_H
#define CS_AARCH64_DISASSEMBLER_H
#include <stdint.h>
#include "../../include/capstone.h"
#include "../../MCRegisterInfo.h"
#include "../../MCInst.h"
void AArch64_init(MCRegisterInfo *MRI);
bool AArch64_getInstruction(csh ud, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address, void *info);
#endif

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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|*Subtarget Enumeration Source Fragment *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
#ifdef GET_SUBTARGETINFO_ENUM
#undef GET_SUBTARGETINFO_ENUM
enum {
AArch64_FeatureCRC = 1ULL << 0,
AArch64_FeatureCrypto = 1ULL << 1,
AArch64_FeatureFPARMv8 = 1ULL << 2,
AArch64_FeatureNEON = 1ULL << 3,
AArch64_FeatureZCRegMove = 1ULL << 4,
AArch64_FeatureZCZeroing = 1ULL << 5,
AArch64_ProcA53 = 1ULL << 6,
AArch64_ProcA57 = 1ULL << 7,
AArch64_ProcCyclone = 1ULL << 8
};
#endif // GET_SUBTARGETINFO_ENUM

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//===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This class prints an AArch64 MCInst to a .s file.
//
//===----------------------------------------------------------------------===//
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
#ifndef CS_LLVM_AARCH64INSTPRINTER_H
#define CS_LLVM_AARCH64INSTPRINTER_H
#include "../../MCInst.h"
#include "../../MCRegisterInfo.h"
#include "../../SStream.h"
void AArch64_printInst(MCInst *MI, SStream *O, void *);
void AArch64_post_printer(csh handle, cs_insn *pub_insn, char *insn_asm, MCInst *mci);
#endif

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/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
#ifndef CS_ARM64_MAP_H
#define CS_ARM64_MAP_H
#include "../../include/capstone.h"
// return name of regiser in friendly string
const char *AArch64_reg_name(csh handle, unsigned int reg);
// given internal insn id, return public instruction info
void AArch64_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
const char *AArch64_insn_name(csh handle, unsigned int id);
const char *AArch64_group_name(csh handle, unsigned int id);
// map instruction name to public instruction ID
arm64_reg AArch64_map_insn(const char *name);
// map internal vregister to public register
arm64_reg AArch64_map_vregister(unsigned int r);
void arm64_op_addReg(MCInst *MI, int reg);
void arm64_op_addVectorArrSpecifier(MCInst * MI, int sp);
void arm64_op_addVectorElementSizeSpecifier(MCInst * MI, int sp);
void arm64_op_addFP(MCInst *MI, float fp);
void arm64_op_addImm(MCInst *MI, int64_t imm);
#endif

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/* Capstone Disassembly Engine */
/* By Dang Hoang Vu <danghvu@gmail.com> 2013 */
#ifdef CAPSTONE_HAS_ARM64
#include "../../utils.h"
#include "../../MCRegisterInfo.h"
#include "AArch64Disassembler.h"
#include "AArch64InstPrinter.h"
#include "AArch64Mapping.h"
static cs_err init(cs_struct *ud)
{
MCRegisterInfo *mri;
// verify if requested mode is valid
if (ud->mode & ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_ARM | CS_MODE_BIG_ENDIAN))
return CS_ERR_MODE;
mri = cs_mem_malloc(sizeof(*mri));
AArch64_init(mri);
ud->printer = AArch64_printInst;
ud->printer_info = mri;
ud->getinsn_info = mri;
ud->disasm = AArch64_getInstruction;
ud->reg_name = AArch64_reg_name;
ud->insn_id = AArch64_get_insn_id;
ud->insn_name = AArch64_insn_name;
ud->group_name = AArch64_group_name;
ud->post_printer = AArch64_post_printer;
return CS_ERR_OK;
}
static cs_err option(cs_struct *handle, cs_opt_type type, size_t value)
{
return CS_ERR_OK;
}
static void destroy(cs_struct *handle)
{
}
void AArch64_enable(void)
{
arch_init[CS_ARCH_ARM64] = init;
arch_option[CS_ARCH_ARM64] = option;
arch_destroy[CS_ARCH_ARM64] = destroy;
// support this arch
all_arch |= (1 << CS_ARCH_ARM64);
}
#endif

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//===-- ARMAddressingModes.h - ARM Addressing Modes -------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the ARM addressing mode implementation stuff.
//
//===----------------------------------------------------------------------===//
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
#ifndef CS_LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
#define CS_LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
#include "../../include/platform.h"
#include "../../MathExtras.h"
/// ARM_AM - ARM Addressing Mode Stuff
typedef enum ARM_AM_ShiftOpc {
ARM_AM_no_shift = 0,
ARM_AM_asr,
ARM_AM_lsl,
ARM_AM_lsr,
ARM_AM_ror,
ARM_AM_rrx
} ARM_AM_ShiftOpc;
typedef enum ARM_AM_AddrOpc {
ARM_AM_sub = 0,
ARM_AM_add
} ARM_AM_AddrOpc;
static inline char *ARM_AM_getAddrOpcStr(ARM_AM_AddrOpc Op)
{
return Op == ARM_AM_sub ? "-" : "";
}
static inline char *ARM_AM_getShiftOpcStr(ARM_AM_ShiftOpc Op)
{
switch (Op) {
default: return ""; //llvm_unreachable("Unknown shift opc!");
case ARM_AM_asr: return "asr";
case ARM_AM_lsl: return "lsl";
case ARM_AM_lsr: return "lsr";
case ARM_AM_ror: return "ror";
case ARM_AM_rrx: return "rrx";
}
}
static inline unsigned ARM_AM_getShiftOpcEncoding(ARM_AM_ShiftOpc Op)
{
switch (Op) {
default: return (unsigned int)-1; //llvm_unreachable("Unknown shift opc!");
case ARM_AM_asr: return 2;
case ARM_AM_lsl: return 0;
case ARM_AM_lsr: return 1;
case ARM_AM_ror: return 3;
}
}
typedef enum ARM_AM_AMSubMode {
ARM_AM_bad_am_submode = 0,
ARM_AM_ia,
ARM_AM_ib,
ARM_AM_da,
ARM_AM_db
} ARM_AM_AMSubMode;
static inline const char *ARM_AM_getAMSubModeStr(ARM_AM_AMSubMode Mode)
{
switch (Mode) {
default: return "";
case ARM_AM_ia: return "ia";
case ARM_AM_ib: return "ib";
case ARM_AM_da: return "da";
case ARM_AM_db: return "db";
}
}
/// rotr32 - Rotate a 32-bit unsigned value right by a specified # bits.
///
static inline unsigned rotr32(unsigned Val, unsigned Amt)
{
//assert(Amt < 32 && "Invalid rotate amount");
return (Val >> Amt) | (Val << ((32-Amt)&31));
}
/// rotl32 - Rotate a 32-bit unsigned value left by a specified # bits.
///
static inline unsigned rotl32(unsigned Val, unsigned Amt)
{
//assert(Amt < 32 && "Invalid rotate amount");
return (Val << Amt) | (Val >> ((32-Amt)&31));
}
//===--------------------------------------------------------------------===//
// Addressing Mode #1: shift_operand with registers
//===--------------------------------------------------------------------===//
//
// This 'addressing mode' is used for arithmetic instructions. It can
// represent things like:
// reg
// reg [asr|lsl|lsr|ror|rrx] reg
// reg [asr|lsl|lsr|ror|rrx] imm
//
// This is stored three operands [rega, regb, opc]. The first is the base
// reg, the second is the shift amount (or reg0 if not present or imm). The
// third operand encodes the shift opcode and the imm if a reg isn't present.
//
static inline unsigned getSORegOpc(ARM_AM_ShiftOpc ShOp, unsigned Imm)
{
return ShOp | (Imm << 3);
}
static inline unsigned getSORegOffset(unsigned Op)
{
return Op >> 3;
}
static inline ARM_AM_ShiftOpc ARM_AM_getSORegShOp(unsigned Op)
{
return (ARM_AM_ShiftOpc)(Op & 7);
}
/// getSOImmValImm - Given an encoded imm field for the reg/imm form, return
/// the 8-bit imm value.
static inline unsigned getSOImmValImm(unsigned Imm)
{
return Imm & 0xFF;
}
/// getSOImmValRot - Given an encoded imm field for the reg/imm form, return
/// the rotate amount.
static inline unsigned getSOImmValRot(unsigned Imm)
{
return (Imm >> 8) * 2;
}
/// getSOImmValRotate - Try to handle Imm with an immediate shifter operand,
/// computing the rotate amount to use. If this immediate value cannot be
/// handled with a single shifter-op, determine a good rotate amount that will
/// take a maximal chunk of bits out of the immediate.
static inline unsigned getSOImmValRotate(unsigned Imm)
{
unsigned TZ, RotAmt;
// 8-bit (or less) immediates are trivially shifter_operands with a rotate
// of zero.
if ((Imm & ~255U) == 0) return 0;
// Use CTZ to compute the rotate amount.
TZ = CountTrailingZeros_32(Imm);
// Rotate amount must be even. Something like 0x200 must be rotated 8 bits,
// not 9.
RotAmt = TZ & ~1;
// If we can handle this spread, return it.
if ((rotr32(Imm, RotAmt) & ~255U) == 0)
return (32-RotAmt)&31; // HW rotates right, not left.
// For values like 0xF000000F, we should ignore the low 6 bits, then
// retry the hunt.
if (Imm & 63U) {
unsigned TZ2 = CountTrailingZeros_32(Imm & ~63U);
unsigned RotAmt2 = TZ2 & ~1;
if ((rotr32(Imm, RotAmt2) & ~255U) == 0)
return (32-RotAmt2)&31; // HW rotates right, not left.
}
// Otherwise, we have no way to cover this span of bits with a single
// shifter_op immediate. Return a chunk of bits that will be useful to
// handle.
return (32-RotAmt)&31; // HW rotates right, not left.
}
/// getSOImmVal - Given a 32-bit immediate, if it is something that can fit
/// into an shifter_operand immediate operand, return the 12-bit encoding for
/// it. If not, return -1.
static inline int getSOImmVal(unsigned Arg)
{
unsigned RotAmt;
// 8-bit (or less) immediates are trivially shifter_operands with a rotate
// of zero.
if ((Arg & ~255U) == 0) return Arg;
RotAmt = getSOImmValRotate(Arg);
// If this cannot be handled with a single shifter_op, bail out.
if (rotr32(~255U, RotAmt) & Arg)
return -1;
// Encode this correctly.
return rotl32(Arg, RotAmt) | ((RotAmt>>1) << 8);
}
/// isSOImmTwoPartVal - Return true if the specified value can be obtained by
/// or'ing together two SOImmVal's.
static inline bool isSOImmTwoPartVal(unsigned V)
{
// If this can be handled with a single shifter_op, bail out.
V = rotr32(~255U, getSOImmValRotate(V)) & V;
if (V == 0)
return false;
// If this can be handled with two shifter_op's, accept.
V = rotr32(~255U, getSOImmValRotate(V)) & V;
return V == 0;
}
/// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal,
/// return the first chunk of it.
static inline unsigned getSOImmTwoPartFirst(unsigned V)
{
return rotr32(255U, getSOImmValRotate(V)) & V;
}
/// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal,
/// return the second chunk of it.
static inline unsigned getSOImmTwoPartSecond(unsigned V)
{
// Mask out the first hunk.
V = rotr32(~255U, getSOImmValRotate(V)) & V;
// Take what's left.
//assert(V == (rotr32(255U, getSOImmValRotate(V)) & V));
return V;
}
/// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed
/// by a left shift. Returns the shift amount to use.
static inline unsigned getThumbImmValShift(unsigned Imm)
{
// 8-bit (or less) immediates are trivially immediate operand with a shift
// of zero.
if ((Imm & ~255U) == 0) return 0;
// Use CTZ to compute the shift amount.
return CountTrailingZeros_32(Imm);
}
/// isThumbImmShiftedVal - Return true if the specified value can be obtained
/// by left shifting a 8-bit immediate.
static inline bool isThumbImmShiftedVal(unsigned V)
{
// If this can be handled with
V = (~255U << getThumbImmValShift(V)) & V;
return V == 0;
}
/// getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed
/// by a left shift. Returns the shift amount to use.
static inline unsigned getThumbImm16ValShift(unsigned Imm)
{
// 16-bit (or less) immediates are trivially immediate operand with a shift
// of zero.
if ((Imm & ~65535U) == 0) return 0;
// Use CTZ to compute the shift amount.
return CountTrailingZeros_32(Imm);
}
/// isThumbImm16ShiftedVal - Return true if the specified value can be
/// obtained by left shifting a 16-bit immediate.
static inline bool isThumbImm16ShiftedVal(unsigned V)
{
// If this can be handled with
V = (~65535U << getThumbImm16ValShift(V)) & V;
return V == 0;
}
/// getThumbImmNonShiftedVal - If V is a value that satisfies
/// isThumbImmShiftedVal, return the non-shiftd value.
static inline unsigned getThumbImmNonShiftedVal(unsigned V)
{
return V >> getThumbImmValShift(V);
}
/// getT2SOImmValSplat - Return the 12-bit encoded representation
/// if the specified value can be obtained by splatting the low 8 bits
/// into every other byte or every byte of a 32-bit value. i.e.,
/// 00000000 00000000 00000000 abcdefgh control = 0
/// 00000000 abcdefgh 00000000 abcdefgh control = 1
/// abcdefgh 00000000 abcdefgh 00000000 control = 2
/// abcdefgh abcdefgh abcdefgh abcdefgh control = 3
/// Return -1 if none of the above apply.
/// See ARM Reference Manual A6.3.2.
static inline int getT2SOImmValSplatVal(unsigned V)
{
unsigned u, Vs, Imm;
// control = 0
if ((V & 0xffffff00) == 0)
return V;
// If the value is zeroes in the first byte, just shift those off
Vs = ((V & 0xff) == 0) ? V >> 8 : V;
// Any passing value only has 8 bits of payload, splatted across the word
Imm = Vs & 0xff;
// Likewise, any passing values have the payload splatted into the 3rd byte
u = Imm | (Imm << 16);
// control = 1 or 2
if (Vs == u)
return (((Vs == V) ? 1 : 2) << 8) | Imm;
// control = 3
if (Vs == (u | (u << 8)))
return (3 << 8) | Imm;
return -1;
}
/// getT2SOImmValRotateVal - Return the 12-bit encoded representation if the
/// specified value is a rotated 8-bit value. Return -1 if no rotation
/// encoding is possible.
/// See ARM Reference Manual A6.3.2.
static inline int getT2SOImmValRotateVal(unsigned V)
{
unsigned RotAmt = CountLeadingZeros_32(V);
if (RotAmt >= 24)
return -1;
// If 'Arg' can be handled with a single shifter_op return the value.
if ((rotr32(0xff000000U, RotAmt) & V) == V)
return (rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7);
return -1;
}
/// getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit
/// into a Thumb-2 shifter_operand immediate operand, return the 12-bit
/// encoding for it. If not, return -1.
/// See ARM Reference Manual A6.3.2.
static inline int getT2SOImmVal(unsigned Arg)
{
int Rot;
// If 'Arg' is an 8-bit splat, then get the encoded value.
int Splat = getT2SOImmValSplatVal(Arg);
if (Splat != -1)
return Splat;
// If 'Arg' can be handled with a single shifter_op return the value.
Rot = getT2SOImmValRotateVal(Arg);
if (Rot != -1)
return Rot;
return -1;
}
static inline unsigned getT2SOImmValRotate(unsigned V)
{
unsigned RotAmt;
if ((V & ~255U) == 0)
return 0;
// Use CTZ to compute the rotate amount.
RotAmt = CountTrailingZeros_32(V);
return (32 - RotAmt) & 31;
}
static inline bool isT2SOImmTwoPartVal (unsigned Imm)
{
unsigned V = Imm;
// Passing values can be any combination of splat values and shifter
// values. If this can be handled with a single shifter or splat, bail
// out. Those should be handled directly, not with a two-part val.
if (getT2SOImmValSplatVal(V) != -1)
return false;
V = rotr32 (~255U, getT2SOImmValRotate(V)) & V;
if (V == 0)
return false;
// If this can be handled as an immediate, accept.
if (getT2SOImmVal(V) != -1) return true;
// Likewise, try masking out a splat value first.
V = Imm;
if (getT2SOImmValSplatVal(V & 0xff00ff00U) != -1)
V &= ~0xff00ff00U;
else if (getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1)
V &= ~0x00ff00ffU;
// If what's left can be handled as an immediate, accept.
if (getT2SOImmVal(V) != -1) return true;
// Otherwise, do not accept.
return false;
}
static inline unsigned getT2SOImmTwoPartFirst(unsigned Imm)
{
//assert (isT2SOImmTwoPartVal(Imm) &&
// "Immedate cannot be encoded as two part immediate!");
// Try a shifter operand as one part
unsigned V = rotr32 (~(unsigned int)255, getT2SOImmValRotate(Imm)) & Imm;
// If the rest is encodable as an immediate, then return it.
if (getT2SOImmVal(V) != -1) return V;
// Try masking out a splat value first.
if (getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1)
return Imm & 0xff00ff00U;
// The other splat is all that's left as an option.
//assert (getT2SOImmValSplatVal(Imm & 0x00ff00ffU) != -1);
return Imm & 0x00ff00ffU;
}
static inline unsigned getT2SOImmTwoPartSecond(unsigned Imm)
{
// Mask out the first hunk
Imm ^= getT2SOImmTwoPartFirst(Imm);
// Return what's left
//assert (getT2SOImmVal(Imm) != -1 &&
// "Unable to encode second part of T2 two part SO immediate");
return Imm;
}
//===--------------------------------------------------------------------===//
// Addressing Mode #2
//===--------------------------------------------------------------------===//
//
// This is used for most simple load/store instructions.
//
// addrmode2 := reg +/- reg shop imm
// addrmode2 := reg +/- imm12
//
// The first operand is always a Reg. The second operand is a reg if in
// reg/reg form, otherwise it's reg#0. The third field encodes the operation
// in bit 12, the immediate in bits 0-11, and the shift op in 13-15. The
// fourth operand 16-17 encodes the index mode.
//
// If this addressing mode is a frame index (before prolog/epilog insertion
// and code rewriting), this operand will have the form: FI#, reg0, <offs>
// with no shift amount for the frame offset.
//
static inline unsigned ARM_AM_getAM2Opc(ARM_AM_AddrOpc Opc, unsigned Imm12, ARM_AM_ShiftOpc SO,
unsigned IdxMode)
{
//assert(Imm12 < (1 << 12) && "Imm too large!");
bool isSub = Opc == ARM_AM_sub;
return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ;
}
static inline unsigned getAM2Offset(unsigned AM2Opc)
{
return AM2Opc & ((1 << 12)-1);
}
static inline ARM_AM_AddrOpc getAM2Op(unsigned AM2Opc)
{
return ((AM2Opc >> 12) & 1) ? ARM_AM_sub : ARM_AM_add;
}
static inline ARM_AM_ShiftOpc getAM2ShiftOpc(unsigned AM2Opc)
{
return (ARM_AM_ShiftOpc)((AM2Opc >> 13) & 7);
}
static inline unsigned getAM2IdxMode(unsigned AM2Opc)
{
return (AM2Opc >> 16);
}
//===--------------------------------------------------------------------===//
// Addressing Mode #3
//===--------------------------------------------------------------------===//
//
// This is used for sign-extending loads, and load/store-pair instructions.
//
// addrmode3 := reg +/- reg
// addrmode3 := reg +/- imm8
//
// The first operand is always a Reg. The second operand is a reg if in
// reg/reg form, otherwise it's reg#0. The third field encodes the operation
// in bit 8, the immediate in bits 0-7. The fourth operand 9-10 encodes the
// index mode.
/// getAM3Opc - This function encodes the addrmode3 opc field.
static inline unsigned getAM3Opc(ARM_AM_AddrOpc Opc, unsigned char Offset,
unsigned IdxMode)
{
bool isSub = Opc == ARM_AM_sub;
return ((int)isSub << 8) | Offset | (IdxMode << 9);
}
static inline unsigned char getAM3Offset(unsigned AM3Opc)
{
return AM3Opc & 0xFF;
}
static inline ARM_AM_AddrOpc getAM3Op(unsigned AM3Opc)
{
return ((AM3Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add;
}
static inline unsigned getAM3IdxMode(unsigned AM3Opc)
{
return (AM3Opc >> 9);
}
//===--------------------------------------------------------------------===//
// Addressing Mode #4
//===--------------------------------------------------------------------===//
//
// This is used for load / store multiple instructions.
//
// addrmode4 := reg, <mode>
//
// The four modes are:
// IA - Increment after
// IB - Increment before
// DA - Decrement after
// DB - Decrement before
// For VFP instructions, only the IA and DB modes are valid.
static inline ARM_AM_AMSubMode getAM4SubMode(unsigned Mode)
{
return (ARM_AM_AMSubMode)(Mode & 0x7);
}
static inline unsigned getAM4ModeImm(ARM_AM_AMSubMode SubMode)
{
return (int)SubMode;
}
//===--------------------------------------------------------------------===//
// Addressing Mode #5
//===--------------------------------------------------------------------===//
//
// This is used for coprocessor instructions, such as FP load/stores.
//
// addrmode5 := reg +/- imm8*4
//
// The first operand is always a Reg. The second operand encodes the
// operation in bit 8 and the immediate in bits 0-7.
/// getAM5Opc - This function encodes the addrmode5 opc field.
static inline unsigned ARM_AM_getAM5Opc(ARM_AM_AddrOpc Opc, unsigned char Offset)
{
bool isSub = Opc == ARM_AM_sub;
return ((int)isSub << 8) | Offset;
}
static inline unsigned char ARM_AM_getAM5Offset(unsigned AM5Opc)
{
return AM5Opc & 0xFF;
}
static inline ARM_AM_AddrOpc ARM_AM_getAM5Op(unsigned AM5Opc)
{
return ((AM5Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add;
}
//===--------------------------------------------------------------------===//
// Addressing Mode #6
//===--------------------------------------------------------------------===//
//
// This is used for NEON load / store instructions.
//
// addrmode6 := reg with optional alignment
//
// This is stored in two operands [regaddr, align]. The first is the
// address register. The second operand is the value of the alignment
// specifier in bytes or zero if no explicit alignment.
// Valid alignments depend on the specific instruction.
//===--------------------------------------------------------------------===//
// NEON Modified Immediates
//===--------------------------------------------------------------------===//
//
// Several NEON instructions (e.g., VMOV) take a "modified immediate"
// vector operand, where a small immediate encoded in the instruction
// specifies a full NEON vector value. These modified immediates are
// represented here as encoded integers. The low 8 bits hold the immediate
// value; bit 12 holds the "Op" field of the instruction, and bits 11-8 hold
// the "Cmode" field of the instruction. The interfaces below treat the
// Op and Cmode values as a single 5-bit value.
static inline unsigned createNEONModImm(unsigned OpCmode, unsigned Val)
{
return (OpCmode << 8) | Val;
}
static inline unsigned getNEONModImmOpCmode(unsigned ModImm)
{
return (ModImm >> 8) & 0x1f;
}
static inline unsigned getNEONModImmVal(unsigned ModImm)
{
return ModImm & 0xff;
}
/// decodeNEONModImm - Decode a NEON modified immediate value into the
/// element value and the element size in bits. (If the element size is
/// smaller than the vector, it is splatted into all the elements.)
static inline uint64_t ARM_AM_decodeNEONModImm(unsigned ModImm, unsigned *EltBits)
{
unsigned OpCmode = getNEONModImmOpCmode(ModImm);
unsigned Imm8 = getNEONModImmVal(ModImm);
uint64_t Val = 0;
unsigned ByteNum;
if (OpCmode == 0xe) {
// 8-bit vector elements
Val = Imm8;
*EltBits = 8;
} else if ((OpCmode & 0xc) == 0x8) {
// 16-bit vector elements
ByteNum = (OpCmode & 0x6) >> 1;
Val = (uint64_t)Imm8 << (8 * ByteNum);
*EltBits = 16;
} else if ((OpCmode & 0x8) == 0) {
// 32-bit vector elements, zero with one byte set
ByteNum = (OpCmode & 0x6) >> 1;
Val = (uint64_t)Imm8 << (8 * ByteNum);
*EltBits = 32;
} else if ((OpCmode & 0xe) == 0xc) {
// 32-bit vector elements, one byte with low bits set
ByteNum = 1 + (OpCmode & 0x1);
Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum)));
*EltBits = 32;
} else if (OpCmode == 0x1e) {
// 64-bit vector elements
for (ByteNum = 0; ByteNum < 8; ++ByteNum) {
if ((ModImm >> ByteNum) & 1)
Val |= (uint64_t)0xff << (8 * ByteNum);
}
*EltBits = 64;
} else {
//llvm_unreachable("Unsupported NEON immediate");
}
return Val;
}
ARM_AM_AMSubMode getLoadStoreMultipleSubMode(int Opcode);
//===--------------------------------------------------------------------===//
// Floating-point Immediates
//
static inline float getFPImmFloat(unsigned Imm)
{
// We expect an 8-bit binary encoding of a floating-point number here.
union {
uint32_t I;
float F;
} FPUnion;
uint8_t Sign = (Imm >> 7) & 0x1;
uint8_t Exp = (Imm >> 4) & 0x7;
uint8_t Mantissa = Imm & 0xf;
// 8-bit FP iEEEE Float Encoding
// abcd efgh aBbbbbbc defgh000 00000000 00000000
//
// where B = NOT(b);
FPUnion.I = 0;
FPUnion.I |= Sign << 31;
FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
FPUnion.I |= (Exp & 0x3) << 23;
FPUnion.I |= Mantissa << 19;
return FPUnion.F;
}
#endif

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//===-- ARMBaseInfo.h - Top level definitions for ARM -------- --*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains small standalone helper functions and enum definitions for
// the ARM target useful for the compiler back-end and the MC libraries.
// As such, it deliberately does not include references to LLVM core
// code gen types, passes, etc..
//
//===----------------------------------------------------------------------===//
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
#ifndef CS_ARMBASEINFO_H
#define CS_ARMBASEINFO_H
#include "../../include/arm.h"
// Defines symbolic names for ARM registers. This defines a mapping from
// register name to register number.
//
#define GET_REGINFO_ENUM
#include "ARMGenRegisterInfo.inc"
// Enums corresponding to ARM condition codes
// The CondCodes constants map directly to the 4-bit encoding of the
// condition field for predicated instructions.
typedef enum ARMCC_CondCodes { // Meaning (integer) Meaning (floating-point)
ARMCC_EQ, // Equal Equal
ARMCC_NE, // Not equal Not equal, or unordered
ARMCC_HS, // Carry set >, ==, or unordered
ARMCC_LO, // Carry clear Less than
ARMCC_MI, // Minus, negative Less than
ARMCC_PL, // Plus, positive or zero >, ==, or unordered
ARMCC_VS, // Overflow Unordered
ARMCC_VC, // No overflow Not unordered
ARMCC_HI, // Unsigned higher Greater than, or unordered
ARMCC_LS, // Unsigned lower or same Less than or equal
ARMCC_GE, // Greater than or equal Greater than or equal
ARMCC_LT, // Less than Less than, or unordered
ARMCC_GT, // Greater than Greater than
ARMCC_LE, // Less than or equal <, ==, or unordered
ARMCC_AL // Always (unconditional) Always (unconditional)
} ARMCC_CondCodes;
inline static ARMCC_CondCodes ARMCC_getOppositeCondition(ARMCC_CondCodes CC)
{
switch (CC) {
case ARMCC_EQ: return ARMCC_NE;
case ARMCC_NE: return ARMCC_EQ;
case ARMCC_HS: return ARMCC_LO;
case ARMCC_LO: return ARMCC_HS;
case ARMCC_MI: return ARMCC_PL;
case ARMCC_PL: return ARMCC_MI;
case ARMCC_VS: return ARMCC_VC;
case ARMCC_VC: return ARMCC_VS;
case ARMCC_HI: return ARMCC_LS;
case ARMCC_LS: return ARMCC_HI;
case ARMCC_GE: return ARMCC_LT;
case ARMCC_LT: return ARMCC_GE;
case ARMCC_GT: return ARMCC_LE;
case ARMCC_LE: return ARMCC_GT;
default: return ARMCC_AL;
}
}
inline static char *ARMCC_ARMCondCodeToString(ARMCC_CondCodes CC)
{
switch (CC) {
case ARMCC_EQ: return "eq";
case ARMCC_NE: return "ne";
case ARMCC_HS: return "hs";
case ARMCC_LO: return "lo";
case ARMCC_MI: return "mi";
case ARMCC_PL: return "pl";
case ARMCC_VS: return "vs";
case ARMCC_VC: return "vc";
case ARMCC_HI: return "hi";
case ARMCC_LS: return "ls";
case ARMCC_GE: return "ge";
case ARMCC_LT: return "lt";
case ARMCC_GT: return "gt";
case ARMCC_LE: return "le";
case ARMCC_AL: return "al";
default: return "";
}
}
inline static char *ARM_PROC_IFlagsToString(unsigned val)
{
switch (val) {
case ARM_CPSFLAG_F: return "f";
case ARM_CPSFLAG_I: return "i";
case ARM_CPSFLAG_A: return "a";
default: return "";
}
}
inline static char *ARM_PROC_IModToString(unsigned val)
{
switch (val) {
case ARM_CPSMODE_IE: return "ie";
case ARM_CPSMODE_ID: return "id";
default: return "";
}
}
inline static char *ARM_MB_MemBOptToString(unsigned val, bool HasV8)
{
switch (val) {
default: return "BUGBUG";
case ARM_MB_SY: return "sy";
case ARM_MB_ST: return "st";
case ARM_MB_LD: return HasV8 ? "ld" : "#0xd";
case ARM_MB_RESERVED_12: return "#0xc";
case ARM_MB_ISH: return "ish";
case ARM_MB_ISHST: return "ishst";
case ARM_MB_ISHLD: return HasV8 ? "ishld" : "#0x9";
case ARM_MB_RESERVED_8: return "#0x8";
case ARM_MB_NSH: return "nsh";
case ARM_MB_NSHST: return "nshst";
case ARM_MB_NSHLD: return HasV8 ? "nshld" : "#0x5";
case ARM_MB_RESERVED_4: return "#0x4";
case ARM_MB_OSH: return "osh";
case ARM_MB_OSHST: return "oshst";
case ARM_MB_OSHLD: return HasV8 ? "oshld" : "#0x1";
case ARM_MB_RESERVED_0: return "#0x0";
}
}
enum ARM_ISB_InstSyncBOpt {
ARM_ISB_RESERVED_0 = 0,
ARM_ISB_RESERVED_1 = 1,
ARM_ISB_RESERVED_2 = 2,
ARM_ISB_RESERVED_3 = 3,
ARM_ISB_RESERVED_4 = 4,
ARM_ISB_RESERVED_5 = 5,
ARM_ISB_RESERVED_6 = 6,
ARM_ISB_RESERVED_7 = 7,
ARM_ISB_RESERVED_8 = 8,
ARM_ISB_RESERVED_9 = 9,
ARM_ISB_RESERVED_10 = 10,
ARM_ISB_RESERVED_11 = 11,
ARM_ISB_RESERVED_12 = 12,
ARM_ISB_RESERVED_13 = 13,
ARM_ISB_RESERVED_14 = 14,
ARM_ISB_SY = 15
};
inline static char *ARM_ISB_InstSyncBOptToString(unsigned val)
{
switch (val) {
default: // never reach
case ARM_ISB_RESERVED_0: return "#0x0";
case ARM_ISB_RESERVED_1: return "#0x1";
case ARM_ISB_RESERVED_2: return "#0x2";
case ARM_ISB_RESERVED_3: return "#0x3";
case ARM_ISB_RESERVED_4: return "#0x4";
case ARM_ISB_RESERVED_5: return "#0x5";
case ARM_ISB_RESERVED_6: return "#0x6";
case ARM_ISB_RESERVED_7: return "#0x7";
case ARM_ISB_RESERVED_8: return "#0x8";
case ARM_ISB_RESERVED_9: return "#0x9";
case ARM_ISB_RESERVED_10: return "#0xa";
case ARM_ISB_RESERVED_11: return "#0xb";
case ARM_ISB_RESERVED_12: return "#0xc";
case ARM_ISB_RESERVED_13: return "#0xd";
case ARM_ISB_RESERVED_14: return "#0xe";
case ARM_ISB_SY: return "sy";
}
}
/// isARMLowRegister - Returns true if the register is a low register (r0-r7).
///
static inline bool isARMLowRegister(unsigned Reg)
{
//using namespace ARM;
switch (Reg) {
case ARM_R0: case ARM_R1: case ARM_R2: case ARM_R3:
case ARM_R4: case ARM_R5: case ARM_R6: case ARM_R7:
return true;
default:
return false;
}
}
/// ARMII - This namespace holds all of the target specific flags that
/// instruction info tracks.
///
/// ARM Index Modes
enum ARMII_IndexMode {
ARMII_IndexModeNone = 0,
ARMII_IndexModePre = 1,
ARMII_IndexModePost = 2,
ARMII_IndexModeUpd = 3
};
/// ARM Addressing Modes
typedef enum ARMII_AddrMode {
ARMII_AddrModeNone = 0,
ARMII_AddrMode1 = 1,
ARMII_AddrMode2 = 2,
ARMII_AddrMode3 = 3,
ARMII_AddrMode4 = 4,
ARMII_AddrMode5 = 5,
ARMII_AddrMode6 = 6,
ARMII_AddrModeT1_1 = 7,
ARMII_AddrModeT1_2 = 8,
ARMII_AddrModeT1_4 = 9,
ARMII_AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
ARMII_AddrModeT2_i12 = 11,
ARMII_AddrModeT2_i8 = 12,
ARMII_AddrModeT2_so = 13,
ARMII_AddrModeT2_pc = 14, // +/- i12 for pc relative data
ARMII_AddrModeT2_i8s4 = 15, // i8 * 4
ARMII_AddrMode_i12 = 16
} ARMII_AddrMode;
inline static char *ARMII_AddrModeToString(ARMII_AddrMode addrmode)
{
switch (addrmode) {
case ARMII_AddrModeNone: return "AddrModeNone";
case ARMII_AddrMode1: return "AddrMode1";
case ARMII_AddrMode2: return "AddrMode2";
case ARMII_AddrMode3: return "AddrMode3";
case ARMII_AddrMode4: return "AddrMode4";
case ARMII_AddrMode5: return "AddrMode5";
case ARMII_AddrMode6: return "AddrMode6";
case ARMII_AddrModeT1_1: return "AddrModeT1_1";
case ARMII_AddrModeT1_2: return "AddrModeT1_2";
case ARMII_AddrModeT1_4: return "AddrModeT1_4";
case ARMII_AddrModeT1_s: return "AddrModeT1_s";
case ARMII_AddrModeT2_i12: return "AddrModeT2_i12";
case ARMII_AddrModeT2_i8: return "AddrModeT2_i8";
case ARMII_AddrModeT2_so: return "AddrModeT2_so";
case ARMII_AddrModeT2_pc: return "AddrModeT2_pc";
case ARMII_AddrModeT2_i8s4: return "AddrModeT2_i8s4";
case ARMII_AddrMode_i12: return "AddrMode_i12";
}
}
/// Target Operand Flag enum.
enum ARMII_TOF {
//===------------------------------------------------------------------===//
// ARM Specific MachineOperand flags.
ARMII_MO_NO_FLAG,
/// MO_LO16 - On a symbol operand, this represents a relocation containing
/// lower 16 bit of the address. Used only via movw instruction.
ARMII_MO_LO16,
/// MO_HI16 - On a symbol operand, this represents a relocation containing
/// higher 16 bit of the address. Used only via movt instruction.
ARMII_MO_HI16,
/// MO_LO16_NONLAZY - On a symbol operand "FOO", this represents a
/// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol,
/// i.e. "FOO$non_lazy_ptr".
/// Used only via movw instruction.
ARMII_MO_LO16_NONLAZY,
/// MO_HI16_NONLAZY - On a symbol operand "FOO", this represents a
/// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol,
/// i.e. "FOO$non_lazy_ptr". Used only via movt instruction.
ARMII_MO_HI16_NONLAZY,
/// MO_LO16_NONLAZY_PIC - On a symbol operand "FOO", this represents a
/// relocation containing lower 16 bit of the PC relative address of the
/// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL".
/// Used only via movw instruction.
ARMII_MO_LO16_NONLAZY_PIC,
/// MO_HI16_NONLAZY_PIC - On a symbol operand "FOO", this represents a
/// relocation containing lower 16 bit of the PC relative address of the
/// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL".
/// Used only via movt instruction.
ARMII_MO_HI16_NONLAZY_PIC,
/// MO_PLT - On a symbol operand, this represents an ELF PLT reference on a
/// call operand.
ARMII_MO_PLT
};
enum {
//===------------------------------------------------------------------===//
// Instruction Flags.
//===------------------------------------------------------------------===//
// This four-bit field describes the addressing mode used.
ARMII_AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
// IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
// and store ops only. Generic "updating" flag is used for ld/st multiple.
// The index mode enums are declared in ARMBaseInfo.h
ARMII_IndexModeShift = 5,
ARMII_IndexModeMask = 3 << ARMII_IndexModeShift,
//===------------------------------------------------------------------===//
// Instruction encoding formats.
//
ARMII_FormShift = 7,
ARMII_FormMask = 0x3f << ARMII_FormShift,
// Pseudo instructions
ARMII_Pseudo = 0 << ARMII_FormShift,
// Multiply instructions
ARMII_MulFrm = 1 << ARMII_FormShift,
// Branch instructions
ARMII_BrFrm = 2 << ARMII_FormShift,
ARMII_BrMiscFrm = 3 << ARMII_FormShift,
// Data Processing instructions
ARMII_DPFrm = 4 << ARMII_FormShift,
ARMII_DPSoRegFrm = 5 << ARMII_FormShift,
// Load and Store
ARMII_LdFrm = 6 << ARMII_FormShift,
ARMII_StFrm = 7 << ARMII_FormShift,
ARMII_LdMiscFrm = 8 << ARMII_FormShift,
ARMII_StMiscFrm = 9 << ARMII_FormShift,
ARMII_LdStMulFrm = 10 << ARMII_FormShift,
ARMII_LdStExFrm = 11 << ARMII_FormShift,
// Miscellaneous arithmetic instructions
ARMII_ArithMiscFrm = 12 << ARMII_FormShift,
ARMII_SatFrm = 13 << ARMII_FormShift,
// Extend instructions
ARMII_ExtFrm = 14 << ARMII_FormShift,
// VFP formats
ARMII_VFPUnaryFrm = 15 << ARMII_FormShift,
ARMII_VFPBinaryFrm = 16 << ARMII_FormShift,
ARMII_VFPConv1Frm = 17 << ARMII_FormShift,
ARMII_VFPConv2Frm = 18 << ARMII_FormShift,
ARMII_VFPConv3Frm = 19 << ARMII_FormShift,
ARMII_VFPConv4Frm = 20 << ARMII_FormShift,
ARMII_VFPConv5Frm = 21 << ARMII_FormShift,
ARMII_VFPLdStFrm = 22 << ARMII_FormShift,
ARMII_VFPLdStMulFrm = 23 << ARMII_FormShift,
ARMII_VFPMiscFrm = 24 << ARMII_FormShift,
// Thumb format
ARMII_ThumbFrm = 25 << ARMII_FormShift,
// Miscelleaneous format
ARMII_MiscFrm = 26 << ARMII_FormShift,
// NEON formats
ARMII_NGetLnFrm = 27 << ARMII_FormShift,
ARMII_NSetLnFrm = 28 << ARMII_FormShift,
ARMII_NDupFrm = 29 << ARMII_FormShift,
ARMII_NLdStFrm = 30 << ARMII_FormShift,
ARMII_N1RegModImmFrm= 31 << ARMII_FormShift,
ARMII_N2RegFrm = 32 << ARMII_FormShift,
ARMII_NVCVTFrm = 33 << ARMII_FormShift,
ARMII_NVDupLnFrm = 34 << ARMII_FormShift,
ARMII_N2RegVShLFrm = 35 << ARMII_FormShift,
ARMII_N2RegVShRFrm = 36 << ARMII_FormShift,
ARMII_N3RegFrm = 37 << ARMII_FormShift,
ARMII_N3RegVShFrm = 38 << ARMII_FormShift,
ARMII_NVExtFrm = 39 << ARMII_FormShift,
ARMII_NVMulSLFrm = 40 << ARMII_FormShift,
ARMII_NVTBLFrm = 41 << ARMII_FormShift,
//===------------------------------------------------------------------===//
// Misc flags.
// UnaryDP - Indicates this is a unary data processing instruction, i.e.
// it doesn't have a Rn operand.
ARMII_UnaryDP = 1 << 13,
// Xform16Bit - Indicates this Thumb2 instruction may be transformed into
// a 16-bit Thumb instruction if certain conditions are met.
ARMII_Xform16Bit = 1 << 14,
// ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb
// instruction. Used by the parser to determine whether to require the 'S'
// suffix on the mnemonic (when not in an IT block) or preclude it (when
// in an IT block).
ARMII_ThumbArithFlagSetting = 1 << 18,
//===------------------------------------------------------------------===//
// Code domain.
ARMII_DomainShift = 15,
ARMII_DomainMask = 7 << ARMII_DomainShift,
ARMII_DomainGeneral = 0 << ARMII_DomainShift,
ARMII_DomainVFP = 1 << ARMII_DomainShift,
ARMII_DomainNEON = 2 << ARMII_DomainShift,
ARMII_DomainNEONA8 = 4 << ARMII_DomainShift,
//===------------------------------------------------------------------===//
// Field shifts - such shifts are used to set field while generating
// machine instructions.
//
// FIXME: This list will need adjusting/fixing as the MC code emitter
// takes shape and the ARMCodeEmitter.cpp bits go away.
ARMII_ShiftTypeShift = 4,
ARMII_M_BitShift = 5,
ARMII_ShiftImmShift = 5,
ARMII_ShiftShift = 7,
ARMII_N_BitShift = 7,
ARMII_ImmHiShift = 8,
ARMII_SoRotImmShift = 8,
ARMII_RegRsShift = 8,
ARMII_ExtRotImmShift = 10,
ARMII_RegRdLoShift = 12,
ARMII_RegRdShift = 12,
ARMII_RegRdHiShift = 16,
ARMII_RegRnShift = 16,
ARMII_S_BitShift = 20,
ARMII_W_BitShift = 21,
ARMII_AM3_I_BitShift = 22,
ARMII_D_BitShift = 22,
ARMII_U_BitShift = 23,
ARMII_P_BitShift = 24,
ARMII_I_BitShift = 25,
ARMII_CondShift = 28
};
#endif

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/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
#ifndef CS_ARMDISASSEMBLER_H
#define CS_ARMDISASSEMBLER_H
#include "../../include/capstone.h"
#include "../../MCRegisterInfo.h"
void ARM_init(MCRegisterInfo *MRI);
bool ARM_getInstruction(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info);
bool Thumb_getInstruction(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info);
uint64_t ARM_getFeatureBits(unsigned int mode);
#endif

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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|*Subtarget Enumeration Source Fragment *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
#ifdef GET_SUBTARGETINFO_ENUM
#undef GET_SUBTARGETINFO_ENUM
#define ARM_FeatureAAPCS (1ULL << 0)
#define ARM_FeatureAClass (1ULL << 1)
#define ARM_FeatureAPCS (1ULL << 2)
#define ARM_FeatureAvoidMOVsShOp (1ULL << 3)
#define ARM_FeatureAvoidPartialCPSR (1ULL << 4)
#define ARM_FeatureCRC (1ULL << 5)
#define ARM_FeatureCrypto (1ULL << 6)
#define ARM_FeatureD16 (1ULL << 7)
#define ARM_FeatureDB (1ULL << 8)
#define ARM_FeatureDSPThumb2 (1ULL << 9)
#define ARM_FeatureFP16 (1ULL << 10)
#define ARM_FeatureFPARMv8 (1ULL << 11)
#define ARM_FeatureHWDiv (1ULL << 12)
#define ARM_FeatureHWDivARM (1ULL << 13)
#define ARM_FeatureHasRAS (1ULL << 14)
#define ARM_FeatureHasSlowFPVMLx (1ULL << 15)
#define ARM_FeatureMClass (1ULL << 16)
#define ARM_FeatureMP (1ULL << 17)
#define ARM_FeatureNEON (1ULL << 18)
#define ARM_FeatureNEONForFP (1ULL << 19)
#define ARM_FeatureNaClTrap (1ULL << 20)
#define ARM_FeatureNoARM (1ULL << 21)
#define ARM_FeaturePerfMon (1ULL << 22)
#define ARM_FeaturePref32BitThumb (1ULL << 23)
#define ARM_FeatureRClass (1ULL << 24)
#define ARM_FeatureSlowFPBrcc (1ULL << 25)
#define ARM_FeatureT2XtPk (1ULL << 26)
#define ARM_FeatureThumb2 (1ULL << 27)
#define ARM_FeatureTrustZone (1ULL << 28)
#define ARM_FeatureVFP2 (1ULL << 29)
#define ARM_FeatureVFP3 (1ULL << 30)
#define ARM_FeatureVFP4 (1ULL << 31)
#define ARM_FeatureVFPOnlySP (1ULL << 32)
#define ARM_FeatureVMLxForwarding (1ULL << 33)
#define ARM_FeatureVirtualization (1ULL << 34)
#define ARM_FeatureZCZeroing (1ULL << 35)
#define ARM_HasV4TOps (1ULL << 36)
#define ARM_HasV5TEOps (1ULL << 37)
#define ARM_HasV5TOps (1ULL << 38)
#define ARM_HasV6MOps (1ULL << 39)
#define ARM_HasV6Ops (1ULL << 40)
#define ARM_HasV6T2Ops (1ULL << 41)
#define ARM_HasV7Ops (1ULL << 42)
#define ARM_HasV8Ops (1ULL << 43)
#define ARM_ModeThumb (1ULL << 44)
#define ARM_ProcA5 (1ULL << 45)
#define ARM_ProcA7 (1ULL << 46)
#define ARM_ProcA8 (1ULL << 47)
#define ARM_ProcA9 (1ULL << 48)
#define ARM_ProcA12 (1ULL << 49)
#define ARM_ProcA15 (1ULL << 50)
#define ARM_ProcA53 (1ULL << 51)
#define ARM_ProcA57 (1ULL << 52)
#define ARM_ProcKrait (1ULL << 53)
#define ARM_ProcR5 (1ULL << 54)
#define ARM_ProcSwift (1ULL << 55)
#endif // GET_SUBTARGETINFO_ENUM

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//===- ARMInstPrinter.h - Convert ARM MCInst to assembly syntax -*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This class prints an ARM MCInst to a .s file.
//
//===----------------------------------------------------------------------===//
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
#ifndef CS_ARMINSTPRINTER_H
#define CS_ARMINSTPRINTER_H
#include "../../MCInst.h"
#include "../../MCRegisterInfo.h"
#include "../../SStream.h"
void ARM_printInst(MCInst *MI, SStream *O, void *Info);
void ARM_post_printer(csh handle, cs_insn *pub_insn, char *mnem, MCInst *mci);
// setup handle->get_regname
void ARM_getRegName(cs_struct *handle, int value);
// specify vector data type for vector instructions
void ARM_addVectorDataType(MCInst *MI, arm_vectordata_type vd);
void ARM_addVectorDataSize(MCInst *MI, int size);
void ARM_addReg(MCInst *MI, int reg);
// load usermode registers (LDM, STM)
void ARM_addUserMode(MCInst *MI);
// sysreg for MRS/MSR
void ARM_addSysReg(MCInst *MI, arm_sysreg reg);
#endif

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/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
#ifndef CS_ARM_MAP_H
#define CS_ARM_MAP_H
#include "../../include/capstone.h"
#include "../../utils.h"
// return name of regiser in friendly string
const char *ARM_reg_name(csh handle, unsigned int reg);
const char *ARM_reg_name2(csh handle, unsigned int reg);
// given internal insn id, return public instruction ID
void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
const char *ARM_insn_name(csh handle, unsigned int id);
const char *ARM_group_name(csh handle, unsigned int id);
// check if this insn is relative branch
bool ARM_rel_branch(cs_struct *h, unsigned int insn_id);
bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int insn_id);
#endif

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/* Capstone Disassembly Engine */
/* By Dang Hoang Vu <danghvu@gmail.com> 2013 */
#ifdef CAPSTONE_HAS_ARM
#include "../../cs_priv.h"
#include "../../MCRegisterInfo.h"
#include "ARMDisassembler.h"
#include "ARMInstPrinter.h"
#include "ARMMapping.h"
static cs_err init(cs_struct *ud)
{
MCRegisterInfo *mri;
// verify if requested mode is valid
if (ud->mode & ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_ARM | CS_MODE_V8 |
CS_MODE_MCLASS | CS_MODE_THUMB | CS_MODE_BIG_ENDIAN))
return CS_ERR_MODE;
mri = cs_mem_malloc(sizeof(*mri));
ARM_init(mri);
ARM_getRegName(ud, 0); // use default get_regname
ud->printer = ARM_printInst;
ud->printer_info = mri;
ud->reg_name = ARM_reg_name;
ud->insn_id = ARM_get_insn_id;
ud->insn_name = ARM_insn_name;
ud->group_name = ARM_group_name;
ud->post_printer = ARM_post_printer;
if (ud->mode & CS_MODE_THUMB)
ud->disasm = Thumb_getInstruction;
else
ud->disasm = ARM_getInstruction;
return CS_ERR_OK;
}
static cs_err option(cs_struct *handle, cs_opt_type type, size_t value)
{
switch(type) {
case CS_OPT_MODE:
if (value & CS_MODE_THUMB)
handle->disasm = Thumb_getInstruction;
else
handle->disasm = ARM_getInstruction;
handle->mode = (cs_mode)value;
break;
case CS_OPT_SYNTAX:
ARM_getRegName(handle, (int)value);
handle->syntax = (int)value;
break;
default:
break;
}
return CS_ERR_OK;
}
static void destroy(cs_struct *handle)
{
}
void ARM_enable(void)
{
arch_init[CS_ARCH_ARM] = init;
arch_option[CS_ARCH_ARM] = option;
arch_destroy[CS_ARCH_ARM] = destroy;
// support this arch
all_arch |= (1 << CS_ARCH_ARM);
}
#endif

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/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
#ifndef CS_MIPSDISASSEMBLER_H
#define CS_MIPSDISASSEMBLER_H
#include "../../include/capstone.h"
#include "../../include/capstone.h"
#include "../../MCRegisterInfo.h"
void Mips_init(MCRegisterInfo *MRI);
bool Mips_getInstruction(csh handle, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address, void *info);
bool Mips64_getInstruction(csh handle, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address, void *info);
#endif

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