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moved ir passes to own folder

This commit is contained in:
Anthony Pesch 2015-07-20 15:09:10 -07:00
parent 700d09992d
commit a33bf95d16
21 changed files with 191 additions and 96 deletions
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26
CMakeLists.txt
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@ -56,13 +56,14 @@ set(DREAVM_SOURCES
src/cpu/frontend/sh4/sh4_emit.cc
src/cpu/frontend/sh4/sh4_frontend.cc
src/cpu/frontend/sh4/sh4_instr.cc
src/cpu/ir/constant_propagation_pass.cc
src/cpu/ir/context_promotion_pass.cc
src/cpu/ir/control_flow_analysis_pass.cc
src/cpu/ir/ir_builder.cc
src/cpu/ir/pass_runner.cc
src/cpu/ir/register_allocation_pass.cc
src/cpu/ir/validate_block_pass.cc
src/cpu/ir/passes/constant_propagation_pass.cc
src/cpu/ir/passes/context_promotion_pass.cc
src/cpu/ir/passes/control_flow_analysis_pass.cc
src/cpu/ir/passes/pass_runner.cc
src/cpu/ir/passes/register_allocation_pass.cc
src/cpu/ir/passes/validate_block_pass.cc
src/cpu/ir/passes/validate_instruction_pass.cc
src/cpu/sh4.cc
src/cpu/sh4_context.cc
src/cpu/runtime.cc
@ -265,13 +266,14 @@ set(DREAVM_TEST_SOURCES
src/cpu/frontend/sh4/sh4_emit.cc
src/cpu/frontend/sh4/sh4_frontend.cc
src/cpu/frontend/sh4/sh4_instr.cc
src/cpu/ir/constant_propagation_pass.cc
src/cpu/ir/context_promotion_pass.cc
src/cpu/ir/control_flow_analysis_pass.cc
src/cpu/ir/ir_builder.cc
src/cpu/ir/pass_runner.cc
src/cpu/ir/register_allocation_pass.cc
src/cpu/ir/validate_block_pass.cc
src/cpu/ir/passes/constant_propagation_pass.cc
src/cpu/ir/passes/context_promotion_pass.cc
src/cpu/ir/passes/control_flow_analysis_pass.cc
src/cpu/ir/passes/pass_runner.cc
src/cpu/ir/passes/register_allocation_pass.cc
src/cpu/ir/passes/validate_block_pass.cc
src/cpu/ir/passes/validate_instruction_pass.cc
src/cpu/sh4.cc
src/cpu/sh4_context.cc
src/cpu/runtime.cc

37
src/cpu/backend/x64/x64_backend.cc
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@ -7,19 +7,30 @@ using namespace dreavm::cpu::backend::x64;
using namespace dreavm::cpu::ir;
using namespace dreavm::emu;
static Register x64_registers[] = {
{"rax", VALUE_INT_MASK}, {"rbx", VALUE_INT_MASK},
{"rcx", VALUE_INT_MASK}, {"rdx", VALUE_INT_MASK},
{"rsi", VALUE_INT_MASK}, {"rdi", VALUE_INT_MASK},
{"rbp", VALUE_INT_MASK}, {"rsp", VALUE_INT_MASK},
{"r8", VALUE_INT_MASK}, {"r9", VALUE_INT_MASK},
{"r10", VALUE_INT_MASK}, {"r11", VALUE_INT_MASK},
{"r12", VALUE_INT_MASK}, {"r13", VALUE_INT_MASK},
{"r14", VALUE_INT_MASK}, {"r15", VALUE_INT_MASK},
{"mm0", VALUE_FLOAT_MASK}, {"mm1", VALUE_FLOAT_MASK},
{"mm2", VALUE_FLOAT_MASK}, {"mm3", VALUE_FLOAT_MASK},
{"mm4", VALUE_FLOAT_MASK}, {"mm5", VALUE_FLOAT_MASK},
{"mm6", VALUE_FLOAT_MASK}, {"mm7", VALUE_FLOAT_MASK}};
static Register x64_registers[] = {{"rax", VALUE_INT_MASK},
{"rbx", VALUE_INT_MASK},
{"rcx", VALUE_INT_MASK},
{"rdx", VALUE_INT_MASK},
{"rsi", VALUE_INT_MASK},
{"rdi", VALUE_INT_MASK},
{"rbp", VALUE_INT_MASK},
{"rsp", VALUE_INT_MASK},
{"r8", VALUE_INT_MASK},
{"r9", VALUE_INT_MASK},
{"r10", VALUE_INT_MASK},
{"r11", VALUE_INT_MASK},
{"r12", VALUE_INT_MASK},
{"r13", VALUE_INT_MASK},
{"r14", VALUE_INT_MASK},
{"r15", VALUE_INT_MASK},
{"mm0", VALUE_FLOAT_MASK},
{"mm1", VALUE_FLOAT_MASK},
{"mm2", VALUE_FLOAT_MASK},
{"mm3", VALUE_FLOAT_MASK},
{"mm4", VALUE_FLOAT_MASK},
{"mm5", VALUE_FLOAT_MASK},
{"mm6", VALUE_FLOAT_MASK},
{"mm7", VALUE_FLOAT_MASK}};
static const Xbyak::Reg *reg_map[] = {
&Xbyak::util::rax, &Xbyak::util::rbx, &Xbyak::util::rcx, &Xbyak::util::rdx,

3
src/cpu/ir/constant_propagation_pass.cc → src/cpu/ir/passes/constant_propagation_pass.cc
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@ -1,8 +1,9 @@
#include "core/core.h"
#include "cpu/ir/constant_propagation_pass.h"
#include "cpu/ir/passes/constant_propagation_pass.h"
using namespace dreavm;
using namespace dreavm::cpu::ir;
using namespace dreavm::cpu::ir::passes;
using namespace dreavm::emu;
// typedef void (*ConstInstrHandler)(Instr *instr);

4
src/cpu/ir/constant_propagation_pass.h → src/cpu/ir/passes/constant_propagation_pass.h
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@ -1,12 +1,13 @@
#ifndef CONSTANT_PROPAGATION_PASS_H
#define CONSTANT_PROPAGATION_PASS_H
#include "cpu/ir/pass_runner.h"
#include "cpu/ir/passes/pass_runner.h"
#include "emu/memory.h"
namespace dreavm {
namespace cpu {
namespace ir {
namespace passes {
class ConstantPropagationPass : public Pass {
public:
@ -20,5 +21,6 @@ class ConstantPropagationPass : public Pass {
}
}
}
}
#endif

3
src/cpu/ir/context_promotion_pass.cc → src/cpu/ir/passes/context_promotion_pass.cc
View File

@ -1,8 +1,9 @@
#include "core/core.h"
#include "cpu/ir/context_promotion_pass.h"
#include "cpu/ir/passes/context_promotion_pass.h"
using namespace dreavm;
using namespace dreavm::cpu::ir;
using namespace dreavm::cpu::ir::passes;
void ContextPromotionPass::Run(IRBuilder &builder) {
for (auto block : builder.blocks()) {

4
src/cpu/ir/context_promotion_pass.h → src/cpu/ir/passes/context_promotion_pass.h
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@ -2,11 +2,12 @@
#define CONTEXT_PROMOTION_PASS_H
#include <vector>
#include "cpu/ir/pass_runner.h"
#include "cpu/ir/passes/pass_runner.h"
namespace dreavm {
namespace cpu {
namespace ir {
namespace passes {
class ContextPromotionPass : public Pass {
public:
@ -24,5 +25,6 @@ class ContextPromotionPass : public Pass {
}
}
}
}
#endif

3
src/cpu/ir/control_flow_analysis_pass.cc → src/cpu/ir/passes/control_flow_analysis_pass.cc
View File

@ -1,8 +1,9 @@
#include "core/core.h"
#include "cpu/ir/control_flow_analysis_pass.h"
#include "cpu/ir/passes/control_flow_analysis_pass.h"
using namespace dreavm;
using namespace dreavm::cpu::ir;
using namespace dreavm::cpu::ir::passes;
void ControlFlowAnalysisPass::Run(IRBuilder &builder) {
// add directed edges between blocks

4
src/cpu/ir/control_flow_analysis_pass.h → src/cpu/ir/passes/control_flow_analysis_pass.h
View File

@ -1,11 +1,12 @@
#ifndef CONTROL_FLOW_ANALYSIS_PASS_H
#define CONTROL_FLOW_ANALYSIS_PASS_H
#include "cpu/ir/pass_runner.h"
#include "cpu/ir/passes/pass_runner.h"
namespace dreavm {
namespace cpu {
namespace ir {
namespace passes {
class ControlFlowAnalysisPass : public Pass {
public:
@ -14,5 +15,6 @@ class ControlFlowAnalysisPass : public Pass {
}
}
}
}
#endif

3
src/cpu/ir/pass_runner.cc → src/cpu/ir/passes/pass_runner.cc
View File

@ -1,9 +1,10 @@
#include "core/core.h"
#include "cpu/ir/ir_builder.h"
#include "cpu/ir/pass_runner.h"
#include "cpu/ir/passes/pass_runner.h"
using namespace dreavm;
using namespace dreavm::cpu::ir;
using namespace dreavm::cpu::ir::passes;
PassRunner::PassRunner() {}

2
src/cpu/ir/pass_runner.h → src/cpu/ir/passes/pass_runner.h
View File

@ -8,6 +8,7 @@
namespace dreavm {
namespace cpu {
namespace ir {
namespace passes {
class Pass {
public:
@ -28,5 +29,6 @@ class PassRunner {
}
}
}
}
#endif

3
src/cpu/ir/register_allocation_pass.cc → src/cpu/ir/passes/register_allocation_pass.cc
View File

@ -1,8 +1,9 @@
#include "core/core.h"
#include "cpu/ir/register_allocation_pass.h"
#include "cpu/ir/passes/register_allocation_pass.h"
using namespace dreavm;
using namespace dreavm::cpu::ir;
using namespace dreavm::cpu::ir::passes;
RegisterAllocationPass::RegisterAllocationPass(
const backend::Backend &backend) {

4
src/cpu/ir/register_allocation_pass.h → src/cpu/ir/passes/register_allocation_pass.h
View File

@ -3,11 +3,12 @@
#include <set>
#include "cpu/backend/backend.h"
#include "cpu/ir/pass_runner.h"
#include "cpu/ir/passes/pass_runner.h"
namespace dreavm {
namespace cpu {
namespace ir {
namespace passes {
static inline int GetOrdinal(Instr *i) { return (int)i->tag(); }
@ -58,5 +59,6 @@ class RegisterAllocationPass : public Pass {
}
}
}
}
#endif

5
src/cpu/ir/validate_block_pass.cc → src/cpu/ir/passes/validate_block_pass.cc
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@ -1,14 +1,17 @@
#include "core/core.h"
#include "cpu/ir/validate_block_pass.h"
#include "cpu/ir/passes/validate_block_pass.h"
using namespace dreavm;
using namespace dreavm::cpu::ir;
using namespace dreavm::cpu::ir::passes;
void ValidateBlockPass::Run(IRBuilder &builder) {
for (auto block : builder.blocks()) {
Instr *tail = block->instrs().tail();
if (!tail || !IRBuilder::IsTerminator(tail)) {
builder.Dump();
LOG(FATAL) << "Block ends in a non-terminating instruction.";
}
}

4
src/cpu/ir/validate_block_pass.h → src/cpu/ir/passes/validate_block_pass.h
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@ -1,11 +1,12 @@
#ifndef VALIDATE_BLOCK_PASS_H
#define VALIDATE_BLOCK_PASS_H
#include "cpu/ir/pass_runner.h"
#include "cpu/ir/passes/pass_runner.h"
namespace dreavm {
namespace cpu {
namespace ir {
namespace passes {
class ValidateBlockPass : public Pass {
public:
@ -14,5 +15,6 @@ class ValidateBlockPass : public Pass {
}
}
}
}
#endif

38
src/cpu/ir/passes/validate_instruction_pass.cc Normal file
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@ -0,0 +1,38 @@
#include "core/core.h"
#include "cpu/ir/passes/validate_instruction_pass.h"
using namespace dreavm;
using namespace dreavm::cpu::ir;
using namespace dreavm::cpu::ir::passes;
void ValidateInstructionPass::Run(IRBuilder &builder) {
for (auto block : builder.blocks()) {
for (auto instr : block->instrs()) {
ValidateInstr(instr);
}
}
}
void ValidateInstructionPass::ValidateInstr(Instr *instr) {
// after constant propagation, there shouldn't be more than a single constant
// argument for most instructions
Opcode op = instr->op();
if (op != OP_STORE_CONTEXT && op != OP_BRANCH_COND) {
int num_constants = 0;
if (instr->arg0() && instr->arg0()->constant()) {
num_constants++;
}
if (instr->arg1() && instr->arg1()->constant()) {
num_constants++;
}
if (instr->arg2() && instr->arg2()->constant()) {
num_constants++;
}
if (num_constants > 1) {
LOG(FATAL) << "More than one constant argument detected for "
<< Opnames[op] << " instruction";
}
}
// result (reg or local) should be equal to one of the incoming arguments
}

23
src/cpu/ir/passes/validate_instruction_pass.h Normal file
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@ -0,0 +1,23 @@
#ifndef VALIDATE_INSTRUCTION_PASS_H
#define VALIDATE_INSTRUCTION_PASS_H
#include "cpu/ir/passes/pass_runner.h"
namespace dreavm {
namespace cpu {
namespace ir {
namespace passes {
class ValidateInstructionPass : public Pass {
public:
void Run(IRBuilder &builder);
private:
void ValidateInstr(Instr *instr);
};
}
}
}
}
#endif

13
src/cpu/runtime.cc
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@ -1,17 +1,19 @@
#include "cpu/backend/backend.h"
#include "cpu/frontend/frontend.h"
#include "cpu/ir/constant_propagation_pass.h"
#include "cpu/ir/context_promotion_pass.h"
#include "cpu/ir/control_flow_analysis_pass.h"
#include "cpu/ir/ir_builder.h"
#include "cpu/ir/register_allocation_pass.h"
#include "cpu/ir/validate_block_pass.h"
#include "cpu/ir/passes/constant_propagation_pass.h"
#include "cpu/ir/passes/context_promotion_pass.h"
#include "cpu/ir/passes/control_flow_analysis_pass.h"
#include "cpu/ir/passes/register_allocation_pass.h"
#include "cpu/ir/passes/validate_block_pass.h"
#include "cpu/ir/passes/validate_instruction_pass.h"
#include "cpu/runtime.h"
#include "emu/profiler.h"
using namespace dreavm;
using namespace dreavm::cpu;
using namespace dreavm::cpu::ir;
using namespace dreavm::cpu::ir::passes;
using namespace dreavm::emu;
Runtime::Runtime(Memory &memory)
@ -43,6 +45,7 @@ bool Runtime::Init(frontend::Frontend *frontend, backend::Backend *backend) {
// std::unique_ptr<Pass>(new ConstantPropagationPass(memory_)));
pass_runner_.AddPass(
std::unique_ptr<Pass>(new RegisterAllocationPass(*backend_)));
// pass_runner_.AddPass(std::unique_ptr<Pass>(new ValidateInstructionPass()));
return true;
}

4
src/cpu/runtime.h
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@ -2,7 +2,7 @@
#define RUNTIME_H
#include <memory>
#include "cpu/ir/pass_runner.h"
#include "cpu/ir/passes/pass_runner.h"
#include "emu/memory.h"
namespace dreavm {
@ -61,7 +61,7 @@ class Runtime {
emu::Memory &memory_;
frontend::Frontend *frontend_;
backend::Backend *backend_;
ir::PassRunner pass_runner_;
ir::passes::PassRunner pass_runner_;
// FIXME 64 mb, could cut down to 8 mb if indices were stored instead of
// pointers
std::unique_ptr<RuntimeBlock> *blocks_;

19
src/holly/maple_controller.cc
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@ -13,12 +13,19 @@ DEFINE_string(controller_profile, "", "Controller profile");
// Controller profile contains button mappings and other misc. configurable
// settings for the controller.
static Json default_profile =
Json::object{{"joyx", ""}, {"joyy", ""}, {"ltrig", ""},
{"rtrig", ""}, {"start", "space"}, {"a", "k"},
{"b", "l"}, {"x", "j"}, {"y", "i"},
{"dpad_up", "w"}, {"dpad_down", "s"}, {"dpad_left", "a"},
{"dpad_right", "d"}};
static Json default_profile = Json::object{{"joyx", ""},
{"joyy", ""},
{"ltrig", ""},
{"rtrig", ""},
{"start", "space"},
{"a", "k"},
{"b", "l"},
{"x", "j"},
{"y", "i"},
{"dpad_up", "w"},
{"dpad_down", "s"},
{"dpad_left", "a"},
{"dpad_right", "d"}};
MapleControllerProfile::MapleControllerProfile() : button_map_() {}

70
src/holly/ta.cc
View File

@ -200,19 +200,17 @@ inline CullFace TranslateCull(uint32_t cull_mode) {
inline BlendFunc TranslateSrcBlendFunc(uint32_t blend_func) {
static BlendFunc src_blend_funcs[] = {
BLEND_ZERO, BLEND_ONE,
BLEND_SRC_COLOR, BLEND_ONE_MINUS_SRC_COLOR,
BLEND_SRC_ALPHA, BLEND_ONE_MINUS_SRC_ALPHA,
BLEND_DST_ALPHA, BLEND_ONE_MINUS_DST_ALPHA};
BLEND_ZERO, BLEND_ONE, BLEND_SRC_COLOR, BLEND_ONE_MINUS_SRC_COLOR,
BLEND_SRC_ALPHA, BLEND_ONE_MINUS_SRC_ALPHA, BLEND_DST_ALPHA,
BLEND_ONE_MINUS_DST_ALPHA};
return src_blend_funcs[blend_func];
}
inline BlendFunc TranslateDstBlendFunc(uint32_t blend_func) {
static BlendFunc dst_blend_funcs[] = {
BLEND_ZERO, BLEND_ONE,
BLEND_DST_COLOR, BLEND_ONE_MINUS_DST_COLOR,
BLEND_SRC_ALPHA, BLEND_ONE_MINUS_SRC_ALPHA,
BLEND_DST_ALPHA, BLEND_ONE_MINUS_DST_ALPHA};
BLEND_ZERO, BLEND_ONE, BLEND_DST_COLOR, BLEND_ONE_MINUS_DST_COLOR,
BLEND_SRC_ALPHA, BLEND_ONE_MINUS_SRC_ALPHA, BLEND_DST_ALPHA,
BLEND_ONE_MINUS_DST_ALPHA};
return dst_blend_funcs[blend_func];
}
@ -515,37 +513,37 @@ void TileAccelerator::ParseOffsetColor(TAContext *tactx, float intensity,
}
void TileAccelerator::ParseBackground(TAContext *tactx) {
auto ParseBackgroundVertex = [&](const ISP_TSP &isp, uint32_t vertex_addr,
Vertex *v) {
v->xyz[0] = memory_.RF32(vertex_addr);
v->xyz[1] = memory_.RF32(vertex_addr + 4);
v->xyz[2] = *(float *)&pvr_.ISP_BACKGND_D;
vertex_addr += 12;
auto ParseBackgroundVertex =
[&](const ISP_TSP &isp, uint32_t vertex_addr, Vertex *v) {
v->xyz[0] = memory_.RF32(vertex_addr);
v->xyz[1] = memory_.RF32(vertex_addr + 4);
v->xyz[2] = *(float *)&pvr_.ISP_BACKGND_D;
vertex_addr += 12;
if (isp.texture) {
v->uv[0] = memory_.RF32(vertex_addr);
v->uv[1] = memory_.RF32(vertex_addr + 4);
vertex_addr += 8;
debug_break();
}
if (isp.texture) {
v->uv[0] = memory_.RF32(vertex_addr);
v->uv[1] = memory_.RF32(vertex_addr + 4);
vertex_addr += 8;
debug_break();
}
uint32_t base_color = memory_.R32(vertex_addr);
v->color[0] = ((base_color >> 16) & 0xff) / 255.0f;
v->color[1] = ((base_color >> 8) & 0xff) / 255.0f;
v->color[2] = (base_color & 0xff) / 255.0f;
v->color[3] = ((base_color >> 24) & 0xff) / 255.0f;
vertex_addr += 4;
uint32_t base_color = memory_.R32(vertex_addr);
v->color[0] = ((base_color >> 16) & 0xff) / 255.0f;
v->color[1] = ((base_color >> 8) & 0xff) / 255.0f;
v->color[2] = (base_color & 0xff) / 255.0f;
v->color[3] = ((base_color >> 24) & 0xff) / 255.0f;
vertex_addr += 4;
if (isp.offset) {
uint32_t offset_color = memory_.R32(vertex_addr);
v->offset_color[0] = ((offset_color >> 16) & 0xff) / 255.0f;
v->offset_color[1] = ((offset_color >> 16) & 0xff) / 255.0f;
v->offset_color[2] = ((offset_color >> 16) & 0xff) / 255.0f;
v->offset_color[3] = 0.0f;
vertex_addr += 4;
debug_break();
}
};
if (isp.offset) {
uint32_t offset_color = memory_.R32(vertex_addr);
v->offset_color[0] = ((offset_color >> 16) & 0xff) / 255.0f;
v->offset_color[1] = ((offset_color >> 16) & 0xff) / 255.0f;
v->offset_color[2] = ((offset_color >> 16) & 0xff) / 255.0f;
v->offset_color[3] = 0.0f;
vertex_addr += 4;
debug_break();
}
};
// according to the hardware docs, this is the correct calculation of the
// background ISP address. however, in practice, the second TA buffer's ISP

15
src/renderer/gl_backend.cc
View File

@ -44,17 +44,10 @@ static GLenum cull_face[] = {
GL_BACK // CULL_BACK
};
static GLenum blendFuncs[] = {GL_NONE,
GL_ZERO,
GL_ONE,
GL_SRC_COLOR,
GL_ONE_MINUS_SRC_COLOR,
GL_SRC_ALPHA,
GL_ONE_MINUS_SRC_ALPHA,
GL_DST_ALPHA,
GL_ONE_MINUS_DST_ALPHA,
GL_DST_COLOR,
GL_ONE_MINUS_DST_COLOR};
static GLenum blendFuncs[] = {
GL_NONE, GL_ZERO, GL_ONE, GL_SRC_COLOR, GL_ONE_MINUS_SRC_COLOR,
GL_SRC_ALPHA, GL_ONE_MINUS_SRC_ALPHA, GL_DST_ALPHA, GL_ONE_MINUS_DST_ALPHA,
GL_DST_COLOR, GL_ONE_MINUS_DST_COLOR};
GLBackend::GLBackend(GLContext &ctx)
: ctx_(ctx), textures_{0}, fb_ta_(0), num_verts2d_(0), num_surfs2d_(0) {}