mirror of https://github.com/inolen/redream.git
split up sh4 header
This commit is contained in:
Anthony Pesch
parent
8b084c6fde
commit
9585dff4bc
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@ -3,6 +3,11 @@
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#include "guest/dreamcast.h"
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#include "guest/memory.h"
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#include "guest/sh4/sh4_ccn.h"
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#include "guest/sh4/sh4_dbg.h"
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#include "guest/sh4/sh4_dmac.h"
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#include "guest/sh4/sh4_intc.h"
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#include "guest/sh4/sh4_mmu.h"
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#include "guest/sh4/sh4_types.h"
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#include "jit/frontend/sh4/sh4_guest.h"
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#include "jit/jit.h"
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@ -15,33 +20,8 @@ struct jit_guest;
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#define SH4_CLOCK_FREQ INT64_C(200000000)
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enum {
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SH4_DMA_FROM_ADDR,
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SH4_DMA_TO_ADDR,
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};
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typedef int (*sh4_exception_handler_cb)(void *, enum sh4_exception);
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struct sh4_dtr {
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int channel;
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int dir;
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/* when data is non-null, a single address mode transfer is performed between
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the external device memory at data, and the memory at addr
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when data is null, a dual address mode transfer is performed between addr
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and SARn / DARn */
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uint8_t *data;
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uint32_t addr;
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/* size is only valid for single address mode transfers, dual address mode
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transfers honor DMATCR */
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int size;
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};
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struct sh4_tlb_entry {
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union pteh hi;
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union ptel lo;
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};
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struct sh4 {
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struct device;
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@ -86,49 +66,6 @@ extern struct sh4_interrupt_info sh4_interrupts[SH4_NUM_INTERRUPTS];
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AM_DECLARE(sh4_data_map);
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/* ccn */
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void sh4_ccn_pref(struct sh4 *sh4, uint32_t addr);
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uint32_t sh4_ccn_cache_read(struct sh4 *sh4, uint32_t addr, uint32_t data_mask);
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void sh4_ccn_cache_write(struct sh4 *sh4, uint32_t addr, uint32_t data,
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uint32_t data_mask);
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uint32_t sh4_ccn_sq_read(struct sh4 *sh4, uint32_t addr, uint32_t data_mask);
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void sh4_ccn_sq_write(struct sh4 *sh4, uint32_t addr, uint32_t data,
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uint32_t data_mask);
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uint32_t sh4_ccn_icache_read(struct sh4 *sh4, uint32_t addr,
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uint32_t data_mask);
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void sh4_ccn_icache_write(struct sh4 *sh4, uint32_t addr, uint32_t data,
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uint32_t data_mask);
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uint32_t sh4_ccn_ocache_read(struct sh4 *sh4, uint32_t addr,
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uint32_t data_mask);
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void sh4_ccn_ocache_write(struct sh4 *sh4, uint32_t addr, uint32_t data,
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uint32_t data_mask);
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/* dbg */
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int sh4_dbg_num_registers(struct device *dev);
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void sh4_dbg_step(struct device *dev);
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void sh4_dbg_add_breakpoint(struct device *dev, int type, uint32_t addr);
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void sh4_dbg_remove_breakpoint(struct device *dev, int type, uint32_t addr);
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void sh4_dbg_read_memory(struct device *dev, uint32_t addr, uint8_t *buffer,
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int size);
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void sh4_dbg_read_register(struct device *dev, int n, uint64_t *value,
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int *size);
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int sh4_dbg_invalid_instr(struct sh4 *sh4);
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void sh4_dmac_ddt(struct sh4 *sh, struct sh4_dtr *dtr);
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/* intc */
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void sh4_intc_update_pending(struct sh4 *sh4);
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void sh4_intc_reprioritize(struct sh4 *sh4);
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/* mmu */
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void sh4_mmu_ltlb(struct sh4 *sh4);
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uint32_t sh4_mmu_itlb_read(struct sh4 *sh4, uint32_t addr, uint32_t data_mask);
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uint32_t sh4_mmu_utlb_read(struct sh4 *sh4, uint32_t addr, uint32_t data_mask);
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void sh4_mmu_itlb_write(struct sh4 *sh4, uint32_t addr, uint32_t data,
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uint32_t data_mask);
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void sh4_mmu_utlb_write(struct sh4 *sh4, uint32_t addr, uint32_t data,
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uint32_t data_mask);
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struct sh4 *sh4_create(struct dreamcast *dc);
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void sh4_destroy(struct sh4 *sh4);
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void sh4_debug_menu(struct sh4 *sh4);
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@ -0,0 +1,20 @@
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#ifndef SH4_CCN_H
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#define SH4_CCN_H
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void sh4_ccn_pref(struct sh4 *sh4, uint32_t addr);
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uint32_t sh4_ccn_cache_read(struct sh4 *sh4, uint32_t addr, uint32_t data_mask);
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void sh4_ccn_cache_write(struct sh4 *sh4, uint32_t addr, uint32_t data,
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uint32_t data_mask);
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uint32_t sh4_ccn_sq_read(struct sh4 *sh4, uint32_t addr, uint32_t data_mask);
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void sh4_ccn_sq_write(struct sh4 *sh4, uint32_t addr, uint32_t data,
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uint32_t data_mask);
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uint32_t sh4_ccn_icache_read(struct sh4 *sh4, uint32_t addr,
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uint32_t data_mask);
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void sh4_ccn_icache_write(struct sh4 *sh4, uint32_t addr, uint32_t data,
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uint32_t data_mask);
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uint32_t sh4_ccn_ocache_read(struct sh4 *sh4, uint32_t addr,
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uint32_t data_mask);
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void sh4_ccn_ocache_write(struct sh4 *sh4, uint32_t addr, uint32_t data,
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uint32_t data_mask);
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#endif
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@ -0,0 +1,14 @@
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#ifndef SH4_DBG_H
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#define SH4_DBG_H
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int sh4_dbg_num_registers(struct device *dev);
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void sh4_dbg_step(struct device *dev);
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void sh4_dbg_add_breakpoint(struct device *dev, int type, uint32_t addr);
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void sh4_dbg_remove_breakpoint(struct device *dev, int type, uint32_t addr);
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void sh4_dbg_read_memory(struct device *dev, uint32_t addr, uint8_t *buffer,
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int size);
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void sh4_dbg_read_register(struct device *dev, int n, uint64_t *value,
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int *size);
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int sh4_dbg_invalid_instr(struct sh4 *sh4);
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#endif
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@ -0,0 +1,26 @@
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#ifndef SH4_DMAC_H
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#define SH4_DMAC_H
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enum {
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SH4_DMA_FROM_ADDR,
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SH4_DMA_TO_ADDR,
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};
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struct sh4_dtr {
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int channel;
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int dir;
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/* when data is non-null, a single address mode transfer is performed between
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the external device memory at data, and the memory at addr
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when data is null, a dual address mode transfer is performed between addr
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and SARn / DARn */
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uint8_t *data;
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uint32_t addr;
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/* size is only valid for single address mode transfers, dual address mode
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transfers honor DMATCR */
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int size;
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};
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void sh4_dmac_ddt(struct sh4 *sh, struct sh4_dtr *dtr);
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#endif
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@ -0,0 +1,7 @@
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#ifndef SH4_INTC_H
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#define SH4_INTC_H
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void sh4_intc_update_pending(struct sh4 *sh4);
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void sh4_intc_reprioritize(struct sh4 *sh4);
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#endif
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@ -0,0 +1,19 @@
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#ifndef SH4_MMU_H
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#define SH4_MMU_H
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#include "guest/sh4/sh4_types.h"
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struct sh4_tlb_entry {
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union pteh hi;
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union ptel lo;
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};
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void sh4_mmu_ltlb(struct sh4 *sh4);
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uint32_t sh4_mmu_itlb_read(struct sh4 *sh4, uint32_t addr, uint32_t data_mask);
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uint32_t sh4_mmu_utlb_read(struct sh4 *sh4, uint32_t addr, uint32_t data_mask);
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void sh4_mmu_itlb_write(struct sh4 *sh4, uint32_t addr, uint32_t data,
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uint32_t data_mask);
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void sh4_mmu_utlb_write(struct sh4 *sh4, uint32_t addr, uint32_t data,
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uint32_t data_mask);
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#endif
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