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rename interrupt enums

This commit is contained in:
Anthony Pesch 2017-06-04 23:06:55 -04:00
parent ff0ffbc8bb
commit 8cc9ca2d09
9 changed files with 111 additions and 111 deletions
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4
src/hw/aica/aica.c
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@ -298,9 +298,9 @@ static void aica_update_sh(struct aica *aica) {
uint32_t pending_intr = aica->common_data->MCIPD & enabled_intr; uint32_t pending_intr = aica->common_data->MCIPD & enabled_intr;
if (pending_intr) { if (pending_intr) {
holly_raise_interrupt(aica->holly, HOLLY_INTC_G2AICINT); holly_raise_interrupt(aica->holly, HOLLY_INT_G2AICINT);
} else { } else {
holly_clear_interrupt(aica->holly, HOLLY_INTC_G2AICINT); holly_clear_interrupt(aica->holly, HOLLY_INT_G2AICINT);
} }
} }

12
src/hw/gdrom/gdrom.c
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@ -107,7 +107,7 @@ static void gdrom_spi_end(struct gdrom *gd) {
gd->status.BSY = 0; gd->status.BSY = 0;
gd->status.DRQ = 0; gd->status.DRQ = 0;
holly_raise_interrupt(gd->holly, HOLLY_INTC_G1GDINT); holly_raise_interrupt(gd->holly, HOLLY_INT_G1GDINT);
gd->state = STATE_READ_ATA_CMD; gd->state = STATE_READ_ATA_CMD;
} }
@ -150,7 +150,7 @@ static void gdrom_spi_cdread(struct gdrom *gd) {
gd->status.DRQ = 1; gd->status.DRQ = 1;
gd->status.BSY = 0; gd->status.BSY = 0;
holly_raise_interrupt(gd->holly, HOLLY_INTC_G1GDINT); holly_raise_interrupt(gd->holly, HOLLY_INT_G1GDINT);
gd->state = STATE_WRITE_SPI_DATA; gd->state = STATE_WRITE_SPI_DATA;
} }
@ -169,7 +169,7 @@ static void gdrom_spi_read(struct gdrom *gd, int offset, int size) {
gd->status.DRQ = 1; gd->status.DRQ = 1;
gd->status.BSY = 0; gd->status.BSY = 0;
holly_raise_interrupt(gd->holly, HOLLY_INTC_G1GDINT); holly_raise_interrupt(gd->holly, HOLLY_INT_G1GDINT);
gd->state = STATE_READ_SPI_DATA; gd->state = STATE_READ_SPI_DATA;
} }
@ -188,7 +188,7 @@ static void gdrom_spi_write(struct gdrom *gd, void *data, int size) {
gd->status.DRQ = 1; gd->status.DRQ = 1;
gd->status.BSY = 0; gd->status.BSY = 0;
holly_raise_interrupt(gd->holly, HOLLY_INTC_G1GDINT); holly_raise_interrupt(gd->holly, HOLLY_INT_G1GDINT);
gd->state = STATE_WRITE_SPI_DATA; gd->state = STATE_WRITE_SPI_DATA;
} }
@ -197,7 +197,7 @@ static void gdrom_ata_end(struct gdrom *gd) {
gd->status.DRDY = 1; gd->status.DRDY = 1;
gd->status.BSY = 0; gd->status.BSY = 0;
holly_raise_interrupt(gd->holly, HOLLY_INTC_G1GDINT); holly_raise_interrupt(gd->holly, HOLLY_INT_G1GDINT);
gd->state = STATE_READ_ATA_CMD; gd->state = STATE_READ_ATA_CMD;
} }
@ -828,7 +828,7 @@ REG_R32(holly_cb, GD_STATUS_COMMAND) {
struct gdrom *gd = dc->gdrom; struct gdrom *gd = dc->gdrom;
uint16_t value = gd->status.full; uint16_t value = gd->status.full;
LOG_GDROM("read GD_STATUS_COMMAND 0x%x", value); LOG_GDROM("read GD_STATUS_COMMAND 0x%x", value);
holly_clear_interrupt(gd->holly, HOLLY_INTC_G1GDINT); holly_clear_interrupt(gd->holly, HOLLY_INT_G1GDINT);
return value; return value;
} }

42
src/hw/holly/holly.c
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@ -21,7 +21,7 @@ static void holly_ch2_dma(struct holly *hl) {
*hl->SB_C2DLEN = 0; *hl->SB_C2DLEN = 0;
*hl->SB_C2DST = 0; *hl->SB_C2DST = 0;
holly_raise_interrupt(hl, HOLLY_INTC_DTDE2INT); holly_raise_interrupt(hl, HOLLY_INT_DTDE2INT);
} }
/* /*
@ -69,7 +69,7 @@ static void holly_gdrom_dma(struct holly *hl) {
*hl->SB_GDSTARD = addr; *hl->SB_GDSTARD = addr;
*hl->SB_GDLEND = transfer_size; *hl->SB_GDLEND = transfer_size;
*hl->SB_GDST = 0; *hl->SB_GDST = 0;
holly_raise_interrupt(hl, HOLLY_INTC_G1DEINT); holly_raise_interrupt(hl, HOLLY_INT_G1DEINT);
} }
/* /*
@ -135,7 +135,7 @@ static void holly_maple_dma(struct holly *hl) {
} }
*hl->SB_MDST = 0; *hl->SB_MDST = 0;
holly_raise_interrupt(hl, HOLLY_INTC_MDEINT); holly_raise_interrupt(hl, HOLLY_INT_MDEINT);
} }
/* /*
@ -149,10 +149,10 @@ struct g2_channel_desc {
}; };
static struct g2_channel_desc g2_channels[] = { static struct g2_channel_desc g2_channels[] = {
{SB_ADSTAG, SB_ADSTAR, SB_ADLEN, SB_ADDIR, SB_ADTSEL, SB_ADEN, SB_ADST, SB_ADSUSP, HOLLY_INTC_G2DEAINT}, {SB_ADSTAG, SB_ADSTAR, SB_ADLEN, SB_ADDIR, SB_ADTSEL, SB_ADEN, SB_ADST, SB_ADSUSP, HOLLY_INT_G2DEAINT},
{SB_E1STAG, SB_E1STAR, SB_E1LEN, SB_E1DIR, SB_E1TSEL, SB_E1EN, SB_E1ST, SB_E1SUSP, HOLLY_INTC_G2DE1INT}, {SB_E1STAG, SB_E1STAR, SB_E1LEN, SB_E1DIR, SB_E1TSEL, SB_E1EN, SB_E1ST, SB_E1SUSP, HOLLY_INT_G2DE1INT},
{SB_E2STAG, SB_E2STAR, SB_E2LEN, SB_E2DIR, SB_E2TSEL, SB_E2EN, SB_E2ST, SB_E2SUSP, HOLLY_INTC_G2DE2INT}, {SB_E2STAG, SB_E2STAR, SB_E2LEN, SB_E2DIR, SB_E2TSEL, SB_E2EN, SB_E2ST, SB_E2SUSP, HOLLY_INT_G2DE2INT},
{SB_DDSTAG, SB_DDSTAR, SB_DDLEN, SB_DDDIR, SB_DDTSEL, SB_DDEN, SB_DDST, SB_DDSUSP, HOLLY_INTC_G2DEDINT}, {SB_DDSTAG, SB_DDSTAR, SB_DDLEN, SB_DDDIR, SB_DDTSEL, SB_DDEN, SB_DDST, SB_DDSUSP, HOLLY_INT_G2DEDINT},
}; };
#define DEFINE_G2_DMA_TIMER(channel) \ #define DEFINE_G2_DMA_TIMER(channel) \
@ -221,9 +221,9 @@ static void holly_update_interrupts(struct holly *hl) {
if ((*hl->SB_ISTNRM & *hl->SB_IML6NRM) || if ((*hl->SB_ISTNRM & *hl->SB_IML6NRM) ||
(*hl->SB_ISTERR & *hl->SB_IML6ERR) || (*hl->SB_ISTERR & *hl->SB_IML6ERR) ||
(*hl->SB_ISTEXT & *hl->SB_IML6EXT)) { (*hl->SB_ISTEXT & *hl->SB_IML6EXT)) {
sh4_raise_interrupt(hl->sh4, SH4_INTC_IRL_9); sh4_raise_interrupt(hl->sh4, SH4_INT_IRL_9);
} else { } else {
sh4_clear_interrupt(hl->sh4, SH4_INTC_IRL_9); sh4_clear_interrupt(hl->sh4, SH4_INT_IRL_9);
} }
} }
@ -231,9 +231,9 @@ static void holly_update_interrupts(struct holly *hl) {
if ((*hl->SB_ISTNRM & *hl->SB_IML4NRM) || if ((*hl->SB_ISTNRM & *hl->SB_IML4NRM) ||
(*hl->SB_ISTERR & *hl->SB_IML4ERR) || (*hl->SB_ISTERR & *hl->SB_IML4ERR) ||
(*hl->SB_ISTEXT & *hl->SB_IML4EXT)) { (*hl->SB_ISTEXT & *hl->SB_IML4EXT)) {
sh4_raise_interrupt(hl->sh4, SH4_INTC_IRL_11); sh4_raise_interrupt(hl->sh4, SH4_INT_IRL_11);
} else { } else {
sh4_clear_interrupt(hl->sh4, SH4_INTC_IRL_11); sh4_clear_interrupt(hl->sh4, SH4_INT_IRL_11);
} }
} }
@ -241,9 +241,9 @@ static void holly_update_interrupts(struct holly *hl) {
if ((*hl->SB_ISTNRM & *hl->SB_IML2NRM) || if ((*hl->SB_ISTNRM & *hl->SB_IML2NRM) ||
(*hl->SB_ISTERR & *hl->SB_IML2ERR) || (*hl->SB_ISTERR & *hl->SB_IML2ERR) ||
(*hl->SB_ISTEXT & *hl->SB_IML2EXT)) { (*hl->SB_ISTEXT & *hl->SB_IML2EXT)) {
sh4_raise_interrupt(hl->sh4, SH4_INTC_IRL_13); sh4_raise_interrupt(hl->sh4, SH4_INT_IRL_13);
} else { } else {
sh4_clear_interrupt(hl->sh4, SH4_INTC_IRL_13); sh4_clear_interrupt(hl->sh4, SH4_INT_IRL_13);
} }
} }
} }
@ -284,11 +284,11 @@ static uint32_t holly_reg_read(struct holly *hl, uint32_t addr,
static uint32_t *holly_interrupt_status(struct holly *hl, static uint32_t *holly_interrupt_status(struct holly *hl,
enum holly_interrupt_type type) { enum holly_interrupt_type type) {
switch (type) { switch (type) {
case HOLLY_INTC_NRM: case HOLLY_INT_NRM:
return hl->SB_ISTNRM; return hl->SB_ISTNRM;
case HOLLY_INTC_EXT: case HOLLY_INT_EXT:
return hl->SB_ISTEXT; return hl->SB_ISTEXT;
case HOLLY_INTC_ERR: case HOLLY_INT_ERR:
return hl->SB_ISTERR; return hl->SB_ISTERR;
default: default:
LOG_FATAL("Invalid interrupt type"); LOG_FATAL("Invalid interrupt type");
@ -315,7 +315,7 @@ void holly_raise_interrupt(struct holly *hl, holly_interrupt_t intr) {
holly_update_interrupts(hl); holly_update_interrupts(hl);
/* check for hardware dma initiation */ /* check for hardware dma initiation */
if (intr == HOLLY_INTC_PCVOINT && *hl->SB_MDTSEL && *hl->SB_MDEN) { if (intr == HOLLY_INT_PCVOINT && *hl->SB_MDTSEL && *hl->SB_MDEN) {
holly_maple_dma(hl); holly_maple_dma(hl);
} }
} }
@ -333,15 +333,15 @@ static void holly_debug_menu(struct device *dev, struct nk_context *ctx) {
hl->log_reg_access = !hl->log_reg_access; hl->log_reg_access = !hl->log_reg_access;
} }
if (nk_button_label(ctx, "raise all HOLLY_INTC_NRM")) { if (nk_button_label(ctx, "raise all HOLLY_INT_NRM")) {
for (int i = 0; i < 22; i++) { for (int i = 0; i < 22; i++) {
holly_raise_interrupt(hl, HOLLY_INTERRUPT(HOLLY_INTC_NRM, 1 << i)); holly_raise_interrupt(hl, HOLLY_INTERRUPT(HOLLY_INT_NRM, 1 << i));
} }
} }
if (nk_button_label(ctx, "raise all HOLLY_INTC_EXT")) { if (nk_button_label(ctx, "raise all HOLLY_INT_EXT")) {
for (int i = 0; i < 4; i++) { for (int i = 0; i < 4; i++) {
holly_raise_interrupt(hl, HOLLY_INTERRUPT(HOLLY_INTC_EXT, 1 << i)); holly_raise_interrupt(hl, HOLLY_INTERRUPT(HOLLY_INT_EXT, 1 << i));
} }
} }

128
src/hw/holly/holly_types.h
View File

@ -17,135 +17,135 @@ enum {
#define HOLLY_INTERRUPT_IRQ(intr) ((uint32_t)(intr)) #define HOLLY_INTERRUPT_IRQ(intr) ((uint32_t)(intr))
enum holly_interrupt_type { enum holly_interrupt_type {
HOLLY_INTC_NRM = 0x1, HOLLY_INT_NRM = 0x1,
HOLLY_INTC_EXT = 0x2, HOLLY_INT_EXT = 0x2,
HOLLY_INTC_ERR = 0x3 HOLLY_INT_ERR = 0x3
}; };
typedef uint64_t holly_interrupt_t; typedef uint64_t holly_interrupt_t;
/* /*
* HOLLY_INTC_NRM * HOLLY_INT_NRM
*/ */
/* Video End of Render */ /* Video End of Render */
#define HOLLY_INTC_PCEOVINT HOLLY_INTERRUPT(HOLLY_INTC_NRM, 0x1) #define HOLLY_INT_PCEOVINT HOLLY_INTERRUPT(HOLLY_INT_NRM, 0x1)
/* ISP End of Render */ /* ISP End of Render */
#define HOLLY_INTC_PCEOIINT HOLLY_INTERRUPT(HOLLY_INTC_NRM, 0x2) #define HOLLY_INT_PCEOIINT HOLLY_INTERRUPT(HOLLY_INT_NRM, 0x2)
/* TSP End of Render */ /* TSP End of Render */
#define HOLLY_INTC_PCEOTINT HOLLY_INTERRUPT(HOLLY_INTC_NRM, 0x4) #define HOLLY_INT_PCEOTINT HOLLY_INTERRUPT(HOLLY_INT_NRM, 0x4)
/* VBlank In */ /* VBlank In */
#define HOLLY_INTC_PCVIINT HOLLY_INTERRUPT(HOLLY_INTC_NRM, 0x8) #define HOLLY_INT_PCVIINT HOLLY_INTERRUPT(HOLLY_INT_NRM, 0x8)
/* VBlank Out */ /* VBlank Out */
#define HOLLY_INTC_PCVOINT HOLLY_INTERRUPT(HOLLY_INTC_NRM, 0x10) #define HOLLY_INT_PCVOINT HOLLY_INTERRUPT(HOLLY_INT_NRM, 0x10)
/* HBlank In */ /* HBlank In */
#define HOLLY_INTC_PCHIINT HOLLY_INTERRUPT(HOLLY_INTC_NRM, 0x20) #define HOLLY_INT_PCHIINT HOLLY_INTERRUPT(HOLLY_INT_NRM, 0x20)
/* End Of YUV Data Storage */ /* End Of YUV Data Storage */
#define HOLLY_INTC_TAYUVINT HOLLY_INTERRUPT(HOLLY_INTC_NRM, 0x40) #define HOLLY_INT_TAYUVINT HOLLY_INTERRUPT(HOLLY_INT_NRM, 0x40)
/* End Of Opaque List Storage */ /* End Of Opaque List Storage */
#define HOLLY_INTC_TAEOINT HOLLY_INTERRUPT(HOLLY_INTC_NRM, 0x80) #define HOLLY_INT_TAEOINT HOLLY_INTERRUPT(HOLLY_INT_NRM, 0x80)
/* End Of Opaque Modifier Volume List Storage */ /* End Of Opaque Modifier Volume List Storage */
#define HOLLY_INTC_TAEOMINT HOLLY_INTERRUPT(HOLLY_INTC_NRM, 0x100) #define HOLLY_INT_TAEOMINT HOLLY_INTERRUPT(HOLLY_INT_NRM, 0x100)
/* End Of Translucent List Storage */ /* End Of Translucent List Storage */
#define HOLLY_INTC_TAETINT HOLLY_INTERRUPT(HOLLY_INTC_NRM, 0x200) #define HOLLY_INT_TAETINT HOLLY_INTERRUPT(HOLLY_INT_NRM, 0x200)
/* End Of Translucent Modifier Volume List Storage */ /* End Of Translucent Modifier Volume List Storage */
#define HOLLY_INTC_TAETMINT HOLLY_INTERRUPT(HOLLY_INTC_NRM, 0x400) #define HOLLY_INT_TAETMINT HOLLY_INTERRUPT(HOLLY_INT_NRM, 0x400)
/* PVR End of DMA */ /* PVR End of DMA */
#define HOLLY_INTC_PIDEINT HOLLY_INTERRUPT(HOLLY_INTC_NRM, 0x800) #define HOLLY_INT_PIDEINT HOLLY_INTERRUPT(HOLLY_INT_NRM, 0x800)
/* MAPLE End of DMA */ /* MAPLE End of DMA */
#define HOLLY_INTC_MDEINT HOLLY_INTERRUPT(HOLLY_INTC_NRM, 0x1000) #define HOLLY_INT_MDEINT HOLLY_INTERRUPT(HOLLY_INT_NRM, 0x1000)
/* MAPLE VBlank Over */ /* MAPLE VBlank Over */
#define HOLLY_INTC_MVOINT HOLLY_INTERRUPT(HOLLY_INTC_NRM, 0x2000) #define HOLLY_INT_MVOINT HOLLY_INTERRUPT(HOLLY_INT_NRM, 0x2000)
/* G1 End of DMA */ /* G1 End of DMA */
#define HOLLY_INTC_G1DEINT HOLLY_INTERRUPT(HOLLY_INTC_NRM, 0x4000) #define HOLLY_INT_G1DEINT HOLLY_INTERRUPT(HOLLY_INT_NRM, 0x4000)
/* G2 End of AICA-DMA */ /* G2 End of AICA-DMA */
#define HOLLY_INTC_G2DEAINT HOLLY_INTERRUPT(HOLLY_INTC_NRM, 0x8000) #define HOLLY_INT_G2DEAINT HOLLY_INTERRUPT(HOLLY_INT_NRM, 0x8000)
/* G2 End of Ext-DMA1 */ /* G2 End of Ext-DMA1 */
#define HOLLY_INTC_G2DE1INT HOLLY_INTERRUPT(HOLLY_INTC_NRM, 0x10000) #define HOLLY_INT_G2DE1INT HOLLY_INTERRUPT(HOLLY_INT_NRM, 0x10000)
/* G2 End of Ext-DMA2 */ /* G2 End of Ext-DMA2 */
#define HOLLY_INTC_G2DE2INT HOLLY_INTERRUPT(HOLLY_INTC_NRM, 0x20000) #define HOLLY_INT_G2DE2INT HOLLY_INTERRUPT(HOLLY_INT_NRM, 0x20000)
/* G2 End of Dev-DMA */ /* G2 End of Dev-DMA */
#define HOLLY_INTC_G2DEDINT HOLLY_INTERRUPT(HOLLY_INTC_NRM, 0x40000) #define HOLLY_INT_G2DEDINT HOLLY_INTERRUPT(HOLLY_INT_NRM, 0x40000)
/* End of ch2-DMA */ /* End of ch2-DMA */
#define HOLLY_INTC_DTDE2INT HOLLY_INTERRUPT(HOLLY_INTC_NRM, 0x80000) #define HOLLY_INT_DTDE2INT HOLLY_INTERRUPT(HOLLY_INT_NRM, 0x80000)
/* End of Sort-DMA */ /* End of Sort-DMA */
#define HOLLY_INTC_DTDESINT HOLLY_INTERRUPT(HOLLY_INTC_NRM, 0x100000) #define HOLLY_INT_DTDESINT HOLLY_INTERRUPT(HOLLY_INT_NRM, 0x100000)
/* End Of Punch Through List Storage */ /* End Of Punch Through List Storage */
#define HOLLY_INTC_TAEPTIN HOLLY_INTERRUPT(HOLLY_INTC_NRM, 0x200000) #define HOLLY_INT_TAEPTIN HOLLY_INTERRUPT(HOLLY_INT_NRM, 0x200000)
/* /*
* HOLLY_INTC_EXT * HOLLY_INT_EXT
*/ */
/* From GD-ROM Drive */ /* From GD-ROM Drive */
#define HOLLY_INTC_G1GDINT HOLLY_INTERRUPT(HOLLY_INTC_EXT, 0x1) #define HOLLY_INT_G1GDINT HOLLY_INTERRUPT(HOLLY_INT_EXT, 0x1)
/* From AICA */ /* From AICA */
#define HOLLY_INTC_G2AICINT HOLLY_INTERRUPT(HOLLY_INTC_EXT, 0x2) #define HOLLY_INT_G2AICINT HOLLY_INTERRUPT(HOLLY_INT_EXT, 0x2)
/* From Modem */ /* From Modem */
#define HOLLY_INTC_G2MDMINT HOLLY_INTERRUPT(HOLLY_INTC_EXT, 0x4) #define HOLLY_INT_G2MDMINT HOLLY_INTERRUPT(HOLLY_INT_EXT, 0x4)
/* From External Device */ /* From External Device */
#define HOLLY_INTC_G2EXTINT HOLLY_INTERRUPT(HOLLY_INTC_EXT, 0x8) #define HOLLY_INT_G2EXTINT HOLLY_INTERRUPT(HOLLY_INT_EXT, 0x8)
/* /*
* HOLLY_INTC_ERR * HOLLY_INT_ERR
*/ */
/* ISP Out of Cache */ /* ISP Out of Cache */
#define HOLLY_INTC_PCIOCINT HOLLY_INTERRUPT(HOLLY_INTC_ERR, 0x1) #define HOLLY_INT_PCIOCINT HOLLY_INTERRUPT(HOLLY_INT_ERR, 0x1)
/* Hazard Processing of Strip Buffer */ /* Hazard Processing of Strip Buffer */
#define HOLLY_INTC_PCHZDINT HOLLY_INTERRUPT(HOLLY_INTC_ERR, 0x2) #define HOLLY_INT_PCHZDINT HOLLY_INTERRUPT(HOLLY_INT_ERR, 0x2)
/* ISP/TSP Parameter Limit Address */ /* ISP/TSP Parameter Limit Address */
#define HOLLY_INTC_TAPOFINT HOLLY_INTERRUPT(HOLLY_INTC_ERR, 0x4) #define HOLLY_INT_TAPOFINT HOLLY_INTERRUPT(HOLLY_INT_ERR, 0x4)
/* Object List Limit Address */ /* Object List Limit Address */
#define HOLLY_INTC_TALOFINT HOLLY_INTERRUPT(HOLLY_INTC_ERR, 0x8) #define HOLLY_INT_TALOFINT HOLLY_INTERRUPT(HOLLY_INT_ERR, 0x8)
/* Illegal Parameter Input */ /* Illegal Parameter Input */
#define HOLLY_INTC_TAIPINT HOLLY_INTERRUPT(HOLLY_INTC_ERR, 0x10) #define HOLLY_INT_TAIPINT HOLLY_INTERRUPT(HOLLY_INT_ERR, 0x10)
/* TA FIFO Over Flow */ /* TA FIFO Over Flow */
#define HOLLY_INTC_TAFOFINT HOLLY_INTERRUPT(HOLLY_INTC_ERR, 0x20) #define HOLLY_INT_TAFOFINT HOLLY_INTERRUPT(HOLLY_INT_ERR, 0x20)
/* PVR Illegal Address Set */ /* PVR Illegal Address Set */
#define HOLLY_INTC_PIIAINT HOLLY_INTERRUPT(HOLLY_INTC_ERR, 0x40) #define HOLLY_INT_PIIAINT HOLLY_INTERRUPT(HOLLY_INT_ERR, 0x40)
/* PVR DMA Over Run */ /* PVR DMA Over Run */
#define HOLLY_INTC_PIORINT HOLLY_INTERRUPT(HOLLY_INTC_ERR, 0x80) #define HOLLY_INT_PIORINT HOLLY_INTERRUPT(HOLLY_INT_ERR, 0x80)
/* MAPLE Illegal Address Set */ /* MAPLE Illegal Address Set */
#define HOLLY_INTC_MIAINT HOLLY_INTERRUPT(HOLLY_INTC_ERR, 0x100) #define HOLLY_INT_MIAINT HOLLY_INTERRUPT(HOLLY_INT_ERR, 0x100)
/* MAPLE DMA Over Run */ /* MAPLE DMA Over Run */
#define HOLLY_INTC_MORINT HOLLY_INTERRUPT(HOLLY_INTC_ERR, 0x200) #define HOLLY_INT_MORINT HOLLY_INTERRUPT(HOLLY_INT_ERR, 0x200)
/* MAPLE Write FIFO Overf Flow */ /* MAPLE Write FIFO Overf Flow */
#define HOLLY_INTC_MFOFINT HOLLY_INTERRUPT(HOLLY_INTC_ERR, 0x400) #define HOLLY_INT_MFOFINT HOLLY_INTERRUPT(HOLLY_INT_ERR, 0x400)
/* MAPLE Illegal Command */ /* MAPLE Illegal Command */
#define HOLLY_INTC_MICINT HOLLY_INTERRUPT(HOLLY_INTC_ERR, 0x800) #define HOLLY_INT_MICINT HOLLY_INTERRUPT(HOLLY_INT_ERR, 0x800)
/* G1 Illegal Address Set */ /* G1 Illegal Address Set */
#define HOLLY_INTC_G1IAINT HOLLY_INTERRUPT(HOLLY_INTC_ERR, 0x1000) #define HOLLY_INT_G1IAINT HOLLY_INTERRUPT(HOLLY_INT_ERR, 0x1000)
/* G1 DMA Over Run */ /* G1 DMA Over Run */
#define HOLLY_INTC_G1ORINT HOLLY_INTERRUPT(HOLLY_INTC_ERR, 0x2000) #define HOLLY_INT_G1ORINT HOLLY_INTERRUPT(HOLLY_INT_ERR, 0x2000)
/* G1 Access at DMA */ /* G1 Access at DMA */
#define HOLLY_INTC_G1ATINT HOLLY_INTERRUPT(HOLLY_INTC_ERR, 0x4000) #define HOLLY_INT_G1ATINT HOLLY_INTERRUPT(HOLLY_INT_ERR, 0x4000)
/* G2 AICA-DMA Illegal Address Set */ /* G2 AICA-DMA Illegal Address Set */
#define HOLLY_INTC_G2IAAINT HOLLY_INTERRUPT(HOLLY_INTC_ERR, 0x8000) #define HOLLY_INT_G2IAAINT HOLLY_INTERRUPT(HOLLY_INT_ERR, 0x8000)
/* G2 Ext1-DMA Illegal Address Set */ /* G2 Ext1-DMA Illegal Address Set */
#define HOLLY_INTC_G2IA1INT HOLLY_INTERRUPT(HOLLY_INTC_ERR, 0x10000) #define HOLLY_INT_G2IA1INT HOLLY_INTERRUPT(HOLLY_INT_ERR, 0x10000)
/* G2 Ext2-DMA Illegal Address Set */ /* G2 Ext2-DMA Illegal Address Set */
#define HOLLY_INTC_G2IA2INT HOLLY_INTERRUPT(HOLLY_INTC_ERR, 0x20000) #define HOLLY_INT_G2IA2INT HOLLY_INTERRUPT(HOLLY_INT_ERR, 0x20000)
/* G2 Dev-DMA Illegal Address Set */ /* G2 Dev-DMA Illegal Address Set */
#define HOLLY_INTC_G2IADINT HOLLY_INTERRUPT(HOLLY_INTC_ERR, 0x40000) #define HOLLY_INT_G2IADINT HOLLY_INTERRUPT(HOLLY_INT_ERR, 0x40000)
/* G2 AICA-DMA Over Run */ /* G2 AICA-DMA Over Run */
#define HOLLY_INTC_G2ORAINT HOLLY_INTERRUPT(HOLLY_INTC_ERR, 0x80000) #define HOLLY_INT_G2ORAINT HOLLY_INTERRUPT(HOLLY_INT_ERR, 0x80000)
/* G2 Ext1-DMA Over Run */ /* G2 Ext1-DMA Over Run */
#define HOLLY_INTC_G2OR1INT HOLLY_INTERRUPT(HOLLY_INTC_ERR, 0x100000) #define HOLLY_INT_G2OR1INT HOLLY_INTERRUPT(HOLLY_INT_ERR, 0x100000)
/* G2 Ext2-DMA Over Run */ /* G2 Ext2-DMA Over Run */
#define HOLLY_INTC_G2OR2INT HOLLY_INTERRUPT(HOLLY_INTC_ERR, 0x200000) #define HOLLY_INT_G2OR2INT HOLLY_INTERRUPT(HOLLY_INT_ERR, 0x200000)
/* G2 Dev-DMA Over Run */ /* G2 Dev-DMA Over Run */
#define HOLLY_INTC_G2ORDINT HOLLY_INTERRUPT(HOLLY_INTC_ERR, 0x400000) #define HOLLY_INT_G2ORDINT HOLLY_INTERRUPT(HOLLY_INT_ERR, 0x400000)
/* G2 AICA-DMA Time Out */ /* G2 AICA-DMA Time Out */
#define HOLLY_INTC_G2TOAINT HOLLY_INTERRUPT(HOLLY_INTC_ERR, 0x800000) #define HOLLY_INT_G2TOAINT HOLLY_INTERRUPT(HOLLY_INT_ERR, 0x800000)
/* G2 Ext1-DMA Time Out */ /* G2 Ext1-DMA Time Out */
#define HOLLY_INTC_G2TO1INT HOLLY_INTERRUPT(HOLLY_INTC_ERR, 0x1000000) #define HOLLY_INT_G2TO1INT HOLLY_INTERRUPT(HOLLY_INT_ERR, 0x1000000)
/* G2 Ext2-DMA Time Out */ /* G2 Ext2-DMA Time Out */
#define HOLLY_INTC_G2TO2INT HOLLY_INTERRUPT(HOLLY_INTC_ERR, 0x2000000) #define HOLLY_INT_G2TO2INT HOLLY_INTERRUPT(HOLLY_INT_ERR, 0x2000000)
/* G2 Dev-DMA Time Out */ /* G2 Dev-DMA Time Out */
#define HOLLY_INTC_G2TODINT HOLLY_INTERRUPT(HOLLY_INTC_ERR, 0x4000000) #define HOLLY_INT_G2TODINT HOLLY_INTERRUPT(HOLLY_INT_ERR, 0x4000000)
/* G2 Time Out in CPU Accessing */ /* G2 Time Out in CPU Accessing */
#define HOLLY_INTC_G2TOCINT HOLLY_INTERRUPT(HOLLY_INTC_ERR, 0x8000000) #define HOLLY_INT_G2TOCINT HOLLY_INTERRUPT(HOLLY_INT_ERR, 0x8000000)
/* Sort-DMA Command Error */ /* Sort-DMA Command Error */
#define HOLLY_INTC_DTCESINT HOLLY_INTERRUPT(HOLLY_INTC_ERR, 0x10000000) #define HOLLY_INT_DTCESINT HOLLY_INTERRUPT(HOLLY_INT_ERR, 0x10000000)
#define HOLLY_INTC_RESERVED1 HOLLY_INTERRUPT(HOLLY_INTC_ERR, 0x20000000) #define HOLLY_INT_RESERVED1 HOLLY_INTERRUPT(HOLLY_INT_ERR, 0x20000000)
#define HOLLY_INTC_RESERVED2 HOLLY_INTERRUPT(HOLLY_INTC_ERR, 0x40000000) #define HOLLY_INT_RESERVED2 HOLLY_INTERRUPT(HOLLY_INT_ERR, 0x40000000)
/* SH4 Accessing to Inhibited Area */ /* SH4 Accessing to Inhibited Area */
#define HOLLY_INTC_CIHINT HOLLY_INTERRUPT(HOLLY_INTC_ERR, 0x80000000) #define HOLLY_INT_CIHINT HOLLY_INTERRUPT(HOLLY_INT_ERR, 0x80000000)
#endif #endif

6
src/hw/pvr/pvr.c
View File

@ -21,16 +21,16 @@ static void pvr_next_scanline(void *data) {
/* vblank in */ /* vblank in */
if (pvr->current_line == pvr->SPG_VBLANK_INT->vblank_in_line_number) { if (pvr->current_line == pvr->SPG_VBLANK_INT->vblank_in_line_number) {
holly_raise_interrupt(pvr->holly, HOLLY_INTC_PCVIINT); holly_raise_interrupt(pvr->holly, HOLLY_INT_PCVIINT);
} }
/* vblank out */ /* vblank out */
if (pvr->current_line == pvr->SPG_VBLANK_INT->vblank_out_line_number) { if (pvr->current_line == pvr->SPG_VBLANK_INT->vblank_out_line_number) {
holly_raise_interrupt(pvr->holly, HOLLY_INTC_PCVOINT); holly_raise_interrupt(pvr->holly, HOLLY_INT_PCVOINT);
} }
/* hblank in */ /* hblank in */
holly_raise_interrupt(pvr->holly, HOLLY_INTC_PCHIINT); holly_raise_interrupt(pvr->holly, HOLLY_INT_PCHIINT);
int was_vsync = pvr->SPG_STATUS->vsync; int was_vsync = pvr->SPG_STATUS->vsync;
if (pvr->SPG_VBLANK->vbstart < pvr->SPG_VBLANK->vbend) { if (pvr->SPG_VBLANK->vbstart < pvr->SPG_VBLANK->vbend) {

18
src/hw/pvr/ta.c
View File

@ -55,11 +55,11 @@ int g_poly_types[0x100 * TA_NUM_PARAMS * TA_NUM_LISTS];
int g_vertex_types[0x100 * TA_NUM_PARAMS * TA_NUM_LISTS]; int g_vertex_types[0x100 * TA_NUM_PARAMS * TA_NUM_LISTS];
static holly_interrupt_t list_interrupts[] = { static holly_interrupt_t list_interrupts[] = {
HOLLY_INTC_TAEOINT, /* TA_LIST_OPAQUE */ HOLLY_INT_TAEOINT, /* TA_LIST_OPAQUE */
HOLLY_INTC_TAEOMINT, /* TA_LIST_OPAQUE_MODVOL */ HOLLY_INT_TAEOMINT, /* TA_LIST_OPAQUE_MODVOL */
HOLLY_INTC_TAETINT, /* TA_LIST_TRANSLUCENT */ HOLLY_INT_TAETINT, /* TA_LIST_TRANSLUCENT */
HOLLY_INTC_TAETMINT, /* TA_LIST_TRANSLUCENT_MODVOL */ HOLLY_INT_TAETMINT, /* TA_LIST_TRANSLUCENT_MODVOL */
HOLLY_INTC_TAEPTIN /* TA_LIST_PUNCH_THROUGH */ HOLLY_INT_TAEPTIN /* TA_LIST_PUNCH_THROUGH */
}; };
/* See "57.1.1.2 Parameter Combinations" for information on the poly types. */ /* See "57.1.1.2 Parameter Combinations" for information on the poly types. */
@ -447,9 +447,9 @@ static void ta_finish_render(void *data) {
ta_free_context(ta, ctx); ta_free_context(ta, ctx);
/* let the game know rendering is complete */ /* let the game know rendering is complete */
holly_raise_interrupt(ta->holly, HOLLY_INTC_PCEOVINT); holly_raise_interrupt(ta->holly, HOLLY_INT_PCEOVINT);
holly_raise_interrupt(ta->holly, HOLLY_INTC_PCEOIINT); holly_raise_interrupt(ta->holly, HOLLY_INT_PCEOIINT);
holly_raise_interrupt(ta->holly, HOLLY_INTC_PCEOTINT); holly_raise_interrupt(ta->holly, HOLLY_INT_PCEOTINT);
} }
static void ta_start_render(struct ta *ta, struct tile_context *ctx) { static void ta_start_render(struct ta *ta, struct tile_context *ctx) {
@ -564,7 +564,7 @@ static void ta_yuv_process_macroblock(struct ta *ta, void *data) {
ta_yuv_init(ta); ta_yuv_init(ta);
/* raise DMA end interrupt */ /* raise DMA end interrupt */
holly_raise_interrupt(ta->holly, HOLLY_INTC_TAYUVINT); holly_raise_interrupt(ta->holly, HOLLY_INT_TAYUVINT);
} }
} }

8
src/hw/sh4/sh4_dmac.c
View File

@ -51,28 +51,28 @@ void sh4_dmac_ddt(struct sh4 *sh4, struct sh4_dtr *dtr) {
dar = sh4->DAR0; dar = sh4->DAR0;
dmatcr = sh4->DMATCR0; dmatcr = sh4->DMATCR0;
chcr = sh4->CHCR0; chcr = sh4->CHCR0;
dmte = SH4_INTC_DMTE0; dmte = SH4_INT_DMTE0;
break; break;
case 1: case 1:
sar = sh4->SAR1; sar = sh4->SAR1;
dar = sh4->DAR1; dar = sh4->DAR1;
dmatcr = sh4->DMATCR1; dmatcr = sh4->DMATCR1;
chcr = sh4->CHCR1; chcr = sh4->CHCR1;
dmte = SH4_INTC_DMTE1; dmte = SH4_INT_DMTE1;
break; break;
case 2: case 2:
sar = sh4->SAR2; sar = sh4->SAR2;
dar = sh4->DAR2; dar = sh4->DAR2;
dmatcr = sh4->DMATCR2; dmatcr = sh4->DMATCR2;
chcr = sh4->CHCR2; chcr = sh4->CHCR2;
dmte = SH4_INTC_DMTE2; dmte = SH4_INT_DMTE2;
break; break;
case 3: case 3:
sar = sh4->SAR3; sar = sh4->SAR3;
dar = sh4->DAR3; dar = sh4->DAR3;
dmatcr = sh4->DMATCR3; dmatcr = sh4->DMATCR3;
chcr = sh4->CHCR3; chcr = sh4->CHCR3;
dmte = SH4_INTC_DMTE3; dmte = SH4_INT_DMTE3;
break; break;
default: default:
LOG_FATAL("Unexpected DMA channel"); LOG_FATAL("Unexpected DMA channel");

2
src/hw/sh4/sh4_tmu.c
View File

@ -9,7 +9,7 @@ static const int PERIPHERAL_SCALE[] = {2, 4, 6, 8, 10, 0, 0, 0};
#define TCNT(n) (n == 0 ? sh4->TCNT0 : n == 1 ? sh4->TCNT1 : sh4->TCNT2) #define TCNT(n) (n == 0 ? sh4->TCNT0 : n == 1 ? sh4->TCNT1 : sh4->TCNT2)
#define TCR(n) (n == 0 ? sh4->TCR0 : n == 1 ? sh4->TCR1 : sh4->TCR2) #define TCR(n) (n == 0 ? sh4->TCR0 : n == 1 ? sh4->TCR1 : sh4->TCR2)
#define TUNI(n) \ #define TUNI(n) \
(n == 0 ? SH4_INTC_TUNI0 : n == 1 ? SH4_INTC_TUNI1 : SH4_INTC_TUNI2) (n == 0 ? SH4_INT_TUNI0 : n == 1 ? SH4_INT_TUNI1 : SH4_INT_TUNI2)
static void sh4_tmu_reschedule(struct sh4 *sh4, int n, uint32_t tcnt, static void sh4_tmu_reschedule(struct sh4 *sh4, int n, uint32_t tcnt,
uint32_t tcr); uint32_t tcr);

2
src/hw/sh4/sh4_types.h
View File

@ -78,7 +78,7 @@ enum {
}; };
enum sh4_interrupt { enum sh4_interrupt {
#define SH4_INT(name, intevt, pri, ipr, ipr_shift) SH4_INTC_##name, #define SH4_INT(name, intevt, pri, ipr, ipr_shift) SH4_INT_##name,
#include "hw/sh4/sh4_int.inc" #include "hw/sh4/sh4_int.inc"
#undef SH4_INT #undef SH4_INT
NUM_SH_INTERRUPTS NUM_SH_INTERRUPTS