mirror of https://github.com/inolen/redream.git
preserve registers when emitting delay slots
This commit is contained in:
Anthony Pesch
parent
5a0642d0a5
commit
6f4aebf144
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@ -97,9 +97,6 @@ IntInstr *AssembleContext::TranslateInstr(Instr &ir_i) {
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i->fn = GetCallback(ir_i.op(), GetSignature(ir_i), GetAccessMask(ir_i));
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i->guest_addr = ir_i.guest_addr;
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i->guest_op = ir_i.guest_op;
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return i;
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}
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@ -65,8 +65,6 @@ union IntValue {
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struct IntInstr {
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IntFn fn;
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IntValue arg[4];
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intptr_t guest_addr;
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intptr_t guest_op;
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};
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class AssembleContext {
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@ -11,7 +11,11 @@ using namespace dreavm::cpu::ir;
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using namespace dreavm::emu;
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SH4Builder::SH4Builder(Memory &memory)
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: memory_(memory), has_delay_instr_(false), last_instr_(nullptr) {}
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: memory_(memory),
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has_delay_instr_(false),
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preserve_offset_(-1),
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preserve_mask_(0),
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offset_preserved_(false) {}
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SH4Builder::~SH4Builder() {}
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@ -36,15 +40,7 @@ void SH4Builder::Emit(uint32_t start_addr) {
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}
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// emit the current instruction
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printf("SH4::Emit %s\n", instr.type->name);
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(emit_callbacks[instr.type->op])(*this, instr);
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// find the first ir instruction emitted for this op
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ir::Instr *emitted = GetFirstEmittedInstr();
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if (emitted) {
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emitted->guest_addr = addr;
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emitted->guest_op = instr.type->op;
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}
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(emit_callbacks[instr.type->op])(*this, fpu_state_, instr);
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// delayed instructions will be emitted already by the instructions handler
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addr += delayed ? 4 : 2;
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@ -81,48 +77,13 @@ void SH4Builder::Emit(uint32_t start_addr) {
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SetMetadata(MD_GUEST_CYCLES, AllocConstant(guest_cycles));
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}
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void SH4Builder::DumpToFile(uint32_t start_addr) {
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char filename[PATH_MAX];
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snprintf(filename, sizeof(filename), "../dreamcast/0x%x.bin", start_addr);
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printf("DUMPING 0x%x to %s\n", start_addr, filename);
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FILE *fp = fopen(filename, "wb");
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if (!fp) {
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printf("FAILED TO OPEN FILE HANDLE\n");
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return;
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}
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uint32_t addr = start_addr;
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while (true) {
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uint16_t opcode = memory_.R16(addr);
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Instr instr(addr, opcode);
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bool delayed = instr.type->flags & OP_FLAG_DELAYED;
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fwrite(&opcode, 2, 1, fp);
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if (delayed) {
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uint16_t delay_opcode = memory_.R16(addr + 2);
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fwrite(&delay_opcode, 2, 1, fp);
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}
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if (instr.type->flags & OP_FLAG_BRANCH) {
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break;
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}
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addr += delayed ? 4 : 2;
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}
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fclose(fp);
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}
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Value *SH4Builder::LoadRegister(int n, ValueTy type) {
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return LoadContext(offsetof(SH4Context, r[n]), type);
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}
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void SH4Builder::StoreRegister(int n, Value *v) {
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CHECK_EQ(v->type(), VALUE_I32);
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return StoreContext(offsetof(SH4Context, r[n]), v);
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return StoreAndPreserveContext(offsetof(SH4Context, r[n]), v);
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}
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Value *SH4Builder::LoadRegisterF(int n, ValueTy type) {
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@ -130,7 +91,7 @@ Value *SH4Builder::LoadRegisterF(int n, ValueTy type) {
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}
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void SH4Builder::StoreRegisterF(int n, Value *v) {
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return StoreContext(offsetof(SH4Context, fr[n]), v);
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return StoreAndPreserveContext(offsetof(SH4Context, fr[n]), v);
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}
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Value *SH4Builder::LoadRegisterXF(int n, ValueTy type) {
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@ -138,7 +99,7 @@ Value *SH4Builder::LoadRegisterXF(int n, ValueTy type) {
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}
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void SH4Builder::StoreRegisterXF(int n, Value *v) {
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return StoreContext(offsetof(SH4Context, xf[n]), v);
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return StoreAndPreserveContext(offsetof(SH4Context, xf[n]), v);
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}
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Value *SH4Builder::LoadSR() {
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@ -147,7 +108,7 @@ Value *SH4Builder::LoadSR() {
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void SH4Builder::StoreSR(Value *v) {
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CHECK_EQ(v->type(), VALUE_I32);
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StoreContext(offsetof(SH4Context, sr), v, IF_INVALIDATE_CONTEXT);
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StoreAndPreserveContext(offsetof(SH4Context, sr), v, IF_INVALIDATE_CONTEXT);
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CallExternal((ExternalFn)&SRUpdated);
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}
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@ -163,7 +124,7 @@ Value *SH4Builder::LoadGBR() {
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}
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void SH4Builder::StoreGBR(Value *v) {
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StoreContext(offsetof(SH4Context, gbr), v);
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StoreAndPreserveContext(offsetof(SH4Context, gbr), v);
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}
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ir::Value *SH4Builder::LoadFPSCR() {
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@ -175,55 +136,75 @@ ir::Value *SH4Builder::LoadFPSCR() {
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void SH4Builder::StoreFPSCR(ir::Value *v) {
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CHECK_EQ(v->type(), VALUE_I32);
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v = And(v, AllocConstant(0x003fffff));
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StoreContext(offsetof(SH4Context, fpscr), v);
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StoreAndPreserveContext(offsetof(SH4Context, fpscr), v);
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CallExternal((ExternalFn)&FPSCRUpdated);
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}
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ir::Value *SH4Builder::LoadPR() {
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return LoadContext(offsetof(SH4Context, pr), VALUE_I32);
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}
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void SH4Builder::StorePR(ir::Value *v) {
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CHECK_EQ(v->type(), VALUE_I32);
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StoreAndPreserveContext(offsetof(SH4Context, pr), v);
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}
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void SH4Builder::PreserveT() {
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preserve_offset_ = offsetof(SH4Context, sr);
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preserve_mask_ = T;
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}
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void SH4Builder::PreservePR() {
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preserve_offset_ = offsetof(SH4Context, pr);
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preserve_mask_ = 0;
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}
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void SH4Builder::PreserveRegister(int n) {
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preserve_offset_ = offsetof(SH4Context, r[n]);
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preserve_mask_ = 0;
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}
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Value *SH4Builder::LoadPreserved() {
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Value *v = offset_preserved_
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// if the offset had to be preserved, load it up
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? LoadContext(offsetof(SH4Context, preserve), VALUE_I32)
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// else, load from its original location
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: LoadContext(preserve_offset_, VALUE_I32);
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if (preserve_mask_) {
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v = And(v, AllocConstant(preserve_mask_));
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}
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// reset preserve state
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preserve_offset_ = -1;
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preserve_mask_ = 0;
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offset_preserved_ = false;
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return v;
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}
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void SH4Builder::EmitDelayInstr() {
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CHECK_EQ(has_delay_instr_, true) << "No delay instruction available";
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has_delay_instr_ = false;
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printf("SH4::Emit %s\n", delay_instr_.type->name);
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(emit_callbacks[delay_instr_.type->op])(*this, delay_instr_);
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ir::Instr *emitted = GetFirstEmittedInstr();
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if (emitted) {
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emitted->guest_addr = delay_instr_.addr;
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emitted->guest_op = delay_instr_.type->op;
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}
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(emit_callbacks[delay_instr_.type->op])(*this, fpu_state_, delay_instr_);
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}
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// FIXME simplify this
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ir::Instr *SH4Builder::GetFirstEmittedInstr() {
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ir::Instr *first = last_instr_;
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// find the first instruction since the tail of the last batch
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if (!first && current_block_ && current_block_->instrs().head()) {
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first = current_block_->instrs().head();
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} else if (first && first->next()) {
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first = first->next();
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} else if (first && first->block()->next() &&
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first->block()->next()->instrs().head()) {
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first = first->block()->next()->instrs().head();
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// When emitting an instruction in the delay slot, it's possible that it will
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// overwrite a register needed by the original branch instruction. The branch
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// emitter can request that a register be preserved with PreserveT, etc. before
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// the delay slot, and if it is overwritten, the register is cached off. After
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// emitting the delay slot, the branch emitter can call LoadPreserved to load
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// either the original value, or if that was overwritten, the cached value.
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void SH4Builder::StoreAndPreserveContext(size_t offset, Value *v,
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InstrFlag flags) {
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// if a register that needs to be preserved is overwritten, cache it
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if (offset == preserve_offset_) {
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CHECK(!offset_preserved_) << "Can only preserve a single value";
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StoreContext(offsetof(SH4Context, preserve),
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LoadContext(offset, VALUE_I32));
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offset_preserved_ = true;
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}
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// nothing new emitted
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if (first == last_instr_) {
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return nullptr;
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}
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// move to end of this batch of emitted instructions
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last_instr_ = first;
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if (last_instr_) {
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while (last_instr_->block()->next() &&
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last_instr_->block()->next()->instrs().head()) {
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last_instr_ = last_instr_->block()->next()->instrs().head();
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}
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while (last_instr_->next()) {
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last_instr_ = last_instr_->next();
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}
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}
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CHECK_NOTNULL(last_instr_);
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return first;
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StoreContext(offset, v, flags);
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}
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@ -38,8 +38,7 @@ class SH4Builder : public ir::IRBuilder {
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SH4Builder(emu::Memory &memory);
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~SH4Builder();
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void Emit(uint32_t start_addr);
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void DumpToFile(uint32_t start_addr);
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void Emit(uint32_t start_addr, const SH4Context &ctx);
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ir::Value *LoadRegister(int n, ir::ValueTy type);
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void StoreRegister(int n, ir::Value *v);
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@ -55,16 +54,26 @@ class SH4Builder : public ir::IRBuilder {
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void StoreGBR(ir::Value *v);
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ir::Value *LoadFPSCR();
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void StoreFPSCR(ir::Value *v);
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ir::Value *LoadPR();
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void StorePR(ir::Value *v);
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void PreserveT();
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void PreservePR();
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void PreserveRegister(int n);
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ir::Value *LoadPreserved();
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void EmitDelayInstr();
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private:
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ir::Instr *GetFirstEmittedInstr();
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void StoreAndPreserveContext(size_t offset, ir::Value *v,
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ir::InstrFlag flags = ir::IF_NONE);
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emu::Memory &memory_;
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Instr delay_instr_;
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bool has_delay_instr_;
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ir::Instr *last_instr_;
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size_t preserve_offset_;
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uint32_t preserve_mask_;
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bool offset_preserved_;
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};
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}
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}
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@ -1069,9 +1069,11 @@ EMITTER(BF) {
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// 1000 1111 dddd dddd 3/1 -
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// BFS disp
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EMITTER(BFS) {
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uint32_t dest_addr = i.addr + 4 + (int8_t)i.disp * 2;
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Value *cond = b.LoadT();
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b.PreserveT();
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b.EmitDelayInstr();
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Value *cond = b.LoadPreserved();
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uint32_t dest_addr = i.addr + 4 + (int8_t)i.disp * 2;
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b.BranchFalse(cond, b.AllocConstant(dest_addr));
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}
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@ -1088,9 +1090,11 @@ EMITTER(BT) {
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// 1000 1101 dddd dddd 2/1 -
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// BTS disp
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EMITTER(BTS) {
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uint32_t dest_addr = i.addr + 4 + (int8_t)i.disp * 2;
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Value *cond = b.LoadT();
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b.PreserveT();
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b.EmitDelayInstr();
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Value *cond = b.LoadPreserved();
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uint32_t dest_addr = i.addr + 4 + (int8_t)i.disp * 2;
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b.BranchTrue(cond, b.AllocConstant(dest_addr));
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}
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@ -1098,10 +1102,11 @@ EMITTER(BTS) {
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// 1010 dddd dddd dddd 2 -
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// BRA disp
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EMITTER(BRA) {
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b.EmitDelayInstr();
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int32_t disp = ((i.disp & 0xfff) << 20) >>
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20; // 12-bit displacement must be sign extended
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uint32_t dest_addr = i.addr + 4 + disp * 2;
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b.EmitDelayInstr();
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b.Branch(b.AllocConstant(dest_addr));
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}
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@ -1109,9 +1114,11 @@ EMITTER(BRA) {
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// 0000 mmmm 0010 0011 2 -
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// BRAF Rn
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EMITTER(BRAF) {
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Value *rn = b.LoadRegister(i.Rn, VALUE_I32);
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Value *dest_addr = b.Add(b.AllocConstant(i.addr + 4), rn);
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b.PreserveRegister(i.Rn);
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b.EmitDelayInstr();
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Value *rn = b.LoadPreserved();
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Value *dest_addr = b.Add(b.AllocConstant(i.addr + 4), rn);
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b.Branch(dest_addr);
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}
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@ -1119,12 +1126,13 @@ EMITTER(BRAF) {
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// 1011 dddd dddd dddd 2 -
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// BSR disp
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EMITTER(BSR) {
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b.EmitDelayInstr();
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int32_t disp = ((i.disp & 0xfff) << 20) >>
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20; // 12-bit displacement must be sign extended
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uint32_t ret_addr = i.addr + 4;
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uint32_t dest_addr = ret_addr + disp * 2;
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b.EmitDelayInstr();
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b.StoreContext(offsetof(SH4Context, pr), b.AllocConstant(ret_addr));
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b.StorePR(b.AllocConstant(ret_addr));
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b.Branch(b.AllocConstant(dest_addr));
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}
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@ -1132,34 +1140,42 @@ EMITTER(BSR) {
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// 0000 mmmm 0000 0011 2 -
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// BSRF Rn
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EMITTER(BSRF) {
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Value *rn = b.LoadRegister(i.Rn, VALUE_I32);
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b.PreserveRegister(i.Rn);
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b.EmitDelayInstr();
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Value *rn = b.LoadPreserved();
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Value *ret_addr = b.AllocConstant(i.addr + 4);
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Value *dest_addr = b.Add(rn, ret_addr);
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b.EmitDelayInstr();
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b.StoreContext(offsetof(SH4Context, pr), ret_addr);
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b.StorePR(ret_addr);
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b.Branch(dest_addr);
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}
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// JMP @Rm
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EMITTER(JMP) {
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Value *dest_addr = b.LoadRegister(i.Rn, VALUE_I32);
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b.PreserveRegister(i.Rn);
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b.EmitDelayInstr();
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Value *dest_addr = b.LoadPreserved();
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b.Branch(dest_addr);
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}
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// JSR @Rn
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EMITTER(JSR) {
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Value *ret_addr = b.AllocConstant(i.addr + 4);
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Value *dest_addr = b.LoadRegister(i.Rn, VALUE_I32);
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b.PreserveRegister(i.Rn);
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b.EmitDelayInstr();
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b.StoreContext(offsetof(SH4Context, pr), ret_addr);
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Value *dest_addr = b.LoadPreserved();
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Value *ret_addr = b.AllocConstant(i.addr + 4);
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b.StorePR(ret_addr);
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b.Branch(dest_addr);
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}
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// RTS
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EMITTER(RTS) {
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b.PreservePR();
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b.EmitDelayInstr();
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Value *dest_addr = b.LoadContext(offsetof(SH4Context, pr), VALUE_I32);
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Value *dest_addr = b.LoadPreserved();
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b.Branch(dest_addr);
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}
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@ -1337,7 +1353,7 @@ EMITTER(LDSMACL) {
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// LDS Rm,PR
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EMITTER(LDSPR) {
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Value *v = b.LoadRegister(i.Rm, VALUE_I32);
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b.StoreContext(offsetof(SH4Context, pr), v);
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b.StorePR(v);
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}
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// LDS.L @Rm+,MACH
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@ -1360,7 +1376,7 @@ EMITTER(LDSMMACL) {
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EMITTER(LDSMPR) {
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Value *addr = b.LoadRegister(i.Rm, VALUE_I32);
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Value *v = b.Load(addr, VALUE_I32);
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b.StoreContext(offsetof(SH4Context, pr), v);
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b.StorePR(v);
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b.StoreRegister(i.Rm, b.Add(addr, b.AllocConstant(4)));
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}
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@ -1620,7 +1636,7 @@ EMITTER(STSMACL) {
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// STS PR,Rn
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EMITTER(STSPR) {
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Value *v = b.LoadContext(offsetof(SH4Context, pr), VALUE_I32);
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Value *v = b.LoadPR();
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b.StoreRegister(i.Rn, v);
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}
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@ -1647,7 +1663,7 @@ EMITTER(STSMPR) {
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Value *addr = b.Sub(b.LoadRegister(i.Rn, VALUE_I32), b.AllocConstant(4));
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b.StoreRegister(i.Rn, addr);
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|
||||
Value *pr = b.LoadContext(offsetof(SH4Context, pr), VALUE_I32);
|
||||
Value *pr = b.LoadPR();
|
||||
b.Store(addr, pr);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -278,10 +278,6 @@ class Instr : public core::IntrusiveListNode<Instr> {
|
|||
intptr_t tag() const { return tag_; }
|
||||
void set_tag(intptr_t tag) { tag_ = tag; }
|
||||
|
||||
// temp debug variables
|
||||
intptr_t guest_addr;
|
||||
intptr_t guest_op;
|
||||
|
||||
private:
|
||||
Block *set_block(Block *block) { return block_ = block; }
|
||||
|
||||
|
|
|
|||
|
|
@ -8,37 +8,31 @@ using namespace dreavm::cpu::ir::passes;
|
|||
void ValidatePass::Run(IRBuilder &builder) {
|
||||
PROFILER_RUNTIME("ValidatePass::Run");
|
||||
|
||||
int cnt = 0;
|
||||
|
||||
for (auto block : builder.blocks()) {
|
||||
ValidateBlock(cnt, builder, block);
|
||||
ValidateBlock(builder, block);
|
||||
}
|
||||
}
|
||||
|
||||
void ValidatePass::ValidateBlock(int &cnt, IRBuilder &builder, Block *block) {
|
||||
void ValidatePass::ValidateBlock(IRBuilder &builder, Block *block) {
|
||||
Instr *tail = block->instrs().tail();
|
||||
|
||||
CHECK(tail && IRBuilder::IsTerminator(tail))
|
||||
<< "Block ends in a non-terminating instruction";
|
||||
|
||||
for (auto instr : block->instrs()) {
|
||||
ValidateInstr(cnt, builder, block, instr);
|
||||
ValidateInstr(builder, block, instr);
|
||||
}
|
||||
}
|
||||
|
||||
void ValidatePass::ValidateInstr(int &cnt, IRBuilder &builder, Block *block,
|
||||
void ValidatePass::ValidateInstr(IRBuilder &builder, Block *block,
|
||||
Instr *instr) {
|
||||
// Value *result = instr->result();
|
||||
Value *result = instr->result();
|
||||
|
||||
// if (result) {
|
||||
// for (auto ref : result->refs()) {
|
||||
// CHECK_EQ(ref->instr()->block(), block)
|
||||
// << "Instruction result is referenced by multiple blocks, values can
|
||||
// "
|
||||
// "only be used in the block they're declared in "
|
||||
// << Opnames[ref->instr()->op()] << " " << cnt;
|
||||
// }
|
||||
// }
|
||||
|
||||
// cnt++;
|
||||
if (result) {
|
||||
for (auto ref : result->refs()) {
|
||||
CHECK_EQ(ref->instr()->block(), block)
|
||||
<< "Instruction result is referenced by multiple blocks, values can "
|
||||
"only be used in the block they're declared in";
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -11,8 +11,8 @@ namespace passes {
|
|||
class ValidatePass : public Pass {
|
||||
public:
|
||||
void Run(IRBuilder &builder);
|
||||
void ValidateBlock(int &cnt, IRBuilder &builder, Block *block);
|
||||
void ValidateInstr(int &cnt, IRBuilder &builder, Block *block, Instr *instr);
|
||||
void ValidateBlock(IRBuilder &builder, Block *block);
|
||||
void ValidateInstr(IRBuilder &builder, Block *block, Instr *instr);
|
||||
};
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -51,6 +51,7 @@ struct SH4Context {
|
|||
uint32_t dbr;
|
||||
uint32_t sq[2][8];
|
||||
uint32_t sq_ext_addr[2];
|
||||
uint32_t preserve;
|
||||
SR_T sr, ssr, old_sr;
|
||||
FPSCR_T fpscr, old_fpscr;
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue