ShuriZma
/
redream
mirror of https://github.com/inolen/redream.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

hide access to the various memory delegates used by hardware

This commit is contained in:
Anthony Pesch 2016-02-14 20:36:23 -08:00
parent b6731d3df6
commit 6df9528856
10 changed files with 113 additions and 89 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/hw/aica/aica.h
View File

@ -7,14 +7,19 @@ namespace re {
namespace hw {
struct Dreamcast;
extern bool MapMemory(Dreamcast &dc);
namespace aica {
class AICA {
friend bool re::hw::MapMemory(Dreamcast &dc);
public:
AICA(Dreamcast *dc);
bool Init();
private:
// static uint32_t ReadRegister(void *ctx, uint32_t addr);
// static void WriteRegister(void *ctx, uint32_t addr, uint32_t value);
@ -24,7 +29,6 @@ class AICA {
template <typename T>
void WriteWave(uint32_t addr, T value);
private:
Dreamcast *dc_;
// uint8_t *aica_regs_;
uint8_t *wave_ram_;

2
src/hw/dreamcast.cc
View File

@ -28,7 +28,7 @@ namespace re {
namespace hw {
// clang-format off
static bool MapMemory(Dreamcast &dc) {
bool MapMemory(Dreamcast &dc) {
Memory *memory = dc.memory;
if (!memory->Init()) {

3
src/hw/gdrom/gdrom.cc
View File

@ -137,8 +137,7 @@ void GDROM::WriteRegister(uint32_t addr, T value) {
*(uint16_t *)(&pio_buffer_[pio_idx_]) = reg.value & 0xffff;
pio_idx_ += 2;
if ((state_ == STATE_SPI_READ_CMD && pio_idx_ == 12) ||
(state_ == STATE_SPI_READ_DATA &&
pio_idx_ == pio_size_)) {
(state_ == STATE_SPI_READ_DATA && pio_idx_ == pio_size_)) {
TriggerEvent(EV_SPI_READ_END);
}
} break;

6
src/hw/gdrom/gdrom.h
View File

@ -11,8 +11,8 @@ class Holly;
}
struct Dreamcast;
class Memory;
struct Register;
class Memory;
namespace gdrom {
@ -203,6 +203,8 @@ enum DataMask {
};
class GDROM {
friend class holly::Holly;
public:
GDROM(Dreamcast *dc);
~GDROM();
@ -211,12 +213,12 @@ class GDROM {
void SetDisc(std::unique_ptr<Disc> disc);
private:
template <typename T>
T ReadRegister(uint32_t addr);
template <typename T>
void WriteRegister(uint32_t addr, T value);
private:
void TriggerEvent(GDEvent ev);
void TriggerEvent(GDEvent ev, intptr_t arg0, intptr_t arg1);
void ProcessATACommand(ATACommand cmd);

6
src/hw/holly/holly.h
View File

@ -18,6 +18,8 @@ class SH4;
struct Dreamcast;
struct Register;
extern bool MapMemory(Dreamcast &dc);
namespace holly {
// interrupts
@ -156,6 +158,8 @@ enum HollyInterrupt : uint64_t {
};
class Holly {
friend bool re::hw::MapMemory(Dreamcast &dc);
public:
Holly(Dreamcast *dc);
@ -164,12 +168,12 @@ class Holly {
void RequestInterrupt(HollyInterrupt intr);
void UnrequestInterrupt(HollyInterrupt intr);
private:
template <typename T>
T ReadRegister(uint32_t addr);
template <typename T>
void WriteRegister(uint32_t addr, T value);
private:
void CH2DMATransfer();
void SortDMATransfer();
void ForwardRequestInterrupts();

7
src/hw/holly/pvr2.h
View File

@ -6,9 +6,12 @@
namespace re {
namespace hw {
struct Dreamcast;
struct Register;
extern bool MapMemory(Dreamcast &dc);
namespace holly {
class Holly;
@ -197,6 +200,8 @@ union TA_ISP_BASE_T {
};
class PVR2 {
friend bool re::hw::MapMemory(Dreamcast &dc);
public:
PVR2(Dreamcast *dc);
@ -204,6 +209,7 @@ class PVR2 {
bool Init();
private:
uint32_t ReadRegister(uint32_t addr);
void WriteRegister(uint32_t addr, uint32_t value);
@ -212,7 +218,6 @@ class PVR2 {
template <typename T>
void WriteVRamInterleaved(uint32_t addr, T value);
private:
void ReconfigureSPG();
void NextScanline();

7
src/hw/holly/tile_accelerator.h
View File

@ -13,9 +13,12 @@ class TraceWriter;
}
namespace hw {
struct Dreamcast;
class Memory;
extern bool MapMemory(Dreamcast &dc);
namespace holly {
class Holly;
@ -481,6 +484,8 @@ typedef std::unordered_map<TextureKey, TileContext *> TileContextMap;
typedef std::queue<TileContext *> TileContextQueue;
class TileAccelerator {
friend bool re::hw::MapMemory(Dreamcast &dc);
public:
static int GetParamSize(const PCW &pcw, int vertex_type);
static int GetPolyType(const PCW &pcw);
@ -497,10 +502,10 @@ class TileAccelerator {
TileContext *GetLastContext();
private:
void WriteCommand(uint32_t addr, uint32_t value);
void WriteTexture(uint32_t addr, uint32_t value);
private:
void WritePVRState(TileContext *tactx);
void WriteBackgroundState(TileContext *tactx);

6
src/hw/maple/maple.h
View File

@ -11,8 +11,8 @@ class Holly;
}
struct Dreamcast;
class Memory;
struct Register;
class Memory;
namespace maple {
@ -100,6 +100,8 @@ class MapleDevice {
};
class Maple {
friend class holly::Holly;
public:
Maple(Dreamcast *dc);
@ -108,12 +110,12 @@ class Maple {
bool HandleInput(int port, sys::Keycode key, int16_t value);
void VBlank();
private:
template <typename T>
T ReadRegister(uint32_t addr);
template <typename T>
void WriteRegister(uint32_t addr, T value);
private:
bool HandleFrame(const MapleFrame &frame, MapleFrame &res);
void StartDMA();

136
src/hw/sh4/sh4.cc
View File

@ -138,6 +138,74 @@ void SH4::UnrequestInterrupt(Interrupt intr) {
UpdatePendingInterrupts();
}
uint32_t SH4::CompilePC() {
SH4CodeCache *code_cache = s_current_cpu->code_cache_;
SH4Context *ctx = &s_current_cpu->ctx_;
BlockEntry *block = code_cache->CompileBlock(ctx->pc, ctx);
return block->run();
}
void SH4::Pref(SH4Context *ctx, uint64_t arg0) {
SH4 *self = reinterpret_cast<SH4 *>(ctx->sh4);
uint32_t addr = static_cast<uint32_t>(arg0);
// only concerned about SQ related prefetches
if (addr < 0xe0000000 || addr > 0xe3ffffff) {
return;
}
// figure out the source and destination
uint32_t dest = addr & 0x03ffffe0;
uint32_t sqi = (addr & 0x20) >> 5;
if (sqi) {
dest |= (self->QACR1 & 0x1c) << 24;
} else {
dest |= (self->QACR0 & 0x1c) << 24;
}
// perform the "burst" 32-byte copy
for (int i = 0; i < 8; i++) {
self->memory_->W32(dest, ctx->sq[sqi][i]);
dest += 4;
}
}
void SH4::SRUpdated(SH4Context *ctx, uint64_t old_sr) {
SH4 *self = reinterpret_cast<SH4 *>(ctx->sh4);
if ((ctx->sr & RB) != (old_sr & RB)) {
self->SwapRegisterBank();
}
if ((ctx->sr & I) != (old_sr & I) || (ctx->sr & BL) != (old_sr & BL)) {
self->UpdatePendingInterrupts();
}
}
void SH4::FPSCRUpdated(SH4Context *ctx, uint64_t old_fpscr) {
SH4 *self = reinterpret_cast<SH4 *>(ctx->sh4);
if ((ctx->fpscr & FR) != (old_fpscr & FR)) {
self->SwapFPRegisterBank();
}
}
void SH4::SwapRegisterBank() {
for (int s = 0; s < 8; s++) {
uint32_t tmp = ctx_.r[s];
ctx_.r[s] = ctx_.ralt[s];
ctx_.ralt[s] = tmp;
}
}
void SH4::SwapFPRegisterBank() {
for (int s = 0; s <= 15; s++) {
uint32_t tmp = ctx_.fr[s];
ctx_.fr[s] = ctx_.xf[s];
ctx_.xf[s] = tmp;
}
}
template uint8_t SH4::ReadRegister(uint32_t addr);
template uint16_t SH4::ReadRegister(uint32_t addr);
template uint32_t SH4::ReadRegister(uint32_t addr);
@ -327,74 +395,6 @@ void SH4::WriteSQ(uint32_t addr, T value) {
ctx_.sq[sqi][idx] = static_cast<uint32_t>(value);
}
uint32_t SH4::CompilePC() {
SH4CodeCache *code_cache = s_current_cpu->code_cache_;
SH4Context *ctx = &s_current_cpu->ctx_;
BlockEntry *block = code_cache->CompileBlock(ctx->pc, ctx);
return block->run();
}
void SH4::Pref(SH4Context *ctx, uint64_t arg0) {
SH4 *self = reinterpret_cast<SH4 *>(ctx->sh4);
uint32_t addr = static_cast<uint32_t>(arg0);
// only concerned about SQ related prefetches
if (addr < 0xe0000000 || addr > 0xe3ffffff) {
return;
}
// figure out the source and destination
uint32_t dest = addr & 0x03ffffe0;
uint32_t sqi = (addr & 0x20) >> 5;
if (sqi) {
dest |= (self->QACR1 & 0x1c) << 24;
} else {
dest |= (self->QACR0 & 0x1c) << 24;
}
// perform the "burst" 32-byte copy
for (int i = 0; i < 8; i++) {
self->memory_->W32(dest, ctx->sq[sqi][i]);
dest += 4;
}
}
void SH4::SRUpdated(SH4Context *ctx, uint64_t old_sr) {
SH4 *self = reinterpret_cast<SH4 *>(ctx->sh4);
if ((ctx->sr & RB) != (old_sr & RB)) {
self->SwapRegisterBank();
}
if ((ctx->sr & I) != (old_sr & I) || (ctx->sr & BL) != (old_sr & BL)) {
self->UpdatePendingInterrupts();
}
}
void SH4::FPSCRUpdated(SH4Context *ctx, uint64_t old_fpscr) {
SH4 *self = reinterpret_cast<SH4 *>(ctx->sh4);
if ((ctx->fpscr & FR) != (old_fpscr & FR)) {
self->SwapFPRegisterBank();
}
}
void SH4::SwapRegisterBank() {
for (int s = 0; s < 8; s++) {
uint32_t tmp = ctx_.r[s];
ctx_.r[s] = ctx_.ralt[s];
ctx_.ralt[s] = tmp;
}
}
void SH4::SwapFPRegisterBank() {
for (int s = 0; s <= 15; s++) {
uint32_t tmp = ctx_.fr[s];
ctx_.fr[s] = ctx_.xf[s];
ctx_.xf[s] = tmp;
}
}
//
// CCN
//

23
src/hw/sh4/sh4.h
View File

@ -12,6 +12,8 @@ namespace hw {
struct Dreamcast;
extern bool MapMemory(Dreamcast &dc);
namespace sh4 {
// registers
@ -107,6 +109,7 @@ enum DDTRW { //
};
class SH4 {
friend bool re::hw::MapMemory(Dreamcast &dc);
friend void RunSH4Test(const SH4Test &);
public:
@ -124,6 +127,16 @@ class SH4 {
void RequestInterrupt(Interrupt intr);
void UnrequestInterrupt(Interrupt intr);
private:
static uint32_t CompilePC();
static void Pref(jit::frontend::sh4::SH4Context *ctx, uint64_t addr);
static void SRUpdated(jit::frontend::sh4::SH4Context *ctx, uint64_t old_sr);
static void FPSCRUpdated(jit::frontend::sh4::SH4Context *ctx,
uint64_t old_fpscr);
void SwapRegisterBank();
void SwapFPRegisterBank();
template <typename T>
T ReadRegister(uint32_t addr);
template <typename T>
@ -139,16 +152,6 @@ class SH4 {
template <typename T>
void WriteSQ(uint32_t addr, T value);
private:
static uint32_t CompilePC();
static void Pref(jit::frontend::sh4::SH4Context *ctx, uint64_t addr);
static void SRUpdated(jit::frontend::sh4::SH4Context *ctx, uint64_t old_sr);
static void FPSCRUpdated(jit::frontend::sh4::SH4Context *ctx,
uint64_t old_fpscr);
void SwapRegisterBank();
void SwapFPRegisterBank();
// CCN
void ResetCache();
void CheckPendingCacheReset();