From 52e509593366697f5fdf0c69fb00b57716cf830e Mon Sep 17 00:00:00 2001
From: Anthony Pesch <inolen@gmail.com>
Date: Thu, 11 May 2017 17:08:49 -0400
Subject: [PATCH] don't assert on disassembling an invalid instruction

---
 src/hw/sh4/sh4.c                    |  8 +-------
 src/jit/frontend/sh4/sh4_analyze.c  | 23 ++++++++++-------------
 src/jit/frontend/sh4/sh4_frontend.h |  1 -
 3 files changed, 11 insertions(+), 21 deletions(-)

diff --git a/src/hw/sh4/sh4.c b/src/hw/sh4/sh4.c
index daf853d9..2fbb6c27 100644
--- a/src/hw/sh4/sh4.c
+++ b/src/hw/sh4/sh4.c
@@ -160,13 +160,7 @@ static void sh4_translate(void *data, uint32_t addr, struct ir *ir, int fastmem,
     if (instr.flags & SH4_FLAG_DELAYED) {
       delay_instr.addr = addr + i;
       delay_instr.opcode = as_read16(sh4->memory_if->space, delay_instr.addr);
-
-      /* instruction must be valid, breakpoints on delay instructions aren't
-         currently supported */
-      CHECK(sh4_disasm(&delay_instr));
-
-      /* delay instruction itself should never have a delay instr */
-      CHECK(!(delay_instr.flags & SH4_FLAG_DELAYED));
+      sh4_disasm(&delay_instr);
 
       i += 2;
     }
diff --git a/src/jit/frontend/sh4/sh4_analyze.c b/src/jit/frontend/sh4/sh4_analyze.c
index f55ae544..17529348 100644
--- a/src/jit/frontend/sh4/sh4_analyze.c
+++ b/src/jit/frontend/sh4/sh4_analyze.c
@@ -15,11 +15,7 @@ void sh4_analyze_block(const struct jit *jit, struct sh4_analysis *as) {
     instr.addr = as->addr + as->size;
     instr.opcode = guest->r16(guest->space, instr.addr);
 
-    /* end block on invalid instruction */
-    if (!sh4_disasm(&instr)) {
-      break;
-    }
-
+    int valid = sh4_disasm(&instr);
     as->size += 2;
     as->cycles += instr.cycles;
 
@@ -28,11 +24,17 @@ void sh4_analyze_block(const struct jit *jit, struct sh4_analysis *as) {
       delay_instr.addr = as->addr + as->size;
       delay_instr.opcode = guest->r16(guest->space, delay_instr.addr);
 
-      CHECK(sh4_disasm(&delay_instr));
-      CHECK(!(delay_instr.flags & SH4_FLAG_DELAYED));
-
+      valid = sh4_disasm(&delay_instr);
       as->size += 2;
       as->cycles += delay_instr.cycles;
+
+      /* delay slots can't have another delay slot */
+      CHECK(!(delay_instr.flags & SH4_FLAG_DELAYED));
+    }
+
+    /* end block on invalid instruction */
+    if (!valid) {
+      break;
     }
 
     /* stop emitting once a branch has been hit. in addition, if fpscr has
@@ -43,10 +45,5 @@ void sh4_analyze_block(const struct jit *jit, struct sh4_analysis *as) {
         (SH4_FLAG_BRANCH | SH4_FLAG_SET_FPSCR | SH4_FLAG_SET_SR)) {
       break;
     }
-
-    /* used by debugger when stepping through instructions */
-    if (as->flags & SH4_SINGLE_INSTR) {
-      break;
-    }
   }
 }
diff --git a/src/jit/frontend/sh4/sh4_frontend.h b/src/jit/frontend/sh4/sh4_frontend.h
index 826033e3..da4e32e6 100644
--- a/src/jit/frontend/sh4/sh4_frontend.h
+++ b/src/jit/frontend/sh4/sh4_frontend.h
@@ -10,7 +10,6 @@ enum {
   SH4_FASTMEM = 0x1,
   SH4_DOUBLE_PR = 0x2,
   SH4_DOUBLE_SZ = 0x4,
-  SH4_SINGLE_INSTR = 0x8,
 };
 
 struct sh4_frontend {