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redream
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added AICA ChannelData and CommonData bitfields 

added ARM7 scaffolding
This commit is contained in:
Anthony Pesch 2016-04-10 22:35:00 -07:00
parent 9a6a98b3d0
commit 4350858651
16 changed files with 370 additions and 83 deletions
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1
CMakeLists.txt
View File

@ -144,6 +144,7 @@ set(REDREAM_SOURCES
src/emu/emulator.cc
src/emu/tracer.cc
src/hw/aica/aica.cc
src/hw/arm7/arm7.cc
src/hw/gdrom/disc.cc
src/hw/gdrom/gdrom.cc
src/hw/holly/holly.cc

9
src/emu/emulator.cc
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@ -2,6 +2,7 @@
#include <gflags/gflags.h>
#include "emu/emulator.h"
#include "hw/aica/aica.h"
#include "hw/arm7/arm7.h"
#include "hw/gdrom/gdrom.h"
#include "hw/holly/holly.h"
#include "hw/holly/pvr2.h"
@ -16,6 +17,7 @@ using namespace re;
using namespace re::emu;
using namespace re::hw;
using namespace re::hw::aica;
using namespace re::hw::arm7;
using namespace re::hw::gdrom;
using namespace re::hw::holly;
using namespace re::hw::maple;
@ -93,6 +95,7 @@ void Emulator::Run(const char *path) {
bool Emulator::CreateDreamcast() {
dc_.sh4 = new SH4(dc_);
dc_.arm7 = new ARM7(dc_);
dc_.aica = new AICA(dc_);
dc_.holly = new Holly(dc_);
dc_.gdrom = new GDROM(dc_);
@ -111,6 +114,8 @@ bool Emulator::CreateDreamcast() {
void Emulator::DestroyDreamcast() {
delete dc_.sh4;
dc_.sh4 = nullptr;
delete dc_.arm7;
dc_.arm7 = nullptr;
delete dc_.aica;
dc_.aica = nullptr;
delete dc_.holly;
@ -142,7 +147,7 @@ bool Emulator::LoadBios(const char *path) {
return false;
}
uint8_t *bios = dc_.memory->TranslateVirtual(BIOS_START);
uint8_t *bios = dc_.memory->TranslateVirtual(BIOS_BEGIN);
int n = static_cast<int>(fread(bios, sizeof(uint8_t), size, fp));
fclose(fp);
@ -171,7 +176,7 @@ bool Emulator::LoadFlash(const char *path) {
return false;
}
uint8_t *flash = dc_.memory->TranslateVirtual(FLASH_START);
uint8_t *flash = dc_.memory->TranslateVirtual(FLASH_BEGIN);
int n = static_cast<int>(fread(flash, sizeof(uint8_t), size, fp));
fclose(fp);

37
src/hw/aica/aica.cc
View File

@ -8,31 +8,43 @@ using namespace re::hw;
using namespace re::hw::aica;
using namespace re::hw::holly;
enum {
AICA_CLOCK_FREQ = 22579200,
};
template <>
uint32_t AICA::ReadWave(uint32_t addr);
AICA::AICA(Dreamcast &dc)
: Device(dc),
ExecuteInterface(this),
MemoryInterface(this),
dc_(dc),
aica_regs_(nullptr),
wave_ram_(nullptr) {}
bool AICA::Init() {
aica_regs_ = dc_.memory->TranslateVirtual(AICA_REG_START);
wave_ram_ = dc_.memory->TranslateVirtual(WAVE_RAM_START);
aica_regs_ = dc_.memory->TranslateVirtual(AICA_REG_BEGIN);
wave_ram_ = dc_.memory->TranslateVirtual(WAVE_RAM_BEGIN);
return true;
}
void AICA::Run(const std::chrono::nanoseconds &delta) {
// int64_t cycles = NANO_TO_CYCLES(delta, AICA_CLOCK_FREQ);
// for (int i = 0; i < 64; i++) {
// }
}
void AICA::MapPhysicalMemory(Memory &memory, MemoryMap &memmap) {
RegionHandle aica_reg_handle = memory.AllocRegion(
AICA_REG_START, AICA_REG_SIZE, nullptr, nullptr,
AICA_REG_BEGIN, AICA_REG_SIZE, nullptr, nullptr,
make_delegate(&AICA::ReadRegister, this), nullptr, nullptr, nullptr,
make_delegate(&AICA::WriteRegister, this), nullptr);
RegionHandle wave_ram_handle = memory.AllocRegion(
WAVE_RAM_START, WAVE_RAM_SIZE,
WAVE_RAM_BEGIN, WAVE_RAM_SIZE,
make_delegate(&AICA::ReadWave<uint8_t>, this),
make_delegate(&AICA::ReadWave<uint16_t>, this),
make_delegate(&AICA::ReadWave<uint32_t>, this), nullptr,
@ -40,23 +52,10 @@ void AICA::MapPhysicalMemory(Memory &memory, MemoryMap &memmap) {
make_delegate(&AICA::WriteWave<uint16_t>, this),
make_delegate(&AICA::WriteWave<uint32_t>, this), nullptr);
memmap.Mount(aica_reg_handle, AICA_REG_SIZE, AICA_REG_START);
memmap.Mount(wave_ram_handle, WAVE_RAM_SIZE, WAVE_RAM_START);
memmap.Mount(aica_reg_handle, AICA_REG_SIZE, AICA_REG_BEGIN);
memmap.Mount(wave_ram_handle, WAVE_RAM_SIZE, WAVE_RAM_BEGIN);
}
// frequency 22579200
// int AICA::Run(int cycles) {
// // uint16_t MCIEB = re::load<uint16_t>(&aica_regs_[MCIEB_OFFSET]);
// // uint16_t MCIPD = re::load<uint16_t>(&aica_regs_[MCIPD_OFFSET]);
// // if (MCIEB || MCIPD) {
// // LOG_INFO("0x%x & 0x%x", MCIEB, MCIPD);
// // }
// // dc_.holly()->RequestInterrupt(HOLLY_INTC_G2AICINT);
// return cycles;
// }
uint32_t AICA::ReadRegister(uint32_t addr) {
return re::load<uint32_t>(&aica_regs_[addr]);
}

5
src/hw/aica/aica.h
View File

@ -10,13 +10,16 @@ class Dreamcast;
namespace aica {
class AICA : public Device, public MemoryInterface {
class AICA : public Device, public ExecuteInterface, public MemoryInterface {
public:
AICA(Dreamcast &dc);
bool Init() final;
private:
// ExecuteInterface
void Run(const std::chrono::nanoseconds &delta) final;
// MemoryInterface
void MapPhysicalMemory(Memory &memory, MemoryMap &memmap) final;
uint32_t ReadRegister(uint32_t addr);

6
src/hw/aica/aica_regs.inc
View File

@ -1,6 +0,0 @@
AICA_REG(0x0070289c, SCIEB, RW, 0, uint16_t)
AICA_REG(0x007028a0, SCIPD, RW, 0, uint16_t)
AICA_REG(0x007028a4, SCIRE, RW, 0, uint16_t)
AICA_REG(0x007028b4, MCIEB, RW, 0, uint16_t)
AICA_REG(0x007028b8, MCIPD, RW, 0, uint16_t)
AICA_REG(0x007028bc, MCIRE, RW, 0, uint16_t)

249
src/hw/aica/aica_types.h
View File

@ -1,21 +1,256 @@
#ifndef AICA_TYPES_H
#define AICA_TYPES_H
#include <stdint.h>
#include "hw/regions.h"
namespace re {
namespace hw {
namespace aica {
enum {
#define AICA_REG(addr, name, flags, default, type) \
name##_OFFSET = addr - AICA_REG_START,
#include "hw/aica/aica_regs.inc"
#undef AICA_REG
NUM_AICA_REGS = AICA_REG_SIZE >> 2,
struct ChannelData {
uint32_t SA_hi : 7;
uint32_t PCMS : 2;
uint32_t LPCTL : 1;
uint32_t SSCTL : 1;
uint32_t : 3;
uint32_t KYONB : 1;
uint32_t KYONEX : 1;
uint32_t : 16;
uint32_t SA_lo : 16;
uint32_t : 16;
uint32_t LSA : 16;
uint32_t : 16;
uint32_t LEA : 16;
uint32_t : 16;
uint32_t AR : 5;
uint32_t : 1;
uint32_t D1R : 5;
uint32_t D2R : 5;
uint32_t : 16;
uint32_t RR : 5;
uint32_t DL : 5;
uint32_t KRS : 4;
uint32_t LPSLNK : 1;
uint32_t : 1;
uint32_t : 16;
uint32_t FNS : 10;
uint32_t : 1;
uint32_t OCT : 4;
uint32_t : 1;
uint32_t : 16;
uint32_t ALFOS : 3;
uint32_t ALFOWS : 2;
uint32_t PLFOS : 3;
uint32_t PLFOWS : 2;
uint32_t LFOF : 5;
uint32_t LFORE : 1;
uint32_t : 16;
uint32_t ISEL : 4;
uint32_t IMXL : 4;
uint32_t : 8;
uint32_t : 16;
uint32_t DIPAN : 5;
uint32_t : 3;
uint32_t DISDL : 4;
uint32_t : 4;
uint32_t : 16;
uint32_t Q : 5;
uint32_t : 3;
uint32_t TL : 8;
uint32_t : 16;
uint32_t FLV0 : 13;
uint32_t : 3;
uint32_t : 16;
uint32_t FLV1 : 13;
uint32_t : 3;
uint32_t : 16;
uint32_t FLV2 : 13;
uint32_t : 3;
uint32_t : 16;
uint32_t FLV3 : 13;
uint32_t : 3;
uint32_t : 16;
uint32_t FLV4 : 13;
uint32_t : 3;
uint32_t : 16;
uint32_t FD1R : 5;
uint32_t : 3;
uint32_t FAR : 5;
uint32_t : 3;
uint32_t : 16;
uint32_t FRR : 5;
uint32_t : 3;
uint32_t FD2R : 5;
uint32_t : 3;
uint32_t : 16;
};
struct CommonData {
uint32_t MVOL : 4;
uint32_t VER : 4;
uint32_t DAC18B : 1;
uint32_t MEM8MB : 1;
uint32_t : 5;
uint32_t MONO : 1;
uint32_t : 16;
uint32_t RBP : 12;
uint32_t : 1;
uint32_t RBL : 2;
uint32_t TESTB0 : 1;
uint32_t : 16;
uint32_t MIBUF : 8;
uint32_t MIEMP : 1;
uint32_t MIFUL : 1;
uint32_t MIOVF : 1;
uint32_t MOEMP : 1;
uint32_t MOFUL : 1;
uint32_t : 3;
uint32_t : 16;
uint32_t MOBUF : 8;
uint32_t MSLC : 6;
uint32_t AFSEL : 1;
uint32_t : 1;
uint32_t : 16;
uint32_t EG : 13;
uint32_t SGC : 2;
uint32_t LP : 1;
uint32_t : 16;
uint32_t CA : 16;
uint32_t : 16;
uint8_t padding0[0x68];
uint32_t MRWINH : 4;
uint32_t T : 1;
uint32_t TSCD : 3;
uint32_t : 1;
uint32_t DMEA_hi : 7;
uint32_t : 16;
uint32_t : 2;
uint32_t DMEA_lo : 14;
uint32_t : 16;
uint32_t : 2;
uint32_t DRGA : 13;
uint32_t DGATE : 1;
uint32_t : 16;
uint32_t DEXE : 1;
uint32_t : 1;
uint32_t DLG : 13;
uint32_t DDIR : 1;
uint32_t : 16;
uint32_t TIMA : 8;
uint32_t TACTL : 3;
uint32_t : 5;
uint32_t : 16;
uint32_t TIMB : 8;
uint32_t TBCTL : 3;
uint32_t : 5;
uint32_t : 16;
uint32_t TIMC : 8;
uint32_t TCCTL : 3;
uint32_t : 5;
uint32_t : 16;
uint32_t SCIEB : 11;
uint32_t : 5;
uint32_t : 16;
uint32_t SCIPD : 11;
uint32_t : 5;
uint32_t : 16;
uint32_t SCIRE : 11;
uint32_t : 5;
uint32_t : 16;
uint32_t SCILV0 : 8;
uint32_t : 8;
uint32_t : 16;
uint32_t SCILV1 : 8;
uint32_t : 8;
uint32_t : 16;
uint32_t SCILV2 : 8;
uint32_t : 8;
uint32_t : 16;
uint32_t MCIEB : 11;
uint32_t : 5;
uint32_t : 16;
uint32_t MCIPD : 11;
uint32_t : 5;
uint32_t : 16;
uint32_t MCIRE : 11;
uint32_t : 5;
uint32_t : 16;
uint8_t padding1[0x340];
uint32_t ARMRST : 1;
uint32_t : 7;
uint32_t VREG : 2;
uint32_t : 6;
uint32_t : 16;
uint8_t padding2[0xfc];
uint32_t L0 : 1;
uint32_t L1 : 1;
uint32_t L2 : 1;
uint32_t L3 : 1;
uint32_t L4 : 1;
uint32_t L5 : 1;
uint32_t L6 : 1;
uint32_t L7 : 1;
uint32_t : 8;
uint32_t : 16;
uint32_t M0 : 1;
uint32_t M1 : 1;
uint32_t M2 : 1;
uint32_t M3 : 1;
uint32_t M4 : 1;
uint32_t M5 : 1;
uint32_t M6 : 1;
uint32_t M7 : 1;
uint32_t RP : 1;
uint32_t : 7;
uint32_t : 16;
};
}
}
]
}
#endif

16
src/hw/arm7/arm7.cc Normal file
View File

@ -0,0 +1,16 @@
#include "hw/arm7/arm7.h"
#include "hw/dreamcast.h"
#include "hw/memory.h"
using namespace re::hw;
using namespace re::hw::arm7;
ARM7::ARM7(Dreamcast &dc) : Device(dc), ExecuteInterface(this), dc_(dc) {}
bool ARM7::Init() {
((void)dc_);
return true;
}
void ARM7::Run(const std::chrono::nanoseconds &delta) {
}

28
src/hw/arm7/arm7.h Normal file
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@ -0,0 +1,28 @@
#ifndef ARM7_H
#define ARM7_H
#include "hw/machine.h"
namespace re {
namespace hw {
class Dreamcast;
namespace arm7 {
class ARM7 : public Device, public ExecuteInterface {
public:
ARM7(Dreamcast &dc);
bool Init() final;
private:
// ExecuteInterface
void Run(const std::chrono::nanoseconds &delta) final;
Dreamcast &dc_;
};
}
}
}
#endif

6
src/hw/dreamcast.h
View File

@ -11,6 +11,10 @@ namespace aica {
class AICA;
}
namespace arm7 {
class ARM7;
}
namespace gdrom {
class GDROM;
}
@ -33,6 +37,7 @@ class Dreamcast : public Machine {
public:
Dreamcast()
: sh4(nullptr),
arm7(nullptr),
aica(nullptr),
holly(nullptr),
gdrom(nullptr),
@ -41,6 +46,7 @@ class Dreamcast : public Machine {
ta(nullptr) {}
hw::sh4::SH4 *sh4;
hw::arm7::ARM7 *arm7;
hw::aica::AICA *aica;
hw::holly::Holly *holly;
hw::gdrom::GDROM *gdrom;

4
src/hw/holly/holly.cc
View File

@ -113,7 +113,7 @@ void Holly::UnrequestInterrupt(HollyInterrupt intr) {
void Holly::MapPhysicalMemory(Memory &memory, MemoryMap &memmap) {
RegionHandle holly_handle = memory.AllocRegion(
HOLLY_REG_START, HOLLY_REG_SIZE,
HOLLY_REG_BEGIN, HOLLY_REG_SIZE,
make_delegate(&Holly::ReadRegister<uint8_t>, this),
make_delegate(&Holly::ReadRegister<uint16_t>, this),
make_delegate(&Holly::ReadRegister<uint32_t>, this), nullptr,
@ -121,7 +121,7 @@ void Holly::MapPhysicalMemory(Memory &memory, MemoryMap &memmap) {
make_delegate(&Holly::WriteRegister<uint16_t>, this),
make_delegate(&Holly::WriteRegister<uint32_t>, this), nullptr);
memmap.Mount(holly_handle, HOLLY_REG_SIZE, HOLLY_REG_START);
memmap.Mount(holly_handle, HOLLY_REG_SIZE, HOLLY_REG_BEGIN);
}
template <typename T>

2
src/hw/holly/holly_types.h
View File

@ -10,7 +10,7 @@ namespace holly {
// registers
enum {
#define HOLLY_REG(addr, name, flags, default, type) \
name##_OFFSET = (addr - HOLLY_REG_START) >> 2,
name##_OFFSET = (addr - HOLLY_REG_BEGIN) >> 2,
#include "hw/holly/holly_regs.inc"
#undef HOLLY_REG
NUM_HOLLY_REGS = HOLLY_REG_SIZE >> 2,

12
src/hw/holly/pvr2.cc
View File

@ -29,8 +29,8 @@ bool PVR2::Init() {
scheduler_ = dc_.scheduler;
holly_ = dc_.holly;
ta_ = dc_.ta;
palette_ram_ = dc_.memory->TranslateVirtual(PVR_PALETTE_START);
video_ram_ = dc_.memory->TranslateVirtual(PVR_VRAM32_START);
palette_ram_ = dc_.memory->TranslateVirtual(PVR_PALETTE_BEGIN);
video_ram_ = dc_.memory->TranslateVirtual(PVR_VRAM32_BEGIN);
// initialize registers
#define PVR_REG(addr, name, flags, default, type) \
@ -49,20 +49,20 @@ bool PVR2::Init() {
void PVR2::MapPhysicalMemory(Memory &memory, MemoryMap &memmap) {
RegionHandle pvr_reg_handle = memory.AllocRegion(
PVR_REG_START, PVR_REG_SIZE, nullptr, nullptr,
PVR_REG_BEGIN, PVR_REG_SIZE, nullptr, nullptr,
make_delegate(&PVR2::ReadRegister, this), nullptr, nullptr, nullptr,
make_delegate(&PVR2::WriteRegister, this), nullptr);
RegionHandle pvr_vram64_handle = memory.AllocRegion(
PVR_VRAM64_START, PVR_VRAM64_SIZE,
PVR_VRAM64_BEGIN, PVR_VRAM64_SIZE,
make_delegate(&PVR2::ReadVRamInterleaved<uint8_t>, this),
make_delegate(&PVR2::ReadVRamInterleaved<uint16_t>, this),
make_delegate(&PVR2::ReadVRamInterleaved<uint32_t>, this), nullptr,
nullptr, make_delegate(&PVR2::WriteVRamInterleaved<uint16_t>, this),
make_delegate(&PVR2::WriteVRamInterleaved<uint32_t>, this), nullptr);
memmap.Mount(pvr_reg_handle, PVR_REG_SIZE, PVR_REG_START);
memmap.Mount(pvr_vram64_handle, PVR_VRAM64_SIZE, PVR_VRAM64_START);
memmap.Mount(pvr_reg_handle, PVR_REG_SIZE, PVR_REG_BEGIN);
memmap.Mount(pvr_vram64_handle, PVR_VRAM64_SIZE, PVR_VRAM64_BEGIN);
}
uint32_t PVR2::ReadRegister(uint32_t addr) {

2
src/hw/holly/pvr2_types.h
View File

@ -191,7 +191,7 @@ union TA_ISP_BASE_T {
enum {
#define PVR_REG(addr, name, flags, default_value, type) \
name##_OFFSET = (addr - PVR_REG_START) >> 2,
name##_OFFSET = (addr - PVR_REG_BEGIN) >> 2,
#include "hw/holly/pvr2_regs.inc"
#undef PVR_REG
NUM_PVR_REGS = PVR_REG_SIZE >> 2,

18
src/hw/holly/tile_accelerator.cc
View File

@ -233,7 +233,7 @@ bool TileAccelerator::Init() {
memory_ = dc_.memory;
holly_ = dc_.holly;
pvr_ = dc_.pvr;
video_ram_ = dc_.memory->TranslateVirtual(PVR_VRAM32_START);
video_ram_ = dc_.memory->TranslateVirtual(PVR_VRAM32_BEGIN);
TA_REGISTER_W32_DELEGATE(SOFTRESET);
TA_REGISTER_W32_DELEGATE(TA_LIST_INIT);
@ -266,7 +266,7 @@ TextureHandle TileAccelerator::GetTexture(
uint32_t texture_addr = tcw.texture_addr << 3;
// get the texture data
uint8_t *video_ram = dc_.memory->TranslateVirtual(PVR_VRAM32_START);
uint8_t *video_ram = dc_.memory->TranslateVirtual(PVR_VRAM32_BEGIN);
uint8_t *texture = &video_ram[texture_addr];
int width = 8 << tsp.texture_u_size;
int height = 8 << tsp.texture_v_size;
@ -276,7 +276,7 @@ TextureHandle TileAccelerator::GetTexture(
int texture_size = (width * height * element_size_bits) >> 3;
// get the palette data
uint8_t *palette_ram = dc_.memory->TranslateVirtual(PVR_PALETTE_START);
uint8_t *palette_ram = dc_.memory->TranslateVirtual(PVR_PALETTE_BEGIN);
uint8_t *palette = nullptr;
uint32_t palette_addr = 0;
int palette_size = 0;
@ -438,16 +438,16 @@ void TileAccelerator::FinalizeContext(uint32_t addr) {
void TileAccelerator::MapPhysicalMemory(Memory &memory, MemoryMap &memmap) {
RegionHandle ta_poly_handle = memory.AllocRegion(
TA_POLY_START, TA_POLY_SIZE, nullptr, nullptr, nullptr, nullptr, nullptr,
TA_POLY_BEGIN, TA_POLY_SIZE, nullptr, nullptr, nullptr, nullptr, nullptr,
nullptr, make_delegate(&TileAccelerator::WritePolyFIFO, this), nullptr);
RegionHandle ta_texture_handle = memory.AllocRegion(
TA_TEXTURE_START, TA_TEXTURE_SIZE, nullptr, nullptr, nullptr, nullptr,
TA_TEXTURE_BEGIN, TA_TEXTURE_SIZE, nullptr, nullptr, nullptr, nullptr,
nullptr, nullptr, make_delegate(&TileAccelerator::WriteTextureFIFO, this),
nullptr);
memmap.Mount(ta_poly_handle, TA_POLY_SIZE, TA_POLY_START);
memmap.Mount(ta_texture_handle, TA_TEXTURE_SIZE, TA_TEXTURE_START);
memmap.Mount(ta_poly_handle, TA_POLY_SIZE, TA_POLY_BEGIN);
memmap.Mount(ta_texture_handle, TA_TEXTURE_SIZE, TA_TEXTURE_BEGIN);
}
void TileAccelerator::WritePolyFIFO(uint32_t addr, uint32_t value) {
@ -573,7 +573,7 @@ void TileAccelerator::SaveRegisterState(TileContext *tctx) {
if (!pvr_->FPU_PARAM_CFG.region_header_type) {
tctx->autosort = !pvr_->ISP_FEED_CFG.presort;
} else {
uint32_t region_data = memory_->R32(PVR_VRAM64_START + pvr_->REGION_BASE);
uint32_t region_data = memory_->R32(PVR_VRAM64_BEGIN + pvr_->REGION_BASE);
tctx->autosort = !(region_data & 0x20000000);
}
@ -602,7 +602,7 @@ void TileAccelerator::SaveRegisterState(TileContext *tctx) {
// available at 0x0 when booting the bios, so masking this seems to be the
// correct solution
uint32_t vram_offset =
PVR_VRAM64_START +
PVR_VRAM64_BEGIN +
((tctx->addr + pvr_->ISP_BACKGND_T.tag_address * 4) & 0x7fffff);
// get surface parameters

2
src/hw/regions.h
View File

@ -5,7 +5,7 @@ namespace re {
namespace hw {
#define MEMORY_REGION(name, start, end) \
name##_START = start, name##_END = end, name##_SIZE = end - start + 1
name##_BEGIN = start, name##_END = end, name##_SIZE = end - start + 1
// clang-format off
enum {

56
src/hw/sh4/sh4.cc
View File

@ -323,15 +323,15 @@ void SH4::ReadRegister(int n, uint64_t *value, int *size) {
void SH4::MapPhysicalMemory(Memory &memory, MemoryMap &memmap) {
// area 2 and 4 are unused
RegionHandle a0_handle = memory.AllocRegion(AREA0_START, AREA0_SIZE);
RegionHandle a1_handle = memory.AllocRegion(AREA1_START, AREA1_SIZE);
RegionHandle a3_handle = memory.AllocRegion(AREA3_START, AREA3_SIZE);
RegionHandle a5_handle = memory.AllocRegion(AREA5_START, AREA5_SIZE);
RegionHandle a6_handle = memory.AllocRegion(AREA6_START, AREA6_SIZE);
RegionHandle a7_handle = memory.AllocRegion(AREA7_START, AREA7_SIZE);
RegionHandle a0_handle = memory.AllocRegion(AREA0_BEGIN, AREA0_SIZE);
RegionHandle a1_handle = memory.AllocRegion(AREA1_BEGIN, AREA1_SIZE);
RegionHandle a3_handle = memory.AllocRegion(AREA3_BEGIN, AREA3_SIZE);
RegionHandle a5_handle = memory.AllocRegion(AREA5_BEGIN, AREA5_SIZE);
RegionHandle a6_handle = memory.AllocRegion(AREA6_BEGIN, AREA6_SIZE);
RegionHandle a7_handle = memory.AllocRegion(AREA7_BEGIN, AREA7_SIZE);
RegionHandle sh4_reg_handle = memory.AllocRegion(
SH4_REG_START, SH4_REG_SIZE,
SH4_REG_BEGIN, SH4_REG_SIZE,
make_delegate(&SH4::ReadRegister<uint8_t>, this),
make_delegate(&SH4::ReadRegister<uint16_t>, this),
make_delegate(&SH4::ReadRegister<uint32_t>, this), nullptr,
@ -339,18 +339,18 @@ void SH4::MapPhysicalMemory(Memory &memory, MemoryMap &memmap) {
make_delegate(&SH4::WriteRegister<uint16_t>, this),
make_delegate(&SH4::WriteRegister<uint32_t>, this), nullptr);
memmap.Mount(a0_handle, AREA0_SIZE, AREA0_START);
memmap.Mount(a1_handle, AREA1_SIZE, AREA1_START);
memmap.Mount(a3_handle, AREA3_SIZE, AREA3_START);
memmap.Mount(a5_handle, AREA5_SIZE, AREA5_START);
memmap.Mount(a6_handle, AREA6_SIZE, AREA6_START);
memmap.Mount(a7_handle, AREA7_SIZE, AREA7_START);
memmap.Mount(sh4_reg_handle, SH4_REG_SIZE, SH4_REG_START);
memmap.Mount(a0_handle, AREA0_SIZE, AREA0_BEGIN);
memmap.Mount(a1_handle, AREA1_SIZE, AREA1_BEGIN);
memmap.Mount(a3_handle, AREA3_SIZE, AREA3_BEGIN);
memmap.Mount(a5_handle, AREA5_SIZE, AREA5_BEGIN);
memmap.Mount(a6_handle, AREA6_SIZE, AREA6_BEGIN);
memmap.Mount(a7_handle, AREA7_SIZE, AREA7_BEGIN);
memmap.Mount(sh4_reg_handle, SH4_REG_SIZE, SH4_REG_BEGIN);
}
void SH4::MapVirtualMemory(Memory &memory, MemoryMap &memmap) {
RegionHandle sh4_cache_handle =
memory.AllocRegion(SH4_CACHE_START, SH4_CACHE_SIZE,
memory.AllocRegion(SH4_CACHE_BEGIN, SH4_CACHE_SIZE,
make_delegate(&SH4::ReadCache<uint8_t>, this),
make_delegate(&SH4::ReadCache<uint16_t>, this),
make_delegate(&SH4::ReadCache<uint32_t>, this),
@ -361,7 +361,7 @@ void SH4::MapVirtualMemory(Memory &memory, MemoryMap &memmap) {
make_delegate(&SH4::WriteCache<uint64_t>, this));
RegionHandle sh4_sq_handle = memory.AllocRegion(
SH4_SQ_START, SH4_SQ_SIZE, make_delegate(&SH4::ReadSQ<uint8_t>, this),
SH4_SQ_BEGIN, SH4_SQ_SIZE, make_delegate(&SH4::ReadSQ<uint8_t>, this),
make_delegate(&SH4::ReadSQ<uint16_t>, this),
make_delegate(&SH4::ReadSQ<uint32_t>, this), nullptr,
make_delegate(&SH4::WriteSQ<uint8_t>, this),
@ -369,22 +369,22 @@ void SH4::MapVirtualMemory(Memory &memory, MemoryMap &memmap) {
make_delegate(&SH4::WriteSQ<uint32_t>, this), nullptr);
// main ram mirrors
memmap.Mirror(MAIN_RAM_1_START, MAIN_RAM_1_SIZE, MAIN_RAM_2_START);
memmap.Mirror(MAIN_RAM_1_START, MAIN_RAM_1_SIZE, MAIN_RAM_3_START);
memmap.Mirror(MAIN_RAM_1_START, MAIN_RAM_1_SIZE, MAIN_RAM_4_START);
memmap.Mirror(MAIN_RAM_1_BEGIN, MAIN_RAM_1_SIZE, MAIN_RAM_2_BEGIN);
memmap.Mirror(MAIN_RAM_1_BEGIN, MAIN_RAM_1_SIZE, MAIN_RAM_3_BEGIN);
memmap.Mirror(MAIN_RAM_1_BEGIN, MAIN_RAM_1_SIZE, MAIN_RAM_4_BEGIN);
// physical mirrors (ignoring p, alt and cache bits in bits 31-29)
memmap.Mirror(P0_1_START, P0_1_SIZE, P0_2_START);
memmap.Mirror(P0_1_START, P0_1_SIZE, P0_3_START);
memmap.Mirror(P0_1_START, P0_1_SIZE, P0_4_START);
memmap.Mirror(P0_1_START, P0_1_SIZE, P1_START);
memmap.Mirror(P0_1_START, P0_1_SIZE, P2_START);
memmap.Mirror(P0_1_START, P0_1_SIZE, P3_START);
memmap.Mirror(P0_1_START, P0_1_SIZE, P4_START);
memmap.Mirror(P0_1_BEGIN, P0_1_SIZE, P0_2_BEGIN);
memmap.Mirror(P0_1_BEGIN, P0_1_SIZE, P0_3_BEGIN);
memmap.Mirror(P0_1_BEGIN, P0_1_SIZE, P0_4_BEGIN);
memmap.Mirror(P0_1_BEGIN, P0_1_SIZE, P1_BEGIN);
memmap.Mirror(P0_1_BEGIN, P0_1_SIZE, P2_BEGIN);
memmap.Mirror(P0_1_BEGIN, P0_1_SIZE, P3_BEGIN);
memmap.Mirror(P0_1_BEGIN, P0_1_SIZE, P4_BEGIN);
// handle some special access only available in P4 after applying mirrors
memmap.Mount(sh4_cache_handle, SH4_CACHE_SIZE, SH4_CACHE_START);
memmap.Mount(sh4_sq_handle, SH4_SQ_SIZE, SH4_SQ_START);
memmap.Mount(sh4_cache_handle, SH4_CACHE_SIZE, SH4_CACHE_BEGIN);
memmap.Mount(sh4_sq_handle, SH4_SQ_SIZE, SH4_SQ_BEGIN);
}
void SH4::OnPaint(bool show_main_menu) {