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update assembly tests to support nested test cases

This commit is contained in:
Anthony Pesch 2015-09-07 15:49:11 -07:00
parent 212a2541ab
commit 24ce88fb00
95 changed files with 2316 additions and 2378 deletions
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50
CMakeLists.txt
View File

@ -192,42 +192,30 @@ set(TEST_ASM
test/asm/div0.s
test/asm/div1s.s
test/asm/div1u.s
test/asm/dmuls.s
test/asm/dmulu.s
test/asm/dmul.s
test/asm/dt.s
test/asm/ext.s
test/asm/fabsd.s
test/asm/fabsf.s
test/asm/faddd.s
test/asm/faddf.s
test/asm/fcmpeqd.s
test/asm/fcmpeqf.s
test/asm/fcmpgtd.s
test/asm/fcmpgtf.s
test/asm/fdivd.s
test/asm/fdivf.s
test/asm/fabs.s
test/asm/fadd.s
test/asm/fcmpeq.s
test/asm/fcmpgt.s
test/asm/fdiv.s
test/asm/fipr.s
test/asm/fld.s
test/asm/floatd.s
test/asm/floatf.s
test/asm/float.s
test/asm/fmac.s
test/asm/fmovd.s
test/asm/fmovf.s
test/asm/fmovsz.s
test/asm/fmuld.s
test/asm/fmulf.s
test/asm/fnegd.s
test/asm/fnegf.s
test/asm/fmul.s
test/asm/fneg.s
test/asm/frchg.s
test/asm/fsca.s
test/asm/fschg.s
test/asm/fsrra.s
test/asm/fsqrtd.s
test/asm/fsqrtf.s
test/asm/fsubd.s
test/asm/fsubf.s
test/asm/ftrcd.s
test/asm/ftrcf.s
test/asm/fsqrt.s
test/asm/fsub.s
test/asm/ftrc.s
test/asm/ftrv.s
test/asm/jmp.s
test/asm/jsr.s
@ -242,6 +230,7 @@ set(TEST_ASM
test/asm/movw.s
test/asm/mul.s
test/asm/neg.s
test/asm/negc.s
test/asm/not.s
test/asm/or.s
test/asm/rot.s
@ -260,18 +249,21 @@ set(asm_inc ${CMAKE_CURRENT_SOURCE_DIR}/test/asm/sh4_test.inc)
find_package(PythonInterp)
find_program(SH_AS NAMES sh-elf-as)
find_program(SH_LD NAMES sh-elf-ld)
find_program(SH_NM NAMES sh-elf-nm)
find_program(SH_OBJCOPY NAMES sh-elf-objcopy)
if(NOT PYTHONINTERP_FOUND)
message(WARNING "Could not find python interpreter, won't be able to update tests")
message(WARNING "Could not find python interpreter, won't be able to generate tests")
elseif(NOT SH_AS)
message(WARNING "Could not find sh-elf-as, won't be able to update tests")
message(WARNING "Could not find sh-elf-as, won't be able to generate tests")
elseif(NOT SH_LD)
message(WARNING "Could not find sh-elf-ld, won't be able to update tests")
message(WARNING "Could not find sh-elf-ld, won't be able to generate tests")
elseif(NOT SH_NM)
message(WARNING "Could not find sh-elf-nm, won't be able to generate tests")
elseif(NOT SH_OBJCOPY)
message(WARNING "Could not find sh-elf-objcopy, won't be able to update tests")
message(WARNING "Could not find sh-elf-objcopy, won't be able to generate tests")
else()
add_custom_command(OUTPUT ${asm_inc}
COMMAND ${PYTHON_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/test/sh4_test.py -as ${SH_AS} -ld ${SH_LD} -objcopy ${SH_OBJCOPY} -o ${asm_inc} ${TEST_ASM}
COMMAND ${PYTHON_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/test/sh4_test.py -as ${SH_AS} -ld ${SH_LD} -nm ${SH_NM} -objcopy ${SH_OBJCOPY} -o ${asm_inc} ${TEST_ASM}
DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/test/sh4_test.py ${TEST_ASM}
COMMENT "Assembling ${asm_inc} for ${TEST_ASM}"
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}

2
src/cpu/frontend/sh4/sh4_emit.cc
View File

@ -963,7 +963,7 @@ EMITTER(SHAR) {
EMITTER(SHLD) {
// when Rm >= 0, Rn << Rm
// when Rm < 0, Rn >> Rm
// when shifting right > 32, Rn = 0
// when shifting right >= 32, Rn = 0
Block *shl_block = b.AppendBlock();
Block *shr_block = b.AppendBlock();
Block *shr_nooverflow_block = b.AppendBlock();

4
src/cpu/sh4.cc
View File

@ -83,7 +83,7 @@ SH4::SH4(Memory &memory, Runtime &runtime)
void SH4::Init() {
memset(&ctx_, 0, sizeof(ctx_));
ctx_.pc = 0xa0000000;
ctx_.pr = 0xdeadbeef;
ctx_.pr = 0x0;
ctx_.sr.full = ctx_.old_sr.full = 0x700000f0;
ctx_.fpscr.full = ctx_.old_fpscr.full = 0x00040001;
@ -115,7 +115,7 @@ uint32_t SH4::Execute(uint32_t cycles) {
RunTimer(i, cycles >> 2);
}
while (ctx_.pc != 0xdeadbeef) {
while (ctx_.pc) {
uint32_t pc = ctx_.pc & ADDR_MASK;
RuntimeBlock *block = runtime_.GetBlock(pc, &ctx_);

12
test/asm/add.s
View File

@ -1,11 +1,7 @@
# REGISTER_IN r0 -4
# REGISTER_IN r1 17
.text
.global start
start:
test_add:
# REGISTER_IN r0 -4
# REGISTER_IN r1 17
add r0, r1
rts
nop
# REGISTER_OUT r1 13
# REGISTER_OUT r1 13

59
test/asm/addc.s
View File

@ -1,35 +1,30 @@
# REGISTER_IN r1 0xfffffffe
# REGISTER_IN r2 0x1
# REGISTER_IN r3 0xffffffff
# REGISTER_IN r4 0x1
# REGISTER_IN r5 0xffffffff
# REGISTER_IN r6 0x1
.little
.text
.global start
start:
# r1 + r2 + T(0)
addc r2, r1
stc SR, r0
and #0x1, r0
mov r0, r2
# r3 + r4 + T(0)
addc r4, r3
stc SR, r0
and #0x1, r0
mov r0, r4
# r5 + r6 + T(1)
addc r6, r5
stc SR, r0
and #0x1, r0
mov r0, r6
test_addc_nocarry:
# REGISTER_IN r0 0xfffffffe
# REGISTER_IN r1 0x1
addc r1, r0
movt r1
rts
nop
# REGISTER_OUT r0 0xffffffff
# REGISTER_OUT r1 0
# REGISTER_OUT r1 0xffffffff
# REGISTER_OUT r2 0
# REGISTER_OUT r3 0x0
# REGISTER_OUT r4 1
# REGISTER_OUT r5 0x1
# REGISTER_OUT r6 1
test_addc_carry_t0:
# REGISTER_IN r0 0xffffffff
# REGISTER_IN r1 0x1
addc r1, r0
movt r1
rts
nop
# REGISTER_OUT r0 0x0
# REGISTER_OUT r1 1
test_addc_carry_t1:
# REGISTER_IN r0 0xffffffff
# REGISTER_IN r1 0x1
sett
addc r1, r0
movt r1
rts
nop
# REGISTER_OUT r0 0x1
# REGISTER_OUT r1 1

182
test/asm/addv.s
View File

@ -1,100 +1,90 @@
# l r sum
# ---------------------------
# 0 0 0
# *OVER* 0 0 1 (adding two positives should be positive)
# 0 1 0
# 0 1 1
# 1 0 0
# 1 0 1
# *OVER* 1 1 0 (adding two negatives should be negative)
# 1 1 1
.little
.text
.global start
start:
# 0x7ffffffe(0) + 0x00000001(0) = 0x7fffffff(0)
mov #0x1, r0
mov.l .L1, r1
# truth table for signed additition, 0 for positive, 1 for negative
# ------------------------------------------------------------------
# 0 + 0 = 0
# 0 + 0 = 1 *OVERFLOW*
# 0 + 1 = 0
# 0 + 1 = 1
# 1 + 0 = 0
# 1 + 0 = 1
# 1 + 1 = 0 *OVERFLOW*
# 1 + 1 + 1
test_addv_ppp:
# REGISTER_IN r0 0x1
# REGISTER_IN r1 0x7ffffffe
addv r0, r1
stc SR, r0
and #0x1, r0
mov r0, r2
# 0x7fffffff(0) + 0x00000001(0) = 0x80000000(1), OVERFLOWED
mov #0x1, r0
mov.l .L2, r3
addv r0, r3
stc SR, r0
and #0x1, r0
mov r0, r4
# 0x7fffffff(0) + 0x80000001(1) = 0x00000000(1)
mov.l .L4, r0
mov.l .L2, r5
addv r0, r5
stc SR, r0
and #0x1, r0
mov r0, r6
# 0x00000001(0) + 0x80000000(1) = 0x80000001(1)
mov.l .L3, r0
mov #0x1, r7
addv r0, r7
stc SR, r0
and #0x1, r0
mov r0, r8
# 0x80000001(1) + 0x7fffffff(0) = 0x00000000(1)
mov.l .L2, r0
mov.l .L4, r9
addv r0, r9
stc SR, r0
and #0x1, r0
mov r0, r10
# 0x80000000(1) + 0x00000001(0) = 0x80000001(1)
mov #0x1, r0
mov.l .L3, r11
addv r0, r11
stc SR, r0
and #0x1, r0
mov r0, r12
# 0x80000000(1) + 0xfffffffff(1) = 0x7fffffff(1), OVERFLOWED
mov #-1, r0
mov.l .L3, r13
addv r0, r13
stc SR, r0
and #0x1, r0
mov r0, r14
# 0x80000001(1) + 0xffffffff(0) = 0x80000000(1)
mov #-1, r0
mov.l .L4, r15
addv r0, r15
stc SR, r0
and #0x1, r0
movt r0
rts
nop
.align 4
.L1:
.long 0x7ffffffe
.align 4
.L2:
.long 0x7fffffff
.align 4
.L3:
.long 0x80000000
.align 4
.L4:
.long 0x80000001
# REGISTER_OUT r1 0x7fffffff
# REGISTER_OUT r0 0
# REGISTER_OUT r1 0x7fffffff
# REGISTER_OUT r2 0
# REGISTER_OUT r3 0x80000000
# REGISTER_OUT r4 1
# REGISTER_OUT r5 0x00000000
# REGISTER_OUT r6 0
# REGISTER_OUT r7 0x80000001
# REGISTER_OUT r8 0
# REGISTER_OUT r9 0x00000000
# REGISTER_OUT r10 0
# REGISTER_OUT r11 0x80000001
# REGISTER_OUT r12 0
# REGISTER_OUT r13 0x7fffffff
# REGISTER_OUT r14 1
# REGISTER_OUT r15 0x80000000
# REGISTER_OUT r0 0
test_addv_ppn_overflow:
# REGISTER_IN r0 0x1
# REGISTER_IN r1 0x7fffffff
addv r0, r1
movt r0
rts
nop
# REGISTER_OUT r1 0x80000000
# REGISTER_OUT r0 1
test_addv_pnp:
# REGISTER_IN r0 0x80000001
# REGISTER_IN r1 0x7fffffff
addv r0, r1
movt r0
rts
nop
# REGISTER_OUT r1 0x00000000
# REGISTER_OUT r0 0
test_addv_pnn:
# REGISTER_IN r0 0x80000000
# REGISTER_IN r1 0x1
addv r0, r1
movt r0
rts
nop
# REGISTER_OUT r1 0x80000001
# REGISTER_OUT r0 0
test_addv_npp:
# REGISTER_IN r0 0x7fffffff
# REGISTER_IN r1 0x80000001
addv r0, r1
movt r0
rts
nop
# REGISTER_OUT r1 0x00000000
# REGISTER_OUT r0 0
test_addv_npn:
# REGISTER_IN r0 0x1
# REGISTER_IN r1 0x80000000
addv r0, r1
movt r0
rts
nop
# REGISTER_OUT r1 0x80000001
# REGISTER_OUT r0 0
test_addv_nnp_overflow:
# REGISTER_IN r0 0xffffffff
# REGISTER_IN r1 0x80000000
addv r0, r1
movt r0
rts
nop
# REGISTER_OUT r1 0x7fffffff
# REGISTER_OUT r0 1
test_addv_nnn:
# REGISTER_IN r0 0xffffffff
# REGISTER_IN r1 0x80000001
addv r0, r1
movt r0
rts
nop
# REGISTER_OUT r1 0x80000000
# REGISTER_OUT r0 0

38
test/asm/and.s
View File

@ -1,31 +1,33 @@
# REGISTER_IN r0 0x00ffffff
# REGISTER_IN r1 0xffffff00
.text
.global start
start:
# AND Rm,Rn
test_and:
# REGISTER_IN r0 0x00ffffff
# REGISTER_IN r1 0xffffff00
and r0, r1
# AND #imm,R0
and #0xff, r0
mov r0, r2
# AND.B #imm,@(R0,GBR)
rts
nop
# REGISTER_OUT r1 0xffff00
test_and_imm:
# REGISTER_IN r0 0x00ffffff
and #0xf0, r0
rts
nop
# REGISTER_OUT r0 0xf0
test_and_disp:
mov.l .L2, r0
ldc r0, GBR
mov #4, r0
and.b #0x3f, @(r0, GBR)
# use mov.l instead of mov.b to avoid sign extension of 0xff
mov.l @(4, GBR), r0
rts
nop
.align 4
# REGISTER_OUT r0 0x3c
.align 4
.L1:
.long 0x0
.long 0x000000fc
.align 4
.align 4
.L2:
.long .L1
# REGISTER_OUT r1 0xffff00
# REGISTER_OUT r2 0xff
# REGISTER_OUT r0 0x3c

44
test/asm/bf.s
View File

@ -1,26 +1,26 @@
# REGISTER_IN r0 7
# REGISTER_IN r1 0
.little
.text
.global start
start:
# BF disp
cmp/eq #8, r0
test_bf:
# REGISTER_IN r0 8
# REGISTER_IN r1 0
cmp/eq #7, r0
bf .L1
bra .L4
nop
.L1:
# BFS disp
cmp/eq #9, r0
bf/s .L3
add #6, r1
bra .L4
nop
.L3:
add #7, r1
.L4:
rts
nop
.L1:
mov #3, r1
rts
nop
# REGISTER_OUT r1 3
# REGISTER_OUT r1 13
test_bfs:
# REGISTER_IN r0 8
# REGISTER_IN r1 0
cmp/eq #7, r0
bf/s .L2
add #6, r1
rts
nop
.L2:
add #7, r1
rts
nop
# REGISTER_OUT r1 13

13
test/asm/bra.s
View File

@ -1,18 +1,11 @@
# REGISTER_IN r0 4
.little
.text
.global start
start:
# BRA label
test_bra:
# REGISTER_IN r0 4
bra .L2
nop
.L1:
add #1, r0
.L2:
add #9, r0
.L4:
rts
nop
# REGISTER_OUT r0 13
# REGISTER_OUT r0 13

14
test/asm/braf.s
View File

@ -1,16 +1,10 @@
# REGISTER_IN r0 2
# REGISTER_IN r1 4
.little
.text
.global start
start:
# BRAF Rn
test_braf:
# REGISTER_IN r0 2
# REGISTER_IN r1 4
braf r0
nop
add #7, r1
add #9, r1
rts
nop
# REGISTER_OUT r1 13
# REGISTER_OUT r1 13

13
test/asm/bsr.s
View File

@ -1,8 +1,4 @@
.little
.text
.global start
start:
# BSR label
test_bsr:
sts.l pr, @-r15
bsr _addnine
add #1, r0
@ -10,13 +6,8 @@ start:
lds.l @r15+, pr
rts
nop
_dontgohere:
add #2, r0
rts
nop
_addnine:
add #9, r0
rts
nop
# REGISTER_OUT r0 13
# REGISTER_OUT r0 13

16
test/asm/bsrf.s
View File

@ -1,10 +1,5 @@
# REGISTER_IN r0 14
.little
.text
.global start
start:
# BSRF Rn
test_bsrf:
# REGISTER_IN r0 8
sts.l pr, @-r15
bsrf r0
add #1, r1
@ -12,13 +7,8 @@ start:
lds.l @r15+, pr
rts
nop
_dontgohere:
add #2, r1
rts
nop
_addnine:
add #9, r1
rts
nop
# REGISTER_OUT r1 13
# REGISTER_OUT r1 13

43
test/asm/bt.s
View File

@ -1,26 +1,27 @@
# REGISTER_IN r0 7
# REGISTER_IN r1 0
.little
.text
.global start
start:
# BT disp
test_bt:
# REGISTER_IN r0 7
# REGISTER_IN r1 0
cmp/eq #7, r0
bt .L1
bra .L4
nop
.L1:
# BTS disp
cmp/eq #7, r0
bt/s .L3
add #6, r1
bra .L4
nop
.L3:
add #7, r1
.L4:
rts
nop
.L1:
mov #3, r1
rts
nop
# REGISTER_OUT r1 3
# REGISTER_OUT r1 13
test_bts:
# REGISTER_IN r0 7
# REGISTER_IN r1 0
# BTS disp
cmp/eq #7, r0
bt/s .L2
add #6, r1
rts
nop
.L2:
add #7, r1
rts
nop
# REGISTER_OUT r1 13

308
test/asm/cmp.s
View File

@ -1,181 +1,131 @@
.text
.global start
start:
# CMP/EQ #imm,R0
mov #0, r2
mov #13, r0
cmp/eq #13, r0 /* true */
stc SR, r0
and #0x1, r0
add r0, r2
mov #13, r0
cmp/eq #17, r0 /* false */
stc SR, r0
and #0x1, r0
add r0, r2
# CMP/EQ Rm,Rn
mov #0, r3
mov #13, r1
mov #13, r0
cmp/eq r0, r1 /* true */
stc SR, r0
and #0x1, r0
add r0, r3
mov #17, r1
mov #13, r0
cmp/eq r0, r1 /* false */
stc SR, r0
and #0x1, r0
add r0, r3
# CMP/HS Rm,Rn
mov #0, r4
mov #-1, r1
mov #13, r0
cmp/hs r0, r1 /* true */
stc SR, r0
and #0x1, r0
add r0, r4
mov #13, r1
mov #13, r0
cmp/hs r0, r1 /* true */
stc SR, r0
and #0x1, r0
add r0, r4
mov #14, r1
mov #13, r0
cmp/hs r0, r1 /* true */
stc SR, r0
and #0x1, r0
add r0, r4
# CMP/GE Rm,Rn
mov #0, r5
mov #-1, r1
mov #13, r0
cmp/ge r0, r1 /* false */
stc SR, r0
and #0x1, r0
add r0, r5
mov #13, r1
mov #13, r0
cmp/ge r0, r1 /* true */
stc SR, r0
and #0x1, r0
add r0, r5
mov #14, r1
mov #13, r0
cmp/ge r0, r1 /* true */
stc SR, r0
and #0x1, r0
add r0, r5
# CMP/HI Rm,Rn
mov #0, r6
mov #-1, r1
mov #13, r0
cmp/hi r0, r1 /* true */
stc SR, r0
and #0x1, r0
add r0, r6
mov #13, r1
mov #13, r0
cmp/hi r0, r1 /* false */
stc SR, r0
and #0x1, r0
add r0, r6
mov #14, r1
mov #13, r0
cmp/hi r0, r1 /* true */
stc SR, r0
and #0x1, r0
add r0, r6
# CMP/GT Rm,Rn
mov #0, r7
mov #-1, r1
mov #13, r0
cmp/gt r0, r1 /* false */
stc SR, r0
and #0x1, r0
add r0, r7
mov #13, r1
mov #13, r0
cmp/gt r0, r1 /* false */
stc SR, r0
and #0x1, r0
add r0, r7
mov #14, r1
mov #13, r0
cmp/gt r0, r1 /* true */
stc SR, r0
and #0x1, r0
add r0, r7
# CMP/PZ Rn
mov #0, r8
mov #-13, r0
cmp/pz r0 /* false */
stc SR, r0
and #0x1, r0
add r0, r8
mov #0, r0
cmp/pz r0 /* true */
stc SR, r0
and #0x1, r0
add r0, r8
mov #13, r0
cmp/pz r0 /* true */
stc SR, r0
and #0x1, r0
add r0, r8
# CMP/PL Rn
mov #0, r9
mov #-13, r0
cmp/pl r0 /* false */
stc SR, r0
and #0x1, r0
add r0, r9
mov #0, r0
cmp/pl r0 /* true */
stc SR, r0
and #0x1, r0
add r0, r9
mov #13, r0
cmp/pl r0 /* true */
stc SR, r0
and #0x1, r0
add r0, r9
# CMP/STR Rm,Rn
mov #0, r10
mov #-1, r1
mov #0, r0
cmp/str r0, r1 /* false */
stc SR, r0
and #0x1, r0
add r0, r10
mov #-1, r1
mov.l .L1, r0
cmp/str r0, r1 /* false */
stc SR, r0
and #0x1, r0
add r0, r10
mov #-1, r1
mov.l .L2, r0
cmp/str r0, r1 /* true */
stc SR, r0
and #0x1, r0
add r0, r10
rts
test_cmpeq_imm:
# REGISTER_IN r0 13
cmp/eq #13, r0
movt r1
cmp/eq #17, r0
movt r2
rts
nop
.align 4
.L1:
.long 0x00f00000
.align 4
.L2:
.long 0x00ff0000
# REGISTER_OUT r1 1
# REGISTER_OUT r2 0
# REGISTER_OUT r2 1
# REGISTER_OUT r3 1
# REGISTER_OUT r4 3
# REGISTER_OUT r5 2
# REGISTER_OUT r6 2
# REGISTER_OUT r7 1
# REGISTER_OUT r8 2
# REGISTER_OUT r9 1
# REGISTER_OUT r10 1
test_cmpeq:
# REGISTER_IN r0 13
# REGISTER_IN r1 17
cmp/eq r0, r0
movt r2
cmp/eq r0, r2
movt r4
rts
nop
# REGISTER_OUT r2 1
# REGISTER_OUT r3 0
test_cmphs:
# REGISTER_IN r0 -1
# REGISTER_IN r1 13
cmp/hs r1, r0
movt r2
cmp/hs r1, r1
movt r3
cmp/hs r0, r1
movt r4
rts
nop
# REGISTER_OUT r2 1
# REGISTER_OUT r3 1
# REGISTER_OUT r4 0
test_cmpge:
# REGISTER_IN r0 -1
# REGISTER_IN r1 13
cmp/ge r1, r0
movt r2
cmp/ge r1, r1
movt r3
cmp/ge r0, r1
movt r4
rts
nop
# REGISTER_OUT r2 0
# REGISTER_OUT r3 1
# REGISTER_OUT r4 1
test_cmphi:
# REGISTER_IN r0 -1
# REGISTER_IN r1 13
cmp/hi r1, r0
movt r2
cmp/hi r1, r1
movt r3
cmp/hi r0, r1
movt r4
rts
nop
# REGISTER_OUT r2 1
# REGISTER_OUT r3 0
# REGISTER_OUT r4 0
test_cmpgt:
# REGISTER_IN r0 -1
# REGISTER_IN r1 13
cmp/gt r1, r0
movt r2
cmp/gt r1, r1
movt r3
cmp/gt r0, r1
movt r4
rts
nop
# REGISTER_OUT r2 0
# REGISTER_OUT r3 0
# REGISTER_OUT r4 1
test_cmppz:
# REGISTER_IN r0 -1
# REGISTER_IN r1 0
# REGISTER_IN r2 1
cmp/pz r0
movt r3
cmp/pz r1
movt r4
cmp/pz r2
movt r5
rts
nop
# REGISTER_OUT r3 0
# REGISTER_OUT r4 1
# REGISTER_OUT r5 1
test_cmppl:
# REGISTER_IN r0 -1
# REGISTER_IN r1 0
# REGISTER_IN r2 1
cmp/pl r0
movt r3
cmp/pl r1
movt r4
cmp/pl r2
movt r5
rts
nop
# REGISTER_OUT r3 0
# REGISTER_OUT r4 0
# REGISTER_OUT r5 1
test_cmpstr:
# REGISTER_IN r0 0x00000000
# REGISTER_IN r1 0xffffffff
# REGISTER_IN r2 0x00f00000
# REGISTER_IN r3 0x00ff0000
cmp/str r0, r1
movt r4
cmp/str r2, r1
movt r5
cmp/str r3, r1
movt r6
rts
nop
# REGISTER_OUT r4 0
# REGISTER_OUT r5 0
# REGISTER_OUT r6 1

87
test/asm/div0.s
View File

@ -1,42 +1,53 @@
# REGISTER_IN r0 0x700000f0
# REGISTER_IN r2 0x2
# REGISTER_IN r3 0x4
# REGISTER_IN r5 0xfffffffe
# REGISTER_IN r6 0xfffffffc
# REGISTER_IN r8 0x2
# REGISTER_IN r9 0xfffffffc
# REGISTER_IN r11 0xfffffffe
# REGISTER_IN r12 0x4
.text
.global start
start:
# div0u
ldc r0, SR
test_div0u:
# REGISTER_IN r0 0x700000f0
ldc r0, sr
div0u
stc SR, r1
stc sr, r1
and r0, r1
# div0s (negative dividend / divisor)
ldc r0, SR
div0s r2, r3
stc SR, r4
# div0s (positive dividend / divisor)
ldc r0, SR
div0s r5, r6
stc SR, r7
# div0s (negative dividend / positive divisor)
ldc r0, SR
div0s r8, r9
stc SR, r10
# div0s (positive dividend / negative divisor)
ldc r0, SR
div0s r11, r12
stc SR, r13
rts
rts
nop
# REGISTER_OUT r1 0x700000f0
# REGISTER_OUT r1 0x700000f0
# REGISTER_OUT r4 0x700000f0
# REGISTER_OUT r7 0x700003f0
# REGISTER_OUT r10 0x700001f1
# REGISTER_OUT r13 0x700002f1
test_div0s_ndividend_ndivisor:
# REGISTER_IN r0 0x700000f0
# REGISTER_IN r1 0x2
# REGISTER_IN r2 0x4
ldc r0, sr
div0s r1, r2
stc sr, r3
rts
nop
# REGISTER_OUT r3 0x700000f0
test_div0s_pdividend_pdivisor:
# REGISTER_IN r0 0x700000f0
# REGISTER_IN r1 0xfffffffe
# REGISTER_IN r2 0xfffffffc
ldc r0, sr
div0s r1, r2
stc sr, r3
rts
nop
# REGISTER_OUT r3 0x700003f0
test_div0s_ndividend_pdivisor:
# REGISTER_IN r0 0x700000f0
# REGISTER_IN r1 0x2
# REGISTER_IN r2 0xfffffffc
ldc r0, sr
div0s r1, r2
stc sr, r3
rts
nop
# REGISTER_OUT r3 0x700001f1
test_div0s_pdividend_ndivisor:
# REGISTER_IN r0 0x700000f0
# REGISTER_IN r1 0xfffffffe
# REGISTER_IN r2 0x4
ldc r0, sr
div0s r1, r2
stc sr, r3
rts
nop
# REGISTER_OUT r3 0x700002f1

390
test/asm/div1s.s
View File

@ -1,16 +1,7 @@
# REGISTER_IN r2 0x2710
# REGISTER_IN r3 0x8012
# REGISTER_IN r4 0xd8f0
# REGISTER_IN r5 0x7fee
# REGISTER_IN r6 0x2710
# REGISTER_IN r7 0xf0000010
# REGISTER_IN r8 0xffffd8f0
# REGISTER_IN r9 0x0ffffff0
.text
.global start
start:
# r3 (negative, 16 bits) / r2 (16 bits) = r3 (16 bits)
test_div1s_16_ndividend:
# REGISTER_IN r2 0x2710
# REGISTER_IN r3 0x8012
# dividend is r3, divisor is r2
shll16 r2
exts.w r3, r3
xor r0, r0
@ -38,184 +29,201 @@ start:
rotcl r3
addc r0, r3
exts.w r3, r3
# r5 (16 bits) / r4 (negative, 16 bits) = r5 (16 bits)
shll16 r4
exts.w r5, r5
xor r0, r0
mov r5, r1
rotcl r1
subc r0, r5
div0s r4, r5
div1 r4, r5
div1 r4, r5
div1 r4, r5
div1 r4, r5
div1 r4, r5
div1 r4, r5
div1 r4, r5
div1 r4, r5
div1 r4, r5
div1 r4, r5
div1 r4, r5
div1 r4, r5
div1 r4, r5
div1 r4, r5
div1 r4, r5
div1 r4, r5
exts.w r5, r5
rotcl r5
addc r0, r5
exts.w r5, r5
# r7 (negative, 32 bits) / r6 (32 bits) = r7 (32 bits)
mov r7, r0
rotcl r0
subc r1, r1
xor r0, r0
subc r0, r7
div0s r6, r1
rotcl r7
div1 r6, r1
rotcl r7
div1 r6, r1
rotcl r7
div1 r6, r1
rotcl r7
div1 r6, r1
rotcl r7
div1 r6, r1
rotcl r7
div1 r6, r1
rotcl r7
div1 r6, r1
rotcl r7
div1 r6, r1
rotcl r7
div1 r6, r1
rotcl r7
div1 r6, r1
rotcl r7
div1 r6, r1
rotcl r7
div1 r6, r1
rotcl r7
div1 r6, r1
rotcl r7
div1 r6, r1
rotcl r7
div1 r6, r1
rotcl r7
div1 r6, r1
rotcl r7
div1 r6, r1
rotcl r7
div1 r6, r1
rotcl r7
div1 r6, r1
rotcl r7
div1 r6, r1
rotcl r7
div1 r6, r1
rotcl r7
div1 r6, r1
rotcl r7
div1 r6, r1
rotcl r7
div1 r6, r1
rotcl r7
div1 r6, r1
rotcl r7
div1 r6, r1
rotcl r7
div1 r6, r1
rotcl r7
div1 r6, r1
rotcl r7
div1 r6, r1
rotcl r7
div1 r6, r1
rotcl r7
div1 r6, r1
rotcl r7
div1 r6, r1
rotcl r7
addc r0, r7
# r9 (32 bits) / r8 (negative, 32 bits) = r9 (32 bits)
mov r9, r0
rotcl r0
subc r1, r1
xor r0, r0
subc r0, r9
div0s r8, r1
rotcl r9
div1 r8, r1
rotcl r9
div1 r8, r1
rotcl r9
div1 r8, r1
rotcl r9
div1 r8, r1
rotcl r9
div1 r8, r1
rotcl r9
div1 r8, r1
rotcl r9
div1 r8, r1
rotcl r9
div1 r8, r1
rotcl r9
div1 r8, r1
rotcl r9
div1 r8, r1
rotcl r9
div1 r8, r1
rotcl r9
div1 r8, r1
rotcl r9
div1 r8, r1
rotcl r9
div1 r8, r1
rotcl r9
div1 r8, r1
rotcl r9
div1 r8, r1
rotcl r9
div1 r8, r1
rotcl r9
div1 r8, r1
rotcl r9
div1 r8, r1
rotcl r9
div1 r8, r1
rotcl r9
div1 r8, r1
rotcl r9
div1 r8, r1
rotcl r9
div1 r8, r1
rotcl r9
div1 r8, r1
rotcl r9
div1 r8, r1
rotcl r9
div1 r8, r1
rotcl r9
div1 r8, r1
rotcl r9
div1 r8, r1
rotcl r9
div1 r8, r1
rotcl r9
div1 r8, r1
rotcl r9
div1 r8, r1
rotcl r9
div1 r8, r1
rotcl r9
addc r0, r9
rts
nop
# REGISTER_OUT r3 0xfffffffd
# REGISTER_OUT r3 0xfffffffd
# REGISTER_OUT r5 0xfffffffd
# REGISTER_OUT r7 0xffff9725
# REGISTER_OUT r9 0xffff9725
test_div1s_16_ndivisor:
# REGISTER_IN r2 0xd8f0
# REGISTER_IN r3 0x7fee
# dividend is r3, divisor is r2
shll16 r2
exts.w r3, r3
xor r0, r0
mov r3, r1
rotcl r1
subc r0, r3
div0s r2, r3
div1 r2, r3
div1 r2, r3
div1 r2, r3
div1 r2, r3
div1 r2, r3
div1 r2, r3
div1 r2, r3
div1 r2, r3
div1 r2, r3
div1 r2, r3
div1 r2, r3
div1 r2, r3
div1 r2, r3
div1 r2, r3
div1 r2, r3
div1 r2, r3
exts.w r3, r3
rotcl r3
addc r0, r3
exts.w r3, r3
rts
nop
# REGISTER_OUT r3 0xfffffffd
test_div1s_32_ndividend:
# REGISTER_IN r2 0x2710
# REGISTER_IN r3 0xf0000010
# dividend is r3, divisor is r2
mov r3, r0
rotcl r0
subc r1, r1
xor r0, r0
subc r0, r3
div0s r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
addc r0, r3
rts
nop
# REGISTER_OUT r3 0xffff9725
test_div1s_32_ndivisor:
# REGISTER_IN r2 0xffffd8f0
# REGISTER_IN r3 0x0ffffff0
# dividend is r3, divisor is r2
mov r3, r0
rotcl r0
subc r1, r1
xor r0, r0
subc r0, r3
div0s r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
div1 r2, r1
rotcl r3
addc r0, r3
rts
nop
# REGISTER_OUT r3 0xffff9725

158
test/asm/div1u.s
View File

@ -1,13 +1,7 @@
# REGISTER_IN r0 0x2710
# REGISTER_IN r1 0x0ffffff0
# REGISTER_IN r2 0x2710
# REGISTER_IN r3 0x00000001
# REGISTER_IN r4 0x2a05f200
.text
.global start
start:
# r1 (32 bits) / r0 (16 bits) = r1 (16 bits)
test_div1u_32_16:
# REGISTER_IN r0 0x2710
# REGISTER_IN r1 0x0ffffff0
# r1 (32 bits) / r0 (16 bits) = r1 (16 bits)
shll16 r0
div0u
div1 r0, r1
@ -28,75 +22,81 @@ start:
div1 r0, r1
rotcl r1
extu.w r1, r1
# r3:r4 (64 bits) / r2 (32 bits) = R4 (32 bits)
div0u
rotcl r4
div1 r2, r3
rotcl r4
div1 r2, r3
rotcl r4
div1 r2, r3
rotcl r4
div1 r2, r3
rotcl r4
div1 r2, r3
rotcl r4
div1 r2, r3
rotcl r4
div1 r2, r3
rotcl r4
div1 r2, r3
rotcl r4
div1 r2, r3
rotcl r4
div1 r2, r3
rotcl r4
div1 r2, r3
rotcl r4
div1 r2, r3
rotcl r4
div1 r2, r3
rotcl r4
div1 r2, r3
rotcl r4
div1 r2, r3
rotcl r4
div1 r2, r3
rotcl r4
div1 r2, r3
rotcl r4
div1 r2, r3
rotcl r4
div1 r2, r3
rotcl r4
div1 r2, r3
rotcl r4
div1 r2, r3
rotcl r4
div1 r2, r3
rotcl r4
div1 r2, r3
rotcl r4
div1 r2, r3
rotcl r4
div1 r2, r3
rotcl r4
div1 r2, r3
rotcl r4
div1 r2, r3
rotcl r4
div1 r2, r3
rotcl r4
div1 r2, r3
rotcl r4
div1 r2, r3
rotcl r4
div1 r2, r3
rotcl r4
div1 r2, r3
rotcl r4
rts
nop
# REGISTER_OUT r1 0x68db
# REGISTER_OUT r1 0x68db
# REGISTER_OUT r4 0x7a120
test_div1u_64_32:
# REGISTER_IN r0 0x00002710
# REGISTER_IN r1 0x00000001
# REGISTER_IN r2 0x2a05f200
# r1:r2 (64 bits) / r0 (32 bits) = r2 (32 bits)
div0u
rotcl r2
div1 r0, r1
rotcl r2
div1 r0, r1
rotcl r2
div1 r0, r1
rotcl r2
div1 r0, r1
rotcl r2
div1 r0, r1
rotcl r2
div1 r0, r1
rotcl r2
div1 r0, r1
rotcl r2
div1 r0, r1
rotcl r2
div1 r0, r1
rotcl r2
div1 r0, r1
rotcl r2
div1 r0, r1
rotcl r2
div1 r0, r1
rotcl r2
div1 r0, r1
rotcl r2
div1 r0, r1
rotcl r2
div1 r0, r1
rotcl r2
div1 r0, r1
rotcl r2
div1 r0, r1
rotcl r2
div1 r0, r1
rotcl r2
div1 r0, r1
rotcl r2
div1 r0, r1
rotcl r2
div1 r0, r1
rotcl r2
div1 r0, r1
rotcl r2
div1 r0, r1
rotcl r2
div1 r0, r1
rotcl r2
div1 r0, r1
rotcl r2
div1 r0, r1
rotcl r2
div1 r0, r1
rotcl r2
div1 r0, r1
rotcl r2
div1 r0, r1
rotcl r2
div1 r0, r1
rotcl r2
div1 r0, r1
rotcl r2
div1 r0, r1
rotcl r2
rts
nop
# REGISTER_OUT r2 0x7a120

22
test/asm/dmul.s Normal file
View File

@ -0,0 +1,22 @@
test_dmuls:
# REGISTER_IN r0 0xfffffffe
# REGISTER_IN r1 0x00005555
dmuls.l r0, r1
sts MACH, r0
sts MACL, r1
rts
nop
# REGISTER_OUT r0 0xffffffff
# REGISTER_OUT r1 0xffff5556
test_dmulu:
# REGISTER_IN r0 0xfffffffe
# REGISTER_IN r1 0x00005555
dmulu.l r0, r1
sts MACH, r0
sts MACL, r1
rts
nop
# REGISTER_OUT r0 0x00005554
# REGISTER_OUT r1 0xffff5556

14
test/asm/dmuls.s
View File

@ -1,14 +0,0 @@
# REGISTER_IN r0 0xfffffffe
# REGISTER_IN r1 0x00005555
.text
.global start
start:
dmuls.l r0, r1
sts MACH, r0
sts MACL, r1
rts
nop
# REGISTER_OUT r0 0xffffffff
# REGISTER_OUT r1 0xffff5556

14
test/asm/dmulu.s
View File

@ -1,14 +0,0 @@
# REGISTER_IN r0 0xfffffffe
# REGISTER_IN r1 0x00005555
.text
.global start
start:
dmulu.l r0, r1
sts MACH, r0
sts MACL, r1
rts
nop
# REGISTER_OUT r0 0x00005554
# REGISTER_OUT r1 0xffff5556

14
test/asm/dt.s
View File

@ -1,14 +1,8 @@
# REGISTER_IN r0 13
# REGISTER_IN r1 0
.text
.global start
start:
test_dt:
# REGISTER_IN r0 13
# REGISTER_IN r1 0
add #1, r1
dt r0
bf start
bf test_dt
rts
nop
# REGISTER_OUT r0 0
# REGISTER_OUT r1 13

45
test/asm/ext.s
View File

@ -1,22 +1,27 @@
# REGISTER_IN r0 0xff
# REGISTER_IN r1 0xffff
# REGISTER_IN r2 0xfffa3002
.text
.global start
start:
# EXTS.B Rm,Rn
exts.b r0, r3
# EXTS.W Rm,Rn
exts.w r1, r4
# EXTU.B Rm,Rn
extu.b r2, r5
# EXTU.W Rm,Rn
extu.w r2, r6
rts
test_extsb:
# REGISTER_IN r0 0xff
exts.b r0, r1
rts
nop
# REGISTER_OUT r1 0xffffffff
# REGISTER_OUT r3 0xffffffff
# REGISTER_OUT r4 0xffffffff
# REGISTER_OUT r5 0x2
# REGISTER_OUT r6 0x3002
test_extsw:
# REGISTER_IN r0 0xffff
exts.w r0, r1
rts
nop
# REGISTER_OUT r1 0xffffffff
test_extub:
# REGISTER_IN r0 0xfffa3002
extu.b r0, r1
rts
nop
# REGISTER_OUT r1 0x2
test_extuw:
# REGISTER_IN r0 0xfffa3002
extu.w r0, r1
rts
nop
# REGISTER_OUT r1 0x3002

15
test/asm/fabs.s Normal file
View File

@ -0,0 +1,15 @@
test_fabsd:
# REGISTER_IN fpscr 0x000c0001
# REGISTER_IN dr2 0xc010000000000000
fabs dr2
rts
nop
# REGISTER_OUT dr2 0x4010000000000000
test_fabsf:
# REGISTER_IN fr1 0xc0800000
fabs fr1
rts
nop
# REGISTER_OUT fr1 0x40800000

12
test/asm/fabsd.s
View File

@ -1,12 +0,0 @@
# REGISTER_IN fpscr 0x000c0001
# REGISTER_IN dr2 0xc010000000000000
.text
.global start
start:
# FABS DRn
fabs dr2
rts
nop
# REGISTER_OUT dr2 0x4010000000000000

11
test/asm/fabsf.s
View File

@ -1,11 +0,0 @@
# REGISTER_IN fr1 0xc0800000
.text
.global start
start:
# FABS FRn
fabs fr1
rts
nop
# REGISTER_OUT fr1 0x40800000

17
test/asm/fadd.s Normal file
View File

@ -0,0 +1,17 @@
test_faddd:
# REGISTER_IN fpscr 0x000c0001
# REGISTER_IN dr0 0x4014000000000000
# REGISTER_IN dr2 0xc018000000000000
fadd dr0, dr2
rts
nop
# REGISTER_OUT dr2 0xbff0000000000000
test_faddf:
# REGISTER_IN fr0 0x40400000
# REGISTER_IN fr1 0xbf800000
fadd fr0, fr1
rts
nop
# REGISTER_OUT fr1 0x40000000

13
test/asm/faddd.s
View File

@ -1,13 +0,0 @@
# REGISTER_IN fpscr 0x000c0001
# REGISTER_IN dr0 0x4014000000000000
# REGISTER_IN dr2 0xc018000000000000
.text
.global start
start:
# FADD DRm,DRn PR=1 1111nnn0mmm00000
fadd dr0, dr2
rts
nop
# REGISTER_OUT dr2 0xbff0000000000000

12
test/asm/faddf.s
View File

@ -1,12 +0,0 @@
# REGISTER_IN fr0 0x40400000
# REGISTER_IN fr1 0xbf800000
.text
.global start
start:
# FADD FRm,FRn PR=0 1111nnnnmmmm0000
fadd fr0, fr1
rts
nop
# REGISTER_OUT fr1 0x40000000

27
test/asm/fcmpeq.s Normal file
View File

@ -0,0 +1,27 @@
test_fcmpeqd:
# REGISTER_IN fpscr 0x000c0001
# REGISTER_IN dr0 0x4014000000000000
# REGISTER_IN dr2 0xc018000000000000
# REGISTER_IN dr4 0xc018000000000000
fcmp/eq dr0, dr2
movt r0
fcmp/eq dr2, dr4
movt r1
rts
nop
# REGISTER_OUT r0 0
# REGISTER_OUT r1 1
test_fcmpeqf:
# REGISTER_IN fr0 0x40400000
# REGISTER_IN fr1 0xbf800000
# REGISTER_IN fr2 0xbf800000
fcmp/eq fr0, fr1
movt r0
fcmp/eq fr1, fr2
movt r1
rts
nop
# REGISTER_OUT r0 0
# REGISTER_OUT r1 1

18
test/asm/fcmpeqd.s
View File

@ -1,18 +0,0 @@
# REGISTER_IN fpscr 0x000c0001
# REGISTER_IN dr0 0x4014000000000000
# REGISTER_IN dr2 0xc018000000000000
# REGISTER_IN dr4 0xc018000000000000
.text
.global start
start:
# FCMP/EQ DRm,DRn
fcmp/eq dr0, dr2
movt r0
fcmp/eq dr2, dr4
movt r1
rts
nop
# REGISTER_OUT r0 0
# REGISTER_OUT r1 1

17
test/asm/fcmpeqf.s
View File

@ -1,17 +0,0 @@
# REGISTER_IN fr0 0x40400000
# REGISTER_IN fr1 0xbf800000
# REGISTER_IN fr2 0xbf800000
.text
.global start
start:
# FCMP/EQ FRm,FRn
fcmp/eq fr0, fr1
movt r0
fcmp/eq fr1, fr2
movt r1
rts
nop
# REGISTER_OUT r0 0
# REGISTER_OUT r1 1

24
test/asm/fcmpgt.s Normal file
View File

@ -0,0 +1,24 @@
test_fcmpgtd:
# REGISTER_IN fpscr 0x000c0001
# REGISTER_IN dr0 0x4014000000000000
# REGISTER_IN dr2 0xc018000000000000
fcmp/gt dr0, dr2
movt r0
fcmp/gt dr2, dr0
movt r1
rts
nop
# REGISTER_OUT r0 0
# REGISTER_OUT r1 1
test_fcmpgtf:
# REGISTER_IN fr0 0x40400000
# REGISTER_IN fr1 0xbf800000
fcmp/gt fr0, fr1
movt r0
fcmp/gt fr1, fr0
movt r1
rts
nop
# REGISTER_OUT r0 0
# REGISTER_OUT r1 1

17
test/asm/fcmpgtd.s
View File

@ -1,17 +0,0 @@
# REGISTER_IN fpscr 0x000c0001
# REGISTER_IN dr0 0x4014000000000000
# REGISTER_IN dr2 0xc018000000000000
.text
.global start
start:
# FCMP/GT DRm,DRn
fcmp/gt dr0, dr2
movt r0
fcmp/gt dr2, dr0
movt r1
rts
nop
# REGISTER_OUT r0 0
# REGISTER_OUT r1 1

16
test/asm/fcmpgtf.s
View File

@ -1,16 +0,0 @@
# REGISTER_IN fr0 0x40400000
# REGISTER_IN fr1 0xbf800000
.text
.global start
start:
# FCMP/GT FRm,FRn
fcmp/gt fr0, fr1
movt r0
fcmp/gt fr1, fr0
movt r1
rts
nop
# REGISTER_OUT r0 0
# REGISTER_OUT r1 1

16
test/asm/fdiv.s Normal file
View File

@ -0,0 +1,16 @@
test_fdivd:
# REGISTER_IN fpscr 0x000c0001
# REGISTER_IN dr0 0xbfe0000000000000
# REGISTER_IN dr2 0xc000000000000000
fdiv dr0, dr2
rts
nop
# REGISTER_OUT dr2 0x4010000000000000
test_fdivf:
# REGISTER_IN fr0 0xc0200000
# REGISTER_IN fr1 0x41200000
fdiv fr0, fr1
rts
nop
# REGISTER_OUT fr1 0xc0800000

13
test/asm/fdivd.s
View File

@ -1,13 +0,0 @@
# REGISTER_IN fpscr 0x000c0001
# REGISTER_IN dr0 0xbfe0000000000000
# REGISTER_IN dr2 0xc000000000000000
.text
.global start
start:
# FDIV DRm,DRn
fdiv dr0, dr2
rts
nop
# REGISTER_OUT dr2 0x4010000000000000

12
test/asm/fdivf.s
View File

@ -1,12 +0,0 @@
# REGISTER_IN fr0 0xc0200000
# REGISTER_IN fr1 0x41200000
.text
.global start
start:
# FDIV FRm,FRn
fdiv fr0, fr1
rts
nop
# REGISTER_OUT fr1 0xc0800000

25
test/asm/fipr.s
View File

@ -1,18 +1,13 @@
# REGISTER_IN fr4 0x3f800000
# REGISTER_IN fr5 0xc0000000
# REGISTER_IN fr6 0xc0400000
# REGISTER_IN fr7 0x40800000
# REGISTER_IN fr12 0x40800000
# REGISTER_IN fr13 0xc0400000
# REGISTER_IN fr14 0xc0000000
# REGISTER_IN fr15 0x3f800000
.text
.global start
start:
# FIPR FVm,FVn
test_fipr:
# REGISTER_IN fr4 0x3f800000
# REGISTER_IN fr5 0xc0000000
# REGISTER_IN fr6 0xc0400000
# REGISTER_IN fr7 0x40800000
# REGISTER_IN fr12 0x40800000
# REGISTER_IN fr13 0xc0400000
# REGISTER_IN fr14 0xc0000000
# REGISTER_IN fr15 0x3f800000
fipr fv4, fv12
rts
nop
# REGISTER_OUT fr15 0x41a00000
# REGISTER_OUT fr15 0x41a00000

33
test/asm/fld.s
View File

@ -1,19 +1,20 @@
# REGISTER_IN fr0 0x11111111
.text
.global start
start:
# FLDI0 FRn
test_fldi0:
# REGISTER_IN fr0 0x11111111
fldi0 fr0
# FLDI1 FRn
fldi1 fr1
# FLDS FRm,FPUL
flds fr1, fpul
# FSTS FPUL,FRn
fsts fpul, fr2
rts
nop
# REGISTER_OUT fr0 0x00000000
test_fldi1:
fldi1 fr0
rts
nop
# REGISTER_OUT fr0 0x3f800000
test_flds_fsts:
# REGISTER_IN fr0 0x3f800000
flds fr0, fpul
fsts fpul, fr1
rts
nop
# REGISTER_OUT fr0 0x00000000
# REGISTER_OUT fr1 0x3f800000
# REGISTER_OUT fr2 0x3f800000
# REGISTER_OUT fr1 0x3f800000

17
test/asm/float.s Normal file
View File

@ -0,0 +1,17 @@
test_floatd:
# REGISTER_IN fpscr 0x000c0001
# REGISTER_IN r1 0x00000004
lds r1, fpul
float fpul, dr2
rts
nop
# REGISTER_OUT dr2 0x4010000000000000
test_floatf:
# REGISTER_IN r0 0x00000002
lds r0, fpul
float fpul, fr3
rts
nop
# REGISTER_OUT fr3 0x40000000

13
test/asm/floatd.s
View File

@ -1,13 +0,0 @@
# REGISTER_IN fpscr 0x000c0001
# REGISTER_IN r1 0x00000004
.text
.global start
start:
# FLOAT FPUL,DRn
lds r1, fpul
float fpul, dr2
rts
nop
# REGISTER_OUT dr2 0x4010000000000000

11
test/asm/floatf.s
View File

@ -1,11 +0,0 @@
# REGISTER_IN r0 0x00000002
.text
.global start
start:
lds r0, fpul
float fpul, fr3
rts
nop
# REGISTER_OUT fr3 0x40000000

15
test/asm/fmac.s
View File

@ -1,13 +1,8 @@
# REGISTER_IN fr0 0xc0000000
# REGISTER_IN fr1 0xc0a00000
# REGISTER_IN fr2 0x40400000
.text
.global start
start:
# FMAC FR0,FRm,FRn
test_fmac:
# REGISTER_IN fr0 0xc0000000
# REGISTER_IN fr1 0xc0a00000
# REGISTER_IN fr2 0x40400000
fmac fr0, fr1, fr2
rts
nop
# REGISTER_OUT fr2 0x41500000
# REGISTER_OUT fr2 0x41500000

69
test/asm/fmovd.s
View File

@ -1,42 +1,39 @@
# REGISTER_IN fpscr 0x000c0001
# REGISTER_IN xd0 0x4020000000000000
# REGISTER_IN xd2 0x4024000000000000
.text
.global start
start:
# FMOV XDm,DRn PR=1
test_fmovd:
# REGISTER_IN fpscr 0x000c0001
# REGISTER_IN xd0 0x4020000000000000
# REGISTER_IN xd2 0x4024000000000000
# FMOV XDm,DRn PR=1
fmov xd0, dr0
# FMOV DRm,XDn PR=1
# FMOV DRm,XDn PR=1
fmov dr0, xd4
# FMOV XDm,XDn PR=1
# FMOV XDm,XDn PR=1
fmov xd2, xd6
# FMOV @Rm,XDn PR=1
# FMOV @Rm,XDn PR=1
mov.l .DATA_ADDR, r0
fmov @r0, xd8
# FMOV @Rm,DRn PR=1
# FMOV @Rm,DRn PR=1
mov.l .DATA_ADDR, r0
fmov @r0, dr2
# FMOV @(R0,Rm),XDn PR=1
# FMOV @(R0,Rm),XDn PR=1
mov.l .DATA_ADDR, r0
mov #8, r1
fmov @(r0, r1), xd10
# FMOV @Rm+,XDn PR=1
# FMOV @Rm+,XDn PR=1
mov.l .DATA_ADDR, r0
fmov @r0+, xd12
fmov @r0+, xd14
# FMOV XDm,@Rn PR=1
# FMOV XDm,@Rn PR=1
mov.l .DATA_OUT, r0
fmov xd0, @r0
mov.l @r0+, r2
mov.l @r0+, r3
# FMOV XDm,@-Rn PR=1
# FMOV XDm,@-Rn PR=1
mov.l .DATA_OUT, r0
add #8, r0
fmov xd2, @-r0
mov.l @r0+, r4
mov.l @r0+, r5
# FMOV XDm,@(R0,Rn) PR=1
# FMOV XDm,@(R0,Rn) PR=1
mov.l .DATA_OUT, r0
mov #8, r1
fmov xd0, @(r0, r1)
@ -45,7 +42,22 @@ start:
mov.l @r0+, r7
rts
nop
.align 4
# REGISTER_OUT dr0 0x4020000000000000
# REGISTER_OUT xd4 0x4020000000000000
# REGISTER_OUT xd6 0x4024000000000000
# REGISTER_OUT xd8 0x4028000000000000
# REGISTER_OUT dr2 0x4028000000000000
# REGISTER_OUT xd10 0x402e000000000000
# REGISTER_OUT xd12 0x4028000000000000
# REGISTER_OUT xd14 0x402e000000000000
# REGISTER_OUT r2 0x40200000
# REGISTER_OUT r3 0x00000000
# REGISTER_OUT r4 0x40240000
# REGISTER_OUT r5 0x00000000
# REGISTER_OUT r6 0x40200000
# REGISTER_OUT r7 0x00000000
.align 4
.DATA:
.long 0x40280000
.long 0x00000000
@ -55,24 +67,11 @@ start:
.long 0x0
.long 0x0
.long 0x0
.align 4
.align 4
.DATA_ADDR:
.long .DATA
.align 4
.align 4
.DATA_OUT:
.long .DATA+16
# REGISTER_OUT dr0 0x4020000000000000
# REGISTER_OUT xd4 0x4020000000000000
# REGISTER_OUT xd6 0x4024000000000000
# REGISTER_OUT xd8 0x4028000000000000
# REGISTER_OUT dr2 0x4028000000000000
# REGISTER_OUT xd10 0x402e000000000000
# REGISTER_OUT xd12 0x4028000000000000
# REGISTER_OUT xd14 0x402e000000000000
# REGISTER_OUT r2 0x40200000
# REGISTER_OUT r3 0x00000000
# REGISTER_OUT r4 0x40240000
# REGISTER_OUT r5 0x00000000
# REGISTER_OUT r6 0x40200000
# REGISTER_OUT r7 0x00000000

47
test/asm/fmovf.s
View File

@ -1,55 +1,54 @@
# REGISTER_IN fr0 0x40400000
.text
.global start
start:
# FMOV FRm,FRn
test_fmovf:
# REGISTER_IN fr0 0x40400000
# FMOV FRm,FRn
fmov fr0, fr1
# FMOV.S @Rm,FRn
# FMOV.S @Rm,FRn
mov.l .DATA_ADDR, r0
fmov.s @r0, fr2
# FMOV.S @(R0,Rm),FRn
# FMOV.S @(R0,Rm),FRn
mov.l .DATA_ADDR, r0
mov #4, r1
fmov.s @(r0, r1), fr3
# FMOV.S @Rm+,FRn
# FMOV.S @Rm+,FRn
mov.l .DATA_ADDR, r0
fmov.s @r0+, fr4
fmov.s @r0+, fr5
# FMOV.S FRm,@Rn
# FMOV.S FRm,@Rn
mov.l .DATA_OUT, r0
fmov.s fr0, @r0
mov.l @r0, r2
# FMOV.S FRm,@-Rn
# FMOV.S FRm,@-Rn
mov.l .DATA_OUT, r0
add #8, r0
fmov.s fr2, @-r0
mov.l @r0, r3
# FMOV.S FRm,@(R0,Rn)
# FMOV.S FRm,@(R0,Rn)
mov.l .DATA_OUT, r0
mov #4, r1
fmov.s fr0, @(r0, r1)
mov.l @(r0, r1), r4
rts
nop
.align 4
# REGISTER_OUT fr1 0x40400000
# REGISTER_OUT fr2 0x40a00000
# REGISTER_OUT fr3 0x40e00000
# REGISTER_OUT fr4 0x40a00000
# REGISTER_OUT fr5 0x40e00000
# REGISTER_OUT r2 0x40400000
# REGISTER_OUT r3 0x40a00000
# REGISTER_OUT r4 0x40400000
.align 4
.DATA:
.long 0x40a00000
.long 0x40e00000
.long 0x0
.long 0x0
.align 4
.align 4
.DATA_ADDR:
.long .DATA
.align 4
.align 4
.DATA_OUT:
.long .DATA+8
# REGISTER_OUT fr1 0x40400000
# REGISTER_OUT fr2 0x40a00000
# REGISTER_OUT fr3 0x40e00000
# REGISTER_OUT fr4 0x40a00000
# REGISTER_OUT fr5 0x40e00000
# REGISTER_OUT r2 0x40400000
# REGISTER_OUT r3 0x40a00000
# REGISTER_OUT r4 0x40400000

87
test/asm/fmovsz.s
View File

@ -1,63 +1,60 @@
# REGISTER_IN fpscr 0x00140001
# REGISTER_IN dr0 0x3f80000040000000
.text
.global start
start:
# FMOV DRm,DRn SZ=1
test_fmovsz:
# REGISTER_IN fpscr 0x00140001
# REGISTER_IN dr0 0x3f80000040000000
# FMOV DRm,DRn SZ=1
fmov dr0, dr2
# FMOV @Rm,DRn SZ=1
# FMOV @Rm,DRn SZ=1
mov.l .DATA_ADDR, r0
fmov @r0, dr4
# FMOV @Rm,XDn SZ=1
# FMOV @Rm,XDn SZ=1
mov.l .DATA_ADDR, r0
fmov @r0, xd2
# FMOV @(R0,Rm),DRn SZ=1
# FMOV @(R0,Rm),DRn SZ=1
mov.l .DATA_ADDR, r0
mov #4, r1
fmov @(r0, r1), dr6
# FMOV @(R0,Rm),XDn SZ=1
# FMOV @(R0,Rm),XDn SZ=1
mov.l .DATA_ADDR, r0
mov #8, r1
fmov @(r0, r1), xd4
# FMOV @Rm+,DRn SZ=1
# FMOV @Rm+,DRn SZ=1
mov.l .DATA_ADDR, r0
fmov @r0+, dr8
fmov @r0+, dr10
# FMOV @Rm+,XDn SZ=1
# FMOV @Rm+,XDn SZ=1
mov.l .DATA_ADDR, r0
fmov @r0+, xd6
fmov @r0+, xd8
# FMOV DRm,@Rn SZ=1
# FMOV DRm,@Rn SZ=1
mov.l .DATA_OUT, r0
fmov dr4, @r0
mov.l @r0+, r2
mov.l @r0+, r3
# FMOV XDm,@Rn SZ=1
# FMOV XDm,@Rn SZ=1
mov.l .DATA_OUT, r0
fmov xd4, @r0
mov.l @r0+, r4
mov.l @r0+, r5
# FMOV DRm,@-Rn SZ=1
# FMOV DRm,@-Rn SZ=1
mov.l .DATA_OUT, r0
add #8, r0
fmov dr6, @-r0
mov.l @r0+, r6
mov.l @r0+, r7
# FMOV XDm,@-Rn SZ=1
# FMOV XDm,@-Rn SZ=1
mov.l .DATA_OUT, r0
add #8, r0
fmov xd6, @-r0
mov.l @r0+, r8
mov.l @r0+, r9
# FMOV DRm,@(R0,Rn) SZ=1
# FMOV DRm,@(R0,Rn) SZ=1
mov.l .DATA_OUT, r0
mov #8, r1
fmov dr0, @(r0, r1)
add #8, r0
mov.l @r0+, r10
mov.l @r0+, r11
# FMOV XDm,@(R0,Rn) SZ=1
# FMOV XDm,@(R0,Rn) SZ=1
mov.l .DATA_OUT, r0
mov #8, r1
fmov xd2, @(r0, r1)
@ -66,7 +63,29 @@ start:
mov.l @r0+, r13
rts
nop
.align 4
# REGISTER_OUT dr2 0x3f80000040000000
# REGISTER_OUT dr4 0x4080000040400000
# REGISTER_OUT xd2 0x4080000040400000
# REGISTER_OUT dr6 0x4110000040800000
# REGISTER_OUT xd4 0x4120000041100000
# REGISTER_OUT dr8 0x4080000040400000
# REGISTER_OUT dr10 0x4120000041100000
# REGISTER_OUT xd6 0x4080000040400000
# REGISTER_OUT xd8 0x4120000041100000
# REGISTER_OUT r2 0x40400000
# REGISTER_OUT r3 0x40800000
# REGISTER_OUT r4 0x41100000
# REGISTER_OUT r5 0x41200000
# REGISTER_OUT r6 0x40800000
# REGISTER_OUT r7 0x41100000
# REGISTER_OUT r8 0x40400000
# REGISTER_OUT r9 0x40800000
# REGISTER_OUT r10 0x40000000
# REGISTER_OUT r11 0x3f800000
# REGISTER_OUT r12 0x40400000
# REGISTER_OUT r13 0x40800000
.align 4
.DATA:
.long 0x40400000
.long 0x40800000
@ -76,31 +95,11 @@ start:
.long 0x0
.long 0x0
.long 0x0
.align 4
.align 4
.DATA_ADDR:
.long .DATA
.align 4
.align 4
.DATA_OUT:
.long .DATA+16
# REGISTER_OUT dr2 0x3f80000040000000
# REGISTER_OUT dr4 0x4080000040400000
# REGISTER_OUT xd2 0x4080000040400000
# REGISTER_OUT dr6 0x4110000040800000
# REGISTER_OUT xd4 0x4120000041100000
# REGISTER_OUT dr8 0x4080000040400000
# REGISTER_OUT dr10 0x4120000041100000
# REGISTER_OUT xd6 0x4080000040400000
# REGISTER_OUT xd8 0x4120000041100000
# REGISTER_OUT r2 0x40400000
# REGISTER_OUT r3 0x40800000
# REGISTER_OUT r4 0x41100000
# REGISTER_OUT r5 0x41200000
# REGISTER_OUT r6 0x40800000
# REGISTER_OUT r7 0x41100000
# REGISTER_OUT r8 0x40400000
# REGISTER_OUT r9 0x40800000
# REGISTER_OUT r10 0x40000000
# REGISTER_OUT r11 0x3f800000
# REGISTER_OUT r12 0x40400000
# REGISTER_OUT r13 0x40800000

17
test/asm/fmul.s Normal file
View File

@ -0,0 +1,17 @@
test_fmuld:
# REGISTER_IN fpscr 0x000c0001
# REGISTER_IN dr0 0x4008000000000000
# REGISTER_IN dr2 0xc01c000000000000
fmul dr0, dr2
rts
nop
# REGISTER_OUT dr2 0xc035000000000000
test_fmulf:
# REGISTER_IN fr0 0x40200000
# REGISTER_IN fr1 0x40000000
fmul fr0, fr1
rts
nop
# REGISTER_OUT fr1 0x40a00000

13
test/asm/fmuld.s
View File

@ -1,13 +0,0 @@
# REGISTER_IN fpscr 0x000c0001
# REGISTER_IN dr0 0x4008000000000000
# REGISTER_IN dr2 0xc01c000000000000
.text
.global start
start:
# FMUL DRm,DRn
fmul dr0, dr2
rts
nop
# REGISTER_OUT dr2 0xc035000000000000

12
test/asm/fmulf.s
View File

@ -1,12 +0,0 @@
# REGISTER_IN fr0 0x40200000
# REGISTER_IN fr1 0x40000000
.text
.global start
start:
# FMUL FRm,FRn
fmul fr0, fr1
rts
nop
# REGISTER_OUT fr1 0x40a00000

15
test/asm/fneg.s Normal file
View File

@ -0,0 +1,15 @@
test_fnegd:
# REGISTER_IN fpscr 0x000c0001
# REGISTER_IN dr0 0x4014000000000000
fneg dr0
rts
nop
# REGISTER_OUT dr0 0xc014000000000000
test_fnegf:
# REGISTER_IN fr0 0x40800000
fneg fr0
rts
nop
# REGISTER_OUT fr0 0xc0800000

12
test/asm/fnegd.s
View File

@ -1,12 +0,0 @@
# REGISTER_IN fpscr 0x000c0001
# REGISTER_IN dr0 0x4014000000000000
.text
.global start
start:
# FNEG DRn
fneg dr0
rts
nop
# REGISTER_OUT dr0 0xc014000000000000

11
test/asm/fnegf.s
View File

@ -1,11 +0,0 @@
# REGISTER_IN fr0 0x40800000
.text
.global start
start:
# FNEG FRn
fneg fr0
rts
nop
# REGISTER_OUT fr0 0xc0800000

23
test/asm/frchg.s
View File

@ -1,13 +1,10 @@
.text
.global start
start:
mov.l .L2, r0
# store 13.0 in fr0
test_frchg:
# REGISTER_IN fr0 0x41500000
sts fpscr, r1
fmov.s @r0, fr0
# swap fp banks and move fr0 to r3
frchg
sts fpscr, r2
mov.l .L2, r0
fmov.s fr0, @r0
mov.l @r0, r3
# swap again and move fr0 to r4
@ -16,14 +13,14 @@ start:
mov.l @r0, r4
rts
nop
.align 4
# REGISTER_OUT r1 0x00040001
# REGISTER_OUT r2 0x00240001
# REGISTER_OUT r3 0x0
# REGISTER_OUT r4 0x41500000
.align 4
.L1:
.long 0x41500000
.long 0x0
.align 4
.L2:
.long .L1
# REGISTER_OUT r1 0x00040001
# REGISTER_OUT r2 0x00240001
# REGISTER_OUT r3 0x0
# REGISTER_OUT r4 0x41500000

13
test/asm/fsca.s
View File

@ -1,13 +1,8 @@
# REGISTER_IN r0 16384
.text
.global start
start:
# FSCA FPUL,DRn
test_fsca:
# REGISTER_IN r0 16384
lds r0, fpul
fsca fpul, dr2
rts
nop
# REGISTER_OUT fr2 0x3f800000
# REGISTER_OUT fr3 0xb33bbd2e
# REGISTER_OUT fr2 0x3f800000
# REGISTER_OUT fr3 0xb33bbd2e

9
test/asm/fschg.s
View File

@ -1,11 +1,8 @@
.text
.global start
start:
test_fschg:
sts fpscr, r0
fschg
sts fpscr, r1
rts
nop
# REGISTER_OUT r0 0x00040001
# REGISTER_OUT r1 0x00140001
# REGISTER_OUT r0 0x00040001
# REGISTER_OUT r1 0x00140001

15
test/asm/fsqrt.s Normal file
View File

@ -0,0 +1,15 @@
test_fsqrtd:
# REGISTER_IN fpscr 0x000c0001
# REGISTER_IN dr0 0x4010000000000000
fsqrt dr0
rts
nop
# REGISTER_OUT dr0 0x4000000000000000
test_fsqrtf:
# REGISTER_IN fr0 0x40800000
fsqrt fr0
rts
nop
# REGISTER_OUT fr0 0x40000000

11
test/asm/fsqrtd.s
View File

@ -1,11 +0,0 @@
# REGISTER_IN fpscr 0x000c0001
# REGISTER_IN dr0 0x4010000000000000
.text
.global start
start:
fsqrt dr0
rts
nop
# REGISTER_OUT dr0 0x4000000000000000

10
test/asm/fsqrtf.s
View File

@ -1,10 +0,0 @@
# REGISTER_IN fr0 0x40800000
.text
.global start
start:
fsqrt fr0
rts
nop
# REGISTER_OUT fr0 0x40000000

10
test/asm/fsrra.s
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@ -1,10 +1,6 @@
# REGISTER_IN fr0 0x40800000
.text
.global start
start:
test_fsrra:
# REGISTER_IN fr0 0x40800000
fsrra fr0
rts
nop
# REGISTER_OUT fr0 0x3f000000
# REGISTER_OUT fr0 0x3f000000

17
test/asm/fsub.s Normal file
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@ -0,0 +1,17 @@
test_fsubd:
# REGISTER_IN fpscr 0x000c0001
# REGISTER_IN dr0 0xc01c000000000000
# REGISTER_IN dr2 0xc010000000000000
fsub dr0, dr2
rts
nop
# REGISTER_OUT dr2 0x4008000000000000
test_fsubf:
# REGISTER_IN fr0 0x40400000
# REGISTER_IN fr1 0xbf800000
fsub fr0, fr1
rts
nop
# REGISTER_OUT fr1 0xc0800000

13
test/asm/fsubd.s
View File

@ -1,13 +0,0 @@
# REGISTER_IN fpscr 0x000c0001
# REGISTER_IN dr0 0xc01c000000000000
# REGISTER_IN dr2 0xc010000000000000
.text
.global start
start:
# FSUB DRm,DRn
fsub dr0, dr2
rts
nop
# REGISTER_OUT dr2 0x4008000000000000

12
test/asm/fsubf.s
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@ -1,12 +0,0 @@
# REGISTER_IN fr0 0x40400000
# REGISTER_IN fr1 0xbf800000
.text
.global start
start:
# FSUB FRm,FRn
fsub fr0, fr1
rts
nop
# REGISTER_OUT fr1 0xc0800000

17
test/asm/ftrc.s Normal file
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@ -0,0 +1,17 @@
test_ftrcd:
# REGISTER_IN fpscr 0x000c0001
# REGISTER_IN dr0 0xc012cccccccccccd
ftrc dr0, fpul
sts fpul, r0
rts
nop
# REGISTER_OUT r0 0xfffffffc
test_ftrcf:
# REGISTER_IN fr0 0xc0966666
ftrc fr0, fpul
sts fpul, r0
rts
nop
# REGISTER_OUT r0 0xfffffffc

13
test/asm/ftrcd.s
View File

@ -1,13 +0,0 @@
# REGISTER_IN fpscr 0x000c0001
# REGISTER_IN dr0 0xc012cccccccccccd
.text
.global start
start:
# FTRC DRm,FPUL
ftrc dr0, fpul
sts fpul, r0
rts
nop
# REGISTER_OUT r0 0xfffffffc

12
test/asm/ftrcf.s
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@ -1,12 +0,0 @@
# REGISTER_IN fr0 0xc0966666
.text
.global start
start:
# FTRC FRm,FPUL
ftrc fr0, fpul
sts fpul, r0
rts
nop
# REGISTER_OUT r0 0xfffffffc

64
test/asm/ftrv.s
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@ -1,38 +1,32 @@
# REGISTER_IN xf0 0x3f800000
# REGISTER_IN xf1 0x00000000
# REGISTER_IN xf2 0x00000000
# REGISTER_IN xf3 0x00000000
# REGISTER_IN xf4 0x00000000
# REGISTER_IN xf5 0x40000000
# REGISTER_IN xf6 0x00000000
# REGISTER_IN xf7 0x00000000
# REGISTER_IN xf8 0x00000000
# REGISTER_IN xf9 0x00000000
# REGISTER_IN xf10 0x3f800000
# REGISTER_IN xf11 0x00000000
# REGISTER_IN xf12 0x00000000
# REGISTER_IN xf13 0x00000000
# REGISTER_IN xf14 0x00000000
# REGISTER_IN xf15 0x3f800000
# REGISTER_IN fr4 0x40000000
# REGISTER_IN fr5 0x40800000
# REGISTER_IN fr6 0x41000000
# REGISTER_IN fr7 0x00000000
.text
.global start
start:
# FTRV XMTRX,FVn
# XF0 XF4 XF8 XF12 FR0 XF0 * FR0 + XF4 * FR1 + XF8 * FR2 + XF12 * FR3
# XF1 XF5 XF9 XF13 * FR1 = XF1 * FR0 + XF5 * FR1 + XF9 * FR2 + XF13 * FR3
# XF2 XF6 XF10 XF14 FR2 XF2 * FR0 + XF6 * FR1 + XF10 * FR2 + XF14 * FR3
# XF3 XF7 XF11 XF15 FR3 XF3 * FR0 + XF7 * FR1 + XF11 * FR2 + XF15 * FR3
test_ftrv:
# REGISTER_IN xf0 0x3f800000
# REGISTER_IN xf1 0x00000000
# REGISTER_IN xf2 0x00000000
# REGISTER_IN xf3 0x00000000
# REGISTER_IN xf4 0x00000000
# REGISTER_IN xf5 0x40000000
# REGISTER_IN xf6 0x00000000
# REGISTER_IN xf7 0x00000000
# REGISTER_IN xf8 0x00000000
# REGISTER_IN xf9 0x00000000
# REGISTER_IN xf10 0x3f800000
# REGISTER_IN xf11 0x00000000
# REGISTER_IN xf12 0x00000000
# REGISTER_IN xf13 0x00000000
# REGISTER_IN xf14 0x00000000
# REGISTER_IN xf15 0x3f800000
# REGISTER_IN fr4 0x40000000
# REGISTER_IN fr5 0x40800000
# REGISTER_IN fr6 0x41000000
# REGISTER_IN fr7 0x00000000
# XF0 XF4 XF8 XF12 FR0 XF0 * FR0 + XF4 * FR1 + XF8 * FR2 + XF12 * FR3
# XF1 XF5 XF9 XF13 * FR1 = XF1 * FR0 + XF5 * FR1 + XF9 * FR2 + XF13 * FR3
# XF2 XF6 XF10 XF14 FR2 XF2 * FR0 + XF6 * FR1 + XF10 * FR2 + XF14 * FR3
# XF3 XF7 XF11 XF15 FR3 XF3 * FR0 + XF7 * FR1 + XF11 * FR2 + XF15 * FR3
ftrv xmtrx, fv4
rts
nop
# REGISTER_OUT fr4 0x40000000
# REGISTER_OUT fr5 0x41000000
# REGISTER_OUT fr6 0x41000000
# REGISTER_OUT fr7 0x00000000
# REGISTER_OUT fr4 0x40000000
# REGISTER_OUT fr5 0x41000000
# REGISTER_OUT fr6 0x41000000
# REGISTER_OUT fr7 0x00000000

25
test/asm/jmp.s
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@ -1,20 +1,15 @@
# REGISTER_IN r1 0
.little
.text
.global start
start:
mov.l .L3, r0
test_jmp:
# REGISTER_IN r1 0
mov.l .L1, r0
jmp @r0
nop
mov #1, r1
.align 1
.global _foobar
rts
nop
_foobar:
rts
add #13, r1
.L3:
.align 2
.long _foobar
mov #13, r1
# REGISTER_OUT r1 13
# REGISTER_OUT r1 13
.align 4
.L1:
.long _foobar

20
test/asm/jsr.s
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@ -1,24 +1,18 @@
# REGISTER_IN r1 0
.little
.text
.global start
start:
test_jsr:
# REGISTER_IN r1 0
sts.l pr, @-r15
mov.l .L3, r0
mov.l .L1, r0
jsr @r0
add #1, r1
add #3, r1
lds.l @r15+, pr
rts
nop
.align 1
.global _foobar
_foobar:
rts
add #9, r1
.L3:
.align 2
.long _foobar
# REGISTER_OUT r1 13
# REGISTER_OUT r1 13
.align 4
.L1:
.long _foobar

110
test/asm/ldc.s
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@ -1,81 +1,93 @@
.text
.global start
start:
# LDC Rm,SR
# STC SR,Rn
test_ldc_stc_sr:
# write control value before swap
mov #1, r2
mov #13, r2
# swap banks
mov.l .ALT_SR, r0
ldc r0, sr
# overwrite control value to test swap
mov #99, r2
# write sr to mem
stc sr, r2
stc sr, r1
mov.l .DATA_ADDR, r0
mov.l r2, @r0
mov.l r1, @r0
# swap back again
mov.l .DEFAULT_SR, r0
ldc r0, sr
# read sr from mem
mov.l .DATA_ADDR, r0
mov.l @r0, r3
# LDCRBANK Rm,Rn_BANK
# STCRBANK Rm_BANK,Rn
mov #1, r0
ldc r0, r4_bank
mov #99, r4
stc r4_bank, r4
# LDC Rm,GBR
# STC GBR,Rn
mov #2, r0
rts
nop
# REGISTER_OUT r2 13
# REGISTER_OUT r3 0x500000f0
test_ldc_stc_rbank:
# REGISTER_IN r0 13
ldc r0, r1_bank
mov #99, r1
stc r1_bank, r1
rts
nop
# REGISTER_OUT r1 13
test_ldc_stc_gbr:
# REGISTER_IN r0 13
ldc r0, gbr
stc gbr, r5
# LDC Rm,VBR
# STC VBR,Rn
mov #3, r0
stc gbr, r1
rts
nop
# REGISTER_OUT r1 13
test_ldc_stc_vbr:
# REGISTER_IN r0 13
ldc r0, vbr
stc vbr, r6
# LDC Rm,SSR
# STC SSR,Rn
mov #4, r0
stc vbr, r1
rts
nop
# REGISTER_OUT r1 13
test_ldc_stc_ssr:
# REGISTER_IN r0 13
ldc r0, ssr
stc ssr, r7
# LDC Rm,SPC
# STC SPC,Rn
mov #5, r0
stc ssr, r1
rts
nop
# REGISTER_OUT r1 13
test_ldc_stc_spc:
# REGISTER_IN r0 13
ldc r0, spc
stc spc, r8
# STC SGR,Rn
stc spc, r1
rts
nop
# REGISTER_OUT r1 13
# TODO
# STC SGR,Rn
# mov r0, r15
# trapa
# stc sgr, r9
# LDC Rm,DBR
# STC DBR,Rn
mov #7, r0
test_ldc_stc_dbr:
# REGISTER_IN r0 13
ldc r0, dbr
stc dbr, r10
rts
stc dbr, r1
rts
nop
.align 4
# REGISTER_OUT r1 13
.align 4
.DATA:
.long 0x0
.align 4
.align 4
.DATA_ADDR:
.long .DATA
.align 4
.align 4
.ALT_SR:
.long 0x500000f0
.align 4
.align 4
.DEFAULT_SR:
.long 0x700000f0
# REGISTER_OUT r2 1
# REGISTER_OUT r3 0x500000f0
# REGISTER_OUT r4 1
# REGISTER_OUT r5 2
# REGISTER_OUT r6 3
# REGISTER_OUT r7 4
# REGISTER_OUT r8 5
# REGISTER_OUT r10 7

248
test/asm/ldcl.s
View File

@ -1,142 +1,150 @@
.text
.global start
start:
# LDC.L @Rm+,SR
# STC.L SR,@-Rn
test_ldcl_stcl_sr:
# write control value before swap
mov #1, r2
mov #13, r2
# swap banks
mov.l .ALT_SR, r0
ldc.l @r0+, sr
# overwrite control value to test swap
mov #99, r2
# write sr to mem
mov.l .OUT_PLUS4, r1
mov.l .DATA_ADDR, r1
add #4, r1
stc.l sr, @-r1
mov.l @r1, r3
# r0 in alt bank should have been post-incremented to 4
cmp/eq #4, r0
movt r0
add r0, r3
# r1 should been pre-decremented by 4
mov.l .OUT, r0
cmp/eq r1, r0
movt r0
add r0, r3
# write back out
mov.l .OUT, r0
mov.l r3, @r0
# swap back again
mov.l .DEFAULT_SR, r0
ldc.l @r0+, sr
mov.l .DEFAULT_SR, r3
ldc.l @r3+, sr
# read result from mem
mov.l .OUT, r0
mov.l .DATA_ADDR, r0
mov.l @r0, r3
# LDC.L @Rm+,Rn_BANK
# STC.L Rm_BANK,@-Rn
mov.l .OUT, r0
mov #1, r1
mov.l r1, @r0
mov.l .OUT_PLUS8, r1
ldc.l @r0+, r4_bank
mov #99, r4
stc.l r4_bank, @-r1
mov.l @r1, r4
cmp/eq r0, r1
movt r0
add r0, r4
# LDC.L @Rm+,GBR
# STC.L GBR,@-Rn
mov.l .OUT, r0
mov #2, r1
mov.l r1, @r0
mov.l .OUT_PLUS8, r1
ldc.l @r0+, gbr
stc.l gbr, @-r1
mov.l @r1, r5
cmp/eq r0, r1
movt r0
add r0, r5
# LDC.L @Rm+,VBR
# STC.L VBR,@-Rn
mov.l .OUT, r0
mov #3, r1
mov.l r1, @r0
mov.l .OUT_PLUS8, r1
ldc.l @r0+, vbr
stc.l vbr, @-r1
mov.l @r1, r6
cmp/eq r0, r1
movt r0
add r0, r6
# LDC.L @Rm+,SSR
# STC.L SSR,@-Rn
mov.l .OUT, r0
mov #4, r1
mov.l r1, @r0
mov.l .OUT_PLUS8, r1
ldc.l @r0+, ssr
stc.l ssr, @-r1
mov.l @r1, r7
cmp/eq r0, r1
movt r0
add r0, r7
# LDC.L @Rm+,SPC
# STC.L SPC,@-Rn
mov.l .OUT, r0
mov #5, r1
mov.l r1, @r0
mov.l .OUT_PLUS8, r1
ldc.l @r0+, spc
stc.l spc, @-r1
mov.l @r1, r8
cmp/eq r0, r1
movt r0
add r0, r8
# STC.L SGR,@-Rn
# TODO
# LDC.L @Rm+,DBR
# STC.L DBR,@-Rn
mov.l .OUT, r0
mov #7, r1
mov.l r1, @r0
mov.l .OUT_PLUS8, r1
ldc.l @r0+, dbr
stc.l dbr, @-r1
mov.l @r1, r10
cmp/eq r0, r1
movt r0
add r0, r10
rts
# r0 in alt bank should have been post-incremented to 4
stc r0_bank, r4
# r1 in alt bank should have been pre-decremented by 4
mov.l .DATA_ADDR, r5
stc r1_bank, r6
cmp/eq r6, r5
movt r5
rts
nop
.align 4
# REGISTER_OUT r2 13
# REGISTER_OUT r3 0x500000f0
# REGISTER_OUT r4 4
# REGISTER_OUT r5 1
test_ldcl_stcl_rbank:
# REGISTER_IN r0 13
mov.l .DATA_ADDR, r1
mov.l r0, @r1
ldc.l @r1+, r3_bank
mov #99, r3
mov.l .DATA_ADDR, r2
add #8, r2
stc.l r3_bank, @-r2
cmp/eq r1, r2
movt r4
mov.l @r2, r5
rts
nop
# REGISTER_OUT r4 1
# REGISTER_OUT r5 13
test_ldcl_stcl_gbr:
# REGISTER_IN r0 13
mov.l .DATA_ADDR, r1
mov.l r0, @r1
mov.l .DATA_ADDR, r2
add #8, r2
ldc.l @r1+, gbr
stc.l gbr, @-r2
cmp/eq r2, r1
movt r3
mov.l @r2, r4
rts
nop
# REGISTER_OUT r3 1
# REGISTER_OUT r4 13
test_ldcl_stcl_vbr:
# REGISTER_IN r0 13
mov.l .DATA_ADDR, r1
mov.l r0, @r1
mov.l .DATA_ADDR, r2
add #8, r2
ldc.l @r1+, vbr
stc.l vbr, @-r2
cmp/eq r2, r1
movt r3
mov.l @r2, r4
rts
nop
# REGISTER_OUT r3 1
# REGISTER_OUT r4 13
test_ldcl_stcl_ssr:
# REGISTER_IN r0 13
mov.l .DATA_ADDR, r1
mov.l r0, @r1
mov.l .DATA_ADDR, r2
add #8, r2
ldc.l @r1+, ssr
stc.l ssr, @-r2
cmp/eq r2, r1
movt r3
mov.l @r2, r4
rts
nop
# REGISTER_OUT r3 1
# REGISTER_OUT r4 13
test_ldcl_stcl_spc:
# REGISTER_IN r0 13
mov.l .DATA_ADDR, r1
mov.l r0, @r1
mov.l .DATA_ADDR, r2
add #8, r2
ldc.l @r1+, spc
stc.l spc, @-r2
cmp/eq r2, r1
movt r3
mov.l @r2, r4
rts
nop
# REGISTER_OUT r3 1
# REGISTER_OUT r4 13
# TODO
# STC.L SGR,@-Rn
test_ldcl_stcl_dbr:
# REGISTER_IN r0 13
mov.l .DATA_ADDR, r1
mov.l r0, @r1
mov.l .DATA_ADDR, r2
add #8, r2
ldc.l @r1+, dbr
stc.l dbr, @-r2
cmp/eq r2, r1
movt r3
mov.l @r2, r4
rts
nop
# REGISTER_OUT r3 1
# REGISTER_OUT r4 13
.align 4
.DATA:
.long 0x500000f0
.long 0x700000f0
.long 0x0
.long 0x0
.align 4
.OUT:
.align 4
.DATA_ADDR:
.long .DATA+8
.align 4
.OUT_PLUS4:
.long .DATA+12
.align 4
.OUT_PLUS8:
.long .DATA+16
.align 4
.align 4
.ALT_SR:
.long .DATA
.align 4
.align 4
.DEFAULT_SR:
.long .DATA+4
.align 4
# REGISTER_OUT r2 1
# REGISTER_OUT r3 0x500000f2
# REGISTER_OUT r4 2
# REGISTER_OUT r5 3
# REGISTER_OUT r6 4
# REGISTER_OUT r7 5
# REGISTER_OUT r8 6
# REGISTER_OUT r10 8

65
test/asm/lds.s
View File

@ -1,37 +1,42 @@
# REGISTER_IN r0 13
# REGISTER_IN r1 0xffd40001
.text
.global start
start:
# LDS Rm,MACH
# STS MACH,Rn
test_lds_sts_mach:
# REGISTER_IN r0 13
lds r0, mach
sts mach, r2
# LDS Rm,MACL
# STS MACL,Rn
sts mach, r1
rts
nop
# REGISTER_OUT r1 13
test_lds_sts_macl:
# REGISTER_IN r0 13
lds r0, macl
sts macl, r3
# LDS Rm,PR
# STS PR,Rn
sts pr, r5
sts macl, r1
rts
nop
# REGISTER_OUT r1 13
test_lds_sts_pr:
# REGISTER_IN r0 13
sts pr, r2
lds r0, pr
sts pr, r4
sts pr, r1
# restore
lds r5, pr
# LDS Rm,FPSCR
# STS FPSCR,Rn
lds r1, fpscr
sts fpscr, r5
# LDS Rm,FPUL
# STS FPUL,Rn
lds r2, pr
rts
nop
# REGISTER_OUT r1 13
test_lds_sts_fpscr:
# REGISTER_IN r0 0xffd40001
lds r0, fpscr
sts fpscr, r1
rts
nop
# REGISTER_OUT r1 0x00140001
test_lds_sts_fpul:
# REGISTER_IN r0 13
lds r0, fpul
sts fpul, r6
sts fpul, r1
rts
nop
# REGISTER_OUT r2 13
# REGISTER_OUT r3 13
# REGISTER_OUT r4 13
# REGISTER_OUT r5 0x00140001
# REGISTER_OUT r6 13
# REGISTER_OUT r1 13

166
test/asm/ldsl.s
View File

@ -1,87 +1,91 @@
.text
.global start
start:
# LDS.L @Rm+,MACH
# STS.L MACH,@-Rn
mov.l .OUT, r0
mov.l .OUT_PLUS8, r1
mov #0xa, r2
mov.l r2, @r0
lds.l @r0+, mach
sts.l mach, @-r1
mov.l @r1, r3
cmp/eq r0, r1
movt r0
add r0, r3
# LDS.L @Rm+,MACL
# STS.L MACL,@-Rn
mov.l .OUT, r0
mov.l .OUT_PLUS8, r1
mov #0xb, r2
mov.l r2, @r0
lds.l @r0+, macl
sts.l macl, @-r1
mov.l @r1, r4
cmp/eq r0, r1
movt r0
add r0, r4
# LDS.L @Rm+,PR
# STS.L PR,@-Rn
sts pr, r6
mov.l .OUT, r0
mov.l .OUT_PLUS8, r1
mov #0xc, r2
mov.l r2, @r0
lds.l @r0+, pr
sts.l pr, @-r1
mov.l @r1, r5
cmp/eq r0, r1
movt r0
add r0, r5
# restore pr
lds r6, pr
# LDS.L @Rm+,FPSCR
# STS.L FPSCR,@-Rn
mov.l .OUT, r0
mov.l .OUT_PLUS8, r1
mov.l .FSPCR_MASKED_BITS_SET, r2
mov.l r2, @r0
lds.l @r0+, fpscr
sts.l fpscr, @-r1
mov.l @r1, r6
cmp/eq r0, r1
movt r0
add r0, r6
# LDS.L @Rm+,FPUL
# STS.L FPSCR,@-Rn
mov.l .OUT, r0
mov.l .OUT_PLUS8, r1
mov #0xd, r2
mov.l r2, @r0
lds.l @r0+, FPUL
sts.l FPUL, @-r1
mov.l @r1, r7
cmp/eq r0, r1
movt r0
add r0, r7
test_ldsl_stsl_mach:
# REGISTER_IN r0 13
mov.l .DATA_ADDR, r1
mov.l .DATA_ADDR, r2
add #8, r2
mov.l r0, @r1
lds.l @r1+, mach
sts.l mach, @-r2
cmp/eq r2, r1
movt r3
mov.l @r2, r4
rts
nop
.align 4
# REGISTER_OUT r3 1
# REGISTER_OUT r4 13
test_ldsl_stsl_macl:
# REGISTER_IN r0 13
mov.l .DATA_ADDR, r1
mov.l .DATA_ADDR, r2
add #8, r2
mov.l r0, @r1
lds.l @r1+, macl
sts.l macl, @-r2
cmp/eq r2, r1
movt r3
mov.l @r2, r4
rts
nop
# REGISTER_OUT r3 1
# REGISTER_OUT r4 13
test_ldsl_stsl_pr:
# REGISTER_IN r0 13
sts pr, r5
mov.l .DATA_ADDR, r1
mov.l .DATA_ADDR, r2
add #8, r2
mov.l r0, @r1
lds.l @r1+, pr
sts.l pr, @-r2
cmp/eq r2, r1
movt r3
mov.l @r2, r4
# restore pr
lds r5, pr
rts
nop
# REGISTER_OUT r3 1
# REGISTER_OUT r4 13
test_ldsl_stsl_fpscr:
# REGISTER_IN r0 0xffd40001
mov.l .DATA_ADDR, r1
mov.l .DATA_ADDR, r2
add #8, r2
mov.l r0, @r1
lds.l @r1+, fpscr
sts.l fpscr, @-r2
cmp/eq r2, r1
movt r3
mov.l @r2, r4
rts
nop
# REGISTER_OUT r3 1
# REGISTER_OUT r4 0x00140001
test_ldsl_stsl_fpul:
# REGISTER_IN r0 13
mov.l .DATA_ADDR, r1
mov.l .DATA_ADDR, r2
add #8, r2
mov.l r0, @r1
lds.l @r1+, fpul
sts.l fpul, @-r2
cmp/eq r2, r1
movt r3
mov.l @r2, r4
rts
nop
# REGISTER_OUT r3 1
# REGISTER_OUT r4 13
.align 4
.DATA:
.long 0
.long 0
.align 4
.OUT:
.long .DATA
.align 4
.OUT_PLUS8:
.long .DATA+8
.align 4
.FSPCR_MASKED_BITS_SET:
.long 0xffd40001
# REGISTER_OUT r3 0xb
# REGISTER_OUT r4 0xc
# REGISTER_OUT r5 0xd
# REGISTER_OUT r6 0x00140002
# REGISTER_OUT r7 0xe
.align 4
.DATA_ADDR:
.long .DATA

13
test/asm/mova.s
View File

@ -1,14 +1,11 @@
.little
.text
.global start
start:
# MOVA @(disp8,PC),R0
test_mova:
mova .L1, r0
mov.l @r0, r2
mov.l @r0, r1
rts
nop
.align 4
.align 4
.L1:
.long -24
# REGISTER_OUT r2 -24
# REGISTER_OUT r1 -24

111
test/asm/movb.s
View File

@ -1,62 +1,63 @@
.little
.text
.global start
start:
# MOV.B Rm,@Rn
# MOV.B @Rm,Rn
mov.l .L2, r0
mov.b @r0, r2
add r2, r2
mov.b r2, @r0
mov.b @r0, r2
# MOV.B Rm,@-Rn
# MOV.B @Rm+,Rn
mov.l .L2, r0
add #1, r0
mov.b @r0+, r3
add r3, r3
mov.b r3, @-r0
mov.b @r0, r3
# MOV.B R0,@(disp4,Rm)
# MOV.B @(disp4,Rm),R0
mov.l .L2, r4
mov.b @(2, r4), r0
add r0, r0
mov.b r0, @(2, r4)
mov.b @(2, r4), r0
mov r0, r4
# MOV.B Rm,@(R0,Rn)
# MOV.B @(R0,Rm),Rn
mov.l .L2, r0
mov #3, r1
mov.b @(r0, r1), r5
add r5, r5
mov.b r5, @(r0, r1)
mov.b @(r0, r1), r5
# MOV.B R0,@(disp8,GBR)
# MOV.B @(disp8,GBR),R0
mov.l .L2, r0
ldc r0, GBR
mov.b @(4, GBR), r0
add r0, r0
mov.b r0, @(4, GBR)
mov.b @(4, GBR), r0
mov r0, r6
test_movbs:
# REGISTER_IN r0 -12
mov.l .L2, r1
mov.b r0, @r1
mov.b @r1, r2
rts
nop
.align 4
# REGISTER_OUT r2 -12
test_movbm:
mov.l .L2, r0
mov.b @r0+, r1
add r1, r1
mov.b r1, @-r0
mov.b @r0, r2
rts
nop
# REGISTER_OUT r2 -24
test_movbs0d:
mov.l .L2, r1
mov.b @(1, r1), r0
add r0, r0
mov.b r0, @(1, r1)
# overwrite r0 to make sure the next instruction is actually working
mov #99, r0
mov.b @(1, r1), r0
rts
nop
# REGISTER_OUT r0 -26
test_movbs0:
mov.l .L2, r0
mov #1, r1
mov.b @(r0, r1), r2
add r2, r2
mov.b r2, @(r0, r1)
mov.b @(r0, r1), r3
rts
nop
# REGISTER_OUT r3 -26
test_movbs0g:
mov.l .L2, r0
ldc r0, GBR
mov.b @(1, GBR), r0
add r0, r0
mov.b r0, @(1, GBR)
# overwrite r0 to make sure the next instruction is actually working
mov #99, r0
mov.b @(1, GBR), r0
rts
nop
# REGISTER_OUT r0 -26
.align 4
.L1:
.byte -12
.byte -13
.byte -14
.byte -15
.byte -16
.align 4
.align 4
.L2:
.long .L1
# REGISTER_OUT r2 -24
# REGISTER_OUT r3 -26
# REGISTER_OUT r4 -28
# REGISTER_OUT r5 -30
# REGISTER_OUT r6 -32

121
test/asm/movl.s
View File

@ -1,67 +1,68 @@
.little
.text
.global start
start:
# MOV.L @(disp8,PC),Rn
test_movllpc:
# MOV.L @(disp8,PC),Rn
mov.l .L1, r2
# MOV.L Rm,@Rn
# MOV.L @Rm,Rn
mov.l .L2, r0
add #4, r0
mov.l @r0, r3
add r3, r3
mov.l r3, @r0
mov.l @r0, r3
# MOV.L Rm,@-Rn
# MOV.L @Rm+,Rn
mov.l .L2, r0
add #8, r0
mov.l @r0+, r4
add r4, r4
mov.l r4, @-r0
mov.l @r0, r4
# MOV.L R0,@(disp4,Rm)
# MOV.L @(disp4,Rm),R0
mov.l .L2, r5
mov.l @(12, r5), r0
add r0, r0
mov.l r0, @(12, r5)
mov.l @(12, r5), r0
mov r0, r5
# MOV.L @(R0,Rm),Rn
# MOV.L Rm,@(R0,Rn)
mov.l .L2, r0
mov #16, r1
mov.l @(r0, r1), r6
add r6, r6
mov.l r6, @(r0, r1)
mov.l @(r0, r1), r6
# MOV.L R0,@(disp8,GBR)
# MOV.L @(disp8,GBR),R0
mov.l .L2, r0
ldc r0, GBR
mov.l @(20, GBR), r0
add r0, r0
mov.l r0, @(20, GBR)
mov.l @(20, GBR), r0
mov r0, r7
rts
nop
.align 4
# REGISTER_OUT r2 -12
test_movls:
# REGISTER_IN r0 -12
mov.l .L2, r1
mov.l r0, @r1
mov.l @r1, r2
rts
nop
# REGISTER_OUT r2 -12
test_movlm:
mov.l .L2, r0
mov.l @r0+, r1
add r1, r1
mov.l r1, @-r0
mov.l @r0, r2
rts
nop
# REGISTER_OUT r2 -24
test_movlsmd:
mov.l .L2, r0
mov.l @(4, r0), r1
add r1, r1
mov.l r1, @(4, r0)
mov.l @(4, r0), r2
rts
nop
# REGISTER_OUT r2 -26
test_movls0:
mov.l .L2, r0
mov #4, r1
mov.l @(r0, r1), r2
add r2, r2
mov.l r2, @(r0, r1)
mov.l @(r0, r1), r3
rts
nop
# REGISTER_OUT r3 -26
test_movls0g:
mov.l .L2, r0
ldc r0, GBR
mov.l @(4, GBR), r0
add r0, r0
mov.l r0, @(4, GBR)
# overwrite r0 to make sure the next instruction is actually working
mov #99, r0
mov.l @(4, GBR), r0
rts
nop
# REGISTER_OUT r0 -26
.align 4
.L1:
.long -24
.long -12
.long -13
.long -14
.long -15
.long -16
.long -17
.align 4
.align 4
.L2:
.long .L1
# REGISTER_OUT r2 -24
# REGISTER_OUT r3 -26
# REGISTER_OUT r4 -28
# REGISTER_OUT r5 -30
# REGISTER_OUT r6 -32
# REGISTER_OUT r7 -34

13
test/asm/movt.s
View File

@ -1,15 +1,10 @@
# REGISTER_IN r0 3
.little
.text
.global start
start:
test_movt:
# REGISTER_IN r0 3
cmp/eq #3, r0
movt r1
cmp/eq #5, r0
movt r2
rts
nop
# REGISTER_OUT r1 1
# REGISTER_OUT r2 0
# REGISTER_OUT r1 1
# REGISTER_OUT r2 0

123
test/asm/movw.s
View File

@ -1,67 +1,70 @@
.little
.text
.global start
start:
# MOV.W @(disp8,PC),Rn
test_movwlpc:
# MOV.W @(disp8,PC),Rn
mov.w .L1, r2
# MOV.W Rm,@Rn
# MOV.W @Rm,Rn
mov.l .L2, r0
add #2, r0
mov.w @r0, r3
add r3, r3
mov.w r3, @r0
mov.w @r0, r3
# MOV.W Rm,@-Rn
# MOV.W @Rm+,Rn
mov.l .L2, r0
add #4, r0
mov.w @r0+, r4
add r4, r4
mov.w r4, @-r0
mov.w @r0, r4
# MOV.W R0,@(disp4,Rm)
# MOV.W @(disp4,Rm),R0
mov.l .L2, r5
mov.w @(6, r5), r0
add r0, r0
mov.w r0, @(6, r5)
mov.w @(6, r5), r0
mov r0, r5
# MOV.W @(R0,Rm),Rn
# MOV.W Rm,@(R0,Rn)
mov.l .L2, r0
mov #8, r1
mov.w @(r0, r1), r6
add r6, r6
mov.w r6, @(r0, r1)
mov.w @(r0, r1), r6
# MOV.W R0,@(disp8,GBR)
# MOV.W @(disp8,GBR),R0
mov.l .L2, r0
ldc r0, GBR
mov.w @(10, GBR), r0
add r0, r0
mov.w r0, @(10, GBR)
mov.w @(10, GBR), r0
mov r0, r7
rts
nop
.align 4
# REGISTER_OUT r2 -12
test_movws:
# REGISTER_IN r0 -12
mov.l .L2, r1
mov.w r0, @r1
mov.w @r1, r2
rts
nop
# REGISTER_OUT r2 -12
test_movwm:
mov.l .L2, r0
mov.w @r0+, r1
add r1, r1
mov.w r1, @-r0
mov.w @r0, r2
rts
nop
# REGISTER_OUT r2 -24
test_movws0d:
mov.l .L2, r1
mov.w @(2, r1), r0
add r0, r0
mov.w r0, @(2, r1)
# overwrite r0 to make sure the next instruction is actually working
mov #99, r0
mov.w @(2, r1), r0
rts
nop
# REGISTER_OUT r0 -26
test_movws0:
mov.l .L2, r0
mov #2, r1
mov.w @(r0, r1), r2
add r2, r2
mov.w r2, @(r0, r1)
mov.w @(r0, r1), r3
rts
nop
# REGISTER_OUT r3 -26
test_movws0g:
mov.l .L2, r0
ldc r0, GBR
mov.w @(2, GBR), r0
add r0, r0
mov.w r0, @(2, GBR)
# overwrite r0 to make sure the next instruction is actually working
mov #99, r0
mov.w @(2, GBR), r0
rts
nop
# REGISTER_OUT r0 -26
.align 4
.L1:
.short -24
.short -12
.short -13
.short -14
.short -15
.short -16
.short -17
.align 4
.align 4
.L2:
.long .L1
# REGISTER_OUT r2 -24
# REGISTER_OUT r3 -26
# REGISTER_OUT r4 -28
# REGISTER_OUT r5 -30
# REGISTER_OUT r6 -32
# REGISTER_OUT r7 -34

46
test/asm/mul.s
View File

@ -1,26 +1,26 @@
# REGISTER_IN r0 0xfffffffe
# REGISTER_IN r1 0x00005555
# REGISTER_IN r2 0xfffffffe
# REGISTER_IN r3 0x00005555
# REGISTER_IN r4 0x00000002
# REGISTER_IN r5 0xffffaaaa
.little
.text
.global start
start:
# MUL.L Rm,Rn
mul.l r0, r1
sts macl, r1
# MULS Rm,Rn
muls r2, r3
sts macl, r3
# MULU Rm,Rn
# mulu r4, r5
# sts macl, r5
test_mull:
# REGISTER_IN r0 0x00fffffe
# REGISTER_IN r1 0x00000004
mul.l r1, r0
sts macl, r0
rts
nop
# REGISTER_OUT r0 0x03fffff8
# REGISTER_OUT r1 0xffff5556
# REGISTER_OUT r3 0xffff5556
# REGISTER_OT r5 0x00015554
test_muls:
# REGISTER_IN r0 0x00fffffe
# REGISTER_IN r1 0x00000004
muls r1, r0
sts macl, r0
rts
nop
# REGISTER_OUT r0 0xfffffff8
test_mulu:
# REGISTER_IN r0 0x00fffffe
# REGISTER_IN r1 0x00000004
mulu r1, r0
sts macl, r0
rts
nop
# REGISTER_OUT r0 0x0003fff8

42
test/asm/neg.s
View File

@ -1,38 +1,6 @@
# REGISTER_IN r0 0x700000f0
# REGISTER_IN r1 0x700000f1
# REGISTER_IN r2 -4
# REGISTER_IN r3 0
.text
.global start
start:
# NEG Rm,Rn
neg r2, r4
# NEGC Rm,Rn - T(0)
ldc r0, SR
negc r2, r5
stc SR, r6
# NEGC Rm(0),Rn - T(0)
ldc r0, SR
negc r3, r7
stc SR, r8
# NEGC Rm,Rn - T(1)
ldc r1, SR
negc r2, r9
stc SR, r10
# NEGC Rm(0),Rn - T(1)
ldc r1, SR
negc r3, r11
stc SR, r12
rts
test_neg:
# REGISTER_IN r0 -1
neg r0, r1
rts
nop
# REGISTER_OUT r4 4
# REGISTER_OUT r5 4
# REGISTER_OUT r6 0x700000f1
# REGISTER_OUT r7 0
# REGISTER_OUT r8 0x700000f0
# REGISTER_OUT r9 3
# REGISTER_OUT r10 0x700000f1
# REGISTER_OUT r11 0xffffffff
# REGISTER_OUT r12 0x700000f1
# REGISTER_OUT r1 1

17
test/asm/negc.s Normal file
View File

@ -0,0 +1,17 @@
test_negc_nocarry:
# REGISTER_IN r0 0x700000f0
# REGISTER_IN r1 -4
ldc r0, SR
negc r1, r2
rts
nop
# REGISTER_OUT r2 4
test_negc_carry:
# REGISTER_IN r0 0x700000f1
# REGISTER_IN r1 -4
ldc r0, SR
negc r1, r2
rts
nop
# REGISTER_OUT r2 3

10
test/asm/not.s
View File

@ -1,10 +1,6 @@
# REGISTER_IN r0 0xf0f0f0f0
.text
.global start
start:
test_not:
# REGISTER_IN r0 0xf0f0f0f0
not r0, r1
rts
nop
# REGISTER_OUT r1 0x0f0f0f0f
# REGISTER_OUT r1 0x0f0f0f0f

40
test/asm/or.s
View File

@ -1,29 +1,33 @@
# REGISTER_IN r0 0xffffff00
# REGISTER_IN r1 0x00ffffff
.text
.global start
start:
# OR Rm,Rn
test_or:
# REGISTER_IN r0 0xffffff00
# REGISTER_IN r1 0x00ffffff
or r0, r1
# OR #imm,R0
or #0xff, r0
mov r0, r2
# OR.B #imm,@(R0,GBR)
rts
nop
# REGISTER_OUT r1 0xffffffff
test_or_imm:
# REGISTER_IN r0 0xffffff00
or #0xf, r0
rts
nop
# REGISTER_OUT r0 0xffffff0f
test_or_disp:
mov.l .L2, r0
ldc r0, GBR
mov #4, r0
or.b #0x3f, @(r0, GBR)
# mov.l instead of mov.b to avoid sign extension of 0xff
or.b #0x22, @(r0, GBR)
mov.l @(4, GBR), r0
rts
nop
.align 4
# REGISTER_OUT r0 0x33
.align 4
.L1:
.long 0x0
.long 0x000000fc
.align 4
.long 0x00000011
.align 4
.L2:
.long .L1
# REGISTER_OUT r2 0xffffffff

166
test/asm/rot.s
View File

@ -1,98 +1,74 @@
.text
.global start
start:
# ROTL Rn (Rn MSB = 0)
mov.l .L1, r2
rotl r2
stc SR, r0
and #0x1, r0
mov r0, r3
# ROTL Rn (Rn MSB = 1)
mov.l .L1+4, r4
rotl r4
stc SR, r0
and #0x1, r0
mov r0, r5
# ROTR Rn (Rn LSB = 0)
mov.l .L1+4, r6
rotr r6
stc SR, r0
and #0x1, r0
mov r0, r7
# ROTR Rn (Rn LSB = 1)
mov.l .L1, r8
rotr r8
stc SR, r0
and #0x1, r0
mov r0, r9
# ROTCL Rn (MSB = 1, T = 0)
# set T = 0
stc SR, r0
mov.l .L1+4, r1
and r1, r0
ldc r0, SR
# rotate
mov.l .L1+4, r10
rotcl r10
stc SR, r0
and #0x1, r0
mov r0, r11
# ROTCL Rn (MSB = 0, T = 1)
# set T = 1
stc SR, r0
or #1, r0
ldc r0, SR
# rotate
mov.l .L1, r12
rotcl r12
stc SR, r0
and #0x1, r0
mov r0, r13
# ROTCR Rn (LSB = 1, T = 0)
# set T = 0
stc SR, r0
mov.l .L1+4, r1
and r1, r0
ldc r0, SR
# rotate
mov.l .L1, r14
rotcr r14
stc SR, r0
and #0x1, r0
mov r0, r15
# ROTCR Rn (LSB = 0, T = 1)
# set T = 1
stc SR, r0
or #1, r0
ldc r0, SR
# rotate
mov.l .L1+4, r1
rotcr r1
stc SR, r0
and #0x1, r0
test_rotl_msb0:
# REGISTER_IN r0 0x7fffffff
rotl r0
movt r1
rts
nop
.align 4
.L1:
.long 0x7fffffff
.long 0xfffffffe
.align 4
.L2:
.long .L1
# REGISTER_OUT r0 0xfffffffe
# REGISTER_OUT r1 0
# REGISTER_OUT r2 0xfffffffe
# REGISTER_OUT r3 0
# REGISTER_OUT r4 0xfffffffd
# REGISTER_OUT r5 1
# REGISTER_OUT r6 0x7fffffff
# REGISTER_OUT r7 0
# REGISTER_OUT r8 0xbfffffff
# REGISTER_OUT r9 1
# REGISTER_OUT r10 0xfffffffc
# REGISTER_OUT r11 1
# REGISTER_OUT r12 0xffffffff
# REGISTER_OUT r13 0
# REGISTER_OUT r14 0x3fffffff
# REGISTER_OUT r15 1
# REGISTER_OUT r1 0xffffffff
# REGISTER_OUT r0 0
test_rotl_msb1:
# REGISTER_IN r0 0xfffffffe
rotl r0
movt r1
rts
nop
# REGISTER_OUT r0 0xfffffffd
# REGISTER_OUT r1 1
test_rotcl_t0_msb1:
# REGISTER_IN r0 0xfffffffe
rotcl r0
movt r1
rts
nop
# REGISTER_OUT r0 0xfffffffc
# REGISTER_OUT r1 1
test_rotcl_t1_msb0:
# REGISTER_IN r0 0x7fffffff
sett
rotcl r0
movt r1
rts
nop
# REGISTER_OUT r0 0xffffffff
# REGISTER_OUT r1 0
test_rotr_lsb0:
# REGISTER_IN r0 0xfffffffe
rotr r0
movt r1
rts
nop
# REGISTER_OUT r0 0x7fffffff
# REGISTER_OUT r1 0
test_rotr_lsb1:
# REGISTER_IN r0 0x7fffffff
rotr r0
movt r1
rts
nop
# REGISTER_OUT r0 0xbfffffff
# REGISTER_OUT r1 1
test_rotcr_t0_lsb1:
# REGISTER_IN r0 0x7fffffff
rotcr r0
movt r1
rts
nop
# REGISTER_OUT r0 0x3fffffff
# REGISTER_OUT r1 1
test_rotcr_t1_lsb0:
# ROTCR Rn (LSB = 0, T = 1)
# REGISTER_IN r0 0xfffffffe
sett
rotcr r0
movt r1
rts
nop
# REGISTER_OUT r0 0xffffffff
# REGISTER_OUT r1 0

261
test/asm/sh4_test.inc
View File

@ -1,75 +1,186 @@
SH4_TEST(add, SH4Test {(uint8_t *)"\x0c\x31\x0b\x00\x09\x00", 6, {{ SH4CTX_R0, -4 }, { SH4CTX_R1, 17 }}, {{ SH4CTX_R1, 13 }}})
SH4_TEST(addc, SH4Test {(uint8_t *)"\x2e\x31\x02\x00\x01\xc9\x03\x62\x4e\x33\x02\x00\x01\xc9\x03\x64\x6e\x35\x02\x00\x01\xc9\x03\x66\x0b\x00\x09\x00", 28, {{ SH4CTX_R1, 0xfffffffe }, { SH4CTX_R2, 0x1 }, { SH4CTX_R3, 0xffffffff }, { SH4CTX_R4, 0x1 }, { SH4CTX_R5, 0xffffffff }, { SH4CTX_R6, 0x1 }}, {{ SH4CTX_R1, 0xffffffff }, { SH4CTX_R2, 0 }, { SH4CTX_R3, 0x0 }, { SH4CTX_R4, 1 }, { SH4CTX_R5, 0x1 }, { SH4CTX_R6, 1 }}})
SH4_TEST(addv, SH4Test {(uint8_t *)"\x01\xe0\x1b\xd1\x0f\x31\x02\x00\x01\xc9\x03\x62\x01\xe0\x1c\xd3\x0f\x33\x02\x00\x01\xc9\x03\x64\x21\xd0\x19\xd5\x0f\x35\x02\x00\x01\xc9\x03\x66\x1a\xd0\x01\xe7\x0f\x37\x02\x00\x01\xc9\x03\x68\x13\xd0\x1b\xd9\x0f\x39\x02\x00\x01\xc9\x03\x6a\x01\xe0\x14\xdb\x0f\x3b\x02\x00\x01\xc9\x03\x6c\xff\xe0\x11\xdd\x0f\x3d\x02\x00\x01\xc9\x03\x6e\xff\xe0\x12\xdf\x0f\x3f\x02\x00\x01\xc9\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xfe\xff\xff\x7f\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xff\xff\xff\x7f\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x80\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x01\x00\x00\x80\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 176, {}, {{ SH4CTX_R1, 0x7fffffff }, { SH4CTX_R2, 0 }, { SH4CTX_R3, 0x80000000 }, { SH4CTX_R4, 1 }, { SH4CTX_R5, 0x00000000 }, { SH4CTX_R6, 0 }, { SH4CTX_R7, 0x80000001 }, { SH4CTX_R8, 0 }, { SH4CTX_R9, 0x00000000 }, { SH4CTX_R10, 0 }, { SH4CTX_R11, 0x80000001 }, { SH4CTX_R12, 0 }, { SH4CTX_R13, 0x7fffffff }, { SH4CTX_R14, 1 }, { SH4CTX_R15, 0x80000000 }, { SH4CTX_R0, 0 }}})
SH4_TEST(and, SH4Test {(uint8_t *)"\x09\x21\xff\xc9\x03\x62\x0a\xd0\x1e\x40\x04\xe0\x3f\xcd\x01\xc6\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x00\xfc\x00\x00\x00\x09\x00\x09\x00\x09\x00\x09\x00\x20\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 64, {{ SH4CTX_R0, 0x00ffffff }, { SH4CTX_R1, 0xffffff00 }}, {{ SH4CTX_R1, 0xffff00 }, { SH4CTX_R2, 0xff }, { SH4CTX_R0, 0x3c }}})
SH4_TEST(bf, SH4Test {(uint8_t *)"\x08\x88\x01\x8b\x06\xa0\x09\x00\x09\x88\x02\x8f\x06\x71\x01\xa0\x09\x00\x07\x71\x0b\x00\x09\x00", 24, {{ SH4CTX_R0, 7 }, { SH4CTX_R1, 0 }}, {{ SH4CTX_R1, 13 }}})
SH4_TEST(bra, SH4Test {(uint8_t *)"\x01\xa0\x09\x00\x01\x70\x09\x70\x0b\x00\x09\x00", 12, {{ SH4CTX_R0, 4 }}, {{ SH4CTX_R0, 13 }}})
SH4_TEST(braf, SH4Test {(uint8_t *)"\x23\x00\x09\x00\x07\x71\x09\x71\x0b\x00\x09\x00", 12, {{ SH4CTX_R0, 2 }, { SH4CTX_R1, 4 }}, {{ SH4CTX_R1, 13 }}})
SH4_TEST(bsr, SH4Test {(uint8_t *)"\x22\x4f\x07\xb0\x01\x70\x03\x70\x26\x4f\x0b\x00\x09\x00\x02\x70\x0b\x00\x09\x00\x09\x70\x0b\x00\x09\x00", 26, {}, {{ SH4CTX_R0, 13 }}})
SH4_TEST(bsrf, SH4Test {(uint8_t *)"\x22\x4f\x03\x00\x01\x71\x03\x71\x26\x4f\x0b\x00\x09\x00\x02\x71\x0b\x00\x09\x00\x09\x71\x0b\x00\x09\x00", 26, {{ SH4CTX_R0, 14 }}, {{ SH4CTX_R1, 13 }}})
SH4_TEST(bt, SH4Test {(uint8_t *)"\x07\x88\x01\x89\x06\xa0\x09\x00\x07\x88\x02\x8d\x06\x71\x01\xa0\x09\x00\x07\x71\x0b\x00\x09\x00", 24, {{ SH4CTX_R0, 7 }, { SH4CTX_R1, 0 }}, {{ SH4CTX_R1, 13 }}})
SH4_TEST(cmp, SH4Test {(uint8_t *)"\x00\xe2\x0d\xe0\x0d\x88\x02\x00\x01\xc9\x0c\x32\x0d\xe0\x11\x88\x02\x00\x01\xc9\x0c\x32\x00\xe3\x0d\xe1\x0d\xe0\x00\x31\x02\x00\x01\xc9\x0c\x33\x11\xe1\x0d\xe0\x00\x31\x02\x00\x01\xc9\x0c\x33\x00\xe4\xff\xe1\x0d\xe0\x02\x31\x02\x00\x01\xc9\x0c\x34\x0d\xe1\x0d\xe0\x02\x31\x02\x00\x01\xc9\x0c\x34\x0e\xe1\x0d\xe0\x02\x31\x02\x00\x01\xc9\x0c\x34\x00\xe5\xff\xe1\x0d\xe0\x03\x31\x02\x00\x01\xc9\x0c\x35\x0d\xe1\x0d\xe0\x03\x31\x02\x00\x01\xc9\x0c\x35\x0e\xe1\x0d\xe0\x03\x31\x02\x00\x01\xc9\x0c\x35\x00\xe6\xff\xe1\x0d\xe0\x06\x31\x02\x00\x01\xc9\x0c\x36\x0d\xe1\x0d\xe0\x06\x31\x02\x00\x01\xc9\x0c\x36\x0e\xe1\x0d\xe0\x06\x31\x02\x00\x01\xc9\x0c\x36\x00\xe7\xff\xe1\x0d\xe0\x07\x31\x02\x00\x01\xc9\x0c\x37\x0d\xe1\x0d\xe0\x07\x31\x02\x00\x01\xc9\x0c\x37\x0e\xe1\x0d\xe0\x07\x31\x02\x00\x01\xc9\x0c\x37\x00\xe8\xf3\xe0\x11\x40\x02\x00\x01\xc9\x0c\x38\x00\xe0\x11\x40\x02\x00\x01\xc9\x0c\x38\x0d\xe0\x11\x40\x02\x00\x01\xc9\x0c\x38\x00\xe9\xf3\xe0\x15\x40\x02\x00\x01\xc9\x0c\x39\x00\xe0\x15\x40\x02\x00\x01\xc9\x0c\x39\x0d\xe0\x15\x40\x02\x00\x01\xc9\x0c\x39\x00\xea\xff\xe1\x00\xe0\x0c\x21\x02\x00\x01\xc9\x0c\x3a\xff\xe1\x09\xd0\x0c\x21\x02\x00\x01\xc9\x0c\x3a\xff\xe1\x0a\xd0\x0c\x21\x02\x00\x01\xc9\x0c\x3a\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x00\x00\xf0\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x00\x00\xff\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 352, {}, {{ SH4CTX_R2, 1 }, { SH4CTX_R3, 1 }, { SH4CTX_R4, 3 }, { SH4CTX_R5, 2 }, { SH4CTX_R6, 2 }, { SH4CTX_R7, 1 }, { SH4CTX_R8, 2 }, { SH4CTX_R9, 1 }, { SH4CTX_R10, 1 }}})
SH4_TEST(div0, SH4Test {(uint8_t *)"\x0e\x40\x19\x00\x02\x01\x09\x21\x0e\x40\x27\x23\x02\x04\x0e\x40\x57\x26\x02\x07\x0e\x40\x87\x29\x02\x0a\x0e\x40\xb7\x2c\x02\x0d\x0b\x00\x09\x00", 36, {{ SH4CTX_R0, 0x700000f0 }, { SH4CTX_R2, 0x2 }, { SH4CTX_R3, 0x4 }, { SH4CTX_R5, 0xfffffffe }, { SH4CTX_R6, 0xfffffffc }, { SH4CTX_R8, 0x2 }, { SH4CTX_R9, 0xfffffffc }, { SH4CTX_R11, 0xfffffffe }, { SH4CTX_R12, 0x4 }}, {{ SH4CTX_R1, 0x700000f0 }, { SH4CTX_R4, 0x700000f0 }, { SH4CTX_R7, 0x700003f0 }, { SH4CTX_R10, 0x700001f1 }, { SH4CTX_R13, 0x700002f1 }}})
SH4_TEST(div1s, SH4Test {(uint8_t *)"\x28\x42\x3f\x63\x0a\x20\x33\x61\x24\x41\x0a\x33\x27\x23\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x3f\x63\x24\x43\x0e\x33\x3f\x63\x28\x44\x5f\x65\x0a\x20\x53\x61\x24\x41\x0a\x35\x47\x25\x44\x35\x44\x35\x44\x35\x44\x35\x44\x35\x44\x35\x44\x35\x44\x35\x44\x35\x44\x35\x44\x35\x44\x35\x44\x35\x44\x35\x44\x35\x44\x35\x5f\x65\x24\x45\x0e\x35\x5f\x65\x73\x60\x24\x40\x1a\x31\x0a\x20\x0a\x37\x67\x21\x24\x47\x64\x31\x24\x47\x64\x31\x24\x47\x64\x31\x24\x47\x64\x31\x24\x47\x64\x31\x24\x47\x64\x31\x24\x47\x64\x31\x24\x47\x64\x31\x24\x47\x64\x31\x24\x47\x64\x31\x24\x47\x64\x31\x24\x47\x64\x31\x24\x47\x64\x31\x24\x47\x64\x31\x24\x47\x64\x31\x24\x47\x64\x31\x24\x47\x64\x31\x24\x47\x64\x31\x24\x47\x64\x31\x24\x47\x64\x31\x24\x47\x64\x31\x24\x47\x64\x31\x24\x47\x64\x31\x24\x47\x64\x31\x24\x47\x64\x31\x24\x47\x64\x31\x24\x47\x64\x31\x24\x47\x64\x31\x24\x47\x64\x31\x24\x47\x64\x31\x24\x47\x64\x31\x24\x47\x64\x31\x24\x47\x0e\x37\x93\x60\x24\x40\x1a\x31\x0a\x20\x0a\x39\x87\x21\x24\x49\x84\x31\x24\x49\x84\x31\x24\x49\x84\x31\x24\x49\x84\x31\x24\x49\x84\x31\x24\x49\x84\x31\x24\x49\x84\x31\x24\x49\x84\x31\x24\x49\x84\x31\x24\x49\x84\x31\x24\x49\x84\x31\x24\x49\x84\x31\x24\x49\x84\x31\x24\x49\x84\x31\x24\x49\x84\x31\x24\x49\x84\x31\x24\x49\x84\x31\x24\x49\x84\x31\x24\x49\x84\x31\x24\x49\x84\x31\x24\x49\x84\x31\x24\x49\x84\x31\x24\x49\x84\x31\x24\x49\x84\x31\x24\x49\x84\x31\x24\x49\x84\x31\x24\x49\x84\x31\x24\x49\x84\x31\x24\x49\x84\x31\x24\x49\x84\x31\x24\x49\x84\x31\x24\x49\x84\x31\x24\x49\x0e\x39\x0b\x00\x09\x00", 400, {{ SH4CTX_R2, 0x2710 }, { SH4CTX_R3, 0x8012 }, { SH4CTX_R4, 0xd8f0 }, { SH4CTX_R5, 0x7fee }, { SH4CTX_R6, 0x2710 }, { SH4CTX_R7, 0xf0000010 }, { SH4CTX_R8, 0xffffd8f0 }, { SH4CTX_R9, 0x0ffffff0 }}, {{ SH4CTX_R3, 0xfffffffd }, { SH4CTX_R5, 0xfffffffd }, { SH4CTX_R7, 0xffff9725 }, { SH4CTX_R9, 0xffff9725 }}})
SH4_TEST(div1u, SH4Test {(uint8_t *)"\x28\x40\x19\x00\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x24\x41\x1d\x61\x19\x00\x24\x44\x24\x33\x24\x44\x24\x33\x24\x44\x24\x33\x24\x44\x24\x33\x24\x44\x24\x33\x24\x44\x24\x33\x24\x44\x24\x33\x24\x44\x24\x33\x24\x44\x24\x33\x24\x44\x24\x33\x24\x44\x24\x33\x24\x44\x24\x33\x24\x44\x24\x33\x24\x44\x24\x33\x24\x44\x24\x33\x24\x44\x24\x33\x24\x44\x24\x33\x24\x44\x24\x33\x24\x44\x24\x33\x24\x44\x24\x33\x24\x44\x24\x33\x24\x44\x24\x33\x24\x44\x24\x33\x24\x44\x24\x33\x24\x44\x24\x33\x24\x44\x24\x33\x24\x44\x24\x33\x24\x44\x24\x33\x24\x44\x24\x33\x24\x44\x24\x33\x24\x44\x24\x33\x24\x44\x24\x33\x24\x44\x0b\x00\x09\x00", 176, {{ SH4CTX_R0, 0x2710 }, { SH4CTX_R1, 0x0ffffff0 }, { SH4CTX_R2, 0x2710 }, { SH4CTX_R3, 0x00000001 }, { SH4CTX_R4, 0x2a05f200 }}, {{ SH4CTX_R1, 0x68db }, { SH4CTX_R4, 0x7a120 }}})
SH4_TEST(dmuls, SH4Test {(uint8_t *)"\x0d\x31\x0a\x00\x1a\x01\x0b\x00\x09\x00", 10, {{ SH4CTX_R0, 0xfffffffe }, { SH4CTX_R1, 0x00005555 }}, {{ SH4CTX_R0, 0xffffffff }, { SH4CTX_R1, 0xffff5556 }}})
SH4_TEST(dmulu, SH4Test {(uint8_t *)"\x05\x31\x0a\x00\x1a\x01\x0b\x00\x09\x00", 10, {{ SH4CTX_R0, 0xfffffffe }, { SH4CTX_R1, 0x00005555 }}, {{ SH4CTX_R0, 0x00005554 }, { SH4CTX_R1, 0xffff5556 }}})
SH4_TEST(dt, SH4Test {(uint8_t *)"\x01\x71\x10\x40\xfc\x8b\x0b\x00\x09\x00", 10, {{ SH4CTX_R0, 13 }, { SH4CTX_R1, 0 }}, {{ SH4CTX_R0, 0 }, { SH4CTX_R1, 13 }}})
SH4_TEST(ext, SH4Test {(uint8_t *)"\x0e\x63\x1f\x64\x2c\x65\x2d\x66\x0b\x00\x09\x00", 12, {{ SH4CTX_R0, 0xff }, { SH4CTX_R1, 0xffff }, { SH4CTX_R2, 0xfffa3002 }}, {{ SH4CTX_R3, 0xffffffff }, { SH4CTX_R4, 0xffffffff }, { SH4CTX_R5, 0x2 }, { SH4CTX_R6, 0x3002 }}})
SH4_TEST(fabsd, SH4Test {(uint8_t *)"\x5d\xf2\x0b\x00\x09\x00", 6, {{ SH4CTX_FPSCR, 0x000c0001 }, { SH4CTX_DR2, 0xc010000000000000 }}, {{ SH4CTX_DR2, 0x4010000000000000 }}})
SH4_TEST(fabsf, SH4Test {(uint8_t *)"\x5d\xf1\x0b\x00\x09\x00", 6, {{ SH4CTX_FR1, 0xc0800000 }}, {{ SH4CTX_FR1, 0x40800000 }}})
SH4_TEST(faddd, SH4Test {(uint8_t *)"\x00\xf2\x0b\x00\x09\x00", 6, {{ SH4CTX_FPSCR, 0x000c0001 }, { SH4CTX_DR0, 0x4014000000000000 }, { SH4CTX_DR2, 0xc018000000000000 }}, {{ SH4CTX_DR2, 0xbff0000000000000 }}})
SH4_TEST(faddf, SH4Test {(uint8_t *)"\x00\xf1\x0b\x00\x09\x00", 6, {{ SH4CTX_FR0, 0x40400000 }, { SH4CTX_FR1, 0xbf800000 }}, {{ SH4CTX_FR1, 0x40000000 }}})
SH4_TEST(fcmpeqd, SH4Test {(uint8_t *)"\x04\xf2\x29\x00\x24\xf4\x29\x01\x0b\x00\x09\x00", 12, {{ SH4CTX_FPSCR, 0x000c0001 }, { SH4CTX_DR0, 0x4014000000000000 }, { SH4CTX_DR2, 0xc018000000000000 }, { SH4CTX_DR4, 0xc018000000000000 }}, {{ SH4CTX_R0, 0 }, { SH4CTX_R1, 1 }}})
SH4_TEST(fcmpeqf, SH4Test {(uint8_t *)"\x04\xf1\x29\x00\x14\xf2\x29\x01\x0b\x00\x09\x00", 12, {{ SH4CTX_FR0, 0x40400000 }, { SH4CTX_FR1, 0xbf800000 }, { SH4CTX_FR2, 0xbf800000 }}, {{ SH4CTX_R0, 0 }, { SH4CTX_R1, 1 }}})
SH4_TEST(fcmpgtd, SH4Test {(uint8_t *)"\x05\xf2\x29\x00\x25\xf0\x29\x01\x0b\x00\x09\x00", 12, {{ SH4CTX_FPSCR, 0x000c0001 }, { SH4CTX_DR0, 0x4014000000000000 }, { SH4CTX_DR2, 0xc018000000000000 }}, {{ SH4CTX_R0, 0 }, { SH4CTX_R1, 1 }}})
SH4_TEST(fcmpgtf, SH4Test {(uint8_t *)"\x05\xf1\x29\x00\x15\xf0\x29\x01\x0b\x00\x09\x00", 12, {{ SH4CTX_FR0, 0x40400000 }, { SH4CTX_FR1, 0xbf800000 }}, {{ SH4CTX_R0, 0 }, { SH4CTX_R1, 1 }}})
SH4_TEST(fdivd, SH4Test {(uint8_t *)"\x03\xf2\x0b\x00\x09\x00", 6, {{ SH4CTX_FPSCR, 0x000c0001 }, { SH4CTX_DR0, 0xbfe0000000000000 }, { SH4CTX_DR2, 0xc000000000000000 }}, {{ SH4CTX_DR2, 0x4010000000000000 }}})
SH4_TEST(fdivf, SH4Test {(uint8_t *)"\x03\xf1\x0b\x00\x09\x00", 6, {{ SH4CTX_FR0, 0xc0200000 }, { SH4CTX_FR1, 0x41200000 }}, {{ SH4CTX_FR1, 0xc0800000 }}})
SH4_TEST(fipr, SH4Test {(uint8_t *)"\xed\xfd\x0b\x00\x09\x00", 6, {{ SH4CTX_FR4, 0x3f800000 }, { SH4CTX_FR5, 0xc0000000 }, { SH4CTX_FR6, 0xc0400000 }, { SH4CTX_FR7, 0x40800000 }, { SH4CTX_FR12, 0x40800000 }, { SH4CTX_FR13, 0xc0400000 }, { SH4CTX_FR14, 0xc0000000 }, { SH4CTX_FR15, 0x3f800000 }}, {{ SH4CTX_FR15, 0x41a00000 }}})
SH4_TEST(fld, SH4Test {(uint8_t *)"\x8d\xf0\x9d\xf1\x1d\xf1\x0d\xf2\x0b\x00\x09\x00", 12, {{ SH4CTX_FR0, 0x11111111 }}, {{ SH4CTX_FR0, 0x00000000 }, { SH4CTX_FR1, 0x3f800000 }, { SH4CTX_FR2, 0x3f800000 }}})
SH4_TEST(floatd, SH4Test {(uint8_t *)"\x5a\x41\x2d\xf2\x0b\x00\x09\x00", 8, {{ SH4CTX_FPSCR, 0x000c0001 }, { SH4CTX_R1, 0x00000004 }}, {{ SH4CTX_DR2, 0x4010000000000000 }}})
SH4_TEST(floatf, SH4Test {(uint8_t *)"\x5a\x40\x2d\xf3\x0b\x00\x09\x00", 8, {{ SH4CTX_R0, 0x00000002 }}, {{ SH4CTX_FR3, 0x40000000 }}})
SH4_TEST(fmac, SH4Test {(uint8_t *)"\x1e\xf2\x0b\x00\x09\x00", 6, {{ SH4CTX_FR0, 0xc0000000 }, { SH4CTX_FR1, 0xc0a00000 }, { SH4CTX_FR2, 0x40400000 }}, {{ SH4CTX_FR2, 0x41500000 }}})
SH4_TEST(fmovd, SH4Test {(uint8_t *)"\x1c\xf0\x0c\xf5\x3c\xf7\x16\xd0\x08\xf9\x15\xd0\x08\xf2\x14\xd0\x08\xe1\x16\xfb\x12\xd0\x09\xfd\x09\xff\x15\xd0\x1a\xf0\x06\x62\x06\x63\x13\xd0\x08\x70\x3b\xf0\x06\x64\x06\x65\x10\xd0\x08\xe1\x17\xf1\x08\x70\x06\x66\x06\x67\x0b\x00\x09\x00\x09\x00\x09\x00\x00\x00\x28\x40\x00\x00\x00\x00\x00\x00\x2e\x40\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x40\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x50\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 128, {{ SH4CTX_FPSCR, 0x000c0001 }, { SH4CTX_XD0, 0x4020000000000000 }, { SH4CTX_XD2, 0x4024000000000000 }}, {{ SH4CTX_DR0, 0x4020000000000000 }, { SH4CTX_XD4, 0x4020000000000000 }, { SH4CTX_XD6, 0x4024000000000000 }, { SH4CTX_XD8, 0x4028000000000000 }, { SH4CTX_DR2, 0x4028000000000000 }, { SH4CTX_XD10, 0x402e000000000000 }, { SH4CTX_XD12, 0x4028000000000000 }, { SH4CTX_XD14, 0x402e000000000000 }, { SH4CTX_R2, 0x40200000 }, { SH4CTX_R3, 0x00000000 }, { SH4CTX_R4, 0x40240000 }, { SH4CTX_R5, 0x00000000 }, { SH4CTX_R6, 0x40200000 }, { SH4CTX_R7, 0x00000000 }}})
SH4_TEST(fmovf, SH4Test {(uint8_t *)"\x0c\xf1\x0f\xd0\x08\xf2\x0e\xd0\x04\xe1\x16\xf3\x0c\xd0\x09\xf4\x09\xf5\x0f\xd0\x0a\xf0\x02\x62\x0d\xd0\x08\x70\x2b\xf0\x02\x63\x0b\xd0\x04\xe1\x07\xf1\x1e\x04\x0b\x00\x09\x00\x09\x00\x09\x00\x00\x00\xa0\x40\x00\x00\xe0\x40\x00\x00\x00\x00\x00\x00\x00\x00\x30\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x38\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 96, {{ SH4CTX_FR0, 0x40400000 }}, {{ SH4CTX_FR1, 0x40400000 }, { SH4CTX_FR2, 0x40a00000 }, { SH4CTX_FR3, 0x40e00000 }, { SH4CTX_FR4, 0x40a00000 }, { SH4CTX_FR5, 0x40e00000 }, { SH4CTX_R2, 0x40400000 }, { SH4CTX_R3, 0x40a00000 }, { SH4CTX_R4, 0x40400000 }}})
SH4_TEST(fmovsz, SH4Test {(uint8_t *)"\x0c\xf2\x23\xd0\x08\xf4\x22\xd0\x08\xf3\x21\xd0\x04\xe1\x16\xf6\x1f\xd0\x08\xe1\x16\xf5\x1e\xd0\x09\xf8\x09\xfa\x1c\xd0\x09\xf7\x09\xf9\x1f\xd0\x4a\xf0\x06\x62\x06\x63\x1d\xd0\x5a\xf0\x06\x64\x06\x65\x1b\xd0\x08\x70\x6b\xf0\x06\x66\x06\x67\x18\xd0\x08\x70\x7b\xf0\x06\x68\x06\x69\x16\xd0\x08\xe1\x07\xf1\x08\x70\x06\x6a\x06\x6b\x13\xd0\x08\xe1\x37\xf1\x08\x70\x06\x6c\x06\x6d\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x00\x00\x40\x40\x00\x00\x80\x40\x00\x00\x10\x41\x00\x00\x20\x41\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x70\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x80\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 176, {{ SH4CTX_FPSCR, 0x00140001 }, { SH4CTX_DR0, 0x3f80000040000000 }}, {{ SH4CTX_DR2, 0x3f80000040000000 }, { SH4CTX_DR4, 0x4080000040400000 }, { SH4CTX_XD2, 0x4080000040400000 }, { SH4CTX_DR6, 0x4110000040800000 }, { SH4CTX_XD4, 0x4120000041100000 }, { SH4CTX_DR8, 0x4080000040400000 }, { SH4CTX_DR10, 0x4120000041100000 }, { SH4CTX_XD6, 0x4080000040400000 }, { SH4CTX_XD8, 0x4120000041100000 }, { SH4CTX_R2, 0x40400000 }, { SH4CTX_R3, 0x40800000 }, { SH4CTX_R4, 0x41100000 }, { SH4CTX_R5, 0x41200000 }, { SH4CTX_R6, 0x40800000 }, { SH4CTX_R7, 0x41100000 }, { SH4CTX_R8, 0x40400000 }, { SH4CTX_R9, 0x40800000 }, { SH4CTX_R10, 0x40000000 }, { SH4CTX_R11, 0x3f800000 }, { SH4CTX_R12, 0x40400000 }, { SH4CTX_R13, 0x40800000 }}})
SH4_TEST(fmuld, SH4Test {(uint8_t *)"\x02\xf2\x0b\x00\x09\x00", 6, {{ SH4CTX_FPSCR, 0x000c0001 }, { SH4CTX_DR0, 0x4008000000000000 }, { SH4CTX_DR2, 0xc01c000000000000 }}, {{ SH4CTX_DR2, 0xc035000000000000 }}})
SH4_TEST(fmulf, SH4Test {(uint8_t *)"\x02\xf1\x0b\x00\x09\x00", 6, {{ SH4CTX_FR0, 0x40200000 }, { SH4CTX_FR1, 0x40000000 }}, {{ SH4CTX_FR1, 0x40a00000 }}})
SH4_TEST(fnegd, SH4Test {(uint8_t *)"\x4d\xf0\x0b\x00\x09\x00", 6, {{ SH4CTX_FPSCR, 0x000c0001 }, { SH4CTX_DR0, 0x4014000000000000 }}, {{ SH4CTX_DR0, 0xc014000000000000 }}})
SH4_TEST(fnegf, SH4Test {(uint8_t *)"\x4d\xf0\x0b\x00\x09\x00", 6, {{ SH4CTX_FR0, 0x40800000 }}, {{ SH4CTX_FR0, 0xc0800000 }}})
SH4_TEST(frchg, SH4Test {(uint8_t *)"\x0b\xd0\x6a\x01\x08\xf0\xfd\xfb\x6a\x02\x0a\xf0\x02\x63\xfd\xfb\x0a\xf0\x02\x64\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x00\x00\x50\x41\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x20\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 64, {}, {{ SH4CTX_R1, 0x00040001 }, { SH4CTX_R2, 0x00240001 }, { SH4CTX_R3, 0x0 }, { SH4CTX_R4, 0x41500000 }}})
SH4_TEST(fsca, SH4Test {(uint8_t *)"\x5a\x40\xfd\xf2\x0b\x00\x09\x00", 8, {{ SH4CTX_R0, 16384 }}, {{ SH4CTX_FR2, 0x3f800000 }, { SH4CTX_FR3, 0xb33bbd2e }}})
SH4_TEST(fschg, SH4Test {(uint8_t *)"\x6a\x00\xfd\xf3\x6a\x01\x0b\x00\x09\x00", 10, {}, {{ SH4CTX_R0, 0x00040001 }, { SH4CTX_R1, 0x00140001 }}})
SH4_TEST(fsrra, SH4Test {(uint8_t *)"\x7d\xf0\x0b\x00\x09\x00", 6, {{ SH4CTX_FR0, 0x40800000 }}, {{ SH4CTX_FR0, 0x3f000000 }}})
SH4_TEST(fsqrtd, SH4Test {(uint8_t *)"\x6d\xf0\x0b\x00\x09\x00", 6, {{ SH4CTX_FPSCR, 0x000c0001 }, { SH4CTX_DR0, 0x4010000000000000 }}, {{ SH4CTX_DR0, 0x4000000000000000 }}})
SH4_TEST(fsqrtf, SH4Test {(uint8_t *)"\x6d\xf0\x0b\x00\x09\x00", 6, {{ SH4CTX_FR0, 0x40800000 }}, {{ SH4CTX_FR0, 0x40000000 }}})
SH4_TEST(fsubd, SH4Test {(uint8_t *)"\x01\xf2\x0b\x00\x09\x00", 6, {{ SH4CTX_FPSCR, 0x000c0001 }, { SH4CTX_DR0, 0xc01c000000000000 }, { SH4CTX_DR2, 0xc010000000000000 }}, {{ SH4CTX_DR2, 0x4008000000000000 }}})
SH4_TEST(fsubf, SH4Test {(uint8_t *)"\x01\xf1\x0b\x00\x09\x00", 6, {{ SH4CTX_FR0, 0x40400000 }, { SH4CTX_FR1, 0xbf800000 }}, {{ SH4CTX_FR1, 0xc0800000 }}})
SH4_TEST(ftrcd, SH4Test {(uint8_t *)"\x3d\xf0\x5a\x00\x0b\x00\x09\x00", 8, {{ SH4CTX_FPSCR, 0x000c0001 }, { SH4CTX_DR0, 0xc012cccccccccccd }}, {{ SH4CTX_R0, 0xfffffffc }}})
SH4_TEST(ftrcf, SH4Test {(uint8_t *)"\x3d\xf0\x5a\x00\x0b\x00\x09\x00", 8, {{ SH4CTX_FR0, 0xc0966666 }}, {{ SH4CTX_R0, 0xfffffffc }}})
SH4_TEST(ftrv, SH4Test {(uint8_t *)"\xfd\xf5\x0b\x00\x09\x00", 6, {{ SH4CTX_XF0, 0x3f800000 }, { SH4CTX_XF1, 0x00000000 }, { SH4CTX_XF2, 0x00000000 }, { SH4CTX_XF3, 0x00000000 }, { SH4CTX_XF4, 0x00000000 }, { SH4CTX_XF5, 0x40000000 }, { SH4CTX_XF6, 0x00000000 }, { SH4CTX_XF7, 0x00000000 }, { SH4CTX_XF8, 0x00000000 }, { SH4CTX_XF9, 0x00000000 }, { SH4CTX_XF10, 0x3f800000 }, { SH4CTX_XF11, 0x00000000 }, { SH4CTX_XF12, 0x00000000 }, { SH4CTX_XF13, 0x00000000 }, { SH4CTX_XF14, 0x00000000 }, { SH4CTX_XF15, 0x3f800000 }, { SH4CTX_FR4, 0x40000000 }, { SH4CTX_FR5, 0x40800000 }, { SH4CTX_FR6, 0x41000000 }, { SH4CTX_FR7, 0x00000000 }}, {{ SH4CTX_FR4, 0x40000000 }, { SH4CTX_FR5, 0x41000000 }, { SH4CTX_FR6, 0x41000000 }, { SH4CTX_FR7, 0x00000000 }}})
SH4_TEST(jmp, SH4Test {(uint8_t *)"\x02\xd0\x2b\x40\x09\x00\x01\xe1\x0b\x00\x0d\x71\x08\x00\x01\x8c", 16, {{ SH4CTX_R1, 0 }}, {{ SH4CTX_R1, 13 }}})
SH4_TEST(jsr, SH4Test {(uint8_t *)"\x22\x4f\x04\xd0\x0b\x40\x01\x71\x03\x71\x26\x4f\x0b\x00\x09\x00\x0b\x00\x09\x71\x10\x00\x01\x8c", 24, {{ SH4CTX_R1, 0 }}, {{ SH4CTX_R1, 13 }}})
SH4_TEST(ldc, SH4Test {(uint8_t *)"\x01\xe2\x17\xd0\x0e\x40\x63\xe2\x02\x02\x11\xd0\x22\x20\x18\xd0\x0e\x40\x0f\xd0\x02\x63\x01\xe0\xce\x40\x63\xe4\xc2\x04\x02\xe0\x1e\x40\x12\x05\x03\xe0\x2e\x40\x22\x06\x04\xe0\x3e\x40\x32\x07\x05\xe0\x4e\x40\x42\x08\x07\xe0\xfa\x40\xfa\x0a\x0b\x00\x09\x00\x00\x00\x00\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x40\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x50\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x70\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 128, {}, {{ SH4CTX_R2, 1 }, { SH4CTX_R3, 0x500000f0 }, { SH4CTX_R4, 1 }, { SH4CTX_R5, 2 }, { SH4CTX_R6, 3 }, { SH4CTX_R7, 4 }, { SH4CTX_R8, 5 }, { SH4CTX_R10, 7 }}})
SH4_TEST(ldcl, SH4Test {(uint8_t *)"\x01\xe2\x3b\xd0\x07\x40\x63\xe2\x31\xd1\x03\x41\x12\x63\x04\x88\x29\x00\x0c\x33\x2a\xd0\x10\x30\x29\x00\x0c\x33\x28\xd0\x32\x20\x37\xd0\x07\x40\x26\xd0\x02\x63\x25\xd0\x01\xe1\x12\x20\x2c\xd1\xc7\x40\x63\xe4\xc3\x41\x12\x64\x00\x31\x29\x00\x0c\x34\x20\xd0\x02\xe1\x12\x20\x26\xd1\x17\x40\x13\x41\x12\x65\x00\x31\x29\x00\x0c\x35\x1b\xd0\x03\xe1\x12\x20\x21\xd1\x27\x40\x23\x41\x12\x66\x00\x31\x29\x00\x0c\x36\x16\xd0\x04\xe1\x12\x20\x1c\xd1\x37\x40\x33\x41\x12\x67\x00\x31\x29\x00\x0c\x37\x11\xd0\x05\xe1\x12\x20\x17\xd1\x47\x40\x43\x41\x12\x68\x00\x31\x29\x00\x0c\x38\x0c\xd0\x07\xe1\x12\x20\x12\xd1\xf6\x40\xf2\x41\x12\x6a\x00\x31\x29\x00\x0c\x3a\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x50\xf0\x00\x00\x70\x00\x00\x00\x00\x00\x00\x00\x00\xb8\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xbc\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xc0\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb0\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb4\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 272, {}, {{ SH4CTX_R2, 1 }, { SH4CTX_R3, 0x500000f2 }, { SH4CTX_R4, 2 }, { SH4CTX_R5, 3 }, { SH4CTX_R6, 4 }, { SH4CTX_R7, 5 }, { SH4CTX_R8, 6 }, { SH4CTX_R10, 8 }}})
SH4_TEST(lds, SH4Test {(uint8_t *)"\x0a\x40\x0a\x02\x1a\x40\x1a\x03\x2a\x05\x2a\x40\x2a\x04\x2a\x45\x6a\x41\x6a\x05\x5a\x40\x5a\x06\x0b\x00\x09\x00", 28, {{ SH4CTX_R0, 13 }, { SH4CTX_R1, 0xffd40001 }}, {{ SH4CTX_R2, 13 }, { SH4CTX_R3, 13 }, { SH4CTX_R4, 13 }, { SH4CTX_R5, 0x00140001 }, { SH4CTX_R6, 13 }}})
SH4_TEST(ldsl, SH4Test {(uint8_t *)"\x1f\xd0\x23\xd1\x0a\xe2\x22\x20\x06\x40\x02\x41\x12\x63\x00\x31\x29\x00\x0c\x33\x1a\xd0\x1e\xd1\x0b\xe2\x22\x20\x16\x40\x12\x41\x12\x64\x00\x31\x29\x00\x0c\x34\x2a\x06\x15\xd0\x18\xd1\x0c\xe2\x22\x20\x26\x40\x22\x41\x12\x65\x00\x31\x29\x00\x0c\x35\x2a\x46\x0f\xd0\x13\xd1\x16\xd2\x22\x20\x66\x40\x62\x41\x12\x66\x00\x31\x29\x00\x0c\x36\x0a\xd0\x0e\xd1\x0d\xe2\x22\x20\x56\x40\x52\x41\x12\x67\x00\x31\x29\x00\x0c\x37\x0b\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x00\x00\x00\x00\x00\x09\x00\x09\x00\x09\x00\x09\x00\x70\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x78\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x01\x00\xd4\xff\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 176, {}, {{ SH4CTX_R3, 0xb }, { SH4CTX_R4, 0xc }, { SH4CTX_R5, 0xd }, { SH4CTX_R6, 0x00140002 }, { SH4CTX_R7, 0xe }}})
SH4_TEST(mova, SH4Test {(uint8_t *)"\x03\xc7\x02\x62\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xe8\xff\xff\xff\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 32, {}, {{ SH4CTX_R2, -24 }}})
SH4_TEST(movb, SH4Test {(uint8_t *)"\x13\xd0\x00\x62\x2c\x32\x20\x20\x00\x62\x11\xd0\x01\x70\x04\x63\x3c\x33\x34\x20\x00\x63\x0e\xd4\x42\x84\x0c\x30\x42\x80\x42\x84\x03\x64\x0b\xd0\x03\xe1\x1c\x05\x5c\x35\x54\x01\x1c\x05\x08\xd0\x1e\x40\x04\xc4\x0c\x30\x04\xc0\x04\xc4\x03\x66\x0b\x00\x09\x00\xf4\xf3\xf2\xf1\xf0\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x40\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 96, {}, {{ SH4CTX_R2, -24 }, { SH4CTX_R3, -26 }, { SH4CTX_R4, -28 }, { SH4CTX_R5, -30 }, { SH4CTX_R6, -32 }}})
SH4_TEST(movl, SH4Test {(uint8_t *)"\x13\xd2\x1b\xd0\x04\x70\x02\x63\x3c\x33\x32\x20\x02\x63\x18\xd0\x08\x70\x06\x64\x4c\x34\x46\x20\x02\x64\x15\xd5\x53\x50\x0c\x30\x03\x15\x53\x50\x03\x65\x12\xd0\x10\xe1\x1e\x06\x6c\x36\x66\x01\x1e\x06\x0f\xd0\x1e\x40\x05\xc6\x0c\x30\x05\xc2\x05\xc6\x03\x67\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xe8\xff\xff\xff\xf3\xff\xff\xff\xf2\xff\xff\xff\xf1\xff\xff\xff\xf0\xff\xff\xff\xef\xff\xff\xff\x09\x00\x09\x00\x09\x00\x09\x00\x50\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 128, {}, {{ SH4CTX_R2, -24 }, { SH4CTX_R3, -26 }, { SH4CTX_R4, -28 }, { SH4CTX_R5, -30 }, { SH4CTX_R6, -32 }, { SH4CTX_R7, -34 }}})
SH4_TEST(movt, SH4Test {(uint8_t *)"\x03\x88\x29\x01\x05\x88\x29\x02\x0b\x00\x09\x00", 12, {{ SH4CTX_R0, 3 }}, {{ SH4CTX_R1, 1 }, { SH4CTX_R2, 0 }}})
SH4_TEST(movw, SH4Test {(uint8_t *)"\x26\x92\x17\xd0\x02\x70\x01\x63\x3c\x33\x31\x20\x01\x63\x14\xd0\x04\x70\x05\x64\x4c\x34\x45\x20\x01\x64\x11\xd5\x53\x85\x0c\x30\x53\x81\x53\x85\x03\x65\x0e\xd0\x08\xe1\x1d\x06\x6c\x36\x65\x01\x1d\x06\x0b\xd0\x1e\x40\x05\xc5\x0c\x30\x05\xc1\x05\xc5\x03\x67\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xe8\xff\xf3\xff\xf2\xff\xf1\xff\xf0\xff\xef\xff\x09\x00\x09\x00\x50\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 112, {}, {{ SH4CTX_R2, -24 }, { SH4CTX_R3, -26 }, { SH4CTX_R4, -28 }, { SH4CTX_R5, -30 }, { SH4CTX_R6, -32 }, { SH4CTX_R7, -34 }}})
SH4_TEST(mul, SH4Test {(uint8_t *)"\x07\x01\x1a\x01\x2f\x23\x1a\x03\x0b\x00\x09\x00", 12, {{ SH4CTX_R0, 0xfffffffe }, { SH4CTX_R1, 0x00005555 }, { SH4CTX_R2, 0xfffffffe }, { SH4CTX_R3, 0x00005555 }, { SH4CTX_R4, 0x00000002 }, { SH4CTX_R5, 0xffffaaaa }}, {{ SH4CTX_R1, 0xffff5556 }, { SH4CTX_R3, 0xffff5556 }}})
SH4_TEST(neg, SH4Test {(uint8_t *)"\x2b\x64\x0e\x40\x2a\x65\x02\x06\x0e\x40\x3a\x67\x02\x08\x0e\x41\x2a\x69\x02\x0a\x0e\x41\x3a\x6b\x02\x0c\x0b\x00\x09\x00", 30, {{ SH4CTX_R0, 0x700000f0 }, { SH4CTX_R1, 0x700000f1 }, { SH4CTX_R2, -4 }, { SH4CTX_R3, 0 }}, {{ SH4CTX_R4, 4 }, { SH4CTX_R5, 4 }, { SH4CTX_R6, 0x700000f1 }, { SH4CTX_R7, 0 }, { SH4CTX_R8, 0x700000f0 }, { SH4CTX_R9, 3 }, { SH4CTX_R10, 0x700000f1 }, { SH4CTX_R11, 0xffffffff }, { SH4CTX_R12, 0x700000f1 }}})
SH4_TEST(not, SH4Test {(uint8_t *)"\x07\x61\x0b\x00\x09\x00", 6, {{ SH4CTX_R0, 0xf0f0f0f0 }}, {{ SH4CTX_R1, 0x0f0f0f0f }}})
SH4_TEST(or, SH4Test {(uint8_t *)"\x0b\x21\xff\xcb\x03\x62\x0a\xd0\x1e\x40\x04\xe0\x3f\xcf\x01\xc6\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x00\xfc\x00\x00\x00\x09\x00\x09\x00\x09\x00\x09\x00\x20\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 64, {{ SH4CTX_R0, 0xffffff00 }, { SH4CTX_R1, 0x00ffffff }}, {{ SH4CTX_R2, 0xffffffff }}})
SH4_TEST(rot, SH4Test {(uint8_t *)"\x1b\xd2\x04\x42\x02\x00\x01\xc9\x03\x63\x1a\xd4\x04\x44\x02\x00\x01\xc9\x03\x65\x17\xd6\x05\x46\x02\x00\x01\xc9\x03\x67\x14\xd8\x05\x48\x02\x00\x01\xc9\x03\x69\x02\x00\x12\xd1\x19\x20\x0e\x40\x10\xda\x24\x4a\x02\x00\x01\xc9\x03\x6b\x02\x00\x01\xcb\x0e\x40\x0b\xdc\x24\x4c\x02\x00\x01\xc9\x03\x6d\x02\x00\x09\xd1\x19\x20\x0e\x40\x07\xde\x25\x4e\x02\x00\x01\xc9\x03\x6f\x02\x00\x01\xcb\x0e\x40\x04\xd1\x25\x41\x02\x00\x01\xc9\x0b\x00\x09\x00\x09\x00\xff\xff\xff\x7f\xfe\xff\xff\xff\x09\x00\x09\x00\x09\x00\x09\x00\x70\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 144, {}, {{ SH4CTX_R2, 0xfffffffe }, { SH4CTX_R3, 0 }, { SH4CTX_R4, 0xfffffffd }, { SH4CTX_R5, 1 }, { SH4CTX_R6, 0x7fffffff }, { SH4CTX_R7, 0 }, { SH4CTX_R8, 0xbfffffff }, { SH4CTX_R9, 1 }, { SH4CTX_R10, 0xfffffffc }, { SH4CTX_R11, 1 }, { SH4CTX_R12, 0xffffffff }, { SH4CTX_R13, 0 }, { SH4CTX_R14, 0x3fffffff }, { SH4CTX_R15, 1 }, { SH4CTX_R1, 0xffffffff }, { SH4CTX_R0, 0 }}})
SH4_TEST(sha, SH4Test {(uint8_t *)"\x1c\x42\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xec\xff\xff\xff\xe0\xff\xff\xff\x00\x00\x18\x80\x14\x00\x00\x00\x01\xf8\xff\xff\x01\x00\x00\x80\x09\x00\x09\x00\x09\x00\x09\x00", 48, {{ SH4CTX_R1, 0xffffffe0 }, { SH4CTX_R2, 0x80180000 }}, {{ SH4CTX_R2, 0xffffffff }}})
SH4_TEST(shl, SH4Test {(uint8_t *)"\x0b\xd1\x0d\xd2\x1d\x42\x0b\xd1\x0b\xd3\x1d\x43\x0b\xd1\x0c\xd4\x1d\x44\x0c\xd5\x00\x45\x02\x00\x01\xc9\x03\x66\x09\xd7\x01\x47\x02\x00\x01\xc9\x03\x68\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\xec\xff\xff\xff\xe0\xff\xff\xff\x00\x00\x18\x80\x14\x00\x00\x00\x01\xf8\xff\xff\x01\x00\x00\x80\x09\x00\x09\x00\x09\x00\x09\x00", 80, {}, {{ SH4CTX_R2, 0x00000801 }, { SH4CTX_R3, 0x0 }, { SH4CTX_R4, 0x80100000 }, { SH4CTX_R5, 0x00000002 }, { SH4CTX_R6, 1 }, { SH4CTX_R7, 0x40000000 }, { SH4CTX_R8, 1 }}})
SH4_TEST(sub, SH4Test {(uint8_t *)"\x18\x32\x0b\x00\x09\x00", 6, {{ SH4CTX_R1, -24 }, { SH4CTX_R2, -11 }}, {{ SH4CTX_R2, 13 }}})
SH4_TEST(subc, SH4Test {(uint8_t *)"\x2a\x31\x02\x00\x01\xc9\x03\x62\x4a\x33\x02\x00\x01\xc9\x03\x64\x6a\x35\x02\x00\x01\xc9\x03\x66\x0b\x00\x09\x00", 28, {{ SH4CTX_R1, 1 }, { SH4CTX_R2, 1 }, { SH4CTX_R3, 0 }, { SH4CTX_R4, 1 }, { SH4CTX_R5, 0 }, { SH4CTX_R6, 1 }}, {{ SH4CTX_R1, 0x0 }, { SH4CTX_R2, 0 }, { SH4CTX_R3, 0xffffffff }, { SH4CTX_R4, 1 }, { SH4CTX_R5, 0xfffffffe }, { SH4CTX_R6, 1 }}})
SH4_TEST(subv, SH4Test {(uint8_t *)"\x27\xd0\x23\xd1\x0b\x31\x02\x00\x01\xc9\x03\x62\x20\xd0\x24\xd3\x0b\x33\x02\x00\x01\xc9\x03\x64\xff\xe0\x21\xd5\x0b\x35\x02\x00\x01\xc9\x03\x66\xff\xe0\x1a\xd7\x0b\x37\x02\x00\x01\xc9\x03\x68\x01\xe0\x13\xd9\x0b\x39\x02\x00\x01\xc9\x03\x6a\x01\xe0\x0c\xdb\x0b\x3b\x02\x00\x01\xc9\x03\x6c\x0d\xd0\x09\xdd\x0b\x3d\x02\x00\x01\xc9\x03\x6e\x06\xd0\x0a\xdf\x0b\x3f\x02\x00\x01\xc9\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x01\x00\x00\x80\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x80\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xff\xff\xff\x7f\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xfe\xff\xff\x7f\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 176, {}, {{ SH4CTX_R1, 0x00000001 }, { SH4CTX_R2, 0 }, { SH4CTX_R3, 0xffffffff }, { SH4CTX_R4, 0 }, { SH4CTX_R5, 0x7fffffff }, { SH4CTX_R6, 0 }, { SH4CTX_R7, 0x80000000 }, { SH4CTX_R8, 1 }, { SH4CTX_R9, 0x7fffffff }, { SH4CTX_R10, 1 }, { SH4CTX_R11, 0x80000000 }, { SH4CTX_R12, 0 }, { SH4CTX_R13, 0x00000001 }, { SH4CTX_R14, 0 }, { SH4CTX_R15, 0xffffffff }, { SH4CTX_R0, 0 }}})
SH4_TEST(swap, SH4Test {(uint8_t *)"\x08\x61\x09\x62\x23\x63\x1d\x23\x0b\x00\x09\x00", 12, {{ SH4CTX_R0, 0xfffffff0 }}, {{ SH4CTX_R1, 0xfffff0ff }, { SH4CTX_R2, 0xfff0ffff }, { SH4CTX_R3, 0xf0fffff0 }}})
SH4_TEST(tst, SH4Test {(uint8_t *)"\x1b\xd1\x1b\x41\x02\x00\x01\xc9\x03\x62\x1b\x41\x02\x00\x01\xc9\x03\x63\x12\x64\x13\xd0\x14\xd1\x18\x20\x02\x00\x01\xc9\x03\x65\x11\xd0\x11\xd1\x18\x20\x02\x00\x01\xc9\x03\x66\x0e\xd0\xff\xc8\x02\x00\x01\xc9\x03\x67\x0b\xd0\xff\xc8\x02\x00\x01\xc9\x03\x68\x0b\xd0\x1e\x40\x08\xe0\xff\xcc\x02\x00\x01\xc9\x03\x69\x08\xd0\x1e\x40\x04\xe0\xff\xcc\x02\x00\x01\xc9\x03\x6a\x0b\x00\x09\x00\x00\x00\x00\x00\xff\xff\x00\x00\x00\x00\xff\xff\x09\x00\x09\x00\x60\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 128, {}, {{ SH4CTX_R2, 1 }, { SH4CTX_R3, 0 }, { SH4CTX_R4, 128 }, { SH4CTX_R5, 1 }, { SH4CTX_R6, 0 }, { SH4CTX_R7, 1 }, { SH4CTX_R8, 0 }, { SH4CTX_R9, 1 }}})
SH4_TEST(xor, SH4Test {(uint8_t *)"\x0a\x21\xff\xca\x0b\x00\x09\x00", 8, {{ SH4CTX_R0, 0x00ffffff }, { SH4CTX_R1, 0xffffff00 }, { SH4CTX_R2, 0x000000fc }}, {{ SH4CTX_R0, 0x00ffff00 }, { SH4CTX_R1, 0xff0000ff }}})
SH4_TEST(test_add, SH4Test {0x0, (uint8_t *)"\x0c\x31\x0b\x00\x09\x00", 6, {{ SH4CTX_R0, -4 }, { SH4CTX_R1, 17 }}, {{ SH4CTX_R1, 13 }}})
SH4_TEST(test_addc_carry_t0, SH4Test {0x8, (uint8_t *)"\x1e\x30\x29\x01\x0b\x00\x09\x00\x1e\x30\x29\x01\x0b\x00\x09\x00\x18\x00\x1e\x30\x29\x01\x0b\x00\x09\x00", 26, {{ SH4CTX_R0, 0xffffffff }, { SH4CTX_R1, 0x1 }}, {{ SH4CTX_R0, 0x0 }, { SH4CTX_R1, 1 }}})
SH4_TEST(test_addc_carry_t1, SH4Test {0x10, (uint8_t *)"\x1e\x30\x29\x01\x0b\x00\x09\x00\x1e\x30\x29\x01\x0b\x00\x09\x00\x18\x00\x1e\x30\x29\x01\x0b\x00\x09\x00", 26, {{ SH4CTX_R0, 0xffffffff }, { SH4CTX_R1, 0x1 }}, {{ SH4CTX_R0, 0x1 }, { SH4CTX_R1, 1 }}})
SH4_TEST(test_addc_nocarry, SH4Test {0x0, (uint8_t *)"\x1e\x30\x29\x01\x0b\x00\x09\x00\x1e\x30\x29\x01\x0b\x00\x09\x00\x18\x00\x1e\x30\x29\x01\x0b\x00\x09\x00", 26, {{ SH4CTX_R0, 0xfffffffe }, { SH4CTX_R1, 0x1 }}, {{ SH4CTX_R0, 0xffffffff }, { SH4CTX_R1, 0 }}})
SH4_TEST(test_addv_ppp, SH4Test {0x0, (uint8_t *)"\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00", 64, {{ SH4CTX_R0, 0x1 }, { SH4CTX_R1, 0x7ffffffe }}, {{ SH4CTX_R1, 0x7fffffff }, { SH4CTX_R0, 0 }}})
SH4_TEST(test_addv_ppn_overflow, SH4Test {0x8, (uint8_t *)"\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00", 64, {{ SH4CTX_R0, 0x1 }, { SH4CTX_R1, 0x7fffffff }}, {{ SH4CTX_R1, 0x80000000 }, { SH4CTX_R0, 1 }}})
SH4_TEST(test_addv_npn, SH4Test {0x28, (uint8_t *)"\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00", 64, {{ SH4CTX_R0, 0x1 }, { SH4CTX_R1, 0x80000000 }}, {{ SH4CTX_R1, 0x80000001 }, { SH4CTX_R0, 0 }}})
SH4_TEST(test_addv_nnp_overflow, SH4Test {0x30, (uint8_t *)"\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00", 64, {{ SH4CTX_R0, 0xffffffff }, { SH4CTX_R1, 0x80000000 }}, {{ SH4CTX_R1, 0x7fffffff }, { SH4CTX_R0, 1 }}})
SH4_TEST(test_addv_npp, SH4Test {0x20, (uint8_t *)"\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00", 64, {{ SH4CTX_R0, 0x7fffffff }, { SH4CTX_R1, 0x80000001 }}, {{ SH4CTX_R1, 0x00000000 }, { SH4CTX_R0, 0 }}})
SH4_TEST(test_addv_pnp, SH4Test {0x10, (uint8_t *)"\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00", 64, {{ SH4CTX_R0, 0x80000001 }, { SH4CTX_R1, 0x7fffffff }}, {{ SH4CTX_R1, 0x00000000 }, { SH4CTX_R0, 0 }}})
SH4_TEST(test_addv_nnn, SH4Test {0x38, (uint8_t *)"\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00", 64, {{ SH4CTX_R0, 0xffffffff }, { SH4CTX_R1, 0x80000001 }}, {{ SH4CTX_R1, 0x80000000 }, { SH4CTX_R0, 0 }}})
SH4_TEST(test_addv_pnn, SH4Test {0x18, (uint8_t *)"\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00\x0f\x31\x29\x00\x0b\x00\x09\x00", 64, {{ SH4CTX_R0, 0x80000000 }, { SH4CTX_R1, 0x1 }}, {{ SH4CTX_R1, 0x80000001 }, { SH4CTX_R0, 0 }}})
SH4_TEST(test_and_imm, SH4Test {0x6, (uint8_t *)"\x09\x21\x0b\x00\x09\x00\xf0\xc9\x0b\x00\x09\x00\x08\xd0\x1e\x40\x04\xe0\x3f\xcd\x01\xc6\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x00\xfc\x00\x00\x00\x09\x00\x09\x00\x09\x00\x09\x00\x20\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 64, {{ SH4CTX_R0, 0x00ffffff }}, {{ SH4CTX_R0, 0xf0 }}})
SH4_TEST(test_and_disp, SH4Test {0xc, (uint8_t *)"\x09\x21\x0b\x00\x09\x00\xf0\xc9\x0b\x00\x09\x00\x08\xd0\x1e\x40\x04\xe0\x3f\xcd\x01\xc6\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x00\xfc\x00\x00\x00\x09\x00\x09\x00\x09\x00\x09\x00\x20\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 64, {}, {{ SH4CTX_R0, 0x3c }}})
SH4_TEST(test_and, SH4Test {0x0, (uint8_t *)"\x09\x21\x0b\x00\x09\x00\xf0\xc9\x0b\x00\x09\x00\x08\xd0\x1e\x40\x04\xe0\x3f\xcd\x01\xc6\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x00\xfc\x00\x00\x00\x09\x00\x09\x00\x09\x00\x09\x00\x20\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 64, {{ SH4CTX_R0, 0x00ffffff }, { SH4CTX_R1, 0xffffff00 }}, {{ SH4CTX_R1, 0xffff00 }}})
SH4_TEST(test_bf, SH4Test {0x0, (uint8_t *)"\x07\x88\x01\x8b\x0b\x00\x09\x00\x03\xe1\x0b\x00\x09\x00\x07\x88\x02\x8f\x06\x71\x0b\x00\x09\x00\x07\x71\x0b\x00\x09\x00", 30, {{ SH4CTX_R0, 8 }, { SH4CTX_R1, 0 }}, {{ SH4CTX_R1, 3 }}})
SH4_TEST(test_bfs, SH4Test {0xe, (uint8_t *)"\x07\x88\x01\x8b\x0b\x00\x09\x00\x03\xe1\x0b\x00\x09\x00\x07\x88\x02\x8f\x06\x71\x0b\x00\x09\x00\x07\x71\x0b\x00\x09\x00", 30, {{ SH4CTX_R0, 8 }, { SH4CTX_R1, 0 }}, {{ SH4CTX_R1, 13 }}})
SH4_TEST(test_bra, SH4Test {0x0, (uint8_t *)"\x01\xa0\x09\x00\x01\x70\x09\x70\x0b\x00\x09\x00", 12, {{ SH4CTX_R0, 4 }}, {{ SH4CTX_R0, 13 }}})
SH4_TEST(test_braf, SH4Test {0x0, (uint8_t *)"\x23\x00\x09\x00\x07\x71\x09\x71\x0b\x00\x09\x00", 12, {{ SH4CTX_R0, 2 }, { SH4CTX_R1, 4 }}, {{ SH4CTX_R1, 13 }}})
SH4_TEST(test_bsr, SH4Test {0x0, (uint8_t *)"\x22\x4f\x04\xb0\x01\x70\x03\x70\x26\x4f\x0b\x00\x09\x00\x09\x70\x0b\x00\x09\x00", 20, {}, {{ SH4CTX_R0, 13 }}})
SH4_TEST(test_bsrf, SH4Test {0x0, (uint8_t *)"\x22\x4f\x03\x00\x01\x71\x03\x71\x26\x4f\x0b\x00\x09\x00\x09\x71\x0b\x00\x09\x00", 20, {{ SH4CTX_R0, 8 }}, {{ SH4CTX_R1, 13 }}})
SH4_TEST(test_bt, SH4Test {0x0, (uint8_t *)"\x07\x88\x01\x89\x0b\x00\x09\x00\x03\xe1\x0b\x00\x09\x00\x07\x88\x02\x8d\x06\x71\x0b\x00\x09\x00\x07\x71\x0b\x00\x09\x00", 30, {{ SH4CTX_R0, 7 }, { SH4CTX_R1, 0 }}, {{ SH4CTX_R1, 3 }}})
SH4_TEST(test_bts, SH4Test {0xe, (uint8_t *)"\x07\x88\x01\x89\x0b\x00\x09\x00\x03\xe1\x0b\x00\x09\x00\x07\x88\x02\x8d\x06\x71\x0b\x00\x09\x00\x07\x71\x0b\x00\x09\x00", 30, {{ SH4CTX_R0, 7 }, { SH4CTX_R1, 0 }}, {{ SH4CTX_R1, 13 }}})
SH4_TEST(test_cmpgt, SH4Test {0x48, (uint8_t *)"\x0d\x88\x29\x01\x11\x88\x29\x02\x0b\x00\x09\x00\x00\x30\x29\x02\x00\x32\x29\x04\x0b\x00\x09\x00\x12\x30\x29\x02\x12\x31\x29\x03\x02\x31\x29\x04\x0b\x00\x09\x00\x13\x30\x29\x02\x13\x31\x29\x03\x03\x31\x29\x04\x0b\x00\x09\x00\x16\x30\x29\x02\x16\x31\x29\x03\x06\x31\x29\x04\x0b\x00\x09\x00\x17\x30\x29\x02\x17\x31\x29\x03\x07\x31\x29\x04\x0b\x00\x09\x00\x11\x40\x29\x03\x11\x41\x29\x04\x11\x42\x29\x05\x0b\x00\x09\x00\x15\x40\x29\x03\x15\x41\x29\x04\x15\x42\x29\x05\x0b\x00\x09\x00\x0c\x21\x29\x04\x2c\x21\x29\x05\x3c\x21\x29\x06\x0b\x00\x09\x00", 136, {{ SH4CTX_R0, -1 }, { SH4CTX_R1, 13 }}, {{ SH4CTX_R2, 0 }, { SH4CTX_R3, 0 }, { SH4CTX_R4, 1 }}})
SH4_TEST(test_cmpstr, SH4Test {0x78, (uint8_t *)"\x0d\x88\x29\x01\x11\x88\x29\x02\x0b\x00\x09\x00\x00\x30\x29\x02\x00\x32\x29\x04\x0b\x00\x09\x00\x12\x30\x29\x02\x12\x31\x29\x03\x02\x31\x29\x04\x0b\x00\x09\x00\x13\x30\x29\x02\x13\x31\x29\x03\x03\x31\x29\x04\x0b\x00\x09\x00\x16\x30\x29\x02\x16\x31\x29\x03\x06\x31\x29\x04\x0b\x00\x09\x00\x17\x30\x29\x02\x17\x31\x29\x03\x07\x31\x29\x04\x0b\x00\x09\x00\x11\x40\x29\x03\x11\x41\x29\x04\x11\x42\x29\x05\x0b\x00\x09\x00\x15\x40\x29\x03\x15\x41\x29\x04\x15\x42\x29\x05\x0b\x00\x09\x00\x0c\x21\x29\x04\x2c\x21\x29\x05\x3c\x21\x29\x06\x0b\x00\x09\x00", 136, {{ SH4CTX_R0, 0x00000000 }, { SH4CTX_R1, 0xffffffff }, { SH4CTX_R2, 0x00f00000 }, { SH4CTX_R3, 0x00ff0000 }}, {{ SH4CTX_R4, 0 }, { SH4CTX_R5, 0 }, { SH4CTX_R6, 1 }}})
SH4_TEST(test_cmphs, SH4Test {0x18, (uint8_t *)"\x0d\x88\x29\x01\x11\x88\x29\x02\x0b\x00\x09\x00\x00\x30\x29\x02\x00\x32\x29\x04\x0b\x00\x09\x00\x12\x30\x29\x02\x12\x31\x29\x03\x02\x31\x29\x04\x0b\x00\x09\x00\x13\x30\x29\x02\x13\x31\x29\x03\x03\x31\x29\x04\x0b\x00\x09\x00\x16\x30\x29\x02\x16\x31\x29\x03\x06\x31\x29\x04\x0b\x00\x09\x00\x17\x30\x29\x02\x17\x31\x29\x03\x07\x31\x29\x04\x0b\x00\x09\x00\x11\x40\x29\x03\x11\x41\x29\x04\x11\x42\x29\x05\x0b\x00\x09\x00\x15\x40\x29\x03\x15\x41\x29\x04\x15\x42\x29\x05\x0b\x00\x09\x00\x0c\x21\x29\x04\x2c\x21\x29\x05\x3c\x21\x29\x06\x0b\x00\x09\x00", 136, {{ SH4CTX_R0, -1 }, { SH4CTX_R1, 13 }}, {{ SH4CTX_R2, 1 }, { SH4CTX_R3, 1 }, { SH4CTX_R4, 0 }}})
SH4_TEST(test_cmppz, SH4Test {0x58, (uint8_t *)"\x0d\x88\x29\x01\x11\x88\x29\x02\x0b\x00\x09\x00\x00\x30\x29\x02\x00\x32\x29\x04\x0b\x00\x09\x00\x12\x30\x29\x02\x12\x31\x29\x03\x02\x31\x29\x04\x0b\x00\x09\x00\x13\x30\x29\x02\x13\x31\x29\x03\x03\x31\x29\x04\x0b\x00\x09\x00\x16\x30\x29\x02\x16\x31\x29\x03\x06\x31\x29\x04\x0b\x00\x09\x00\x17\x30\x29\x02\x17\x31\x29\x03\x07\x31\x29\x04\x0b\x00\x09\x00\x11\x40\x29\x03\x11\x41\x29\x04\x11\x42\x29\x05\x0b\x00\x09\x00\x15\x40\x29\x03\x15\x41\x29\x04\x15\x42\x29\x05\x0b\x00\x09\x00\x0c\x21\x29\x04\x2c\x21\x29\x05\x3c\x21\x29\x06\x0b\x00\x09\x00", 136, {{ SH4CTX_R0, -1 }, { SH4CTX_R1, 0 }, { SH4CTX_R2, 1 }}, {{ SH4CTX_R3, 0 }, { SH4CTX_R4, 1 }, { SH4CTX_R5, 1 }}})
SH4_TEST(test_cmppl, SH4Test {0x68, (uint8_t *)"\x0d\x88\x29\x01\x11\x88\x29\x02\x0b\x00\x09\x00\x00\x30\x29\x02\x00\x32\x29\x04\x0b\x00\x09\x00\x12\x30\x29\x02\x12\x31\x29\x03\x02\x31\x29\x04\x0b\x00\x09\x00\x13\x30\x29\x02\x13\x31\x29\x03\x03\x31\x29\x04\x0b\x00\x09\x00\x16\x30\x29\x02\x16\x31\x29\x03\x06\x31\x29\x04\x0b\x00\x09\x00\x17\x30\x29\x02\x17\x31\x29\x03\x07\x31\x29\x04\x0b\x00\x09\x00\x11\x40\x29\x03\x11\x41\x29\x04\x11\x42\x29\x05\x0b\x00\x09\x00\x15\x40\x29\x03\x15\x41\x29\x04\x15\x42\x29\x05\x0b\x00\x09\x00\x0c\x21\x29\x04\x2c\x21\x29\x05\x3c\x21\x29\x06\x0b\x00\x09\x00", 136, {{ SH4CTX_R0, -1 }, { SH4CTX_R1, 0 }, { SH4CTX_R2, 1 }}, {{ SH4CTX_R3, 0 }, { SH4CTX_R4, 0 }, { SH4CTX_R5, 1 }}})
SH4_TEST(test_cmphi, SH4Test {0x38, (uint8_t *)"\x0d\x88\x29\x01\x11\x88\x29\x02\x0b\x00\x09\x00\x00\x30\x29\x02\x00\x32\x29\x04\x0b\x00\x09\x00\x12\x30\x29\x02\x12\x31\x29\x03\x02\x31\x29\x04\x0b\x00\x09\x00\x13\x30\x29\x02\x13\x31\x29\x03\x03\x31\x29\x04\x0b\x00\x09\x00\x16\x30\x29\x02\x16\x31\x29\x03\x06\x31\x29\x04\x0b\x00\x09\x00\x17\x30\x29\x02\x17\x31\x29\x03\x07\x31\x29\x04\x0b\x00\x09\x00\x11\x40\x29\x03\x11\x41\x29\x04\x11\x42\x29\x05\x0b\x00\x09\x00\x15\x40\x29\x03\x15\x41\x29\x04\x15\x42\x29\x05\x0b\x00\x09\x00\x0c\x21\x29\x04\x2c\x21\x29\x05\x3c\x21\x29\x06\x0b\x00\x09\x00", 136, {{ SH4CTX_R0, -1 }, { SH4CTX_R1, 13 }}, {{ SH4CTX_R2, 1 }, { SH4CTX_R3, 0 }, { SH4CTX_R4, 0 }}})
SH4_TEST(test_cmpge, SH4Test {0x28, (uint8_t *)"\x0d\x88\x29\x01\x11\x88\x29\x02\x0b\x00\x09\x00\x00\x30\x29\x02\x00\x32\x29\x04\x0b\x00\x09\x00\x12\x30\x29\x02\x12\x31\x29\x03\x02\x31\x29\x04\x0b\x00\x09\x00\x13\x30\x29\x02\x13\x31\x29\x03\x03\x31\x29\x04\x0b\x00\x09\x00\x16\x30\x29\x02\x16\x31\x29\x03\x06\x31\x29\x04\x0b\x00\x09\x00\x17\x30\x29\x02\x17\x31\x29\x03\x07\x31\x29\x04\x0b\x00\x09\x00\x11\x40\x29\x03\x11\x41\x29\x04\x11\x42\x29\x05\x0b\x00\x09\x00\x15\x40\x29\x03\x15\x41\x29\x04\x15\x42\x29\x05\x0b\x00\x09\x00\x0c\x21\x29\x04\x2c\x21\x29\x05\x3c\x21\x29\x06\x0b\x00\x09\x00", 136, {{ SH4CTX_R0, -1 }, { SH4CTX_R1, 13 }}, {{ SH4CTX_R2, 0 }, { SH4CTX_R3, 1 }, { SH4CTX_R4, 1 }}})
SH4_TEST(test_cmpeq_imm, SH4Test {0x0, (uint8_t *)"\x0d\x88\x29\x01\x11\x88\x29\x02\x0b\x00\x09\x00\x00\x30\x29\x02\x00\x32\x29\x04\x0b\x00\x09\x00\x12\x30\x29\x02\x12\x31\x29\x03\x02\x31\x29\x04\x0b\x00\x09\x00\x13\x30\x29\x02\x13\x31\x29\x03\x03\x31\x29\x04\x0b\x00\x09\x00\x16\x30\x29\x02\x16\x31\x29\x03\x06\x31\x29\x04\x0b\x00\x09\x00\x17\x30\x29\x02\x17\x31\x29\x03\x07\x31\x29\x04\x0b\x00\x09\x00\x11\x40\x29\x03\x11\x41\x29\x04\x11\x42\x29\x05\x0b\x00\x09\x00\x15\x40\x29\x03\x15\x41\x29\x04\x15\x42\x29\x05\x0b\x00\x09\x00\x0c\x21\x29\x04\x2c\x21\x29\x05\x3c\x21\x29\x06\x0b\x00\x09\x00", 136, {{ SH4CTX_R0, 13 }}, {{ SH4CTX_R1, 1 }, { SH4CTX_R2, 0 }}})
SH4_TEST(test_cmpeq, SH4Test {0xc, (uint8_t *)"\x0d\x88\x29\x01\x11\x88\x29\x02\x0b\x00\x09\x00\x00\x30\x29\x02\x00\x32\x29\x04\x0b\x00\x09\x00\x12\x30\x29\x02\x12\x31\x29\x03\x02\x31\x29\x04\x0b\x00\x09\x00\x13\x30\x29\x02\x13\x31\x29\x03\x03\x31\x29\x04\x0b\x00\x09\x00\x16\x30\x29\x02\x16\x31\x29\x03\x06\x31\x29\x04\x0b\x00\x09\x00\x17\x30\x29\x02\x17\x31\x29\x03\x07\x31\x29\x04\x0b\x00\x09\x00\x11\x40\x29\x03\x11\x41\x29\x04\x11\x42\x29\x05\x0b\x00\x09\x00\x15\x40\x29\x03\x15\x41\x29\x04\x15\x42\x29\x05\x0b\x00\x09\x00\x0c\x21\x29\x04\x2c\x21\x29\x05\x3c\x21\x29\x06\x0b\x00\x09\x00", 136, {{ SH4CTX_R0, 13 }, { SH4CTX_R1, 17 }}, {{ SH4CTX_R2, 1 }, { SH4CTX_R3, 0 }}})
SH4_TEST(test_div0s_pdividend_pdivisor, SH4Test {0x16, (uint8_t *)"\x0e\x40\x19\x00\x02\x01\x09\x21\x0b\x00\x09\x00\x0e\x40\x17\x22\x02\x03\x0b\x00\x09\x00\x0e\x40\x17\x22\x02\x03\x0b\x00\x09\x00\x0e\x40\x17\x22\x02\x03\x0b\x00\x09\x00\x0e\x40\x17\x22\x02\x03\x0b\x00\x09\x00", 52, {{ SH4CTX_R0, 0x700000f0 }, { SH4CTX_R1, 0xfffffffe }, { SH4CTX_R2, 0xfffffffc }}, {{ SH4CTX_R3, 0x700003f0 }}})
SH4_TEST(test_div0s_ndividend_pdivisor, SH4Test {0x20, (uint8_t *)"\x0e\x40\x19\x00\x02\x01\x09\x21\x0b\x00\x09\x00\x0e\x40\x17\x22\x02\x03\x0b\x00\x09\x00\x0e\x40\x17\x22\x02\x03\x0b\x00\x09\x00\x0e\x40\x17\x22\x02\x03\x0b\x00\x09\x00\x0e\x40\x17\x22\x02\x03\x0b\x00\x09\x00", 52, {{ SH4CTX_R0, 0x700000f0 }, { SH4CTX_R1, 0x2 }, { SH4CTX_R2, 0xfffffffc }}, {{ SH4CTX_R3, 0x700001f1 }}})
SH4_TEST(test_div0s_ndividend_ndivisor, SH4Test {0xc, (uint8_t *)"\x0e\x40\x19\x00\x02\x01\x09\x21\x0b\x00\x09\x00\x0e\x40\x17\x22\x02\x03\x0b\x00\x09\x00\x0e\x40\x17\x22\x02\x03\x0b\x00\x09\x00\x0e\x40\x17\x22\x02\x03\x0b\x00\x09\x00\x0e\x40\x17\x22\x02\x03\x0b\x00\x09\x00", 52, {{ SH4CTX_R0, 0x700000f0 }, { SH4CTX_R1, 0x2 }, { SH4CTX_R2, 0x4 }}, {{ SH4CTX_R3, 0x700000f0 }}})
SH4_TEST(test_div0u, SH4Test {0x0, (uint8_t *)"\x0e\x40\x19\x00\x02\x01\x09\x21\x0b\x00\x09\x00\x0e\x40\x17\x22\x02\x03\x0b\x00\x09\x00\x0e\x40\x17\x22\x02\x03\x0b\x00\x09\x00\x0e\x40\x17\x22\x02\x03\x0b\x00\x09\x00\x0e\x40\x17\x22\x02\x03\x0b\x00\x09\x00", 52, {{ SH4CTX_R0, 0x700000f0 }}, {{ SH4CTX_R1, 0x700000f0 }}})
SH4_TEST(test_div0s_pdividend_ndivisor, SH4Test {0x2a, (uint8_t *)"\x0e\x40\x19\x00\x02\x01\x09\x21\x0b\x00\x09\x00\x0e\x40\x17\x22\x02\x03\x0b\x00\x09\x00\x0e\x40\x17\x22\x02\x03\x0b\x00\x09\x00\x0e\x40\x17\x22\x02\x03\x0b\x00\x09\x00\x0e\x40\x17\x22\x02\x03\x0b\x00\x09\x00", 52, {{ SH4CTX_R0, 0x700000f0 }, { SH4CTX_R1, 0xfffffffe }, { SH4CTX_R2, 0x4 }}, {{ SH4CTX_R3, 0x700002f1 }}})
SH4_TEST(test_div1s_32_ndividend, SH4Test {0x74, (uint8_t *)"\x28\x42\x3f\x63\x0a\x20\x33\x61\x24\x41\x0a\x33\x27\x23\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x3f\x63\x24\x43\x0e\x33\x3f\x63\x0b\x00\x09\x00\x28\x42\x3f\x63\x0a\x20\x33\x61\x24\x41\x0a\x33\x27\x23\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x3f\x63\x24\x43\x0e\x33\x3f\x63\x0b\x00\x09\x00\x33\x60\x24\x40\x1a\x31\x0a\x20\x0a\x33\x27\x21\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x0e\x33\x0b\x00\x09\x00\x33\x60\x24\x40\x1a\x31\x0a\x20\x0a\x33\x27\x21\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x0e\x33\x0b\x00\x09\x00", 412, {{ SH4CTX_R2, 0x2710 }, { SH4CTX_R3, 0xf0000010 }}, {{ SH4CTX_R3, 0xffff9725 }}})
SH4_TEST(test_div1s_16_ndivisor, SH4Test {0x3a, (uint8_t *)"\x28\x42\x3f\x63\x0a\x20\x33\x61\x24\x41\x0a\x33\x27\x23\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x3f\x63\x24\x43\x0e\x33\x3f\x63\x0b\x00\x09\x00\x28\x42\x3f\x63\x0a\x20\x33\x61\x24\x41\x0a\x33\x27\x23\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x3f\x63\x24\x43\x0e\x33\x3f\x63\x0b\x00\x09\x00\x33\x60\x24\x40\x1a\x31\x0a\x20\x0a\x33\x27\x21\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x0e\x33\x0b\x00\x09\x00\x33\x60\x24\x40\x1a\x31\x0a\x20\x0a\x33\x27\x21\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x0e\x33\x0b\x00\x09\x00", 412, {{ SH4CTX_R2, 0xd8f0 }, { SH4CTX_R3, 0x7fee }}, {{ SH4CTX_R3, 0xfffffffd }}})
SH4_TEST(test_div1s_32_ndivisor, SH4Test {0x108, (uint8_t *)"\x28\x42\x3f\x63\x0a\x20\x33\x61\x24\x41\x0a\x33\x27\x23\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x3f\x63\x24\x43\x0e\x33\x3f\x63\x0b\x00\x09\x00\x28\x42\x3f\x63\x0a\x20\x33\x61\x24\x41\x0a\x33\x27\x23\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x3f\x63\x24\x43\x0e\x33\x3f\x63\x0b\x00\x09\x00\x33\x60\x24\x40\x1a\x31\x0a\x20\x0a\x33\x27\x21\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x0e\x33\x0b\x00\x09\x00\x33\x60\x24\x40\x1a\x31\x0a\x20\x0a\x33\x27\x21\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x0e\x33\x0b\x00\x09\x00", 412, {{ SH4CTX_R2, 0xffffd8f0 }, { SH4CTX_R3, 0x0ffffff0 }}, {{ SH4CTX_R3, 0xffff9725 }}})
SH4_TEST(test_div1s_16_ndividend, SH4Test {0x0, (uint8_t *)"\x28\x42\x3f\x63\x0a\x20\x33\x61\x24\x41\x0a\x33\x27\x23\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x3f\x63\x24\x43\x0e\x33\x3f\x63\x0b\x00\x09\x00\x28\x42\x3f\x63\x0a\x20\x33\x61\x24\x41\x0a\x33\x27\x23\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x24\x33\x3f\x63\x24\x43\x0e\x33\x3f\x63\x0b\x00\x09\x00\x33\x60\x24\x40\x1a\x31\x0a\x20\x0a\x33\x27\x21\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x0e\x33\x0b\x00\x09\x00\x33\x60\x24\x40\x1a\x31\x0a\x20\x0a\x33\x27\x21\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x24\x31\x24\x43\x0e\x33\x0b\x00\x09\x00", 412, {{ SH4CTX_R2, 0x2710 }, { SH4CTX_R3, 0x8012 }}, {{ SH4CTX_R3, 0xfffffffd }}})
SH4_TEST(test_div1u_32_16, SH4Test {0x0, (uint8_t *)"\x28\x40\x19\x00\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x24\x41\x1d\x61\x0b\x00\x09\x00\x19\x00\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x0b\x00\x09\x00", 180, {{ SH4CTX_R0, 0x2710 }, { SH4CTX_R1, 0x0ffffff0 }}, {{ SH4CTX_R1, 0x68db }}})
SH4_TEST(test_div1u_64_32, SH4Test {0x2c, (uint8_t *)"\x28\x40\x19\x00\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x04\x31\x24\x41\x1d\x61\x0b\x00\x09\x00\x19\x00\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x04\x31\x24\x42\x0b\x00\x09\x00", 180, {{ SH4CTX_R0, 0x00002710 }, { SH4CTX_R1, 0x00000001 }, { SH4CTX_R2, 0x2a05f200 }}, {{ SH4CTX_R2, 0x7a120 }}})
SH4_TEST(test_dmulu, SH4Test {0xa, (uint8_t *)"\x0d\x31\x0a\x00\x1a\x01\x0b\x00\x09\x00\x05\x31\x0a\x00\x1a\x01\x0b\x00\x09\x00", 20, {{ SH4CTX_R0, 0xfffffffe }, { SH4CTX_R1, 0x00005555 }}, {{ SH4CTX_R0, 0x00005554 }, { SH4CTX_R1, 0xffff5556 }}})
SH4_TEST(test_dmuls, SH4Test {0x0, (uint8_t *)"\x0d\x31\x0a\x00\x1a\x01\x0b\x00\x09\x00\x05\x31\x0a\x00\x1a\x01\x0b\x00\x09\x00", 20, {{ SH4CTX_R0, 0xfffffffe }, { SH4CTX_R1, 0x00005555 }}, {{ SH4CTX_R0, 0xffffffff }, { SH4CTX_R1, 0xffff5556 }}})
SH4_TEST(test_dt, SH4Test {0x0, (uint8_t *)"\x01\x71\x10\x40\xfc\x8b\x0b\x00\x09\x00", 10, {{ SH4CTX_R0, 13 }, { SH4CTX_R1, 0 }}, {}})
SH4_TEST(test_extsb, SH4Test {0x0, (uint8_t *)"\x0e\x61\x0b\x00\x09\x00\x0f\x61\x0b\x00\x09\x00\x0c\x61\x0b\x00\x09\x00\x0d\x61\x0b\x00\x09\x00", 24, {{ SH4CTX_R0, 0xff }}, {{ SH4CTX_R1, 0xffffffff }}})
SH4_TEST(test_extuw, SH4Test {0x12, (uint8_t *)"\x0e\x61\x0b\x00\x09\x00\x0f\x61\x0b\x00\x09\x00\x0c\x61\x0b\x00\x09\x00\x0d\x61\x0b\x00\x09\x00", 24, {{ SH4CTX_R0, 0xfffa3002 }}, {{ SH4CTX_R1, 0x3002 }}})
SH4_TEST(test_extsw, SH4Test {0x6, (uint8_t *)"\x0e\x61\x0b\x00\x09\x00\x0f\x61\x0b\x00\x09\x00\x0c\x61\x0b\x00\x09\x00\x0d\x61\x0b\x00\x09\x00", 24, {{ SH4CTX_R0, 0xffff }}, {{ SH4CTX_R1, 0xffffffff }}})
SH4_TEST(test_extub, SH4Test {0xc, (uint8_t *)"\x0e\x61\x0b\x00\x09\x00\x0f\x61\x0b\x00\x09\x00\x0c\x61\x0b\x00\x09\x00\x0d\x61\x0b\x00\x09\x00", 24, {{ SH4CTX_R0, 0xfffa3002 }}, {{ SH4CTX_R1, 0x2 }}})
SH4_TEST(test_fabsd, SH4Test {0x0, (uint8_t *)"\x5d\xf2\x0b\x00\x09\x00\x5d\xf1\x0b\x00\x09\x00", 12, {{ SH4CTX_FPSCR, 0x000c0001 }, { SH4CTX_DR2, 0xc010000000000000 }}, {{ SH4CTX_DR2, 0x4010000000000000 }}})
SH4_TEST(test_fabsf, SH4Test {0x6, (uint8_t *)"\x5d\xf2\x0b\x00\x09\x00\x5d\xf1\x0b\x00\x09\x00", 12, {{ SH4CTX_FR1, 0xc0800000 }}, {{ SH4CTX_FR1, 0x40800000 }}})
SH4_TEST(test_faddf, SH4Test {0x6, (uint8_t *)"\x00\xf2\x0b\x00\x09\x00\x00\xf1\x0b\x00\x09\x00", 12, {{ SH4CTX_FR0, 0x40400000 }, { SH4CTX_FR1, 0xbf800000 }}, {{ SH4CTX_FR1, 0x40000000 }}})
SH4_TEST(test_faddd, SH4Test {0x0, (uint8_t *)"\x00\xf2\x0b\x00\x09\x00\x00\xf1\x0b\x00\x09\x00", 12, {{ SH4CTX_FPSCR, 0x000c0001 }, { SH4CTX_DR0, 0x4014000000000000 }, { SH4CTX_DR2, 0xc018000000000000 }}, {{ SH4CTX_DR2, 0xbff0000000000000 }}})
SH4_TEST(test_fcmpeqd, SH4Test {0x0, (uint8_t *)"\x04\xf2\x29\x00\x24\xf4\x29\x01\x0b\x00\x09\x00\x04\xf1\x29\x00\x14\xf2\x29\x01\x0b\x00\x09\x00", 24, {{ SH4CTX_FPSCR, 0x000c0001 }, { SH4CTX_DR0, 0x4014000000000000 }, { SH4CTX_DR2, 0xc018000000000000 }, { SH4CTX_DR4, 0xc018000000000000 }}, {{ SH4CTX_R0, 0 }, { SH4CTX_R1, 1 }}})
SH4_TEST(test_fcmpeqf, SH4Test {0xc, (uint8_t *)"\x04\xf2\x29\x00\x24\xf4\x29\x01\x0b\x00\x09\x00\x04\xf1\x29\x00\x14\xf2\x29\x01\x0b\x00\x09\x00", 24, {{ SH4CTX_FR0, 0x40400000 }, { SH4CTX_FR1, 0xbf800000 }, { SH4CTX_FR2, 0xbf800000 }}, {{ SH4CTX_R0, 0 }, { SH4CTX_R1, 1 }}})
SH4_TEST(test_fcmpgtd, SH4Test {0x0, (uint8_t *)"\x05\xf2\x29\x00\x25\xf0\x29\x01\x0b\x00\x09\x00\x05\xf1\x29\x00\x15\xf0\x29\x01\x0b\x00\x09\x00", 24, {{ SH4CTX_FPSCR, 0x000c0001 }, { SH4CTX_DR0, 0x4014000000000000 }, { SH4CTX_DR2, 0xc018000000000000 }}, {{ SH4CTX_R0, 0 }, { SH4CTX_R1, 1 }}})
SH4_TEST(test_fcmpgtf, SH4Test {0xc, (uint8_t *)"\x05\xf2\x29\x00\x25\xf0\x29\x01\x0b\x00\x09\x00\x05\xf1\x29\x00\x15\xf0\x29\x01\x0b\x00\x09\x00", 24, {{ SH4CTX_FR0, 0x40400000 }, { SH4CTX_FR1, 0xbf800000 }}, {{ SH4CTX_R0, 0 }, { SH4CTX_R1, 1 }}})
SH4_TEST(test_fdivf, SH4Test {0x6, (uint8_t *)"\x03\xf2\x0b\x00\x09\x00\x03\xf1\x0b\x00\x09\x00", 12, {{ SH4CTX_FR0, 0xc0200000 }, { SH4CTX_FR1, 0x41200000 }}, {{ SH4CTX_FR1, 0xc0800000 }}})
SH4_TEST(test_fdivd, SH4Test {0x0, (uint8_t *)"\x03\xf2\x0b\x00\x09\x00\x03\xf1\x0b\x00\x09\x00", 12, {{ SH4CTX_FPSCR, 0x000c0001 }, { SH4CTX_DR0, 0xbfe0000000000000 }, { SH4CTX_DR2, 0xc000000000000000 }}, {{ SH4CTX_DR2, 0x4010000000000000 }}})
SH4_TEST(test_fipr, SH4Test {0x0, (uint8_t *)"\xed\xfd\x0b\x00\x09\x00", 6, {{ SH4CTX_FR4, 0x3f800000 }, { SH4CTX_FR5, 0xc0000000 }, { SH4CTX_FR6, 0xc0400000 }, { SH4CTX_FR7, 0x40800000 }, { SH4CTX_FR12, 0x40800000 }, { SH4CTX_FR13, 0xc0400000 }, { SH4CTX_FR14, 0xc0000000 }, { SH4CTX_FR15, 0x3f800000 }}, {{ SH4CTX_FR15, 0x41a00000 }}})
SH4_TEST(test_flds_fsts, SH4Test {0xc, (uint8_t *)"\x8d\xf0\x0b\x00\x09\x00\x9d\xf0\x0b\x00\x09\x00\x1d\xf0\x0d\xf1\x0b\x00\x09\x00", 20, {{ SH4CTX_FR0, 0x3f800000 }}, {{ SH4CTX_FR1, 0x3f800000 }}})
SH4_TEST(test_fldi0, SH4Test {0x0, (uint8_t *)"\x8d\xf0\x0b\x00\x09\x00\x9d\xf0\x0b\x00\x09\x00\x1d\xf0\x0d\xf1\x0b\x00\x09\x00", 20, {{ SH4CTX_FR0, 0x11111111 }}, {{ SH4CTX_FR0, 0x00000000 }}})
SH4_TEST(test_fldi1, SH4Test {0x6, (uint8_t *)"\x8d\xf0\x0b\x00\x09\x00\x9d\xf0\x0b\x00\x09\x00\x1d\xf0\x0d\xf1\x0b\x00\x09\x00", 20, {}, {{ SH4CTX_FR0, 0x3f800000 }}})
SH4_TEST(test_floatf, SH4Test {0x8, (uint8_t *)"\x5a\x41\x2d\xf2\x0b\x00\x09\x00\x5a\x40\x2d\xf3\x0b\x00\x09\x00", 16, {{ SH4CTX_R0, 0x00000002 }}, {{ SH4CTX_FR3, 0x40000000 }}})
SH4_TEST(test_floatd, SH4Test {0x0, (uint8_t *)"\x5a\x41\x2d\xf2\x0b\x00\x09\x00\x5a\x40\x2d\xf3\x0b\x00\x09\x00", 16, {{ SH4CTX_FPSCR, 0x000c0001 }, { SH4CTX_R1, 0x00000004 }}, {{ SH4CTX_DR2, 0x4010000000000000 }}})
SH4_TEST(test_fmac, SH4Test {0x0, (uint8_t *)"\x1e\xf2\x0b\x00\x09\x00", 6, {{ SH4CTX_FR0, 0xc0000000 }, { SH4CTX_FR1, 0xc0a00000 }, { SH4CTX_FR2, 0x40400000 }}, {{ SH4CTX_FR2, 0x41500000 }}})
SH4_TEST(test_fmovd, SH4Test {0x0, (uint8_t *)"\x1c\xf0\x0c\xf5\x3c\xf7\x16\xd0\x08\xf9\x15\xd0\x08\xf2\x14\xd0\x08\xe1\x16\xfb\x12\xd0\x09\xfd\x09\xff\x15\xd0\x1a\xf0\x06\x62\x06\x63\x13\xd0\x08\x70\x3b\xf0\x06\x64\x06\x65\x10\xd0\x08\xe1\x17\xf1\x08\x70\x06\x66\x06\x67\x0b\x00\x09\x00\x09\x00\x09\x00\x00\x00\x28\x40\x00\x00\x00\x00\x00\x00\x2e\x40\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x40\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x50\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 128, {{ SH4CTX_FPSCR, 0x000c0001 }, { SH4CTX_XD0, 0x4020000000000000 }, { SH4CTX_XD2, 0x4024000000000000 }}, {{ SH4CTX_DR0, 0x4020000000000000 }, { SH4CTX_XD4, 0x4020000000000000 }, { SH4CTX_XD6, 0x4024000000000000 }, { SH4CTX_XD8, 0x4028000000000000 }, { SH4CTX_DR2, 0x4028000000000000 }, { SH4CTX_XD10, 0x402e000000000000 }, { SH4CTX_XD12, 0x4028000000000000 }, { SH4CTX_XD14, 0x402e000000000000 }, { SH4CTX_R2, 0x40200000 }, { SH4CTX_R3, 0x00000000 }, { SH4CTX_R4, 0x40240000 }, { SH4CTX_R5, 0x00000000 }, { SH4CTX_R6, 0x40200000 }, { SH4CTX_R7, 0x00000000 }}})
SH4_TEST(test_fmovf, SH4Test {0x0, (uint8_t *)"\x0c\xf1\x0f\xd0\x08\xf2\x0e\xd0\x04\xe1\x16\xf3\x0c\xd0\x09\xf4\x09\xf5\x0f\xd0\x0a\xf0\x02\x62\x0d\xd0\x08\x70\x2b\xf0\x02\x63\x0b\xd0\x04\xe1\x07\xf1\x1e\x04\x0b\x00\x09\x00\x09\x00\x09\x00\x00\x00\xa0\x40\x00\x00\xe0\x40\x00\x00\x00\x00\x00\x00\x00\x00\x30\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x38\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 96, {{ SH4CTX_FR0, 0x40400000 }}, {{ SH4CTX_FR1, 0x40400000 }, { SH4CTX_FR2, 0x40a00000 }, { SH4CTX_FR3, 0x40e00000 }, { SH4CTX_FR4, 0x40a00000 }, { SH4CTX_FR5, 0x40e00000 }, { SH4CTX_R2, 0x40400000 }, { SH4CTX_R3, 0x40a00000 }, { SH4CTX_R4, 0x40400000 }}})
SH4_TEST(test_fmovsz, SH4Test {0x0, (uint8_t *)"\x0c\xf2\x23\xd0\x08\xf4\x22\xd0\x08\xf3\x21\xd0\x04\xe1\x16\xf6\x1f\xd0\x08\xe1\x16\xf5\x1e\xd0\x09\xf8\x09\xfa\x1c\xd0\x09\xf7\x09\xf9\x1f\xd0\x4a\xf0\x06\x62\x06\x63\x1d\xd0\x5a\xf0\x06\x64\x06\x65\x1b\xd0\x08\x70\x6b\xf0\x06\x66\x06\x67\x18\xd0\x08\x70\x7b\xf0\x06\x68\x06\x69\x16\xd0\x08\xe1\x07\xf1\x08\x70\x06\x6a\x06\x6b\x13\xd0\x08\xe1\x37\xf1\x08\x70\x06\x6c\x06\x6d\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x00\x00\x40\x40\x00\x00\x80\x40\x00\x00\x10\x41\x00\x00\x20\x41\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x70\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x80\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 176, {{ SH4CTX_FPSCR, 0x00140001 }, { SH4CTX_DR0, 0x3f80000040000000 }}, {{ SH4CTX_DR2, 0x3f80000040000000 }, { SH4CTX_DR4, 0x4080000040400000 }, { SH4CTX_XD2, 0x4080000040400000 }, { SH4CTX_DR6, 0x4110000040800000 }, { SH4CTX_XD4, 0x4120000041100000 }, { SH4CTX_DR8, 0x4080000040400000 }, { SH4CTX_DR10, 0x4120000041100000 }, { SH4CTX_XD6, 0x4080000040400000 }, { SH4CTX_XD8, 0x4120000041100000 }, { SH4CTX_R2, 0x40400000 }, { SH4CTX_R3, 0x40800000 }, { SH4CTX_R4, 0x41100000 }, { SH4CTX_R5, 0x41200000 }, { SH4CTX_R6, 0x40800000 }, { SH4CTX_R7, 0x41100000 }, { SH4CTX_R8, 0x40400000 }, { SH4CTX_R9, 0x40800000 }, { SH4CTX_R10, 0x40000000 }, { SH4CTX_R11, 0x3f800000 }, { SH4CTX_R12, 0x40400000 }, { SH4CTX_R13, 0x40800000 }}})
SH4_TEST(test_fmulf, SH4Test {0x6, (uint8_t *)"\x02\xf2\x0b\x00\x09\x00\x02\xf1\x0b\x00\x09\x00", 12, {{ SH4CTX_FR0, 0x40200000 }, { SH4CTX_FR1, 0x40000000 }}, {{ SH4CTX_FR1, 0x40a00000 }}})
SH4_TEST(test_fmuld, SH4Test {0x0, (uint8_t *)"\x02\xf2\x0b\x00\x09\x00\x02\xf1\x0b\x00\x09\x00", 12, {{ SH4CTX_FPSCR, 0x000c0001 }, { SH4CTX_DR0, 0x4008000000000000 }, { SH4CTX_DR2, 0xc01c000000000000 }}, {{ SH4CTX_DR2, 0xc035000000000000 }}})
SH4_TEST(test_fnegf, SH4Test {0x6, (uint8_t *)"\x4d\xf0\x0b\x00\x09\x00\x4d\xf0\x0b\x00\x09\x00", 12, {{ SH4CTX_FR0, 0x40800000 }}, {{ SH4CTX_FR0, 0xc0800000 }}})
SH4_TEST(test_fnegd, SH4Test {0x0, (uint8_t *)"\x4d\xf0\x0b\x00\x09\x00\x4d\xf0\x0b\x00\x09\x00", 12, {{ SH4CTX_FPSCR, 0x000c0001 }, { SH4CTX_DR0, 0x4014000000000000 }}, {{ SH4CTX_DR0, 0xc014000000000000 }}})
SH4_TEST(test_frchg, SH4Test {0x0, (uint8_t *)"\x6a\x01\xfd\xfb\x6a\x02\x0a\xd0\x0a\xf0\x02\x63\xfd\xfb\x0a\xf0\x02\x64\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x20\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 64, {{ SH4CTX_FR0, 0x41500000 }}, {{ SH4CTX_R1, 0x00040001 }, { SH4CTX_R2, 0x00240001 }, { SH4CTX_R3, 0x0 }, { SH4CTX_R4, 0x41500000 }}})
SH4_TEST(test_fsca, SH4Test {0x0, (uint8_t *)"\x5a\x40\xfd\xf2\x0b\x00\x09\x00", 8, {{ SH4CTX_R0, 16384 }}, {{ SH4CTX_FR2, 0x3f800000 }, { SH4CTX_FR3, 0xb33bbd2e }}})
SH4_TEST(test_fschg, SH4Test {0x0, (uint8_t *)"\x6a\x00\xfd\xf3\x6a\x01\x0b\x00\x09\x00", 10, {}, {{ SH4CTX_R0, 0x00040001 }, { SH4CTX_R1, 0x00140001 }}})
SH4_TEST(test_fsrra, SH4Test {0x0, (uint8_t *)"\x7d\xf0\x0b\x00\x09\x00", 6, {{ SH4CTX_FR0, 0x40800000 }}, {{ SH4CTX_FR0, 0x3f000000 }}})
SH4_TEST(test_fsqrtd, SH4Test {0x0, (uint8_t *)"\x6d\xf0\x0b\x00\x09\x00\x6d\xf0\x0b\x00\x09\x00", 12, {{ SH4CTX_FPSCR, 0x000c0001 }, { SH4CTX_DR0, 0x4010000000000000 }}, {{ SH4CTX_DR0, 0x4000000000000000 }}})
SH4_TEST(test_fsqrtf, SH4Test {0x6, (uint8_t *)"\x6d\xf0\x0b\x00\x09\x00\x6d\xf0\x0b\x00\x09\x00", 12, {{ SH4CTX_FR0, 0x40800000 }}, {{ SH4CTX_FR0, 0x40000000 }}})
SH4_TEST(test_fsubf, SH4Test {0x6, (uint8_t *)"\x01\xf2\x0b\x00\x09\x00\x01\xf1\x0b\x00\x09\x00", 12, {{ SH4CTX_FR0, 0x40400000 }, { SH4CTX_FR1, 0xbf800000 }}, {{ SH4CTX_FR1, 0xc0800000 }}})
SH4_TEST(test_fsubd, SH4Test {0x0, (uint8_t *)"\x01\xf2\x0b\x00\x09\x00\x01\xf1\x0b\x00\x09\x00", 12, {{ SH4CTX_FPSCR, 0x000c0001 }, { SH4CTX_DR0, 0xc01c000000000000 }, { SH4CTX_DR2, 0xc010000000000000 }}, {{ SH4CTX_DR2, 0x4008000000000000 }}})
SH4_TEST(test_ftrcf, SH4Test {0x8, (uint8_t *)"\x3d\xf0\x5a\x00\x0b\x00\x09\x00\x3d\xf0\x5a\x00\x0b\x00\x09\x00", 16, {{ SH4CTX_FR0, 0xc0966666 }}, {{ SH4CTX_R0, 0xfffffffc }}})
SH4_TEST(test_ftrcd, SH4Test {0x0, (uint8_t *)"\x3d\xf0\x5a\x00\x0b\x00\x09\x00\x3d\xf0\x5a\x00\x0b\x00\x09\x00", 16, {{ SH4CTX_FPSCR, 0x000c0001 }, { SH4CTX_DR0, 0xc012cccccccccccd }}, {{ SH4CTX_R0, 0xfffffffc }}})
SH4_TEST(test_ftrv, SH4Test {0x0, (uint8_t *)"\xfd\xf5\x0b\x00\x09\x00", 6, {{ SH4CTX_XF0, 0x3f800000 }, { SH4CTX_XF1, 0x00000000 }, { SH4CTX_XF2, 0x00000000 }, { SH4CTX_XF3, 0x00000000 }, { SH4CTX_XF4, 0x00000000 }, { SH4CTX_XF5, 0x40000000 }, { SH4CTX_XF6, 0x00000000 }, { SH4CTX_XF7, 0x00000000 }, { SH4CTX_XF8, 0x00000000 }, { SH4CTX_XF9, 0x00000000 }, { SH4CTX_XF10, 0x3f800000 }, { SH4CTX_XF11, 0x00000000 }, { SH4CTX_XF12, 0x00000000 }, { SH4CTX_XF13, 0x00000000 }, { SH4CTX_XF14, 0x00000000 }, { SH4CTX_XF15, 0x3f800000 }, { SH4CTX_FR4, 0x40000000 }, { SH4CTX_FR5, 0x40800000 }, { SH4CTX_FR6, 0x41000000 }, { SH4CTX_FR7, 0x00000000 }}, {{ SH4CTX_FR4, 0x40000000 }, { SH4CTX_FR5, 0x41000000 }, { SH4CTX_FR6, 0x41000000 }, { SH4CTX_FR7, 0x00000000 }}})
SH4_TEST(test_jmp, SH4Test {0x0, (uint8_t *)"\x03\xd0\x2b\x40\x09\x00\x0b\x00\x09\x00\x0b\x00\x0d\xe1\x09\x00\x0a\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 32, {{ SH4CTX_R1, 0 }}, {{ SH4CTX_R1, 13 }}})
SH4_TEST(test_jsr, SH4Test {0x0, (uint8_t *)"\x22\x4f\x07\xd0\x0b\x40\x01\x71\x03\x71\x26\x4f\x0b\x00\x09\x00\x0b\x00\x09\x71\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x10\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 48, {{ SH4CTX_R1, 0 }}, {{ SH4CTX_R1, 13 }}})
SH4_TEST(test_ldc_stc_vbr, SH4Test {0x2c, (uint8_t *)"\x0d\xe2\x1b\xd0\x0e\x40\x63\xe2\x02\x01\x15\xd0\x12\x20\x1c\xd0\x0e\x40\x13\xd0\x02\x63\x0b\x00\x09\x00\x9e\x40\x63\xe1\x92\x01\x0b\x00\x09\x00\x1e\x40\x12\x01\x0b\x00\x09\x00\x2e\x40\x22\x01\x0b\x00\x09\x00\x3e\x40\x32\x01\x0b\x00\x09\x00\x4e\x40\x42\x01\x0b\x00\x09\x00\xfa\x40\xfa\x01\x0b\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x50\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x50\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x70\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 144, {{ SH4CTX_R0, 13 }}, {{ SH4CTX_R1, 13 }}})
SH4_TEST(test_ldc_stc_spc, SH4Test {0x3c, (uint8_t *)"\x0d\xe2\x1b\xd0\x0e\x40\x63\xe2\x02\x01\x15\xd0\x12\x20\x1c\xd0\x0e\x40\x13\xd0\x02\x63\x0b\x00\x09\x00\x9e\x40\x63\xe1\x92\x01\x0b\x00\x09\x00\x1e\x40\x12\x01\x0b\x00\x09\x00\x2e\x40\x22\x01\x0b\x00\x09\x00\x3e\x40\x32\x01\x0b\x00\x09\x00\x4e\x40\x42\x01\x0b\x00\x09\x00\xfa\x40\xfa\x01\x0b\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x50\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x50\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x70\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 144, {{ SH4CTX_R0, 13 }}, {{ SH4CTX_R1, 13 }}})
SH4_TEST(test_ldc_stc_gbr, SH4Test {0x24, (uint8_t *)"\x0d\xe2\x1b\xd0\x0e\x40\x63\xe2\x02\x01\x15\xd0\x12\x20\x1c\xd0\x0e\x40\x13\xd0\x02\x63\x0b\x00\x09\x00\x9e\x40\x63\xe1\x92\x01\x0b\x00\x09\x00\x1e\x40\x12\x01\x0b\x00\x09\x00\x2e\x40\x22\x01\x0b\x00\x09\x00\x3e\x40\x32\x01\x0b\x00\x09\x00\x4e\x40\x42\x01\x0b\x00\x09\x00\xfa\x40\xfa\x01\x0b\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x50\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x50\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x70\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 144, {{ SH4CTX_R0, 13 }}, {{ SH4CTX_R1, 13 }}})
SH4_TEST(test_ldc_stc_sr, SH4Test {0x0, (uint8_t *)"\x0d\xe2\x1b\xd0\x0e\x40\x63\xe2\x02\x01\x15\xd0\x12\x20\x1c\xd0\x0e\x40\x13\xd0\x02\x63\x0b\x00\x09\x00\x9e\x40\x63\xe1\x92\x01\x0b\x00\x09\x00\x1e\x40\x12\x01\x0b\x00\x09\x00\x2e\x40\x22\x01\x0b\x00\x09\x00\x3e\x40\x32\x01\x0b\x00\x09\x00\x4e\x40\x42\x01\x0b\x00\x09\x00\xfa\x40\xfa\x01\x0b\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x50\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x50\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x70\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 144, {}, {{ SH4CTX_R2, 13 }, { SH4CTX_R3, 0x500000f0 }}})
SH4_TEST(test_ldc_stc_rbank, SH4Test {0x1a, (uint8_t *)"\x0d\xe2\x1b\xd0\x0e\x40\x63\xe2\x02\x01\x15\xd0\x12\x20\x1c\xd0\x0e\x40\x13\xd0\x02\x63\x0b\x00\x09\x00\x9e\x40\x63\xe1\x92\x01\x0b\x00\x09\x00\x1e\x40\x12\x01\x0b\x00\x09\x00\x2e\x40\x22\x01\x0b\x00\x09\x00\x3e\x40\x32\x01\x0b\x00\x09\x00\x4e\x40\x42\x01\x0b\x00\x09\x00\xfa\x40\xfa\x01\x0b\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x50\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x50\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x70\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 144, {{ SH4CTX_R0, 13 }}, {{ SH4CTX_R1, 13 }}})
SH4_TEST(test_ldc_stc_ssr, SH4Test {0x34, (uint8_t *)"\x0d\xe2\x1b\xd0\x0e\x40\x63\xe2\x02\x01\x15\xd0\x12\x20\x1c\xd0\x0e\x40\x13\xd0\x02\x63\x0b\x00\x09\x00\x9e\x40\x63\xe1\x92\x01\x0b\x00\x09\x00\x1e\x40\x12\x01\x0b\x00\x09\x00\x2e\x40\x22\x01\x0b\x00\x09\x00\x3e\x40\x32\x01\x0b\x00\x09\x00\x4e\x40\x42\x01\x0b\x00\x09\x00\xfa\x40\xfa\x01\x0b\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x50\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x50\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x70\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 144, {{ SH4CTX_R0, 13 }}, {{ SH4CTX_R1, 13 }}})
SH4_TEST(test_ldc_stc_dbr, SH4Test {0x44, (uint8_t *)"\x0d\xe2\x1b\xd0\x0e\x40\x63\xe2\x02\x01\x15\xd0\x12\x20\x1c\xd0\x0e\x40\x13\xd0\x02\x63\x0b\x00\x09\x00\x9e\x40\x63\xe1\x92\x01\x0b\x00\x09\x00\x1e\x40\x12\x01\x0b\x00\x09\x00\x2e\x40\x22\x01\x0b\x00\x09\x00\x3e\x40\x32\x01\x0b\x00\x09\x00\x4e\x40\x42\x01\x0b\x00\x09\x00\xfa\x40\xfa\x01\x0b\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x50\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x50\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x70\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 144, {{ SH4CTX_R0, 13 }}, {{ SH4CTX_R1, 13 }}})
SH4_TEST(test_ldcl_stcl_spc, SH4Test {0x7e, (uint8_t *)"\x0d\xe2\x33\xd0\x07\x40\x63\xe2\x2d\xd1\x04\x71\x03\x41\x34\xd3\x07\x43\x2b\xd0\x02\x63\x82\x04\x29\xd5\x92\x06\x60\x35\x29\x05\x0b\x00\x09\x00\x26\xd1\x02\x21\xb7\x41\x63\xe3\x24\xd2\x08\x72\xb3\x42\x10\x32\x29\x04\x22\x65\x0b\x00\x09\x00\x20\xd1\x02\x21\x1f\xd2\x08\x72\x17\x41\x13\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x1b\xd1\x02\x21\x1a\xd2\x08\x72\x27\x41\x23\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x15\xd1\x02\x21\x14\xd2\x08\x72\x37\x41\x33\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x10\xd1\x02\x21\x0f\xd2\x08\x72\x47\x41\x43\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x0a\xd1\x02\x21\x09\xd2\x08\x72\xf6\x41\xf2\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x50\xf0\x00\x00\x70\x00\x00\x00\x00\x00\x00\x00\x00\xb8\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb0\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb4\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 240, {{ SH4CTX_R0, 13 }}, {{ SH4CTX_R3, 1 }, { SH4CTX_R4, 13 }}})
SH4_TEST(test_ldcl_stcl_sr, SH4Test {0x0, (uint8_t *)"\x0d\xe2\x33\xd0\x07\x40\x63\xe2\x2d\xd1\x04\x71\x03\x41\x34\xd3\x07\x43\x2b\xd0\x02\x63\x82\x04\x29\xd5\x92\x06\x60\x35\x29\x05\x0b\x00\x09\x00\x26\xd1\x02\x21\xb7\x41\x63\xe3\x24\xd2\x08\x72\xb3\x42\x10\x32\x29\x04\x22\x65\x0b\x00\x09\x00\x20\xd1\x02\x21\x1f\xd2\x08\x72\x17\x41\x13\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x1b\xd1\x02\x21\x1a\xd2\x08\x72\x27\x41\x23\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x15\xd1\x02\x21\x14\xd2\x08\x72\x37\x41\x33\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x10\xd1\x02\x21\x0f\xd2\x08\x72\x47\x41\x43\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x0a\xd1\x02\x21\x09\xd2\x08\x72\xf6\x41\xf2\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x50\xf0\x00\x00\x70\x00\x00\x00\x00\x00\x00\x00\x00\xb8\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb0\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb4\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 240, {}, {{ SH4CTX_R2, 13 }, { SH4CTX_R3, 0x500000f0 }, { SH4CTX_R4, 4 }, { SH4CTX_R5, 1 }}})
SH4_TEST(test_ldcl_stcl_rbank, SH4Test {0x24, (uint8_t *)"\x0d\xe2\x33\xd0\x07\x40\x63\xe2\x2d\xd1\x04\x71\x03\x41\x34\xd3\x07\x43\x2b\xd0\x02\x63\x82\x04\x29\xd5\x92\x06\x60\x35\x29\x05\x0b\x00\x09\x00\x26\xd1\x02\x21\xb7\x41\x63\xe3\x24\xd2\x08\x72\xb3\x42\x10\x32\x29\x04\x22\x65\x0b\x00\x09\x00\x20\xd1\x02\x21\x1f\xd2\x08\x72\x17\x41\x13\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x1b\xd1\x02\x21\x1a\xd2\x08\x72\x27\x41\x23\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x15\xd1\x02\x21\x14\xd2\x08\x72\x37\x41\x33\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x10\xd1\x02\x21\x0f\xd2\x08\x72\x47\x41\x43\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x0a\xd1\x02\x21\x09\xd2\x08\x72\xf6\x41\xf2\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x50\xf0\x00\x00\x70\x00\x00\x00\x00\x00\x00\x00\x00\xb8\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb0\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb4\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 240, {{ SH4CTX_R0, 13 }}, {{ SH4CTX_R4, 1 }, { SH4CTX_R5, 13 }}})
SH4_TEST(test_ldcl_stcl_vbr, SH4Test {0x52, (uint8_t *)"\x0d\xe2\x33\xd0\x07\x40\x63\xe2\x2d\xd1\x04\x71\x03\x41\x34\xd3\x07\x43\x2b\xd0\x02\x63\x82\x04\x29\xd5\x92\x06\x60\x35\x29\x05\x0b\x00\x09\x00\x26\xd1\x02\x21\xb7\x41\x63\xe3\x24\xd2\x08\x72\xb3\x42\x10\x32\x29\x04\x22\x65\x0b\x00\x09\x00\x20\xd1\x02\x21\x1f\xd2\x08\x72\x17\x41\x13\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x1b\xd1\x02\x21\x1a\xd2\x08\x72\x27\x41\x23\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x15\xd1\x02\x21\x14\xd2\x08\x72\x37\x41\x33\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x10\xd1\x02\x21\x0f\xd2\x08\x72\x47\x41\x43\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x0a\xd1\x02\x21\x09\xd2\x08\x72\xf6\x41\xf2\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x50\xf0\x00\x00\x70\x00\x00\x00\x00\x00\x00\x00\x00\xb8\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb0\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb4\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 240, {{ SH4CTX_R0, 13 }}, {{ SH4CTX_R3, 1 }, { SH4CTX_R4, 13 }}})
SH4_TEST(test_ldcl_stcl_gbr, SH4Test {0x3c, (uint8_t *)"\x0d\xe2\x33\xd0\x07\x40\x63\xe2\x2d\xd1\x04\x71\x03\x41\x34\xd3\x07\x43\x2b\xd0\x02\x63\x82\x04\x29\xd5\x92\x06\x60\x35\x29\x05\x0b\x00\x09\x00\x26\xd1\x02\x21\xb7\x41\x63\xe3\x24\xd2\x08\x72\xb3\x42\x10\x32\x29\x04\x22\x65\x0b\x00\x09\x00\x20\xd1\x02\x21\x1f\xd2\x08\x72\x17\x41\x13\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x1b\xd1\x02\x21\x1a\xd2\x08\x72\x27\x41\x23\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x15\xd1\x02\x21\x14\xd2\x08\x72\x37\x41\x33\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x10\xd1\x02\x21\x0f\xd2\x08\x72\x47\x41\x43\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x0a\xd1\x02\x21\x09\xd2\x08\x72\xf6\x41\xf2\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x50\xf0\x00\x00\x70\x00\x00\x00\x00\x00\x00\x00\x00\xb8\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb0\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb4\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 240, {{ SH4CTX_R0, 13 }}, {{ SH4CTX_R3, 1 }, { SH4CTX_R4, 13 }}})
SH4_TEST(test_ldcl_stcl_ssr, SH4Test {0x68, (uint8_t *)"\x0d\xe2\x33\xd0\x07\x40\x63\xe2\x2d\xd1\x04\x71\x03\x41\x34\xd3\x07\x43\x2b\xd0\x02\x63\x82\x04\x29\xd5\x92\x06\x60\x35\x29\x05\x0b\x00\x09\x00\x26\xd1\x02\x21\xb7\x41\x63\xe3\x24\xd2\x08\x72\xb3\x42\x10\x32\x29\x04\x22\x65\x0b\x00\x09\x00\x20\xd1\x02\x21\x1f\xd2\x08\x72\x17\x41\x13\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x1b\xd1\x02\x21\x1a\xd2\x08\x72\x27\x41\x23\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x15\xd1\x02\x21\x14\xd2\x08\x72\x37\x41\x33\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x10\xd1\x02\x21\x0f\xd2\x08\x72\x47\x41\x43\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x0a\xd1\x02\x21\x09\xd2\x08\x72\xf6\x41\xf2\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x50\xf0\x00\x00\x70\x00\x00\x00\x00\x00\x00\x00\x00\xb8\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb0\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb4\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 240, {{ SH4CTX_R0, 13 }}, {{ SH4CTX_R3, 1 }, { SH4CTX_R4, 13 }}})
SH4_TEST(test_ldcl_stcl_dbr, SH4Test {0x94, (uint8_t *)"\x0d\xe2\x33\xd0\x07\x40\x63\xe2\x2d\xd1\x04\x71\x03\x41\x34\xd3\x07\x43\x2b\xd0\x02\x63\x82\x04\x29\xd5\x92\x06\x60\x35\x29\x05\x0b\x00\x09\x00\x26\xd1\x02\x21\xb7\x41\x63\xe3\x24\xd2\x08\x72\xb3\x42\x10\x32\x29\x04\x22\x65\x0b\x00\x09\x00\x20\xd1\x02\x21\x1f\xd2\x08\x72\x17\x41\x13\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x1b\xd1\x02\x21\x1a\xd2\x08\x72\x27\x41\x23\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x15\xd1\x02\x21\x14\xd2\x08\x72\x37\x41\x33\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x10\xd1\x02\x21\x0f\xd2\x08\x72\x47\x41\x43\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x0a\xd1\x02\x21\x09\xd2\x08\x72\xf6\x41\xf2\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf0\x00\x00\x50\xf0\x00\x00\x70\x00\x00\x00\x00\x00\x00\x00\x00\xb8\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb0\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xb4\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 240, {{ SH4CTX_R0, 13 }}, {{ SH4CTX_R3, 1 }, { SH4CTX_R4, 13 }}})
SH4_TEST(test_lds_sts_mach, SH4Test {0x0, (uint8_t *)"\x0a\x40\x0a\x01\x0b\x00\x09\x00\x1a\x40\x1a\x01\x0b\x00\x09\x00\x2a\x02\x2a\x40\x2a\x01\x2a\x42\x0b\x00\x09\x00\x6a\x40\x6a\x01\x0b\x00\x09\x00\x5a\x40\x5a\x01\x0b\x00\x09\x00", 44, {{ SH4CTX_R0, 13 }}, {{ SH4CTX_R1, 13 }}})
SH4_TEST(test_lds_sts_fpul, SH4Test {0x24, (uint8_t *)"\x0a\x40\x0a\x01\x0b\x00\x09\x00\x1a\x40\x1a\x01\x0b\x00\x09\x00\x2a\x02\x2a\x40\x2a\x01\x2a\x42\x0b\x00\x09\x00\x6a\x40\x6a\x01\x0b\x00\x09\x00\x5a\x40\x5a\x01\x0b\x00\x09\x00", 44, {{ SH4CTX_R0, 13 }}, {{ SH4CTX_R1, 13 }}})
SH4_TEST(test_lds_sts_macl, SH4Test {0x8, (uint8_t *)"\x0a\x40\x0a\x01\x0b\x00\x09\x00\x1a\x40\x1a\x01\x0b\x00\x09\x00\x2a\x02\x2a\x40\x2a\x01\x2a\x42\x0b\x00\x09\x00\x6a\x40\x6a\x01\x0b\x00\x09\x00\x5a\x40\x5a\x01\x0b\x00\x09\x00", 44, {{ SH4CTX_R0, 13 }}, {{ SH4CTX_R1, 13 }}})
SH4_TEST(test_lds_sts_fpscr, SH4Test {0x1c, (uint8_t *)"\x0a\x40\x0a\x01\x0b\x00\x09\x00\x1a\x40\x1a\x01\x0b\x00\x09\x00\x2a\x02\x2a\x40\x2a\x01\x2a\x42\x0b\x00\x09\x00\x6a\x40\x6a\x01\x0b\x00\x09\x00\x5a\x40\x5a\x01\x0b\x00\x09\x00", 44, {{ SH4CTX_R0, 0xffd40001 }}, {{ SH4CTX_R1, 0x00140001 }}})
SH4_TEST(test_lds_sts_pr, SH4Test {0x10, (uint8_t *)"\x0a\x40\x0a\x01\x0b\x00\x09\x00\x1a\x40\x1a\x01\x0b\x00\x09\x00\x2a\x02\x2a\x40\x2a\x01\x2a\x42\x0b\x00\x09\x00\x6a\x40\x6a\x01\x0b\x00\x09\x00\x5a\x40\x5a\x01\x0b\x00\x09\x00", 44, {{ SH4CTX_R0, 13 }}, {{ SH4CTX_R1, 13 }}})
SH4_TEST(test_ldsl_stsl_macl, SH4Test {0x16, (uint8_t *)"\x23\xd1\x23\xd2\x08\x72\x02\x21\x06\x41\x02\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x1e\xd1\x1d\xd2\x08\x72\x02\x21\x16\x41\x12\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x2a\x05\x18\xd1\x17\xd2\x08\x72\x02\x21\x26\x41\x22\x42\x20\x31\x29\x03\x22\x64\x2a\x45\x0b\x00\x09\x00\x12\xd1\x11\xd2\x08\x72\x02\x21\x66\x41\x62\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x0c\xd1\x0c\xd2\x08\x72\x02\x21\x56\x41\x52\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x00\x00\x00\x00\x00\x09\x00\x09\x00\x09\x00\x09\x00\x80\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 160, {{ SH4CTX_R0, 13 }}, {{ SH4CTX_R3, 1 }, { SH4CTX_R4, 13 }}})
SH4_TEST(test_ldsl_stsl_fpul, SH4Test {0x5c, (uint8_t *)"\x23\xd1\x23\xd2\x08\x72\x02\x21\x06\x41\x02\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x1e\xd1\x1d\xd2\x08\x72\x02\x21\x16\x41\x12\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x2a\x05\x18\xd1\x17\xd2\x08\x72\x02\x21\x26\x41\x22\x42\x20\x31\x29\x03\x22\x64\x2a\x45\x0b\x00\x09\x00\x12\xd1\x11\xd2\x08\x72\x02\x21\x66\x41\x62\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x0c\xd1\x0c\xd2\x08\x72\x02\x21\x56\x41\x52\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x00\x00\x00\x00\x00\x09\x00\x09\x00\x09\x00\x09\x00\x80\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 160, {{ SH4CTX_R0, 13 }}, {{ SH4CTX_R3, 1 }, { SH4CTX_R4, 13 }}})
SH4_TEST(test_ldsl_stsl_mach, SH4Test {0x0, (uint8_t *)"\x23\xd1\x23\xd2\x08\x72\x02\x21\x06\x41\x02\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x1e\xd1\x1d\xd2\x08\x72\x02\x21\x16\x41\x12\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x2a\x05\x18\xd1\x17\xd2\x08\x72\x02\x21\x26\x41\x22\x42\x20\x31\x29\x03\x22\x64\x2a\x45\x0b\x00\x09\x00\x12\xd1\x11\xd2\x08\x72\x02\x21\x66\x41\x62\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x0c\xd1\x0c\xd2\x08\x72\x02\x21\x56\x41\x52\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x00\x00\x00\x00\x00\x09\x00\x09\x00\x09\x00\x09\x00\x80\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 160, {{ SH4CTX_R0, 13 }}, {{ SH4CTX_R3, 1 }, { SH4CTX_R4, 13 }}})
SH4_TEST(test_ldsl_stsl_fpscr, SH4Test {0x46, (uint8_t *)"\x23\xd1\x23\xd2\x08\x72\x02\x21\x06\x41\x02\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x1e\xd1\x1d\xd2\x08\x72\x02\x21\x16\x41\x12\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x2a\x05\x18\xd1\x17\xd2\x08\x72\x02\x21\x26\x41\x22\x42\x20\x31\x29\x03\x22\x64\x2a\x45\x0b\x00\x09\x00\x12\xd1\x11\xd2\x08\x72\x02\x21\x66\x41\x62\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x0c\xd1\x0c\xd2\x08\x72\x02\x21\x56\x41\x52\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x00\x00\x00\x00\x00\x09\x00\x09\x00\x09\x00\x09\x00\x80\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 160, {{ SH4CTX_R0, 0xffd40001 }}, {{ SH4CTX_R3, 1 }, { SH4CTX_R4, 0x00140001 }}})
SH4_TEST(test_ldsl_stsl_pr, SH4Test {0x2c, (uint8_t *)"\x23\xd1\x23\xd2\x08\x72\x02\x21\x06\x41\x02\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x1e\xd1\x1d\xd2\x08\x72\x02\x21\x16\x41\x12\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x2a\x05\x18\xd1\x17\xd2\x08\x72\x02\x21\x26\x41\x22\x42\x20\x31\x29\x03\x22\x64\x2a\x45\x0b\x00\x09\x00\x12\xd1\x11\xd2\x08\x72\x02\x21\x66\x41\x62\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x0c\xd1\x0c\xd2\x08\x72\x02\x21\x56\x41\x52\x42\x20\x31\x29\x03\x22\x64\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x00\x00\x00\x00\x00\x09\x00\x09\x00\x09\x00\x09\x00\x80\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 160, {{ SH4CTX_R0, 13 }}, {{ SH4CTX_R3, 1 }, { SH4CTX_R4, 13 }}})
SH4_TEST(test_mova, SH4Test {0x0, (uint8_t *)"\x03\xc7\x02\x61\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\xe8\xff\xff\xff\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 32, {}, {}})
SH4_TEST(test_movbs0, SH4Test {0x28, (uint8_t *)"\x17\xd1\x00\x21\x10\x62\x0b\x00\x09\x00\x15\xd0\x04\x61\x1c\x31\x14\x20\x00\x62\x0b\x00\x09\x00\x11\xd1\x11\x84\x0c\x30\x11\x80\x63\xe0\x11\x84\x0b\x00\x09\x00\x0d\xd0\x01\xe1\x1c\x02\x2c\x32\x24\x01\x1c\x03\x0b\x00\x09\x00\x09\xd0\x1e\x40\x01\xc4\x0c\x30\x01\xc0\x63\xe0\x01\xc4\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf4\xf3\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x50\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 112, {}, {{ SH4CTX_R3, -26 }}})
SH4_TEST(test_movbm, SH4Test {0xa, (uint8_t *)"\x17\xd1\x00\x21\x10\x62\x0b\x00\x09\x00\x15\xd0\x04\x61\x1c\x31\x14\x20\x00\x62\x0b\x00\x09\x00\x11\xd1\x11\x84\x0c\x30\x11\x80\x63\xe0\x11\x84\x0b\x00\x09\x00\x0d\xd0\x01\xe1\x1c\x02\x2c\x32\x24\x01\x1c\x03\x0b\x00\x09\x00\x09\xd0\x1e\x40\x01\xc4\x0c\x30\x01\xc0\x63\xe0\x01\xc4\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf4\xf3\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x50\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 112, {}, {{ SH4CTX_R2, -24 }}})
SH4_TEST(test_movbs, SH4Test {0x0, (uint8_t *)"\x17\xd1\x00\x21\x10\x62\x0b\x00\x09\x00\x15\xd0\x04\x61\x1c\x31\x14\x20\x00\x62\x0b\x00\x09\x00\x11\xd1\x11\x84\x0c\x30\x11\x80\x63\xe0\x11\x84\x0b\x00\x09\x00\x0d\xd0\x01\xe1\x1c\x02\x2c\x32\x24\x01\x1c\x03\x0b\x00\x09\x00\x09\xd0\x1e\x40\x01\xc4\x0c\x30\x01\xc0\x63\xe0\x01\xc4\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf4\xf3\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x50\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 112, {{ SH4CTX_R0, -12 }}, {{ SH4CTX_R2, -12 }}})
SH4_TEST(test_movbs0g, SH4Test {0x38, (uint8_t *)"\x17\xd1\x00\x21\x10\x62\x0b\x00\x09\x00\x15\xd0\x04\x61\x1c\x31\x14\x20\x00\x62\x0b\x00\x09\x00\x11\xd1\x11\x84\x0c\x30\x11\x80\x63\xe0\x11\x84\x0b\x00\x09\x00\x0d\xd0\x01\xe1\x1c\x02\x2c\x32\x24\x01\x1c\x03\x0b\x00\x09\x00\x09\xd0\x1e\x40\x01\xc4\x0c\x30\x01\xc0\x63\xe0\x01\xc4\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf4\xf3\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x50\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 112, {}, {{ SH4CTX_R0, -26 }}})
SH4_TEST(test_movbs0d, SH4Test {0x18, (uint8_t *)"\x17\xd1\x00\x21\x10\x62\x0b\x00\x09\x00\x15\xd0\x04\x61\x1c\x31\x14\x20\x00\x62\x0b\x00\x09\x00\x11\xd1\x11\x84\x0c\x30\x11\x80\x63\xe0\x11\x84\x0b\x00\x09\x00\x0d\xd0\x01\xe1\x1c\x02\x2c\x32\x24\x01\x1c\x03\x0b\x00\x09\x00\x09\xd0\x1e\x40\x01\xc4\x0c\x30\x01\xc0\x63\xe0\x01\xc4\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\xf4\xf3\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x50\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 112, {}, {{ SH4CTX_R0, -26 }}})
SH4_TEST(test_movls, SH4Test {0x6, (uint8_t *)"\x13\xd2\x0b\x00\x09\x00\x16\xd1\x02\x21\x12\x62\x0b\x00\x09\x00\x13\xd0\x06\x61\x1c\x31\x16\x20\x02\x62\x0b\x00\x09\x00\x10\xd0\x01\x51\x1c\x31\x11\x10\x01\x52\x0b\x00\x09\x00\x0c\xd0\x04\xe1\x1e\x02\x2c\x32\x26\x01\x1e\x03\x0b\x00\x09\x00\x08\xd0\x1e\x40\x01\xc6\x0c\x30\x01\xc2\x63\xe0\x01\xc6\x0b\x00\x09\x00\x09\x00\xf4\xff\xff\xff\xf3\xff\xff\xff\x09\x00\x09\x00\x09\x00\x09\x00\x50\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 112, {{ SH4CTX_R0, -12 }}, {{ SH4CTX_R2, -12 }}})
SH4_TEST(test_movls0, SH4Test {0x2c, (uint8_t *)"\x13\xd2\x0b\x00\x09\x00\x16\xd1\x02\x21\x12\x62\x0b\x00\x09\x00\x13\xd0\x06\x61\x1c\x31\x16\x20\x02\x62\x0b\x00\x09\x00\x10\xd0\x01\x51\x1c\x31\x11\x10\x01\x52\x0b\x00\x09\x00\x0c\xd0\x04\xe1\x1e\x02\x2c\x32\x26\x01\x1e\x03\x0b\x00\x09\x00\x08\xd0\x1e\x40\x01\xc6\x0c\x30\x01\xc2\x63\xe0\x01\xc6\x0b\x00\x09\x00\x09\x00\xf4\xff\xff\xff\xf3\xff\xff\xff\x09\x00\x09\x00\x09\x00\x09\x00\x50\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 112, {}, {{ SH4CTX_R3, -26 }}})
SH4_TEST(test_movllpc, SH4Test {0x0, (uint8_t *)"\x13\xd2\x0b\x00\x09\x00\x16\xd1\x02\x21\x12\x62\x0b\x00\x09\x00\x13\xd0\x06\x61\x1c\x31\x16\x20\x02\x62\x0b\x00\x09\x00\x10\xd0\x01\x51\x1c\x31\x11\x10\x01\x52\x0b\x00\x09\x00\x0c\xd0\x04\xe1\x1e\x02\x2c\x32\x26\x01\x1e\x03\x0b\x00\x09\x00\x08\xd0\x1e\x40\x01\xc6\x0c\x30\x01\xc2\x63\xe0\x01\xc6\x0b\x00\x09\x00\x09\x00\xf4\xff\xff\xff\xf3\xff\xff\xff\x09\x00\x09\x00\x09\x00\x09\x00\x50\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 112, {}, {{ SH4CTX_R2, -12 }}})
SH4_TEST(test_movls0g, SH4Test {0x3c, (uint8_t *)"\x13\xd2\x0b\x00\x09\x00\x16\xd1\x02\x21\x12\x62\x0b\x00\x09\x00\x13\xd0\x06\x61\x1c\x31\x16\x20\x02\x62\x0b\x00\x09\x00\x10\xd0\x01\x51\x1c\x31\x11\x10\x01\x52\x0b\x00\x09\x00\x0c\xd0\x04\xe1\x1e\x02\x2c\x32\x26\x01\x1e\x03\x0b\x00\x09\x00\x08\xd0\x1e\x40\x01\xc6\x0c\x30\x01\xc2\x63\xe0\x01\xc6\x0b\x00\x09\x00\x09\x00\xf4\xff\xff\xff\xf3\xff\xff\xff\x09\x00\x09\x00\x09\x00\x09\x00\x50\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 112, {}, {{ SH4CTX_R0, -26 }}})
SH4_TEST(test_movlsmd, SH4Test {0x1e, (uint8_t *)"\x13\xd2\x0b\x00\x09\x00\x16\xd1\x02\x21\x12\x62\x0b\x00\x09\x00\x13\xd0\x06\x61\x1c\x31\x16\x20\x02\x62\x0b\x00\x09\x00\x10\xd0\x01\x51\x1c\x31\x11\x10\x01\x52\x0b\x00\x09\x00\x0c\xd0\x04\xe1\x1e\x02\x2c\x32\x26\x01\x1e\x03\x0b\x00\x09\x00\x08\xd0\x1e\x40\x01\xc6\x0c\x30\x01\xc2\x63\xe0\x01\xc6\x0b\x00\x09\x00\x09\x00\xf4\xff\xff\xff\xf3\xff\xff\xff\x09\x00\x09\x00\x09\x00\x09\x00\x50\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 112, {}, {{ SH4CTX_R2, -26 }}})
SH4_TEST(test_movlm, SH4Test {0x10, (uint8_t *)"\x13\xd2\x0b\x00\x09\x00\x16\xd1\x02\x21\x12\x62\x0b\x00\x09\x00\x13\xd0\x06\x61\x1c\x31\x16\x20\x02\x62\x0b\x00\x09\x00\x10\xd0\x01\x51\x1c\x31\x11\x10\x01\x52\x0b\x00\x09\x00\x0c\xd0\x04\xe1\x1e\x02\x2c\x32\x26\x01\x1e\x03\x0b\x00\x09\x00\x08\xd0\x1e\x40\x01\xc6\x0c\x30\x01\xc2\x63\xe0\x01\xc6\x0b\x00\x09\x00\x09\x00\xf4\xff\xff\xff\xf3\xff\xff\xff\x09\x00\x09\x00\x09\x00\x09\x00\x50\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 112, {}, {{ SH4CTX_R2, -24 }}})
SH4_TEST(test_movt, SH4Test {0x0, (uint8_t *)"\x03\x88\x29\x01\x05\x88\x29\x02\x0b\x00\x09\x00", 12, {{ SH4CTX_R0, 3 }}, {{ SH4CTX_R1, 1 }, { SH4CTX_R2, 0 }}})
SH4_TEST(test_movws, SH4Test {0x6, (uint8_t *)"\x26\x92\x0b\x00\x09\x00\x16\xd1\x01\x21\x11\x62\x0b\x00\x09\x00\x13\xd0\x05\x61\x1c\x31\x15\x20\x01\x62\x0b\x00\x09\x00\x10\xd1\x11\x85\x0c\x30\x11\x81\x63\xe0\x11\x85\x0b\x00\x09\x00\x0c\xd0\x02\xe1\x1d\x02\x2c\x32\x25\x01\x1d\x03\x0b\x00\x09\x00\x08\xd0\x1e\x40\x01\xc5\x0c\x30\x01\xc1\x63\xe0\x01\xc5\x0b\x00\x09\x00\xf4\xff\xf3\xff\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x50\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 112, {{ SH4CTX_R0, -12 }}, {{ SH4CTX_R2, -12 }}})
SH4_TEST(test_movwm, SH4Test {0x10, (uint8_t *)"\x26\x92\x0b\x00\x09\x00\x16\xd1\x01\x21\x11\x62\x0b\x00\x09\x00\x13\xd0\x05\x61\x1c\x31\x15\x20\x01\x62\x0b\x00\x09\x00\x10\xd1\x11\x85\x0c\x30\x11\x81\x63\xe0\x11\x85\x0b\x00\x09\x00\x0c\xd0\x02\xe1\x1d\x02\x2c\x32\x25\x01\x1d\x03\x0b\x00\x09\x00\x08\xd0\x1e\x40\x01\xc5\x0c\x30\x01\xc1\x63\xe0\x01\xc5\x0b\x00\x09\x00\xf4\xff\xf3\xff\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x50\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 112, {}, {{ SH4CTX_R2, -24 }}})
SH4_TEST(test_movws0, SH4Test {0x2e, (uint8_t *)"\x26\x92\x0b\x00\x09\x00\x16\xd1\x01\x21\x11\x62\x0b\x00\x09\x00\x13\xd0\x05\x61\x1c\x31\x15\x20\x01\x62\x0b\x00\x09\x00\x10\xd1\x11\x85\x0c\x30\x11\x81\x63\xe0\x11\x85\x0b\x00\x09\x00\x0c\xd0\x02\xe1\x1d\x02\x2c\x32\x25\x01\x1d\x03\x0b\x00\x09\x00\x08\xd0\x1e\x40\x01\xc5\x0c\x30\x01\xc1\x63\xe0\x01\xc5\x0b\x00\x09\x00\xf4\xff\xf3\xff\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x50\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 112, {}, {{ SH4CTX_R3, -26 }}})
SH4_TEST(test_movws0d, SH4Test {0x1e, (uint8_t *)"\x26\x92\x0b\x00\x09\x00\x16\xd1\x01\x21\x11\x62\x0b\x00\x09\x00\x13\xd0\x05\x61\x1c\x31\x15\x20\x01\x62\x0b\x00\x09\x00\x10\xd1\x11\x85\x0c\x30\x11\x81\x63\xe0\x11\x85\x0b\x00\x09\x00\x0c\xd0\x02\xe1\x1d\x02\x2c\x32\x25\x01\x1d\x03\x0b\x00\x09\x00\x08\xd0\x1e\x40\x01\xc5\x0c\x30\x01\xc1\x63\xe0\x01\xc5\x0b\x00\x09\x00\xf4\xff\xf3\xff\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x50\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 112, {}, {{ SH4CTX_R0, -26 }}})
SH4_TEST(test_movws0g, SH4Test {0x3e, (uint8_t *)"\x26\x92\x0b\x00\x09\x00\x16\xd1\x01\x21\x11\x62\x0b\x00\x09\x00\x13\xd0\x05\x61\x1c\x31\x15\x20\x01\x62\x0b\x00\x09\x00\x10\xd1\x11\x85\x0c\x30\x11\x81\x63\xe0\x11\x85\x0b\x00\x09\x00\x0c\xd0\x02\xe1\x1d\x02\x2c\x32\x25\x01\x1d\x03\x0b\x00\x09\x00\x08\xd0\x1e\x40\x01\xc5\x0c\x30\x01\xc1\x63\xe0\x01\xc5\x0b\x00\x09\x00\xf4\xff\xf3\xff\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x50\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 112, {}, {{ SH4CTX_R0, -26 }}})
SH4_TEST(test_movwlpc, SH4Test {0x0, (uint8_t *)"\x26\x92\x0b\x00\x09\x00\x16\xd1\x01\x21\x11\x62\x0b\x00\x09\x00\x13\xd0\x05\x61\x1c\x31\x15\x20\x01\x62\x0b\x00\x09\x00\x10\xd1\x11\x85\x0c\x30\x11\x81\x63\xe0\x11\x85\x0b\x00\x09\x00\x0c\xd0\x02\xe1\x1d\x02\x2c\x32\x25\x01\x1d\x03\x0b\x00\x09\x00\x08\xd0\x1e\x40\x01\xc5\x0c\x30\x01\xc1\x63\xe0\x01\xc5\x0b\x00\x09\x00\xf4\xff\xf3\xff\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x50\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 112, {}, {{ SH4CTX_R2, -12 }}})
SH4_TEST(test_mull, SH4Test {0x0, (uint8_t *)"\x17\x00\x1a\x00\x0b\x00\x09\x00\x1f\x20\x1a\x00\x0b\x00\x09\x00\x1e\x20\x1a\x00\x0b\x00\x09\x00", 24, {{ SH4CTX_R0, 0x00fffffe }, { SH4CTX_R1, 0x00000004 }}, {{ SH4CTX_R0, 0x03fffff8 }}})
SH4_TEST(test_mulu, SH4Test {0x10, (uint8_t *)"\x17\x00\x1a\x00\x0b\x00\x09\x00\x1f\x20\x1a\x00\x0b\x00\x09\x00\x1e\x20\x1a\x00\x0b\x00\x09\x00", 24, {{ SH4CTX_R0, 0x00fffffe }, { SH4CTX_R1, 0x00000004 }}, {{ SH4CTX_R0, 0x0003fff8 }}})
SH4_TEST(test_muls, SH4Test {0x8, (uint8_t *)"\x17\x00\x1a\x00\x0b\x00\x09\x00\x1f\x20\x1a\x00\x0b\x00\x09\x00\x1e\x20\x1a\x00\x0b\x00\x09\x00", 24, {{ SH4CTX_R0, 0x00fffffe }, { SH4CTX_R1, 0x00000004 }}, {{ SH4CTX_R0, 0xfffffff8 }}})
SH4_TEST(test_neg, SH4Test {0x0, (uint8_t *)"\x0b\x61\x0b\x00\x09\x00", 6, {{ SH4CTX_R0, -1 }}, {{ SH4CTX_R1, 1 }}})
SH4_TEST(test_negc_nocarry, SH4Test {0x0, (uint8_t *)"\x0e\x40\x1a\x62\x0b\x00\x09\x00\x0e\x40\x1a\x62\x0b\x00\x09\x00", 16, {{ SH4CTX_R0, 0x700000f0 }, { SH4CTX_R1, -4 }}, {{ SH4CTX_R2, 4 }}})
SH4_TEST(test_negc_carry, SH4Test {0x8, (uint8_t *)"\x0e\x40\x1a\x62\x0b\x00\x09\x00\x0e\x40\x1a\x62\x0b\x00\x09\x00", 16, {{ SH4CTX_R0, 0x700000f1 }, { SH4CTX_R1, -4 }}, {{ SH4CTX_R2, 3 }}})
SH4_TEST(test_not, SH4Test {0x0, (uint8_t *)"\x07\x61\x0b\x00\x09\x00", 6, {{ SH4CTX_R0, 0xf0f0f0f0 }}, {{ SH4CTX_R1, 0x0f0f0f0f }}})
SH4_TEST(test_or_disp, SH4Test {0xc, (uint8_t *)"\x0b\x21\x0b\x00\x09\x00\x0f\xcb\x0b\x00\x09\x00\x08\xd0\x1e\x40\x04\xe0\x22\xcf\x01\xc6\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x00\x11\x00\x00\x00\x09\x00\x09\x00\x09\x00\x09\x00\x20\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 64, {}, {{ SH4CTX_R0, 0x33 }}})
SH4_TEST(test_or_imm, SH4Test {0x6, (uint8_t *)"\x0b\x21\x0b\x00\x09\x00\x0f\xcb\x0b\x00\x09\x00\x08\xd0\x1e\x40\x04\xe0\x22\xcf\x01\xc6\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x00\x11\x00\x00\x00\x09\x00\x09\x00\x09\x00\x09\x00\x20\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 64, {{ SH4CTX_R0, 0xffffff00 }}, {{ SH4CTX_R0, 0xffffff0f }}})
SH4_TEST(test_or, SH4Test {0x0, (uint8_t *)"\x0b\x21\x0b\x00\x09\x00\x0f\xcb\x0b\x00\x09\x00\x08\xd0\x1e\x40\x04\xe0\x22\xcf\x01\xc6\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x00\x11\x00\x00\x00\x09\x00\x09\x00\x09\x00\x09\x00\x20\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 64, {{ SH4CTX_R0, 0xffffff00 }, { SH4CTX_R1, 0x00ffffff }}, {{ SH4CTX_R1, 0xffffffff }}})
SH4_TEST(test_rotcr_t0_lsb1, SH4Test {0x32, (uint8_t *)"\x04\x40\x29\x01\x0b\x00\x09\x00\x04\x40\x29\x01\x0b\x00\x09\x00\x24\x40\x29\x01\x0b\x00\x09\x00\x18\x00\x24\x40\x29\x01\x0b\x00\x09\x00\x05\x40\x29\x01\x0b\x00\x09\x00\x05\x40\x29\x01\x0b\x00\x09\x00\x25\x40\x29\x01\x0b\x00\x09\x00\x18\x00\x25\x40\x29\x01\x0b\x00\x09\x00", 68, {{ SH4CTX_R0, 0x7fffffff }}, {{ SH4CTX_R0, 0x3fffffff }, { SH4CTX_R1, 1 }}})
SH4_TEST(test_rotcl_t1_msb0, SH4Test {0x18, (uint8_t *)"\x04\x40\x29\x01\x0b\x00\x09\x00\x04\x40\x29\x01\x0b\x00\x09\x00\x24\x40\x29\x01\x0b\x00\x09\x00\x18\x00\x24\x40\x29\x01\x0b\x00\x09\x00\x05\x40\x29\x01\x0b\x00\x09\x00\x05\x40\x29\x01\x0b\x00\x09\x00\x25\x40\x29\x01\x0b\x00\x09\x00\x18\x00\x25\x40\x29\x01\x0b\x00\x09\x00", 68, {{ SH4CTX_R0, 0x7fffffff }}, {{ SH4CTX_R0, 0xffffffff }, { SH4CTX_R1, 0 }}})
SH4_TEST(test_rotr_lsb0, SH4Test {0x22, (uint8_t *)"\x04\x40\x29\x01\x0b\x00\x09\x00\x04\x40\x29\x01\x0b\x00\x09\x00\x24\x40\x29\x01\x0b\x00\x09\x00\x18\x00\x24\x40\x29\x01\x0b\x00\x09\x00\x05\x40\x29\x01\x0b\x00\x09\x00\x05\x40\x29\x01\x0b\x00\x09\x00\x25\x40\x29\x01\x0b\x00\x09\x00\x18\x00\x25\x40\x29\x01\x0b\x00\x09\x00", 68, {{ SH4CTX_R0, 0xfffffffe }}, {{ SH4CTX_R0, 0x7fffffff }, { SH4CTX_R1, 0 }}})
SH4_TEST(test_rotr_lsb1, SH4Test {0x2a, (uint8_t *)"\x04\x40\x29\x01\x0b\x00\x09\x00\x04\x40\x29\x01\x0b\x00\x09\x00\x24\x40\x29\x01\x0b\x00\x09\x00\x18\x00\x24\x40\x29\x01\x0b\x00\x09\x00\x05\x40\x29\x01\x0b\x00\x09\x00\x05\x40\x29\x01\x0b\x00\x09\x00\x25\x40\x29\x01\x0b\x00\x09\x00\x18\x00\x25\x40\x29\x01\x0b\x00\x09\x00", 68, {{ SH4CTX_R0, 0x7fffffff }}, {{ SH4CTX_R0, 0xbfffffff }, { SH4CTX_R1, 1 }}})
SH4_TEST(test_rotl_msb1, SH4Test {0x8, (uint8_t *)"\x04\x40\x29\x01\x0b\x00\x09\x00\x04\x40\x29\x01\x0b\x00\x09\x00\x24\x40\x29\x01\x0b\x00\x09\x00\x18\x00\x24\x40\x29\x01\x0b\x00\x09\x00\x05\x40\x29\x01\x0b\x00\x09\x00\x05\x40\x29\x01\x0b\x00\x09\x00\x25\x40\x29\x01\x0b\x00\x09\x00\x18\x00\x25\x40\x29\x01\x0b\x00\x09\x00", 68, {{ SH4CTX_R0, 0xfffffffe }}, {{ SH4CTX_R0, 0xfffffffd }, { SH4CTX_R1, 1 }}})
SH4_TEST(test_rotl_msb0, SH4Test {0x0, (uint8_t *)"\x04\x40\x29\x01\x0b\x00\x09\x00\x04\x40\x29\x01\x0b\x00\x09\x00\x24\x40\x29\x01\x0b\x00\x09\x00\x18\x00\x24\x40\x29\x01\x0b\x00\x09\x00\x05\x40\x29\x01\x0b\x00\x09\x00\x05\x40\x29\x01\x0b\x00\x09\x00\x25\x40\x29\x01\x0b\x00\x09\x00\x18\x00\x25\x40\x29\x01\x0b\x00\x09\x00", 68, {{ SH4CTX_R0, 0x7fffffff }}, {{ SH4CTX_R0, 0xfffffffe }, { SH4CTX_R1, 0 }}})
SH4_TEST(test_rotcr_t1_lsb0, SH4Test {0x3a, (uint8_t *)"\x04\x40\x29\x01\x0b\x00\x09\x00\x04\x40\x29\x01\x0b\x00\x09\x00\x24\x40\x29\x01\x0b\x00\x09\x00\x18\x00\x24\x40\x29\x01\x0b\x00\x09\x00\x05\x40\x29\x01\x0b\x00\x09\x00\x05\x40\x29\x01\x0b\x00\x09\x00\x25\x40\x29\x01\x0b\x00\x09\x00\x18\x00\x25\x40\x29\x01\x0b\x00\x09\x00", 68, {{ SH4CTX_R0, 0xfffffffe }}, {{ SH4CTX_R0, 0xffffffff }, { SH4CTX_R1, 0 }}})
SH4_TEST(test_rotcl_t0_msb1, SH4Test {0x10, (uint8_t *)"\x04\x40\x29\x01\x0b\x00\x09\x00\x04\x40\x29\x01\x0b\x00\x09\x00\x24\x40\x29\x01\x0b\x00\x09\x00\x18\x00\x24\x40\x29\x01\x0b\x00\x09\x00\x05\x40\x29\x01\x0b\x00\x09\x00\x05\x40\x29\x01\x0b\x00\x09\x00\x25\x40\x29\x01\x0b\x00\x09\x00\x18\x00\x25\x40\x29\x01\x0b\x00\x09\x00", 68, {{ SH4CTX_R0, 0xfffffffe }}, {{ SH4CTX_R0, 0xfffffffc }, { SH4CTX_R1, 1 }}})
SH4_TEST(test_shad, SH4Test {0x0, (uint8_t *)"\x1c\x42\x0b\x00\x09\x00", 6, {{ SH4CTX_R1, 0xffffffe0 }, { SH4CTX_R2, 0x80180000 }}, {{ SH4CTX_R2, 0xffffffff }}})
SH4_TEST(test_shlr8, SH4Test {0x3c, (uint8_t *)"\x1d\x40\x0b\x00\x09\x00\x1d\x40\x0b\x00\x09\x00\x1d\x40\x0b\x00\x09\x00\x20\x40\x29\x01\x0b\x00\x09\x00\x00\x40\x29\x01\x0b\x00\x09\x00\x01\x40\x29\x01\x0b\x00\x09\x00\x08\x40\x0b\x00\x09\x00\x09\x40\x0b\x00\x09\x00\x18\x40\x0b\x00\x09\x00\x19\x40\x0b\x00\x09\x00\x28\x40\x0b\x00\x09\x00\x29\x40\x0b\x00\x09\x00", 78, {{ SH4CTX_R0, 0x100 }}, {}})
SH4_TEST(test_shld_left, SH4Test {0x0, (uint8_t *)"\x1d\x40\x0b\x00\x09\x00\x1d\x40\x0b\x00\x09\x00\x1d\x40\x0b\x00\x09\x00\x20\x40\x29\x01\x0b\x00\x09\x00\x00\x40\x29\x01\x0b\x00\x09\x00\x01\x40\x29\x01\x0b\x00\x09\x00\x08\x40\x0b\x00\x09\x00\x09\x40\x0b\x00\x09\x00\x18\x40\x0b\x00\x09\x00\x19\x40\x0b\x00\x09\x00\x28\x40\x0b\x00\x09\x00\x29\x40\x0b\x00\x09\x00", 78, {{ SH4CTX_R0, 0x00008018 }, { SH4CTX_R1, 16 }}, {{ SH4CTX_R0, 0x80180000 }}})
SH4_TEST(test_shll, SH4Test {0x1a, (uint8_t *)"\x1d\x40\x0b\x00\x09\x00\x1d\x40\x0b\x00\x09\x00\x1d\x40\x0b\x00\x09\x00\x20\x40\x29\x01\x0b\x00\x09\x00\x00\x40\x29\x01\x0b\x00\x09\x00\x01\x40\x29\x01\x0b\x00\x09\x00\x08\x40\x0b\x00\x09\x00\x09\x40\x0b\x00\x09\x00\x18\x40\x0b\x00\x09\x00\x19\x40\x0b\x00\x09\x00\x28\x40\x0b\x00\x09\x00\x29\x40\x0b\x00\x09\x00", 78, {{ SH4CTX_R0, 0x80000001 }}, {{ SH4CTX_R0, 0x2 }, { SH4CTX_R1, 1 }}})
SH4_TEST(test_shlr2, SH4Test {0x30, (uint8_t *)"\x1d\x40\x0b\x00\x09\x00\x1d\x40\x0b\x00\x09\x00\x1d\x40\x0b\x00\x09\x00\x20\x40\x29\x01\x0b\x00\x09\x00\x00\x40\x29\x01\x0b\x00\x09\x00\x01\x40\x29\x01\x0b\x00\x09\x00\x08\x40\x0b\x00\x09\x00\x09\x40\x0b\x00\x09\x00\x18\x40\x0b\x00\x09\x00\x19\x40\x0b\x00\x09\x00\x28\x40\x0b\x00\x09\x00\x29\x40\x0b\x00\x09\x00", 78, {{ SH4CTX_R0, 0x4 }}, {}})
SH4_TEST(test_shll16, SH4Test {0x42, (uint8_t *)"\x1d\x40\x0b\x00\x09\x00\x1d\x40\x0b\x00\x09\x00\x1d\x40\x0b\x00\x09\x00\x20\x40\x29\x01\x0b\x00\x09\x00\x00\x40\x29\x01\x0b\x00\x09\x00\x01\x40\x29\x01\x0b\x00\x09\x00\x08\x40\x0b\x00\x09\x00\x09\x40\x0b\x00\x09\x00\x18\x40\x0b\x00\x09\x00\x19\x40\x0b\x00\x09\x00\x28\x40\x0b\x00\x09\x00\x29\x40\x0b\x00\x09\x00", 78, {{ SH4CTX_R0, 0x1 }}, {}})
SH4_TEST(test_shld_right_overflow, SH4Test {0xc, (uint8_t *)"\x1d\x40\x0b\x00\x09\x00\x1d\x40\x0b\x00\x09\x00\x1d\x40\x0b\x00\x09\x00\x20\x40\x29\x01\x0b\x00\x09\x00\x00\x40\x29\x01\x0b\x00\x09\x00\x01\x40\x29\x01\x0b\x00\x09\x00\x08\x40\x0b\x00\x09\x00\x09\x40\x0b\x00\x09\x00\x18\x40\x0b\x00\x09\x00\x19\x40\x0b\x00\x09\x00\x28\x40\x0b\x00\x09\x00\x29\x40\x0b\x00\x09\x00", 78, {{ SH4CTX_R0, 0x80180000 }, { SH4CTX_R1, -32 }}, {{ SH4CTX_R0, 0x0 }}})
SH4_TEST(test_shll2, SH4Test {0x2a, (uint8_t *)"\x1d\x40\x0b\x00\x09\x00\x1d\x40\x0b\x00\x09\x00\x1d\x40\x0b\x00\x09\x00\x20\x40\x29\x01\x0b\x00\x09\x00\x00\x40\x29\x01\x0b\x00\x09\x00\x01\x40\x29\x01\x0b\x00\x09\x00\x08\x40\x0b\x00\x09\x00\x09\x40\x0b\x00\x09\x00\x18\x40\x0b\x00\x09\x00\x19\x40\x0b\x00\x09\x00\x28\x40\x0b\x00\x09\x00\x29\x40\x0b\x00\x09\x00", 78, {{ SH4CTX_R0, 0x1 }}, {}})
SH4_TEST(test_shal, SH4Test {0x12, (uint8_t *)"\x1d\x40\x0b\x00\x09\x00\x1d\x40\x0b\x00\x09\x00\x1d\x40\x0b\x00\x09\x00\x20\x40\x29\x01\x0b\x00\x09\x00\x00\x40\x29\x01\x0b\x00\x09\x00\x01\x40\x29\x01\x0b\x00\x09\x00\x08\x40\x0b\x00\x09\x00\x09\x40\x0b\x00\x09\x00\x18\x40\x0b\x00\x09\x00\x19\x40\x0b\x00\x09\x00\x28\x40\x0b\x00\x09\x00\x29\x40\x0b\x00\x09\x00", 78, {{ SH4CTX_R0, 0x80000001 }}, {{ SH4CTX_R0, 0x2 }, { SH4CTX_R1, 1 }}})
SH4_TEST(test_shld_right, SH4Test {0x6, (uint8_t *)"\x1d\x40\x0b\x00\x09\x00\x1d\x40\x0b\x00\x09\x00\x1d\x40\x0b\x00\x09\x00\x20\x40\x29\x01\x0b\x00\x09\x00\x00\x40\x29\x01\x0b\x00\x09\x00\x01\x40\x29\x01\x0b\x00\x09\x00\x08\x40\x0b\x00\x09\x00\x09\x40\x0b\x00\x09\x00\x18\x40\x0b\x00\x09\x00\x19\x40\x0b\x00\x09\x00\x28\x40\x0b\x00\x09\x00\x29\x40\x0b\x00\x09\x00", 78, {{ SH4CTX_R0, 0x80180000 }, { SH4CTX_R1, -16 }}, {{ SH4CTX_R0, 0x00008018 }}})
SH4_TEST(test_shll8, SH4Test {0x36, (uint8_t *)"\x1d\x40\x0b\x00\x09\x00\x1d\x40\x0b\x00\x09\x00\x1d\x40\x0b\x00\x09\x00\x20\x40\x29\x01\x0b\x00\x09\x00\x00\x40\x29\x01\x0b\x00\x09\x00\x01\x40\x29\x01\x0b\x00\x09\x00\x08\x40\x0b\x00\x09\x00\x09\x40\x0b\x00\x09\x00\x18\x40\x0b\x00\x09\x00\x19\x40\x0b\x00\x09\x00\x28\x40\x0b\x00\x09\x00\x29\x40\x0b\x00\x09\x00", 78, {{ SH4CTX_R0, 0x1 }}, {}})
SH4_TEST(test_shlr, SH4Test {0x22, (uint8_t *)"\x1d\x40\x0b\x00\x09\x00\x1d\x40\x0b\x00\x09\x00\x1d\x40\x0b\x00\x09\x00\x20\x40\x29\x01\x0b\x00\x09\x00\x00\x40\x29\x01\x0b\x00\x09\x00\x01\x40\x29\x01\x0b\x00\x09\x00\x08\x40\x0b\x00\x09\x00\x09\x40\x0b\x00\x09\x00\x18\x40\x0b\x00\x09\x00\x19\x40\x0b\x00\x09\x00\x28\x40\x0b\x00\x09\x00\x29\x40\x0b\x00\x09\x00", 78, {{ SH4CTX_R0, 0x80000001 }}, {{ SH4CTX_R0, 0x40000000 }, { SH4CTX_R1, 1 }}})
SH4_TEST(test_shlr16, SH4Test {0x48, (uint8_t *)"\x1d\x40\x0b\x00\x09\x00\x1d\x40\x0b\x00\x09\x00\x1d\x40\x0b\x00\x09\x00\x20\x40\x29\x01\x0b\x00\x09\x00\x00\x40\x29\x01\x0b\x00\x09\x00\x01\x40\x29\x01\x0b\x00\x09\x00\x08\x40\x0b\x00\x09\x00\x09\x40\x0b\x00\x09\x00\x18\x40\x0b\x00\x09\x00\x19\x40\x0b\x00\x09\x00\x28\x40\x0b\x00\x09\x00\x29\x40\x0b\x00\x09\x00", 78, {{ SH4CTX_R0, 0x10000 }}, {}})
SH4_TEST(test_sub, SH4Test {0x0, (uint8_t *)"\x18\x32\x0b\x00\x09\x00", 6, {{ SH4CTX_R1, -24 }, { SH4CTX_R2, -11 }}, {{ SH4CTX_R2, 13 }}})
SH4_TEST(test_subc_nocarry, SH4Test {0x0, (uint8_t *)"\x1a\x30\x29\x01\x0b\x00\x09\x00\x1a\x30\x29\x01\x0b\x00\x09\x00\x18\x00\x1a\x30\x29\x01\x0b\x00\x09\x00", 26, {{ SH4CTX_R0, 1 }, { SH4CTX_R1, 1 }}, {{ SH4CTX_R0, 0x0 }, { SH4CTX_R1, 0 }}})
SH4_TEST(test_subc_carry_t1, SH4Test {0x10, (uint8_t *)"\x1a\x30\x29\x01\x0b\x00\x09\x00\x1a\x30\x29\x01\x0b\x00\x09\x00\x18\x00\x1a\x30\x29\x01\x0b\x00\x09\x00", 26, {{ SH4CTX_R0, 0 }, { SH4CTX_R1, 1 }}, {{ SH4CTX_R0, 0xfffffffe }, { SH4CTX_R1, 1 }}})
SH4_TEST(test_subc_carry_t0, SH4Test {0x8, (uint8_t *)"\x1a\x30\x29\x01\x0b\x00\x09\x00\x1a\x30\x29\x01\x0b\x00\x09\x00\x18\x00\x1a\x30\x29\x01\x0b\x00\x09\x00", 26, {{ SH4CTX_R0, 0 }, { SH4CTX_R1, 1 }}, {{ SH4CTX_R0, 0xffffffff }, { SH4CTX_R1, 1 }}})
SH4_TEST(test_subv_pnp, SH4Test {0x10, (uint8_t *)"\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00", 64, {{ SH4CTX_R0, 0x7ffffffe }, { SH4CTX_R1, 0xffffffff }}, {{ SH4CTX_R0, 0x7fffffff }, { SH4CTX_R1, 0 }}})
SH4_TEST(test_subv_ppp, SH4Test {0x0, (uint8_t *)"\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00", 64, {{ SH4CTX_R0, 0x7fffffff }, { SH4CTX_R1, 0x7ffffffe }}, {{ SH4CTX_R0, 0x00000001 }, { SH4CTX_R1, 0 }}})
SH4_TEST(test_subv_pnn_overflow, SH4Test {0x18, (uint8_t *)"\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00", 64, {{ SH4CTX_R0, 0x7fffffff }, { SH4CTX_R1, 0xffffffff }}, {{ SH4CTX_R0, 0x80000000 }, { SH4CTX_R1, 1 }}})
SH4_TEST(test_subv_nnn, SH4Test {0x38, (uint8_t *)"\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00", 64, {{ SH4CTX_R0, 0x80000000 }, { SH4CTX_R1, 0x80000001 }}, {{ SH4CTX_R0, 0xffffffff }, { SH4CTX_R1, 0 }}})
SH4_TEST(test_subv_nnp, SH4Test {0x30, (uint8_t *)"\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00", 64, {{ SH4CTX_R0, 0x80000001 }, { SH4CTX_R1, 0x80000000 }}, {{ SH4CTX_R0, 0x00000001 }, { SH4CTX_R1, 0 }}})
SH4_TEST(test_subv_npn, SH4Test {0x28, (uint8_t *)"\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00", 64, {{ SH4CTX_R0, 0x80000001 }, { SH4CTX_R1, 0x00000001 }}, {{ SH4CTX_R0, 0x80000000 }, { SH4CTX_R1, 0 }}})
SH4_TEST(test_subv_npp_overflow, SH4Test {0x20, (uint8_t *)"\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00", 64, {{ SH4CTX_R0, 0x80000000 }, { SH4CTX_R1, 0x00000001 }}, {{ SH4CTX_R0, 0x7fffffff }, { SH4CTX_R1, 1 }}})
SH4_TEST(test_subv_ppn, SH4Test {0x8, (uint8_t *)"\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00\x1b\x30\x29\x01\x0b\x00\x09\x00", 64, {{ SH4CTX_R0, 0x7ffffffe }, { SH4CTX_R1, 0x7fffffff }}, {{ SH4CTX_R0, 0xffffffff }, { SH4CTX_R1, 0 }}})
SH4_TEST(test_swapb, SH4Test {0x0, (uint8_t *)"\x08\x61\x0b\x00\x09\x00\x09\x61\x0b\x00\x09\x00\x0d\x21\x0b\x00\x09\x00", 18, {{ SH4CTX_R0, 0xfffffff0 }}, {{ SH4CTX_R1, 0xfffff0ff }}})
SH4_TEST(test_xtrct, SH4Test {0xc, (uint8_t *)"\x08\x61\x0b\x00\x09\x00\x09\x61\x0b\x00\x09\x00\x0d\x21\x0b\x00\x09\x00", 18, {{ SH4CTX_R0, 0xfffff0ff }, { SH4CTX_R1, 0xfff0ffff }}, {{ SH4CTX_R1, 0xf0fffff0 }}})
SH4_TEST(test_swapw, SH4Test {0x6, (uint8_t *)"\x08\x61\x0b\x00\x09\x00\x09\x61\x0b\x00\x09\x00\x0d\x21\x0b\x00\x09\x00", 18, {{ SH4CTX_R0, 0xfffffff0 }}, {{ SH4CTX_R1, 0xfff0ffff }}})
SH4_TEST(test_tst_imm_nonzero, SH4Test {0x34, (uint8_t *)"\x1b\xd1\x1b\x41\x29\x02\x12\x63\x0b\x00\x09\x00\x18\xd1\x22\x21\x1b\x41\x29\x02\x12\x63\x0b\x00\x09\x00\x18\x20\x29\x02\x0b\x00\x09\x00\x18\x20\x29\x02\x0b\x00\x09\x00\xf0\xe0\x0f\xc8\x29\x01\x0b\x00\x09\x00\xff\xe0\xff\xc8\x29\x01\x0b\x00\x09\x00\x0c\xd0\x1e\x40\x08\xe0\xff\xcc\x29\x01\x0b\x00\x09\x00\x08\xd0\x1e\x40\x04\xe0\xff\xcc\x29\x01\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x00\xff\xff\x00\x00\x00\x00\xff\xff\x09\x00\x09\x00\x60\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 128, {}, {{ SH4CTX_R1, 0 }}})
SH4_TEST(test_tst_nonzero, SH4Test {0x22, (uint8_t *)"\x1b\xd1\x1b\x41\x29\x02\x12\x63\x0b\x00\x09\x00\x18\xd1\x22\x21\x1b\x41\x29\x02\x12\x63\x0b\x00\x09\x00\x18\x20\x29\x02\x0b\x00\x09\x00\x18\x20\x29\x02\x0b\x00\x09\x00\xf0\xe0\x0f\xc8\x29\x01\x0b\x00\x09\x00\xff\xe0\xff\xc8\x29\x01\x0b\x00\x09\x00\x0c\xd0\x1e\x40\x08\xe0\xff\xcc\x29\x01\x0b\x00\x09\x00\x08\xd0\x1e\x40\x04\xe0\xff\xcc\x29\x01\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x00\xff\xff\x00\x00\x00\x00\xff\xff\x09\x00\x09\x00\x60\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 128, {{ SH4CTX_R0, 0xffff0000 }, { SH4CTX_R1, 0xffff0000 }}, {{ SH4CTX_R2, 0 }}})
SH4_TEST(test_tasb_zero, SH4Test {0x0, (uint8_t *)"\x1b\xd1\x1b\x41\x29\x02\x12\x63\x0b\x00\x09\x00\x18\xd1\x22\x21\x1b\x41\x29\x02\x12\x63\x0b\x00\x09\x00\x18\x20\x29\x02\x0b\x00\x09\x00\x18\x20\x29\x02\x0b\x00\x09\x00\xf0\xe0\x0f\xc8\x29\x01\x0b\x00\x09\x00\xff\xe0\xff\xc8\x29\x01\x0b\x00\x09\x00\x0c\xd0\x1e\x40\x08\xe0\xff\xcc\x29\x01\x0b\x00\x09\x00\x08\xd0\x1e\x40\x04\xe0\xff\xcc\x29\x01\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x00\xff\xff\x00\x00\x00\x00\xff\xff\x09\x00\x09\x00\x60\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 128, {}, {{ SH4CTX_R2, 1 }, { SH4CTX_R3, 128 }}})
SH4_TEST(test_tasb_nonzero, SH4Test {0xc, (uint8_t *)"\x1b\xd1\x1b\x41\x29\x02\x12\x63\x0b\x00\x09\x00\x18\xd1\x22\x21\x1b\x41\x29\x02\x12\x63\x0b\x00\x09\x00\x18\x20\x29\x02\x0b\x00\x09\x00\x18\x20\x29\x02\x0b\x00\x09\x00\xf0\xe0\x0f\xc8\x29\x01\x0b\x00\x09\x00\xff\xe0\xff\xc8\x29\x01\x0b\x00\x09\x00\x0c\xd0\x1e\x40\x08\xe0\xff\xcc\x29\x01\x0b\x00\x09\x00\x08\xd0\x1e\x40\x04\xe0\xff\xcc\x29\x01\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x00\xff\xff\x00\x00\x00\x00\xff\xff\x09\x00\x09\x00\x60\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 128, {{ SH4CTX_R2, 1 }}, {{ SH4CTX_R2, 0 }, { SH4CTX_R3, 129 }}})
SH4_TEST(test_tst_disp_nonzero, SH4Test {0x4c, (uint8_t *)"\x1b\xd1\x1b\x41\x29\x02\x12\x63\x0b\x00\x09\x00\x18\xd1\x22\x21\x1b\x41\x29\x02\x12\x63\x0b\x00\x09\x00\x18\x20\x29\x02\x0b\x00\x09\x00\x18\x20\x29\x02\x0b\x00\x09\x00\xf0\xe0\x0f\xc8\x29\x01\x0b\x00\x09\x00\xff\xe0\xff\xc8\x29\x01\x0b\x00\x09\x00\x0c\xd0\x1e\x40\x08\xe0\xff\xcc\x29\x01\x0b\x00\x09\x00\x08\xd0\x1e\x40\x04\xe0\xff\xcc\x29\x01\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x00\xff\xff\x00\x00\x00\x00\xff\xff\x09\x00\x09\x00\x60\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 128, {}, {}})
SH4_TEST(test_tst_zero, SH4Test {0x1a, (uint8_t *)"\x1b\xd1\x1b\x41\x29\x02\x12\x63\x0b\x00\x09\x00\x18\xd1\x22\x21\x1b\x41\x29\x02\x12\x63\x0b\x00\x09\x00\x18\x20\x29\x02\x0b\x00\x09\x00\x18\x20\x29\x02\x0b\x00\x09\x00\xf0\xe0\x0f\xc8\x29\x01\x0b\x00\x09\x00\xff\xe0\xff\xc8\x29\x01\x0b\x00\x09\x00\x0c\xd0\x1e\x40\x08\xe0\xff\xcc\x29\x01\x0b\x00\x09\x00\x08\xd0\x1e\x40\x04\xe0\xff\xcc\x29\x01\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x00\xff\xff\x00\x00\x00\x00\xff\xff\x09\x00\x09\x00\x60\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 128, {{ SH4CTX_R0, 0x0000ffff }, { SH4CTX_R1, 0xffff0000 }}, {{ SH4CTX_R2, 1 }}})
SH4_TEST(test_tst_imm_zero, SH4Test {0x2a, (uint8_t *)"\x1b\xd1\x1b\x41\x29\x02\x12\x63\x0b\x00\x09\x00\x18\xd1\x22\x21\x1b\x41\x29\x02\x12\x63\x0b\x00\x09\x00\x18\x20\x29\x02\x0b\x00\x09\x00\x18\x20\x29\x02\x0b\x00\x09\x00\xf0\xe0\x0f\xc8\x29\x01\x0b\x00\x09\x00\xff\xe0\xff\xc8\x29\x01\x0b\x00\x09\x00\x0c\xd0\x1e\x40\x08\xe0\xff\xcc\x29\x01\x0b\x00\x09\x00\x08\xd0\x1e\x40\x04\xe0\xff\xcc\x29\x01\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x00\xff\xff\x00\x00\x00\x00\xff\xff\x09\x00\x09\x00\x60\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 128, {}, {{ SH4CTX_R1, 1 }}})
SH4_TEST(test_tst_disp_zero, SH4Test {0x3e, (uint8_t *)"\x1b\xd1\x1b\x41\x29\x02\x12\x63\x0b\x00\x09\x00\x18\xd1\x22\x21\x1b\x41\x29\x02\x12\x63\x0b\x00\x09\x00\x18\x20\x29\x02\x0b\x00\x09\x00\x18\x20\x29\x02\x0b\x00\x09\x00\xf0\xe0\x0f\xc8\x29\x01\x0b\x00\x09\x00\xff\xe0\xff\xc8\x29\x01\x0b\x00\x09\x00\x0c\xd0\x1e\x40\x08\xe0\xff\xcc\x29\x01\x0b\x00\x09\x00\x08\xd0\x1e\x40\x04\xe0\xff\xcc\x29\x01\x0b\x00\x09\x00\x09\x00\x09\x00\x09\x00\x00\x00\x00\x00\xff\xff\x00\x00\x00\x00\xff\xff\x09\x00\x09\x00\x60\x00\x01\x8c\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00\x09\x00", 128, {}, {{ SH4CTX_R1, 1 }}})
SH4_TEST(test_xor_imm, SH4Test {0x6, (uint8_t *)"\x1a\x20\x0b\x00\x09\x00\xff\xca\x0b\x00\x09\x00", 12, {{ SH4CTX_R0, 0x00ffffff }}, {{ SH4CTX_R0, 0x00ffff00 }}})
SH4_TEST(test_xor, SH4Test {0x0, (uint8_t *)"\x1a\x20\x0b\x00\x09\x00\xff\xca\x0b\x00\x09\x00", 12, {{ SH4CTX_R0, 0x00ffffff }, { SH4CTX_R1, 0xffffff00 }}, {{ SH4CTX_R0, 0xff0000ff }}})

23
test/asm/sha.s
View File

@ -1,20 +1,9 @@
# REGISTER_IN r1 0xffffffe0
# REGISTER_IN r2 0x80180000
.text
.global start
start:
# SHAD Rm,Rn (-
test_shad:
# REGISTER_IN r1 0xffffffe0
# REGISTER_IN r2 0x80180000
shad r1, r2
rts
rts
nop
.align 4
.CONST:
.long 0xffffffec /* -20 */
.long 0xffffffe0 /* -32 */
.long 0x80180000 /* -2145910784 */
.long 0x00000014 /* 20 */
.long 0xfffff801 /* -2047 */
.long 0x80000001 /* -2147483647 */
# REGISTER_OUT r2 0xffffffff
# REGISTER_OUT r2 0xffffffff
# TODO ADD MORE TESTS

131
test/asm/shl.s
View File

@ -1,45 +1,92 @@
.text
.global start
start:
# SHLD Rm,Rn (-2145910784 >> 20) == -2047
mov.l .CONST, r1
mov.l .CONST+8, r2
shld r1, r2
# SHLD Rm,Rn (-2145910784 >> 32)
mov.l .CONST+4, r1
mov.l .CONST+8, r3
shld r1, r3
# SHLD Rm,Rn (-2047 << 20) == -2145910784
mov.l .CONST+12, r1
mov.l .CONST+16, r4
shld r1, r4
# SHLL Rn
mov.l .CONST+20, r5
shll r5
stc SR, r0
and #0x1, r0
mov r0, r6
# SHLR Rn
mov.l .CONST+20, r7
shlr r7
stc SR, r0
and #0x1, r0
mov r0, r8
test_shld_left:
# REGISTER_IN r0 0x00008018
# REGISTER_IN r1 16
shld r1, r0
rts
nop
# REGISTER_OUT r0 0x80180000
test_shld_right:
# REGISTER_IN r0 0x80180000
# REGISTER_IN r1 -16
shld r1, r0
rts
nop
# REGISTER_OUT r0 0x00008018
test_shld_right_overflow:
# REGISTER_IN r0 0x80180000
# REGISTER_IN r1 -32
shld r1, r0
rts
nop
# REGISTER_OUT r0 0x0
test_shal:
# REGISTER_IN r0 0x80000001
shal r0
movt r1
rts
nop
# REGISTER_OUT r0 0x2
# REGISTER_OUT r1 1
test_shll:
# REGISTER_IN r0 0x80000001
shll r0
movt r1
rts
nop
# REGISTER_OUT r0 0x2
# REGISTER_OUT r1 1
test_shlr:
# REGISTER_IN r0 0x80000001
shlr r0
movt r1
rts
nop
.align 4
.CONST:
.long 0xffffffec /* -20 */
.long 0xffffffe0 /* -32 */
.long 0x80180000 /* -2145910784 */
.long 0x00000014 /* 20 */
.long 0xfffff801 /* -2047 */
.long 0x80000001 /* -2147483647 */
# REGISTER_OUT r0 0x40000000
# REGISTER_OUT r1 1
# REGISTER_OUT r2 0x00000801
# REGISTER_OUT r3 0x0
# REGISTER_OUT r4 0x80100000
# REGISTER_OUT r5 0x00000002
# REGISTER_OUT r6 1
# REGISTER_OUT r7 0x40000000
# REGISTER_OUT r8 1
test_shll2:
# REGISTER_IN r0 0x1
shll2 r0
rts
nop
# REGISTER_OUT 0x4
test_shlr2:
# REGISTER_IN r0 0x4
shlr2 r0
rts
nop
# REGISTER_OUT 0x1
test_shll8:
# REGISTER_IN r0 0x1
shll8 r0
rts
nop
# REGISTER_OUT 0x100
test_shlr8:
# REGISTER_IN r0 0x100
shlr8 r0
rts
nop
# REGISTER_OUT 0x1
test_shll16:
# REGISTER_IN r0 0x1
shll16 r0
rts
nop
# REGISTER_OUT 0x10000
test_shlr16:
# REGISTER_IN r0 0x10000
shlr16 r0
rts
nop
# REGISTER_OUT 0x1

11
test/asm/sub.s
View File

@ -1,10 +1,7 @@
# REGISTER_IN r1 -24
# REGISTER_IN r2 -11
.text
.global start
start:
test_sub:
# REGISTER_IN r1 -24
# REGISTER_IN r2 -11
sub r1, r2
rts
nop
# REGISTER_OUT r2 13
# REGISTER_OUT r2 13

59
test/asm/subc.s
View File

@ -1,35 +1,30 @@
# REGISTER_IN r1 1
# REGISTER_IN r2 1
# REGISTER_IN r3 0
# REGISTER_IN r4 1
# REGISTER_IN r5 0
# REGISTER_IN r6 1
.little
.text
.global start
start:
# r1 - r2 - T(0)
subc r2, r1
stc SR, r0
and #0x1, r0
mov r0, r2
# r3 - r4 - T(0)
subc r4, r3
stc SR, r0
and #0x1, r0
mov r0, r4
# r5 - r6 - T(1)
subc r6, r5
stc SR, r0
and #0x1, r0
mov r0, r6
test_subc_nocarry:
# REGISTER_IN r0 1
# REGISTER_IN r1 1
subc r1, r0
movt r1
rts
nop
# REGISTER_OUT r0 0x0
# REGISTER_OUT r1 0
# REGISTER_OUT r1 0x0
# REGISTER_OUT r2 0
# REGISTER_OUT r3 0xffffffff
# REGISTER_OUT r4 1
# REGISTER_OUT r5 0xfffffffe
# REGISTER_OUT r6 1
test_subc_carry_t0:
# REGISTER_IN r0 0
# REGISTER_IN r1 1
subc r1, r0
movt r1
rts
nop
# REGISTER_OUT r0 0xffffffff
# REGISTER_OUT r1 1
test_subc_carry_t1:
# REGISTER_IN r0 0
# REGISTER_IN r1 1
sett
subc r1, r0
movt r1
rts
nop
# REGISTER_OUT r0 0xfffffffe
# REGISTER_OUT r1 1

183
test/asm/subv.s
View File

@ -1,101 +1,90 @@
# l r sum
# ---------------------------
# 0 0 0
# 0 0 1
# 0 1 0
# *OVER* 0 1 1 (subtracting a negative is the same as adding a positive)
# *OVER* 1 0 0 (subtracting a positive is the same as adding a negative)
# 1 0 1
# 1 1 0
# 1 1 1
.little
.text
.global start
start:
# 0x7fffffff(0) - 0x7ffffffe(0) = 0x00000001(0)
mov.l .L4, r0
mov.l .L3, r1
subv r0, r1
stc SR, r0
and #0x1, r0
mov r0, r2
# 0x7ffffffe(0) - 0x7fffffff(0) = 0xffffffff(1)
mov.l .L3, r0
mov.l .L4, r3
subv r0, r3
stc SR, r0
and #0x1, r0
mov r0, r4
# 0x7ffffffe(0) - 0xffffffff(1) = 0x7fffffff(1)
mov #-1, r0
mov.l .L4, r5
subv r0, r5
stc SR, r0
and #0x1, r0
mov r0, r6
# 0x7fffffff(0) - 0xfffffffff(1) = 0x80000000(1), OVERFLOWED
mov #-1, r0
mov.l .L3, r7
subv r0, r7
stc SR, r0
and #0x1, r0
mov r0, r8
# 0x80000000(1) - 0x00000001(0) = 0x7fffffff(0), OVERFLOWED
mov #0x1, r0
mov.l .L2, r9
subv r0, r9
stc SR, r0
and #0x1, r0
mov r0, r10
# 0x80000001(1) - 0x00000001(0) = 0x80000000(1)
mov #0x1, r0
mov.l .L1, r11
subv r0, r11
stc SR, r0
and #0x1, r0
mov r0, r12
# 0x80000001(1) - 0x80000000(1) = 0x00000001(0)
mov.l .L2, r0
mov.l .L1, r13
subv r0, r13
stc SR, r0
and #0x1, r0
mov r0, r14
# 0x80000000(1) - 0x80000001(1) = 0xffffffff(1)
mov.l .L1, r0
mov.l .L2, r15
subv r0, r15
stc SR, r0
and #0x1, r0
# truth table for signed subtraction, 0 for positive, 1 for negative
# ------------------------------------------------------------------
# 0 - 0 = 0
# 0 - 0 = 1
# 0 - 1 = 0
# 0 - 1 = 1 *OVERFLOW*
# 1 - 0 = 0 *OVERFLOW*
# 1 - 0 = 1
# 1 - 1 = 0
# 1 - 1 = 1
test_subv_ppp:
# REGISTER_IN r0 0x7fffffff
# REGISTER_IN r1 0x7ffffffe
subv r1, r0
movt r1
rts
nop
.align 4
.L1:
.long 0x80000001
.align 4
.L2:
.long 0x80000000
.align 4
.L3:
.long 0x7fffffff
.align 4
.L4:
.long 0x7ffffffe
# REGISTER_OUT r0 0x00000001
# REGISTER_OUT r1 0
# REGISTER_OUT r1 0x00000001
# REGISTER_OUT r2 0
# REGISTER_OUT r3 0xffffffff
# REGISTER_OUT r4 0
# REGISTER_OUT r5 0x7fffffff
# REGISTER_OUT r6 0
# REGISTER_OUT r7 0x80000000
# REGISTER_OUT r8 1
# REGISTER_OUT r9 0x7fffffff
# REGISTER_OUT r10 1
# REGISTER_OUT r11 0x80000000
# REGISTER_OUT r12 0
# REGISTER_OUT r13 0x00000001
# REGISTER_OUT r14 0
# REGISTER_OUT r15 0xffffffff
# REGISTER_OUT r0 0
test_subv_ppn:
# REGISTER_IN r0 0x7ffffffe
# REGISTER_IN r1 0x7fffffff
subv r1, r0
movt r1
rts
nop
# REGISTER_OUT r0 0xffffffff
# REGISTER_OUT r1 0
test_subv_pnp:
# REGISTER_IN r0 0x7ffffffe
# REGISTER_IN r1 0xffffffff
subv r1, r0
movt r1
rts
nop
# REGISTER_OUT r0 0x7fffffff
# REGISTER_OUT r1 0
test_subv_pnn_overflow:
# REGISTER_IN r0 0x7fffffff
# REGISTER_IN r1 0xffffffff
subv r1, r0
movt r1
rts
nop
# REGISTER_OUT r0 0x80000000
# REGISTER_OUT r1 1
test_subv_npp_overflow:
# REGISTER_IN r0 0x80000000
# REGISTER_IN r1 0x00000001
subv r1, r0
movt r1
rts
nop
# REGISTER_OUT r0 0x7fffffff
# REGISTER_OUT r1 1
test_subv_npn:
# REGISTER_IN r0 0x80000001
# REGISTER_IN r1 0x00000001
subv r1, r0
movt r1
rts
nop
# REGISTER_OUT r0 0x80000000
# REGISTER_OUT r1 0
test_subv_nnp:
# REGISTER_IN r0 0x80000001
# REGISTER_IN r1 0x80000000
subv r1, r0
movt r1
rts
nop
# REGISTER_OUT r0 0x00000001
# REGISTER_OUT r1 0
test_subv_nnn:
# REGISTER_IN r0 0x80000000
# REGISTER_IN r1 0x80000001
subv r1, r0
movt r1
rts
nop
# REGISTER_OUT r0 0xffffffff
# REGISTER_OUT r1 0

29
test/asm/swap.s
View File

@ -1,16 +1,21 @@
# REGISTER_IN r0 0xfffffff0
.little
.text
.global start
start:
test_swapb:
# REGISTER_IN r0 0xfffffff0
swap.b r0, r1
swap.w r0, r2
mov r2, r3
xtrct r1, r3
rts
nop
# REGISTER_OUT r1 0xfffff0ff
# REGISTER_OUT r1 0xfffff0ff
# REGISTER_OUT r2 0xfff0ffff
# REGISTER_OUT r3 0xf0fffff0
test_swapw:
# REGISTER_IN r0 0xfffffff0
swap.w r0, r1
rts
nop
# REGISTER_OUT r1 0xfff0ffff
test_xtrct:
# REGISTER_IN r0 0xfffff0ff
# REGISTER_IN r1 0xfff0ffff
xtrct r0, r1
rts
nop
# REGISTER_OUT r1 0xf0fffff0

118
test/asm/tst.s
View File

@ -1,77 +1,85 @@
.text
.global start
start:
# TAS.B @Rn, (Rn)=0
test_tasb_zero:
mov.l .L2, r1
tas.b @r1
stc SR, r0
and #0x1, r0
mov r0, r2
# TAS.B @Rn, (Rn)=1
movt r2
mov.l @r1, r3
rts
nop
# REGISTER_OUT r2 1
# REGISTER_OUT r3 128
test_tasb_nonzero:
# REGISTER_IN r2 1
mov.l .L2, r1
mov.l r2, @r1
tas.b @r1
stc SR, r0
and #0x1, r0
mov r0, r3
mov.l @r1, r4
# TST Rm,Rn, Rn & Rm = 0
mov.l .L1+4, r0
mov.l .L1+8, r1
movt r2
mov.l @r1, r3
rts
nop
# REGISTER_OUT r2 0
# REGISTER_OUT r3 129
test_tst_zero:
# REGISTER_IN r0 0x0000ffff
# REGISTER_IN r1 0xffff0000
tst r1, r0
stc SR, r0
and #0x1, r0
mov r0, r5
# TST Rm,Rn, Rn & Rm = 0xffff0000
mov.l .L1+8, r0
mov.l .L1+8, r1
movt r2
rts
nop
# REGISTER_OUT r2 1
test_tst_nonzero:
# REGISTER_IN r0 0xffff0000
# REGISTER_IN r1 0xffff0000
tst r1, r0
stc SR, r0
and #0x1, r0
mov r0, r6
# TST #imm,R0, R0 & imm = 0
mov.l .L1+8, r0
movt r2
rts
nop
# REGISTER_OUT r2 0
test_tst_imm_zero:
mov #0xf0, r0
tst #0x0f, r0
movt r1
rts
nop
# REGISTER_OUT r1 1
test_tst_imm_nonzero:
mov #0xff, r0
tst #0xff, r0
stc SR, r0
and #0x1, r0
mov r0, r7
# TST #imm,R0, R0 & imm = 0x000000ff
mov.l .L1+4, r0
tst #0xff, r0
stc SR, r0
and #0x1, r0
mov r0, r8
# TST.B #imm,@(R0,GBR), (R0 + GBR) & imm = 0
movt r1
rts
nop
# REGISTER_OUT r1 0
test_tst_disp_zero:
mov.l .L2, r0
ldc r0, GBR
mov #8, r0
tst.b #0xff, @(r0, GBR)
stc SR, r0
and #0x1, r0
mov r0, r9
# TST.B #imm,@(R0,GBR), (R0 + GBR) & imm = 0x000000ff
movt r1
rts
nop
# REGISTER_OUT r1 1
test_tst_disp_nonzero:
mov.l .L2, r0
ldc r0, GBR
mov #4, r0
tst.b #0xff, @(r0, GBR)
stc SR, r0
and #0x1, r0
mov r0, r10
movt r1
rts
nop
.align 4
# REGISTER_OU r1 0
.align 4
.L1:
.long 0x0
.long 0x0000ffff
.long 0xffff0000
.align 4
.align 4
.L2:
.long .L1
# REGISTER_OUT r2 1
# REGISTER_OUT r3 0
# REGISTER_OUT r4 128
# REGISTER_OUT r5 1
# REGISTER_OUT r6 0
# REGISTER_OUT r7 1
# REGISTER_OUT r8 0
# REGISTER_OUT r9 1
# REGISTER_OU r10 0

22
test/asm/xor.s
View File

@ -1,16 +1,14 @@
# REGISTER_IN r0 0x00ffffff
# REGISTER_IN r1 0xffffff00
# REGISTER_IN r2 0x000000fc
test_xor:
# REGISTER_IN r0 0x00ffffff
# REGISTER_IN r1 0xffffff00
xor r1, r0
# REGISTER_OUT r0 0xff0000ff
rts
nop
.text
.global start
start:
# XOR Rm,Rn
xor r0, r1
# XOR #imm,R0
test_xor_imm:
# REGISTER_IN r0 0x00ffffff
xor #0xff, r0
rts
nop
# REGISTER_OUT r0 0x00ffff00
# REGISTER_OUT r1 0xff0000ff
# REGISTER_OUT r0 0x00ffff00

1
test/sh4_test.h
View File

@ -19,6 +19,7 @@ struct SH4CTXReg {
extern SH4CTXReg sh4ctx_reg[NUM_SH4CTX_REGS];
struct SH4Test {
uint32_t offset;
uint8_t *buffer;
size_t buffer_size;
std::map<int, uint64_t> r_in;

90
test/sh4_test.py
View File

@ -12,55 +12,89 @@ parser = argparse.ArgumentParser(description='Process an assembly source file an
parser.add_argument('input', nargs='+', help='Specifies the input file(s).')
parser.add_argument('-as', help='sh-elf-as path.', required=True)
parser.add_argument('-ld', help='sh-elf-ld path.', required=True)
parser.add_argument('-nm', help='sh-elf-nm path.', required=True)
parser.add_argument('-objcopy', help='sh-elf-objcopy path.', required=True)
parser.add_argument('-o', help='Specifies the output file.', required=True)
args = parser.parse_args()
def asm_to_bin(input_path):
obj = tempfile.mktemp(suffix='.obj')
srec = tempfile.mktemp(suffix='.srec')
bin = tempfile.mktemp(suffix='.bin')
subprocess.call([vars(args)['as'], '-little', '-o', obj, input_path])
subprocess.call([vars(args)['ld'], '--oformat', 'srec', '-Ttext', '0x8c010000', '-o', srec, obj])
subprocess.call([vars(args)['objcopy'], '-I', 'srec', '-O', 'binary', '-R', '.sec1', srec, bin])
with open(bin, 'r') as f:
return f.read()
def compile_asm(input_path):
obj_file = tempfile.mktemp(suffix='.obj')
srec_file = tempfile.mktemp(suffix='.srec')
bin_file = tempfile.mktemp(suffix='.bin')
subprocess.call([vars(args)['as'], '-little', '-o', obj_file, input_path])
subprocess.call([vars(args)['ld'], '--oformat', 'srec', '-Ttext', '0x8c010000', '-e', '0x8c010000', '-o', srec_file, obj_file])
map = subprocess.check_output([vars(args)['nm'], obj_file])
subprocess.call([vars(args)['objcopy'], '-I', 'srec', '-O', 'binary', '-R', '.sec1', srec_file, bin_file])
with open(bin_file, 'r') as f:
bin = f.read()
return (map, bin)
def asm_to_test(input_path):
# parse input
def parse_symbol_map(map, bin):
tests = {}
symbols = re.findall('([\d\w]+)\s+t\s+(test_.+)', map)
for i, symbol in enumerate(symbols):
offset = int(symbol[0], 16)
name = symbol[1]
tests[name] = { 'offset': offset, 'bin': bin, 'register_in': [], 'register_out': [] }
return tests
def asm_to_tests(input_path):
map, bin = compile_asm(input_path)
# generate a test for each symbol in the map
tests = parse_symbol_map(map, bin)
# parse input, generating input / output registers for each test
with open(input_path, 'r') as f:
input_str = f.read()
lines = f.readlines()
binary = asm_to_bin(input_path)
register_in = re.findall('# REGISTER_IN\s+([^\s]+)\s+(.+)', input_str)
register_out = re.findall('# REGISTER_OUT\s+([^\s]+)\s+(.+)', input_str)
current_test = None
# generate output
for line in lines:
m = re.match('(test_.+?):', line)
if m:
current_test = m.group(1)
continue
m = re.match('\s+# REGISTER_IN\s+([^\s]+)\s+(.+)', line)
if m:
test = tests[current_test]
test['register_in'].append((m.group(1), m.group(2)))
continue
m = re.match('\s+# REGISTER_OUT\s+([^\s]+)\s+(.+)', line)
if m:
test = tests[current_test]
test['register_out'].append((m.group(1), m.group(2)))
continue
return tests
def test_to_struct(test):
output = 'SH4Test {'
output += '(uint8_t *)"' + ''.join('\\x' + x.encode('hex') for x in binary) + '", '
output += str(len(binary)) + ', '
output += hex(test['offset']) + ', '
output += '(uint8_t *)"' + ''.join('\\x' + x.encode('hex') for x in test['bin']) + '", '
output += str(len(test['bin'])) + ', '
output += '{'
for i, entry in enumerate(register_in):
output += '{ SH4CTX_' + entry[0].upper() + ', ' + entry[1] + ' }'
if (i != len(register_in) - 1):
for i, val in enumerate(test['register_in']):
output += '{ SH4CTX_' + val[0].upper() + ', ' + val[1] + ' }'
if (i != len(test['register_in']) - 1):
output += ', '
output += '}, '
output += '{'
for i, entry in enumerate(register_out):
output += '{ SH4CTX_' + entry[0].upper() + ', ' + entry[1] + ' }'
if (i != len(register_out) - 1):
for i, val in enumerate(test['register_out']):
output += '{ SH4CTX_' + val[0].upper() + ', ' + val[1] + ' }'
if (i != len(test['register_out']) - 1):
output += ', '
output += '}'
output += '}'
return output
def list_to_inc(inputs, output_path):
with open(output_path, 'w') as f:
for input in inputs:
test_name = os.path.splitext(os.path.basename(input))[0]
test = asm_to_test(input)
f.write('SH4_TEST(' + test_name + ', ' + test + ')\n')
tests = asm_to_tests(input)
for name in tests:
struct = test_to_struct(tests[name])
f.write('SH4_TEST(' + name + ', ' + struct + ')\n')
if __name__ == '__main__':
list_to_inc(args.input, args.o)

12
test/test_sh4.cc
View File

@ -22,7 +22,7 @@ namespace cpu {
template <typename BACKEND>
void RunSH4Test(const SH4Test &test) {
static uint32_t pc = 0x8c010000;
static const uint32_t load_address = 0x8c010000;
Memory memory;
SH4Frontend rt_frontend(memory);
@ -32,7 +32,6 @@ void RunSH4Test(const SH4Test &test) {
// initialize cpu
SH4 sh4(memory, runtime);
sh4.Init();
sh4.SetPC(pc);
// mount a small stack (stack grows down)
uint8_t stack[MAX_PAGE_SIZE];
@ -44,7 +43,10 @@ void RunSH4Test(const SH4Test &test) {
static_cast<uint32_t>(MAX_PAGE_SIZE));
uint8_t *binary = new uint8_t[binary_size];
memcpy(binary, test.buffer, test.buffer_size);
memory.Mount(pc, pc + binary_size - 1, ~ADDR_MASK, binary);
memory.Mount(load_address, load_address + binary_size - 1, ~ADDR_MASK, binary);
// skip to the test's offset
sh4.SetPC(load_address + test.offset);
// setup in registers
for (auto it : test.r_in) {
@ -72,11 +74,11 @@ void RunSH4Test(const SH4Test &test) {
}
#define SH4_TEST(name, ...) \
TEST(SH4_interpreter, name) { \
TEST(sh4_interpreter, name) { \
SH4Test test = __VA_ARGS__; \
RunSH4Test<InterpreterBackend>(test); \
} \
TEST(SH4_x64, name) { \
TEST(sh4_x64, name) { \
SH4Test test = __VA_ARGS__; \
RunSH4Test<X64Backend>(test); \
}