mirror of https://github.com/inolen/redream.git
initial g2 dma support
This commit is contained in:
Anthony Pesch
parent
fdc4f3ae45
commit
1a761877c4
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@ -6,7 +6,157 @@
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struct reg_cb holly_cb[NUM_HOLLY_REGS];
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static void holly_update_sh4_interrupts(struct holly *hl) {
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static void holly_ch2_dma(struct holly *hl) {
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// FIXME what are SB_LMMODE0 / SB_LMMODE1
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struct sh4_dtr dtr = {0};
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dtr.channel = 2;
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dtr.rw = false;
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dtr.addr = *hl->SB_C2DSTAT;
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sh4_ddt(hl->sh4, &dtr);
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*hl->SB_C2DLEN = 0;
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*hl->SB_C2DST = 0;
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holly_raise_interrupt(hl, HOLLY_INTC_DTDE2INT);
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}
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static void holly_gdrom_dma(struct holly *hl) {
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if (!*hl->SB_GDEN) {
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return;
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}
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struct gdrom *gd = hl->gdrom;
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struct sh4 *sh4 = hl->sh4;
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CHECK_EQ(*hl->SB_GDDIR, 1); // gdrom -> sh4
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int transfer_size = *hl->SB_GDLEN;
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int remaining = transfer_size;
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uint32_t addr = *hl->SB_GDSTAR;
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gdrom_dma_begin(gd);
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while (remaining) {
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// read a single sector at a time from the gdrom
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uint8_t sector_data[SECTOR_SIZE];
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int n = gdrom_dma_read(gd, sector_data, sizeof(sector_data));
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struct sh4_dtr dtr = {0};
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dtr.channel = 0;
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dtr.rw = true;
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dtr.data = sector_data;
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dtr.addr = addr;
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dtr.size = n;
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sh4_ddt(sh4, &dtr);
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remaining -= n;
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addr += n;
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}
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gdrom_dma_end(gd);
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*hl->SB_GDSTARD = addr;
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*hl->SB_GDLEND = transfer_size;
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*hl->SB_GDST = 0;
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holly_raise_interrupt(hl, HOLLY_INTC_G1DEINT);
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}
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static void holly_g2_dma(struct holly *hl, int channel) {
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// clang-format off
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struct g2_channel_desc {
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int STAG, STAR, LEN, DIR, TSEL, EN, ST, SUSP;
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holly_interrupt_t INTR;
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};
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static struct g2_channel_desc channel_descs[] = {
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{SB_ADSTAG, SB_ADSTAR, SB_ADLEN, SB_ADDIR, SB_ADTSEL, SB_ADEN, SB_ADST, SB_ADSUSP, HOLLY_INTC_G2DEAINT},
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{SB_E1STAG, SB_E1STAR, SB_E1LEN, SB_E1DIR, SB_E1TSEL, SB_E1EN, SB_E1ST, SB_E1SUSP, HOLLY_INTC_G2DE1INT},
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{SB_E2STAG, SB_E2STAR, SB_E2LEN, SB_E2DIR, SB_E2TSEL, SB_E2EN, SB_E2ST, SB_E2SUSP, HOLLY_INTC_G2DE2INT},
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{SB_DDSTAG, SB_DDSTAR, SB_DDLEN, SB_DDDIR, SB_DDTSEL, SB_DDEN, SB_DDST, SB_DDSUSP, HOLLY_INTC_G2DEDINT},
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};
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// clang-format on
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struct g2_channel_desc *desc = &channel_descs[channel];
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uint32_t *STAG = &hl->reg[desc->STAG];
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uint32_t *STAR = &hl->reg[desc->STAR];
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uint32_t *LEN = &hl->reg[desc->LEN];
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uint32_t *DIR = &hl->reg[desc->DIR];
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uint32_t *TSEL = &hl->reg[desc->TSEL];
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uint32_t *EN = &hl->reg[desc->EN];
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uint32_t *ST = &hl->reg[desc->ST];
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uint32_t *SUSP = &hl->reg[desc->SUSP];
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holly_interrupt_t INTR = desc->INTR;
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if (!*EN) {
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return;
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}
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struct address_space *space = hl->sh4->memory_if->space;
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int transfer_size = *LEN & 0x7fffffff;
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int enable = *LEN >> 31;
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int remaining = transfer_size;
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uint32_t src = *STAR;
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uint32_t dst = *STAG;
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// only sh4 -> g2 supported for now
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CHECK_EQ(*DIR, 0);
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while (remaining) {
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as_write32(space, dst, as_read32(space, src));
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remaining -= 4;
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src += 4;
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dst += 4;
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}
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*STAR = src;
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*STAG = dst;
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*LEN = 0;
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*EN = enable ? 1 : *EN;
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*ST = 0;
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holly_raise_interrupt(hl, INTR);
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}
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static void holly_maple_dma(struct holly *hl) {
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if (!*hl->SB_MDEN) {
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return;
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}
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struct maple *mp = hl->maple;
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struct address_space *space = hl->sh4->memory_if->space;
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uint32_t addr = *hl->SB_MDSTAR;
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union maple_transfer desc;
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struct maple_frame frame, res;
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do {
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desc.full = as_read64(space, addr);
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addr += 8;
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// read input
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frame.header.full = as_read32(space, addr);
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addr += 4;
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for (uint32_t i = 0; i < frame.header.num_words; i++) {
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frame.params[i] = as_read32(space, addr);
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addr += 4;
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}
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// handle command and write response
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if (maple_handle_command(mp, desc.port, &frame, &res)) {
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as_write32(space, desc.result_addr, res.header.full);
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desc.result_addr += 4;
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for (uint32_t i = 0; i < res.header.num_words; i++) {
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as_write32(space, desc.result_addr, res.params[i]);
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desc.result_addr += 4;
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}
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} else {
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as_write32(space, desc.result_addr, 0xffffffff);
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}
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} while (!desc.last);
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*hl->SB_MDST = 0;
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holly_raise_interrupt(hl, HOLLY_INTC_MDEINT);
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}
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static void holly_update_interrupts(struct holly *hl) {
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// trigger the respective level-encoded interrupt on the sh4 interrupt
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// controller
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{
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@ -38,6 +188,8 @@ static void holly_update_sh4_interrupts(struct holly *hl) {
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sh4_clear_interrupt(hl->sh4, SH4_INTC_IRL_13);
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}
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}
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// TODO check for hardware DMA initiation
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}
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#define define_reg_read(name, type) \
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@ -92,14 +244,15 @@ void holly_raise_interrupt(struct holly *hl, holly_interrupt_t intr) {
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enum holly_interrupt_type type = HOLLY_INTERRUPT_TYPE(intr);
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uint32_t irq = HOLLY_INTERRUPT_IRQ(intr);
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if (intr == HOLLY_INTC_PCVOINT) {
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maple_vblank(hl->maple);
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}
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uint32_t *status = holly_interrupt_status(hl, type);
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*status |= irq;
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holly_update_sh4_interrupts(hl);
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holly_update_interrupts(hl);
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// check for hardware dma initiation
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if (intr == HOLLY_INTC_PCVOINT && *hl->SB_MDTSEL && *hl->SB_MDEN) {
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holly_maple_dma(hl);
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}
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}
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void holly_clear_interrupt(struct holly *hl, holly_interrupt_t intr) {
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@ -109,7 +262,7 @@ void holly_clear_interrupt(struct holly *hl, holly_interrupt_t intr) {
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uint32_t *status = holly_interrupt_status(hl, type);
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*status &= ~irq;
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holly_update_sh4_interrupts(hl);
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holly_update_interrupts(hl);
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}
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void holly_toggle_interrupt(struct holly *hl, holly_interrupt_t intr) {
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@ -161,240 +314,136 @@ REG_W32(holly_cb, SB_ISTNRM) {
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struct holly *hl = dc->holly;
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// writing a 1 clears the interrupt
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*hl->SB_ISTNRM &= ~value;
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holly_update_sh4_interrupts(hl);
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holly_update_interrupts(hl);
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}
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REG_W32(holly_cb, SB_ISTEXT) {
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struct holly *hl = dc->holly;
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*hl->SB_ISTEXT &= ~value;
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holly_update_sh4_interrupts(hl);
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holly_update_interrupts(hl);
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}
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REG_W32(holly_cb, SB_ISTERR) {
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struct holly *hl = dc->holly;
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*hl->SB_ISTERR &= ~value;
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holly_update_sh4_interrupts(hl);
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holly_update_interrupts(hl);
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}
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REG_W32(holly_cb, SB_IML2NRM) {
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struct holly *hl = dc->holly;
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*hl->SB_IML2NRM = value;
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holly_update_sh4_interrupts(hl);
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holly_update_interrupts(hl);
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}
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REG_W32(holly_cb, SB_IML2EXT) {
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struct holly *hl = dc->holly;
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*hl->SB_IML2EXT = value;
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holly_update_sh4_interrupts(hl);
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holly_update_interrupts(hl);
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}
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REG_W32(holly_cb, SB_IML2ERR) {
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struct holly *hl = dc->holly;
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*hl->SB_IML2ERR = value;
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holly_update_sh4_interrupts(hl);
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holly_update_interrupts(hl);
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}
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REG_W32(holly_cb, SB_IML4NRM) {
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struct holly *hl = dc->holly;
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*hl->SB_IML4NRM = value;
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holly_update_sh4_interrupts(hl);
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holly_update_interrupts(hl);
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}
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REG_W32(holly_cb, SB_IML4EXT) {
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struct holly *hl = dc->holly;
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*hl->SB_IML4EXT = value;
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holly_update_sh4_interrupts(hl);
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holly_update_interrupts(hl);
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}
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REG_W32(holly_cb, SB_IML4ERR) {
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struct holly *hl = dc->holly;
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*hl->SB_IML4ERR = value;
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holly_update_sh4_interrupts(hl);
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holly_update_interrupts(hl);
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}
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REG_W32(holly_cb, SB_IML6NRM) {
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struct holly *hl = dc->holly;
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*hl->SB_IML6NRM = value;
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holly_update_sh4_interrupts(hl);
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holly_update_interrupts(hl);
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}
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REG_W32(holly_cb, SB_IML6EXT) {
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struct holly *hl = dc->holly;
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*hl->SB_IML6EXT = value;
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holly_update_sh4_interrupts(hl);
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holly_update_interrupts(hl);
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}
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REG_W32(holly_cb, SB_IML6ERR) {
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struct holly *hl = dc->holly;
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*hl->SB_IML6ERR = value;
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holly_update_sh4_interrupts(hl);
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holly_update_interrupts(hl);
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}
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REG_W32(holly_cb, SB_C2DST) {
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struct holly *hl = dc->holly;
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*hl->SB_C2DST = value;
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if (!*hl->SB_C2DST) {
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return;
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if ((*hl->SB_C2DST = value)) {
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holly_ch2_dma(hl);
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}
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// FIXME what are SB_LMMODE0 / SB_LMMODE1
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struct sh4_dtr dtr = {0};
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dtr.channel = 2;
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dtr.rw = false;
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dtr.addr = *hl->SB_C2DSTAT;
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sh4_ddt(hl->sh4, &dtr);
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*hl->SB_C2DLEN = 0;
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*hl->SB_C2DST = 0;
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holly_raise_interrupt(hl, HOLLY_INTC_DTDE2INT);
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}
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REG_W32(holly_cb, SB_SDST) {
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struct holly *hl = dc->holly;
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*hl->SB_SDST = value;
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if (!*hl->SB_SDST) {
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return;
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if ((*hl->SB_SDST = value)) {
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LOG_FATAL("Sort DMA not supported");
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}
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}
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REG_W32(holly_cb, SB_MDST) {
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struct holly *hl = dc->holly;
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if ((*hl->SB_MDST = value)) {
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holly_maple_dma(hl);
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}
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LOG_FATAL("Sort DMA not supported");
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}
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REG_W32(holly_cb, SB_GDST) {
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struct gdrom *gd = dc->gdrom;
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struct holly *hl = dc->holly;
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// if a "0" is written to this register, it is ignored
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*hl->SB_GDST |= value;
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if (!*hl->SB_GDST) {
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return;
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if ((*hl->SB_GDST = value)) {
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holly_gdrom_dma(hl);
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}
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CHECK_EQ(*hl->SB_GDEN, 1); // dma enabled
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CHECK_EQ(*hl->SB_GDDIR, 1); // gd-rom -> system memory
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int transfer_size = *hl->SB_GDLEN;
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uint32_t start = *hl->SB_GDSTAR;
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int remaining = transfer_size;
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uint32_t addr = start;
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gdrom_dma_begin(gd);
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while (remaining) {
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// read a single sector at a time from the gdrom
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uint8_t sector_data[SECTOR_SIZE];
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int n = gdrom_dma_read(gd, sector_data, sizeof(sector_data));
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struct sh4_dtr dtr = {0};
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dtr.channel = 0;
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dtr.rw = true;
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dtr.data = sector_data;
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dtr.addr = addr;
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dtr.size = n;
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sh4_ddt(dc->sh4, &dtr);
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remaining -= n;
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addr += n;
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}
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gdrom_dma_end(gd);
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*hl->SB_GDSTARD = start + transfer_size;
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*hl->SB_GDLEND = transfer_size;
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*hl->SB_GDST = 0;
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holly_raise_interrupt(hl, HOLLY_INTC_G1DEINT);
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}
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REG_W32(holly_cb, SB_ADEN) {
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struct holly *hl = dc->holly;
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*hl->SB_ADEN = value;
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if (!*hl->SB_ADEN) {
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return;
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}
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LOG_WARNING("Ignored aica DMA request");
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}
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REG_W32(holly_cb, SB_ADST) {
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struct holly *hl = dc->holly;
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*hl->SB_ADST = value;
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if (!*hl->SB_ADST) {
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return;
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if ((*hl->SB_ADST = value)) {
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holly_g2_dma(hl, 0);
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}
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LOG_WARNING("Ignored aica DMA request");
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}
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REG_W32(holly_cb, SB_E1EN) {
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struct holly *hl = dc->holly;
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*hl->SB_E1EN = value;
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if (!*hl->SB_E1EN) {
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return;
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}
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LOG_WARNING("Ignored ext1 DMA request");
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}
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REG_W32(holly_cb, SB_E1ST) {
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struct holly *hl = dc->holly;
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*hl->SB_E1ST = value;
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if (!*hl->SB_E1ST) {
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return;
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if ((*hl->SB_E1ST = value)) {
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holly_g2_dma(hl, 1);
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}
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LOG_WARNING("Ignored ext1 DMA request");
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}
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REG_W32(holly_cb, SB_E2EN) {
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struct holly *hl = dc->holly;
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*hl->SB_E2EN = value;
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if (!*hl->SB_E2EN) {
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return;
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}
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LOG_WARNING("Ignored ext2 DMA request");
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}
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REG_W32(holly_cb, SB_E2ST) {
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struct holly *hl = dc->holly;
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*hl->SB_E2ST = value;
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if (!*hl->SB_E2ST) {
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return;
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if ((*hl->SB_E2ST = value)) {
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holly_g2_dma(hl, 2);
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}
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LOG_WARNING("Ignored ext2 DMA request");
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}
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REG_W32(holly_cb, SB_DDEN) {
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struct holly *hl = dc->holly;
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*hl->SB_DDEN = value;
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if (!*hl->SB_DDEN) {
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return;
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}
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LOG_WARNING("Ignored dev DMA request");
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}
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REG_W32(holly_cb, SB_DDST) {
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struct holly *hl = dc->holly;
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*hl->SB_DDST = value;
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if (!*hl->SB_DDST) {
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return;
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if ((*hl->SB_DDST = value)) {
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holly_g2_dma(hl, 3);
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}
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LOG_WARNING("Ignored dev DMA request");
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}
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REG_W32(holly_cb, SB_PDEN) {
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struct holly *hl = dc->holly;
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*hl->SB_PDEN = value;
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if (!*hl->SB_PDEN) {
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return;
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}
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||||
LOG_WARNING("Ignored pvr DMA request");
|
||||
}
|
||||
|
||||
REG_W32(holly_cb, SB_PDST) {
|
||||
struct holly *hl = dc->holly;
|
||||
*hl->SB_PDST = value;
|
||||
if (!*hl->SB_PDST) {
|
||||
return;
|
||||
if ((*hl->SB_PDST = value)) {
|
||||
LOG_WARNING("Ignored pvr DMA request");
|
||||
}
|
||||
LOG_WARNING("Ignored pvr DMA request");
|
||||
}
|
||||
|
||||
// clang-format off
|
||||
|
|
|
|||
|
|
@ -8,45 +8,6 @@ struct maple {
|
|||
struct maple_device *devices[4];
|
||||
};
|
||||
|
||||
static void maple_dma(struct maple *mp) {
|
||||
struct address_space *space = mp->sh4->memory_if->space;
|
||||
uint32_t start_addr = mp->holly->reg[SB_MDSTAR];
|
||||
union maple_transfer desc;
|
||||
struct maple_frame frame, res;
|
||||
|
||||
do {
|
||||
desc.full = as_read64(space, start_addr);
|
||||
start_addr += 8;
|
||||
|
||||
// read input
|
||||
frame.header.full = as_read32(space, start_addr);
|
||||
start_addr += 4;
|
||||
|
||||
for (uint32_t i = 0; i < frame.header.num_words; i++) {
|
||||
frame.params[i] = as_read32(space, start_addr);
|
||||
start_addr += 4;
|
||||
}
|
||||
|
||||
// handle frame and write response
|
||||
struct maple_device *dev = mp->devices[desc.port];
|
||||
|
||||
if (dev && dev->frame(dev, &frame, &res)) {
|
||||
as_write32(space, desc.result_addr, res.header.full);
|
||||
desc.result_addr += 4;
|
||||
|
||||
for (uint32_t i = 0; i < res.header.num_words; i++) {
|
||||
as_write32(space, desc.result_addr, res.params[i]);
|
||||
desc.result_addr += 4;
|
||||
}
|
||||
} else {
|
||||
as_write32(space, desc.result_addr, 0xffffffff);
|
||||
}
|
||||
} while (!desc.last);
|
||||
|
||||
mp->holly->reg[SB_MDST] = 0;
|
||||
holly_raise_interrupt(mp->holly, HOLLY_INTC_MDEINT);
|
||||
}
|
||||
|
||||
static bool maple_init(struct device *dev) {
|
||||
// struct maple *mp = (struct maple *)dev;
|
||||
return true;
|
||||
|
|
@ -61,19 +22,15 @@ static void maple_keydown(struct device *dev, enum keycode key, int16_t value) {
|
|||
}
|
||||
}
|
||||
|
||||
void maple_vblank(struct maple *mp) {
|
||||
uint32_t enabled = mp->holly->reg[SB_MDEN];
|
||||
uint32_t vblank_initiate = mp->holly->reg[SB_MDTSEL];
|
||||
int maple_handle_command(struct maple *mp, int port, struct maple_frame *frame,
|
||||
struct maple_frame *res) {
|
||||
struct maple_device *dev = mp->devices[port];
|
||||
|
||||
// The controller can be started up by two methods: by software, or by
|
||||
// hardware
|
||||
// in synchronization with the V-BLANK signal. These methods are selected
|
||||
// through the trigger selection register (SB_MDTSEL).
|
||||
if (enabled && vblank_initiate) {
|
||||
maple_dma(mp);
|
||||
if (!dev) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
// TODO maple vblank interrupt?
|
||||
return dev->frame(dev, frame, res);
|
||||
}
|
||||
|
||||
struct maple *maple_create(struct dreamcast *dc) {
|
||||
|
|
@ -98,18 +55,3 @@ void maple_destroy(struct maple *mp) {
|
|||
dc_destroy_window_interface(mp->window_if);
|
||||
dc_destroy_device((struct device *)mp);
|
||||
}
|
||||
|
||||
REG_W32(holly_cb, SB_MDST) {
|
||||
struct maple *mp = dc->maple;
|
||||
struct holly *hl = dc->holly;
|
||||
|
||||
*hl->SB_MDST = value;
|
||||
|
||||
if (*hl->SB_MDEN) {
|
||||
if (*hl->SB_MDST) {
|
||||
maple_dma(mp);
|
||||
}
|
||||
} else {
|
||||
*hl->SB_MDST = 0;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -18,7 +18,9 @@ struct maple_device {
|
|||
|
||||
struct maple_device *controller_create();
|
||||
|
||||
void maple_vblank(struct maple *mp);
|
||||
int maple_handle_command(struct maple *mp, int port, struct maple_frame *frame,
|
||||
struct maple_frame *res);
|
||||
|
||||
struct maple *maple_create(struct dreamcast *dc);
|
||||
void maple_destroy(struct maple *mp);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue