542 lines
17 KiB
C++
542 lines
17 KiB
C++
/****************************************************************************
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* *
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* Project64 - A Nintendo 64 emulator. *
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* http://www.pj64-emu.com/ *
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* Copyright (C) 2012 Project64. All rights reserved. *
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* *
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* License: *
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* GNU/GPLv2 http://www.gnu.org/licenses/gpl-2.0.html *
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* *
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****************************************************************************/
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#include "stdafx.h"
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const char * CRegName::GPR[32] = {"r0","at","v0","v1","a0","a1","a2","a3",
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"t0","t1","t2","t3","t4","t5","t6","t7",
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"s0","s1","s2","s3","s4","s5","s6","s7",
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"t8","t9","k0","k1","gp","sp","s8","ra"};
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const char *CRegName::GPR_Hi[32] = {"r0.HI","at.HI","v0.HI","v1.HI","a0.HI","a1.HI",
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"a2.HI","a3.HI","t0.HI","t1.HI","t2.HI","t3.HI",
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"t4.HI","t5.HI","t6.HI","t7.HI","s0.HI","s1.HI",
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"s2.HI","s3.HI","s4.HI","s5.HI","s6.HI","s7.HI",
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"t8.HI","t9.HI","k0.HI","k1.HI","gp.HI","sp.HI",
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"s8.HI","ra.HI"};
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const char *CRegName::GPR_Lo[32] = {"r0.LO","at.LO","v0.LO","v1.LO","a0.LO","a1.LO",
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"a2.LO","a3.LO","t0.LO","t1.LO","t2.LO","t3.LO",
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"t4.LO","t5.LO","t6.LO","t7.LO","s0.LO","s1.LO",
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"s2.LO","s3.LO","s4.LO","s5.LO","s6.LO","s7.LO",
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"t8.LO","t9.LO","k0.LO","k1.LO","gp.LO","sp.LO",
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"s8.LO","ra.LO"};
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const char * CRegName::Cop0[32] = {"Index","Random","EntryLo0","EntryLo1","Context","PageMask","Wired","",
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"BadVAddr","Count","EntryHi","Compare","Status","Cause","EPC","PRId",
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"Config","LLAddr","WatchLo","WatchHi","XContext","","","",
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"","","ECC","CacheErr","TagLo","TagHi","ErrEPC",""};
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const char * CRegName::FPR[32] = {"f0","f1","f2","f3","f4","f5","f6","f7",
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"f8","f9","f10","f11","f12","f13","f14","f15",
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"f16","f17","f18","f19","f20","f21","f22","f23",
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"f24","f25","f26","f27","f28","f29","f30","f31"};
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const char * CRegName::FPR_Ctrl[32] = {"Revision","Unknown","Unknown","Unknown","Unknown",
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"Unknown","Unknown","Unknown","Unknown","Unknown","Unknown",
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"Unknown","Unknown","Unknown","Unknown","Unknown","Unknown",
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"Unknown","Unknown","Unknown","Unknown","Unknown","Unknown",
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"Unknown","Unknown","Unknown","Unknown","Unknown","Unknown",
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"Unknown","Unknown","FCSR"};
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uint32_t * CSystemRegisters::_PROGRAM_COUNTER = NULL;
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MIPS_DWORD * CSystemRegisters::_GPR = NULL;
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MIPS_DWORD * CSystemRegisters::_FPR = NULL;
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uint32_t * CSystemRegisters::_CP0 = NULL;
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MIPS_DWORD * CSystemRegisters::_RegHI = NULL;
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MIPS_DWORD * CSystemRegisters::_RegLO = NULL;
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float ** CSystemRegisters::_FPR_S;
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double ** CSystemRegisters::_FPR_D;
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uint32_t * CSystemRegisters::_FPCR = NULL;
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uint32_t * CSystemRegisters::_LLBit = NULL;
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ROUNDING_MODE * CSystemRegisters::_RoundingModel = NULL;
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CP0registers::CP0registers(uint32_t * _CP0) :
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INDEX_REGISTER(_CP0[0]),
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RANDOM_REGISTER(_CP0[1]),
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ENTRYLO0_REGISTER(_CP0[2]),
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ENTRYLO1_REGISTER(_CP0[3]),
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CONTEXT_REGISTER(_CP0[4]),
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PAGE_MASK_REGISTER(_CP0[5]),
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WIRED_REGISTER(_CP0[6]),
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BAD_VADDR_REGISTER(_CP0[8]),
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COUNT_REGISTER(_CP0[9]),
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ENTRYHI_REGISTER(_CP0[10]),
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COMPARE_REGISTER(_CP0[11]),
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STATUS_REGISTER(_CP0[12]),
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CAUSE_REGISTER(_CP0[13]),
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EPC_REGISTER(_CP0[14]),
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CONFIG_REGISTER(_CP0[16]),
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TAGLO_REGISTER(_CP0[28]),
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TAGHI_REGISTER(_CP0[29]),
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ERROREPC_REGISTER(_CP0[30]),
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FAKE_CAUSE_REGISTER(_CP0[32])
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{
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}
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Rdram_InterfaceReg::Rdram_InterfaceReg(uint32_t * _RdramInterface) :
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RDRAM_CONFIG_REG(_RdramInterface[0]),
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RDRAM_DEVICE_TYPE_REG(_RdramInterface[0]),
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RDRAM_DEVICE_ID_REG(_RdramInterface[1]),
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RDRAM_DELAY_REG(_RdramInterface[2]),
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RDRAM_MODE_REG(_RdramInterface[3]),
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RDRAM_REF_INTERVAL_REG(_RdramInterface[4]),
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RDRAM_REF_ROW_REG(_RdramInterface[5]),
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RDRAM_RAS_INTERVAL_REG(_RdramInterface[6]),
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RDRAM_MIN_INTERVAL_REG(_RdramInterface[7]),
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RDRAM_ADDR_SELECT_REG(_RdramInterface[8]),
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RDRAM_DEVICE_MANUF_REG(_RdramInterface[9])
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{
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}
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Mips_InterfaceReg::Mips_InterfaceReg(uint32_t * _MipsInterface) :
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MI_INIT_MODE_REG(_MipsInterface[0]),
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MI_MODE_REG(_MipsInterface[0]),
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MI_VERSION_REG(_MipsInterface[1]),
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MI_NOOP_REG(_MipsInterface[1]),
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MI_INTR_REG(_MipsInterface[2]),
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MI_INTR_MASK_REG(_MipsInterface[3])
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{
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}
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Video_InterfaceReg::Video_InterfaceReg(uint32_t * _VideoInterface) :
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VI_STATUS_REG(_VideoInterface[0]),
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VI_CONTROL_REG(_VideoInterface[0]),
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VI_ORIGIN_REG(_VideoInterface[1]),
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VI_DRAM_ADDR_REG(_VideoInterface[1]),
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VI_WIDTH_REG(_VideoInterface[2]),
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VI_H_WIDTH_REG(_VideoInterface[2]),
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VI_INTR_REG(_VideoInterface[3]),
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VI_V_INTR_REG(_VideoInterface[3]),
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VI_CURRENT_REG(_VideoInterface[4]),
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VI_V_CURRENT_LINE_REG(_VideoInterface[4]),
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VI_BURST_REG(_VideoInterface[5]),
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VI_TIMING_REG(_VideoInterface[5]),
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VI_V_SYNC_REG(_VideoInterface[6]),
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VI_H_SYNC_REG(_VideoInterface[7]),
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VI_LEAP_REG(_VideoInterface[8]),
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VI_H_SYNC_LEAP_REG(_VideoInterface[8]),
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VI_H_START_REG(_VideoInterface[9]),
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VI_H_VIDEO_REG(_VideoInterface[9]),
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VI_V_START_REG(_VideoInterface[10]),
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VI_V_VIDEO_REG(_VideoInterface[10]),
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VI_V_BURST_REG(_VideoInterface[11]),
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VI_X_SCALE_REG(_VideoInterface[12]),
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VI_Y_SCALE_REG(_VideoInterface[13])
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{
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}
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AudioInterfaceReg::AudioInterfaceReg(uint32_t * _AudioInterface) :
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AI_DRAM_ADDR_REG(_AudioInterface[0]),
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AI_LEN_REG(_AudioInterface[1]),
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AI_CONTROL_REG(_AudioInterface[2]),
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AI_STATUS_REG(_AudioInterface[3]),
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AI_DACRATE_REG(_AudioInterface[4]),
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AI_BITRATE_REG(_AudioInterface[5])
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{
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}
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PeripheralInterfaceReg::PeripheralInterfaceReg(uint32_t * PeripheralInterface) :
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PI_DRAM_ADDR_REG(PeripheralInterface[0]),
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PI_CART_ADDR_REG(PeripheralInterface[1]),
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PI_RD_LEN_REG(PeripheralInterface[2]),
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PI_WR_LEN_REG(PeripheralInterface[3]),
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PI_STATUS_REG(PeripheralInterface[4]),
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PI_BSD_DOM1_LAT_REG(PeripheralInterface[5]),
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PI_DOMAIN1_REG(PeripheralInterface[5]),
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PI_BSD_DOM1_PWD_REG(PeripheralInterface[6]),
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PI_BSD_DOM1_PGS_REG(PeripheralInterface[7]),
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PI_BSD_DOM1_RLS_REG(PeripheralInterface[8]),
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PI_BSD_DOM2_LAT_REG(PeripheralInterface[9]),
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PI_DOMAIN2_REG(PeripheralInterface[9]),
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PI_BSD_DOM2_PWD_REG(PeripheralInterface[10]),
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PI_BSD_DOM2_PGS_REG(PeripheralInterface[11]),
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PI_BSD_DOM2_RLS_REG(PeripheralInterface[12])
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{
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}
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RDRAMInt_InterfaceReg::RDRAMInt_InterfaceReg(uint32_t * RdramInterface) :
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RI_MODE_REG(RdramInterface[0]),
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RI_CONFIG_REG(RdramInterface[1]),
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RI_CURRENT_LOAD_REG(RdramInterface[2]),
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RI_SELECT_REG(RdramInterface[3]),
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RI_COUNT_REG(RdramInterface[4]),
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RI_REFRESH_REG(RdramInterface[4]),
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RI_LATENCY_REG(RdramInterface[5]),
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RI_RERROR_REG(RdramInterface[6]),
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RI_WERROR_REG(RdramInterface[7])
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{
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}
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DisplayControlReg::DisplayControlReg(uint32_t * _DisplayProcessor) :
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DPC_START_REG(_DisplayProcessor[0]),
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DPC_END_REG(_DisplayProcessor[1]),
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DPC_CURRENT_REG(_DisplayProcessor[2]),
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DPC_STATUS_REG(_DisplayProcessor[3]),
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DPC_CLOCK_REG(_DisplayProcessor[4]),
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DPC_BUFBUSY_REG(_DisplayProcessor[5]),
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DPC_PIPEBUSY_REG(_DisplayProcessor[6]),
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DPC_TMEM_REG(_DisplayProcessor[7])
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{
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}
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SigProcessor_InterfaceReg::SigProcessor_InterfaceReg(uint32_t * _SignalProcessorInterface) :
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SP_MEM_ADDR_REG(_SignalProcessorInterface[0]),
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SP_DRAM_ADDR_REG(_SignalProcessorInterface[1]),
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SP_RD_LEN_REG(_SignalProcessorInterface[2]),
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SP_WR_LEN_REG(_SignalProcessorInterface[3]),
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SP_STATUS_REG(_SignalProcessorInterface[4]),
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SP_DMA_FULL_REG(_SignalProcessorInterface[5]),
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SP_DMA_BUSY_REG(_SignalProcessorInterface[6]),
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SP_SEMAPHORE_REG(_SignalProcessorInterface[7]),
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SP_PC_REG(_SignalProcessorInterface[8]),
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SP_IBIST_REG(_SignalProcessorInterface[9])
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{
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}
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Serial_InterfaceReg::Serial_InterfaceReg(uint32_t * SerialInterface) :
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SI_DRAM_ADDR_REG(SerialInterface[0]),
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SI_PIF_ADDR_RD64B_REG(SerialInterface[1]),
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SI_PIF_ADDR_WR64B_REG(SerialInterface[2]),
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SI_STATUS_REG(SerialInterface[3])
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{
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}
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CRegisters::CRegisters(CN64System * System, CSystemEvents * SystemEvents) :
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CP0registers(m_CP0),
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Rdram_InterfaceReg(m_RDRAM_Registers),
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Mips_InterfaceReg(m_Mips_Interface),
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Video_InterfaceReg(m_Video_Interface),
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AudioInterfaceReg(m_Audio_Interface),
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PeripheralInterfaceReg(m_Peripheral_Interface),
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RDRAMInt_InterfaceReg(m_RDRAM_Interface),
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SigProcessor_InterfaceReg(m_SigProcessor_Interface),
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DisplayControlReg(m_Display_ControlReg),
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Serial_InterfaceReg(m_SerialInterface),
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m_System(System),
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m_SystemEvents(SystemEvents)
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{
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Reset();
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}
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void CRegisters::Reset()
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{
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m_FirstInterupt = true;
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memset(m_GPR,0,sizeof(m_GPR));
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memset(m_CP0,0,sizeof(m_CP0));
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memset(m_FPR,0,sizeof(m_FPR));
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memset(m_FPCR,0,sizeof(m_FPCR));
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m_HI.DW = 0;
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m_LO.DW = 0;
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m_RoundingModel = ROUND_NEAR;
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m_LLBit = 0;
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//Reset System Registers
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memset(m_RDRAM_Interface,0,sizeof(m_RDRAM_Interface));
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memset(m_RDRAM_Registers,0,sizeof(m_RDRAM_Registers));
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memset(m_Mips_Interface,0,sizeof(m_Mips_Interface));
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memset(m_Video_Interface,0,sizeof(m_Video_Interface));
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memset(m_Display_ControlReg,0,sizeof(m_Display_ControlReg));
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memset(m_Audio_Interface,0,sizeof(m_Audio_Interface));
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memset(m_SigProcessor_Interface,0,sizeof(m_SigProcessor_Interface));
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memset(m_Peripheral_Interface,0,sizeof(m_Peripheral_Interface));
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memset(m_SerialInterface,0,sizeof(m_SerialInterface));
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m_AudioIntrReg = 0;
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m_GfxIntrReg = 0;
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m_RspIntrReg = 0;
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FixFpuLocations();
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}
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void CRegisters::SetAsCurrentSystem()
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{
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_PROGRAM_COUNTER = &m_PROGRAM_COUNTER;
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_GPR = m_GPR;
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_FPR = m_FPR;
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_CP0 = m_CP0;
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_RegHI = &m_HI;
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_RegLO = &m_LO;
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_FPR_S = m_FPR_S;
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_FPR_D = m_FPR_D;
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_FPCR = m_FPCR;
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_LLBit = &m_LLBit;
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_RoundingModel = &m_RoundingModel;
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}
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void CRegisters::CheckInterrupts()
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{
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if (!m_System->bFixedAudio() && CpuType() != CPU_SyncCores)
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{
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MI_INTR_REG &= ~MI_INTR_AI;
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MI_INTR_REG |= (m_AudioIntrReg & MI_INTR_AI);
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}
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MI_INTR_REG |= (m_RspIntrReg & MI_INTR_SP);
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MI_INTR_REG |= (m_GfxIntrReg & MI_INTR_DP);
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if ((MI_INTR_MASK_REG & MI_INTR_REG) != 0)
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{
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FAKE_CAUSE_REGISTER |= CAUSE_IP2;
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}
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else
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{
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FAKE_CAUSE_REGISTER &= ~CAUSE_IP2;
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}
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if (( STATUS_REGISTER & STATUS_IE ) == 0 )
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{
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return;
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}
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if (( STATUS_REGISTER & STATUS_EXL ) != 0 )
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{
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return;
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}
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if (( STATUS_REGISTER & STATUS_ERL ) != 0 )
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{
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return;
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}
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if (( STATUS_REGISTER & FAKE_CAUSE_REGISTER & 0xFF00) != 0)
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{
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if (m_FirstInterupt)
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{
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m_FirstInterupt = false;
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if (g_Recompiler)
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{
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g_Recompiler->ClearRecompCode_Virt(0x80000000,0x200,CRecompiler::Remove_InitialCode);
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}
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}
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m_SystemEvents->QueueEvent(SysEvent_ExecuteInterrupt);
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}
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}
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void CRegisters::DoAddressError(bool DelaySlot, uint32_t BadVaddr, bool FromRead)
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{
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if (bHaveDebugger())
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{
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g_Notify->DisplayError(L"AddressError");
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if (( STATUS_REGISTER & STATUS_EXL ) != 0 )
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{
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g_Notify->DisplayError(L"EXL set in AddressError Exception");
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}
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if (( STATUS_REGISTER & STATUS_ERL ) != 0 )
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{
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g_Notify->DisplayError(L"ERL set in AddressError Exception");
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}
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}
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if (FromRead)
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{
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CAUSE_REGISTER = EXC_RADE;
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}
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else
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{
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CAUSE_REGISTER = EXC_WADE;
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}
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BAD_VADDR_REGISTER = BadVaddr;
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if (DelaySlot)
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{
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CAUSE_REGISTER |= CAUSE_BD;
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EPC_REGISTER = m_PROGRAM_COUNTER - 4;
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}
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else
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{
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EPC_REGISTER = m_PROGRAM_COUNTER;
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}
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STATUS_REGISTER |= STATUS_EXL;
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m_PROGRAM_COUNTER = 0x80000180;
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}
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void CRegisters::FixFpuLocations()
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{
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if ((STATUS_REGISTER & STATUS_FR) == 0)
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{
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for (int count = 0; count < 32; count ++)
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{
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m_FPR_S[count] = &m_FPR[count >> 1].F[count & 1];
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m_FPR_D[count] = &m_FPR[count >> 1].D;
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}
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}
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else
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{
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for (int count = 0; count < 32; count ++) {
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m_FPR_S[count] = &m_FPR[count].F[1];
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m_FPR_D[count] = &m_FPR[count].D;
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}
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}
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}
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void CRegisters::DoBreakException(bool DelaySlot)
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{
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if (bHaveDebugger())
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{
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if (( STATUS_REGISTER & STATUS_EXL ) != 0 )
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{
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g_Notify->DisplayError(L"EXL set in Break Exception");
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}
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if (( STATUS_REGISTER & STATUS_ERL ) != 0 )
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{
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g_Notify->DisplayError(L"ERL set in Break Exception");
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}
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}
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CAUSE_REGISTER = EXC_BREAK;
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if (DelaySlot)
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{
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CAUSE_REGISTER |= CAUSE_BD;
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EPC_REGISTER = m_PROGRAM_COUNTER - 4;
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}
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else
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{
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EPC_REGISTER = m_PROGRAM_COUNTER;
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}
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STATUS_REGISTER |= STATUS_EXL;
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m_PROGRAM_COUNTER = 0x80000180;
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}
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void CRegisters::DoCopUnusableException(bool DelaySlot, int Coprocessor)
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{
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if (bHaveDebugger())
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{
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if (( STATUS_REGISTER & STATUS_EXL ) != 0 )
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{
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g_Notify->DisplayError(L"EXL set in Break Exception");
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}
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if (( STATUS_REGISTER & STATUS_ERL ) != 0 )
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{
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g_Notify->DisplayError(L"ERL set in Break Exception");
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}
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}
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CAUSE_REGISTER = EXC_CPU;
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if (Coprocessor == 1)
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{
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CAUSE_REGISTER |= 0x10000000;
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}
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if (DelaySlot)
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{
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CAUSE_REGISTER |= CAUSE_BD;
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EPC_REGISTER = m_PROGRAM_COUNTER - 4;
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}
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else
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{
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EPC_REGISTER = m_PROGRAM_COUNTER;
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}
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STATUS_REGISTER |= STATUS_EXL;
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m_PROGRAM_COUNTER = 0x80000180;
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}
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bool CRegisters::DoIntrException(bool DelaySlot)
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{
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if ((STATUS_REGISTER & STATUS_IE) == 0)
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{
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return false;
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}
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if ((STATUS_REGISTER & STATUS_EXL) != 0)
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{
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return false;
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}
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if ((STATUS_REGISTER & STATUS_ERL) != 0)
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{
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return false;
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}
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|
if (g_LogOptions.GenerateLog && g_LogOptions.LogExceptions && !g_LogOptions.NoInterrupts)
|
|
{
|
|
LogMessage("%08X: Interrupt Generated", m_PROGRAM_COUNTER);
|
|
}
|
|
|
|
CAUSE_REGISTER = FAKE_CAUSE_REGISTER;
|
|
CAUSE_REGISTER |= EXC_INT;
|
|
|
|
if (DelaySlot)
|
|
{
|
|
CAUSE_REGISTER |= CAUSE_BD;
|
|
EPC_REGISTER = m_PROGRAM_COUNTER - 4;
|
|
}
|
|
else
|
|
{
|
|
EPC_REGISTER = m_PROGRAM_COUNTER;
|
|
}
|
|
|
|
STATUS_REGISTER |= STATUS_EXL;
|
|
m_PROGRAM_COUNTER = 0x80000180;
|
|
return true;
|
|
}
|
|
|
|
void CRegisters::DoTLBReadMiss(bool DelaySlot, uint32_t BadVaddr)
|
|
{
|
|
CAUSE_REGISTER = EXC_RMISS;
|
|
BAD_VADDR_REGISTER = BadVaddr;
|
|
CONTEXT_REGISTER &= 0xFF80000F;
|
|
CONTEXT_REGISTER |= (BadVaddr >> 9) & 0x007FFFF0;
|
|
ENTRYHI_REGISTER = (BadVaddr & 0xFFFFE000);
|
|
if ((STATUS_REGISTER & STATUS_EXL) == 0)
|
|
{
|
|
if (DelaySlot)
|
|
{
|
|
CAUSE_REGISTER |= CAUSE_BD;
|
|
EPC_REGISTER = m_PROGRAM_COUNTER - 4;
|
|
}
|
|
else
|
|
{
|
|
EPC_REGISTER = m_PROGRAM_COUNTER;
|
|
}
|
|
if (g_TLB->AddressDefined(BadVaddr))
|
|
{
|
|
m_PROGRAM_COUNTER = 0x80000180;
|
|
}
|
|
else
|
|
{
|
|
m_PROGRAM_COUNTER = 0x80000000;
|
|
}
|
|
STATUS_REGISTER |= STATUS_EXL;
|
|
}
|
|
else
|
|
{
|
|
if (bHaveDebugger())
|
|
{
|
|
g_Notify->DisplayError(stdstr_f("TLBMiss - EXL Set\nBadVaddr = %X\nAddress Defined: %s",BadVaddr,g_TLB->AddressDefined(BadVaddr)?"TRUE":"FALSE").ToUTF16().c_str());
|
|
}
|
|
m_PROGRAM_COUNTER = 0x80000180;
|
|
}
|
|
}
|
|
|
|
void CRegisters::DoSysCallException(bool DelaySlot)
|
|
{
|
|
if (bHaveDebugger())
|
|
{
|
|
if (( STATUS_REGISTER & STATUS_EXL ) != 0 )
|
|
{
|
|
g_Notify->DisplayError(L"EXL set in SysCall Exception");
|
|
}
|
|
if (( STATUS_REGISTER & STATUS_ERL ) != 0 )
|
|
{
|
|
g_Notify->DisplayError(L"ERL set in SysCall Exception");
|
|
}
|
|
}
|
|
|
|
CAUSE_REGISTER = EXC_SYSCALL;
|
|
if (DelaySlot)
|
|
{
|
|
CAUSE_REGISTER |= CAUSE_BD;
|
|
EPC_REGISTER = m_PROGRAM_COUNTER - 4;
|
|
}
|
|
else
|
|
{
|
|
EPC_REGISTER = m_PROGRAM_COUNTER;
|
|
}
|
|
STATUS_REGISTER |= STATUS_EXL;
|
|
m_PROGRAM_COUNTER = 0x80000180;
|
|
}
|