1314 lines
46 KiB
C++
1314 lines
46 KiB
C++
#include "stdafx.h"
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#include <string.h>
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#include "LoopAnalysis.h"
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#include <Project64-core/N64System/N64Types.h>
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#include <Project64-core/N64System/Recompiler/CodeBlock.h>
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#include <Project64-core/N64System/Recompiler/RecompilerCodeLog.h>
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#include <Project64-core/N64System/SystemGlobals.h>
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#include <Project64-core/N64System/Mips/MemoryVirtualMem.h>
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#include <Project64-core/N64System/Mips/OpcodeName.h>
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#ifdef _DEBUG
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#define CHECKED_BUILD 1
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#endif
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bool DelaySlotEffectsCompare(uint32_t PC, uint32_t Reg1, uint32_t Reg2);
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LoopAnalysis::LoopAnalysis(CCodeBlock * CodeBlock, CCodeSection * Section) :
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m_EnterSection(Section),
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m_BlockInfo(CodeBlock),
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m_PC((uint32_t)-1),
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m_NextInstruction(NORMAL),
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m_Test(m_BlockInfo->NextTest())
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{
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memset(&m_Command, 0, sizeof(m_Command));
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}
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LoopAnalysis::~LoopAnalysis()
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{
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for (RegisterMap::iterator itr = m_EnterRegisters.begin(); itr != m_EnterRegisters.end(); itr++)
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{
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delete itr->second;
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}
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m_EnterRegisters.clear();
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for (RegisterMap::iterator itr = m_ContinueRegisters.begin(); itr != m_ContinueRegisters.end(); itr++)
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{
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delete itr->second;
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}
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m_ContinueRegisters.clear();
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for (RegisterMap::iterator itr = m_JumpRegisters.begin(); itr != m_JumpRegisters.end(); itr++)
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{
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delete itr->second;
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}
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m_JumpRegisters.clear();
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}
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bool LoopAnalysis::SetupRegisterForLoop()
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{
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if (!m_EnterSection->m_InLoop)
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{
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return false;
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}
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CPU_Message("%s: Section ID: %d Test: %X", __FUNCTION__, m_EnterSection->m_SectionID, m_Test);
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if (!CheckLoopRegisterUsage(m_EnterSection))
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{
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return false;
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}
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RegisterMap::iterator itr = m_EnterRegisters.find(m_EnterSection->m_SectionID);
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if (itr == m_EnterRegisters.end())
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{
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return false;
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}
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m_EnterSection->m_RegEnter = *(itr->second);
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return true;
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}
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bool LoopAnalysis::SetupEnterSection(CCodeSection * Section, bool & bChanged, bool & bSkipedSection)
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{
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bChanged = false;
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bSkipedSection = false;
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if (Section->m_ParentSection.empty()) { g_Notify->BreakPoint(__FILE__, __LINE__); return true; }
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CPU_Message("%s: Block EnterPC: %X Section ID %d Test: %X Section Test: %X CompiledLocation: %X", __FUNCTION__, m_BlockInfo->VAddrEnter(), Section->m_SectionID, m_Test, Section->m_Test, Section->m_CompiledLocation);
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bool bFirstParent = true;
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CRegInfo RegEnter;
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for (CCodeSection::SECTION_LIST::iterator iter = Section->m_ParentSection.begin(); iter != Section->m_ParentSection.end(); iter++)
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{
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CCodeSection * Parent = *iter;
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CPU_Message("%s: Parent Section ID %d Test: %X Section Test: %X CompiledLocation: %X", __FUNCTION__, Parent->m_SectionID, m_Test, Parent->m_Test, Parent->m_CompiledLocation);
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if (Parent->m_Test != m_Test && (m_EnterSection != Section || Parent->m_CompiledLocation == nullptr) && Parent->m_InLoop)
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{
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CPU_Message("%s: Ignore Parent Section ID %d Test: %X Section Test: %X CompiledLocation: %X", __FUNCTION__, Parent->m_SectionID, m_Test, Parent->m_Test, Parent->m_CompiledLocation);
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bSkipedSection = true;
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continue;
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}
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RegisterMap::iterator Continue_itr = m_ContinueRegisters.find(Parent->m_SectionID);
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RegisterMap::iterator Jump_itr = m_JumpRegisters.find(Parent->m_SectionID);
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CCodeSection * TargetSection[] = { Parent->m_ContinueSection, Parent->m_JumpSection };
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CRegInfo * JumpRegInfo[] =
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{
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Continue_itr == m_ContinueRegisters.end() ? &Parent->m_Cont.RegSet : Continue_itr->second,
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Jump_itr == m_JumpRegisters.end() ? &Parent->m_Jump.RegSet : Jump_itr->second
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};
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for (int i = 0; i < 2; i++)
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{
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if (TargetSection[i] != Section) { continue; }
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if (bFirstParent)
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{
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bFirstParent = false;
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RegEnter = *JumpRegInfo[i];
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}
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else
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{
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if (*JumpRegInfo[i] == RegEnter)
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{
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continue;
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}
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SyncRegState(RegEnter, *JumpRegInfo[i]);
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}
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}
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}
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if (bFirstParent)
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{
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g_Notify->BreakPoint(__FILE__, __LINE__);
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}
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RegisterMap::iterator itr = m_EnterRegisters.find(Section->m_SectionID);
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if (itr != m_EnterRegisters.end())
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{
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if (SyncRegState(*(itr->second), RegEnter))
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{
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bChanged = true;
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}
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}
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else
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{
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m_EnterRegisters.insert(RegisterMap::value_type(Section->m_SectionID, new CRegInfo(RegEnter)));
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}
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return true;
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}
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bool LoopAnalysis::CheckLoopRegisterUsage(CCodeSection * Section)
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{
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if (Section == nullptr) { return true; }
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if (!Section->m_InLoop) { return true; }
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CPU_Message("%s: Section %d Block PC: 0x%X", __FUNCTION__, Section->m_SectionID, m_BlockInfo->VAddrEnter());
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bool bChanged = false, bSkipedSection = false;
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if (Section == m_EnterSection && Section->m_Test == m_Test)
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{
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if (!SetupEnterSection(Section, bChanged, bSkipedSection)) { return false; }
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return true;
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}
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if (!SetupEnterSection(Section, bChanged, bSkipedSection)) { return false; }
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if (Section->m_Test == m_Test && !bChanged)
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{
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return true;
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}
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CPU_Message("%s: Set Section %d test to %X from %X", __FUNCTION__, Section->m_SectionID, m_Test, Section->m_Test);
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Section->m_Test = m_Test;
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m_PC = Section->m_EnterPC;
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RegisterMap::iterator itr = m_EnterRegisters.find(Section->m_SectionID);
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m_Reg = itr != m_EnterRegisters.end() ? *(itr->second) : Section->m_RegEnter;
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m_NextInstruction = NORMAL;
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uint32_t ContinueSectionPC = Section->m_ContinueSection ? Section->m_ContinueSection->m_EnterPC : (uint32_t)-1;
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CPU_Message("ContinueSectionPC = %08X", ContinueSectionPC);
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do
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{
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if (!g_MMU->LW_VAddr(m_PC, m_Command.Hex))
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{
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g_Notify->BreakPoint(__FILE__, __LINE__);
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return false;
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}
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CPU_Message(" %08X: %s", m_PC, R4300iOpcodeName(m_Command.Hex, m_PC));
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switch (m_Command.op)
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{
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case R4300i_SPECIAL:
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switch (m_Command.funct)
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{
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case R4300i_SPECIAL_SLL: SPECIAL_SLL(); break;
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case R4300i_SPECIAL_SRL: SPECIAL_SRL(); break;
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case R4300i_SPECIAL_SRA: SPECIAL_SRA(); break;
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case R4300i_SPECIAL_SLLV: SPECIAL_SLLV(); break;
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case R4300i_SPECIAL_SRLV: SPECIAL_SRLV(); break;
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case R4300i_SPECIAL_SRAV: SPECIAL_SRAV(); break;
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case R4300i_SPECIAL_JR: SPECIAL_JR(); break;
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case R4300i_SPECIAL_JALR: SPECIAL_JALR(); break;
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case R4300i_SPECIAL_SYSCALL: SPECIAL_SYSCALL(Section); break;
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case R4300i_SPECIAL_BREAK: SPECIAL_BREAK(Section); break;
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case R4300i_SPECIAL_MFHI: SPECIAL_MFHI(); break;
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case R4300i_SPECIAL_MTHI: SPECIAL_MTHI(); break;
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case R4300i_SPECIAL_MFLO: SPECIAL_MFLO(); break;
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case R4300i_SPECIAL_MTLO: SPECIAL_MTLO(); break;
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case R4300i_SPECIAL_DSLLV: SPECIAL_DSLLV(); break;
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case R4300i_SPECIAL_DSRLV: SPECIAL_DSRLV(); break;
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case R4300i_SPECIAL_DSRAV: SPECIAL_DSRAV(); break;
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case R4300i_SPECIAL_MULT: break;
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case R4300i_SPECIAL_MULTU: break;
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case R4300i_SPECIAL_DIV: break;
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case R4300i_SPECIAL_DIVU: break;
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case R4300i_SPECIAL_DMULT: break;
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case R4300i_SPECIAL_DMULTU: break;
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case R4300i_SPECIAL_DDIV: break;
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case R4300i_SPECIAL_DDIVU: break;
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case R4300i_SPECIAL_ADD: SPECIAL_ADD(); break;
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case R4300i_SPECIAL_ADDU: SPECIAL_ADDU(); break;
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case R4300i_SPECIAL_SUB: SPECIAL_SUB(); break;
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case R4300i_SPECIAL_SUBU: SPECIAL_SUBU(); break;
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case R4300i_SPECIAL_AND: SPECIAL_AND(); break;
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case R4300i_SPECIAL_OR: SPECIAL_OR(); break;
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case R4300i_SPECIAL_XOR: SPECIAL_XOR(); break;
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case R4300i_SPECIAL_NOR: SPECIAL_NOR(); break;
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case R4300i_SPECIAL_SLT: SPECIAL_SLT(); break;
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case R4300i_SPECIAL_SLTU: SPECIAL_SLTU(); break;
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case R4300i_SPECIAL_DADD: SPECIAL_DADD(); break;
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case R4300i_SPECIAL_DADDU: SPECIAL_DADDU(); break;
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case R4300i_SPECIAL_DSUB: SPECIAL_DSUB(); break;
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case R4300i_SPECIAL_DSUBU: SPECIAL_DSUBU(); break;
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case R4300i_SPECIAL_DSLL: SPECIAL_DSLL(); break;
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case R4300i_SPECIAL_DSRL: SPECIAL_DSRL(); break;
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case R4300i_SPECIAL_DSRA: SPECIAL_DSRA(); break;
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case R4300i_SPECIAL_DSLL32: SPECIAL_DSLL32(); break;
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case R4300i_SPECIAL_DSRL32: SPECIAL_DSRL32(); break;
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case R4300i_SPECIAL_DSRA32: SPECIAL_DSRA32(); break;
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case R4300i_SPECIAL_TEQ: case R4300i_SPECIAL_TNE: case R4300i_SPECIAL_TGE:
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case R4300i_SPECIAL_TGEU: case R4300i_SPECIAL_TLT: case R4300i_SPECIAL_TLTU:
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break;
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default:
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g_Notify->BreakPoint(__FILE__, __LINE__);
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#ifdef legacycode
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if (m_Command.Hex == 0x00000001) { break; }
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g_Notify->DisplayError("Unhandled R4300i OpCode in FillSectionInfo 5\n%s",
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R4300iOpcodeName(m_Command.Hex, m_PC));
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#endif
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m_NextInstruction = END_BLOCK;
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m_PC -= 4;
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}
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break;
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case R4300i_REGIMM:
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switch (m_Command.rt)
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{
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case R4300i_REGIMM_TEQI: case R4300i_REGIMM_TNEI: case R4300i_REGIMM_TGEI:
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case R4300i_REGIMM_TGEIU: case R4300i_REGIMM_TLTI: case R4300i_REGIMM_TLTIU:
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break;
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case R4300i_REGIMM_BLTZ:
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case R4300i_REGIMM_BGEZ:
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m_NextInstruction = DELAY_SLOT;
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#ifdef CHECKED_BUILD
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if (Section->m_Cont.TargetPC != m_PC + 8 &&
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Section->m_ContinueSection != nullptr &&
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Section->m_Cont.TargetPC != (uint32_t)-1)
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{
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g_Notify->BreakPoint(__FILE__, __LINE__);
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}
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if (Section->m_Jump.TargetPC != m_PC + ((int16_t)m_Command.offset << 2) + 4 &&
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Section->m_JumpSection != nullptr &&
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Section->m_Jump.TargetPC != (uint32_t)-1)
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{
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g_Notify->BreakPoint(__FILE__, __LINE__);
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}
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if (m_PC == Section->m_Jump.TargetPC)
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{
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if (!DelaySlotEffectsCompare(m_PC, m_Command.rs, 0) && !Section->m_Jump.PermLoop)
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{
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g_Notify->BreakPoint(__FILE__, __LINE__);
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}
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}
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#endif
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break;
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case R4300i_REGIMM_BLTZL:
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case R4300i_REGIMM_BGEZL:
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m_NextInstruction = LIKELY_DELAY_SLOT;
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#ifdef CHECKED_BUILD
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if (Section->m_Cont.TargetPC != m_PC + 8 &&
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Section->m_ContinueSection != nullptr &&
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Section->m_Cont.TargetPC != (uint32_t)-1)
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{
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g_Notify->BreakPoint(__FILE__, __LINE__);
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}
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if (Section->m_Jump.TargetPC != m_PC + 4 &&
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Section->m_JumpSection != nullptr &&
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Section->m_Jump.TargetPC != (uint32_t)-1)
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{
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g_Notify->BreakPoint(__FILE__, __LINE__);
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}
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/*if (Section->m_Jump.TargetPC != m_PC + ((int16_t)m_Command.offset << 2) + 4)
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{
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g_Notify->BreakPoint(__FILE__, __LINE__);
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}*/
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if (m_PC == m_PC + ((int16_t)m_Command.offset << 2) + 4)
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{
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if (!DelaySlotEffectsCompare(m_PC, m_Command.rs, 0) && !Section->m_Jump.PermLoop)
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{
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g_Notify->BreakPoint(__FILE__, __LINE__);
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}
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}
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#endif
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break;
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case R4300i_REGIMM_BLTZAL:
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g_Notify->BreakPoint(__FILE__, __LINE__);
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#ifdef legacycode
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m_Reg.GetMipsRegLo(31) = m_PC + 8;
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m_Reg.SetMipsRegState(31, CRegInfo::STATE_CONST_32_SIGN);
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Section->m_Cont.TargetPC = m_PC + 8;
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Section->m_Jump.TargetPC = m_PC + ((int16_t)m_Command.offset << 2) + 4;
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if (m_PC == Section->m_Jump.TargetPC)
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{
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if (!DelaySlotEffectsCompare(m_PC, m_Command.rs, 0))
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{
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Section->m_Jump.PermLoop = true;
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}
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}
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#endif
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break;
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case R4300i_REGIMM_BGEZAL:
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g_Notify->BreakPoint(__FILE__, __LINE__);
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#ifdef legacycode
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m_NextInstruction = DELAY_SLOT;
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if (m_Reg.IsConst(m_Command.rs))
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{
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int64_t Value;
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if (m_Reg.Is32Bit(m_Command.rs))
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{
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Value = m_Reg.GetMipsRegLo_S(m_Command.rs);
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}
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else {
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Value = m_Reg.GetMipsReg_S(m_Command.rs);
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}
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if (Value >= 0)
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{
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m_Reg.GetMipsRegLo(31) = m_PC + 8;
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m_Reg.SetMipsRegState(31, CRegInfo::STATE_CONST_32_SIGN);
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Section->m_Jump.TargetPC = m_PC + ((int16_t)m_Command.offset << 2) + 4;
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if (m_PC == Section->m_Jump.TargetPC)
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{
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if (!DelaySlotEffectsCompare(m_PC, 31, 0))
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{
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Section->m_Jump.PermLoop = true;
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}
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}
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break;
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}
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}
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m_Reg.GetMipsRegLo(31) = m_PC + 8;
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m_Reg.SetMipsRegState(31, CRegInfo::STATE_CONST_32_SIGN);
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Section->m_Cont.TargetPC = m_PC + 8;
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Section->m_Jump.TargetPC = m_PC + ((int16_t)m_Command.offset << 2) + 4;
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if (m_PC == Section->m_Jump.TargetPC)
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{
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if (!DelaySlotEffectsCompare(m_PC, m_Command.rs, 0))
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{
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Section->m_Jump.PermLoop = true;
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}
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}
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#endif
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break;
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default:
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g_Notify->BreakPoint(__FILE__, __LINE__);
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#ifdef legacycode
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if (m_Command.Hex == 0x0407000D) { break; }
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g_Notify->DisplayError("Unhandled R4300i OpCode in FillSectionInfo 4\n%s",
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R4300iOpcodeName(m_Command.Hex, m_PC));
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m_NextInstruction = END_BLOCK;
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m_PC -= 4;
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#endif
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}
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break;
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case R4300i_JAL:
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g_Notify->BreakPoint(__FILE__, __LINE__);
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#ifdef legacycode
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m_NextInstruction = DELAY_SLOT;
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m_Reg.GetMipsRegLo(31) = m_PC + 8;
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m_Reg.SetMipsRegState(31, CRegInfo::STATE_CONST_32_SIGN);
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Section->m_Jump.TargetPC = (m_PC & 0xF0000000) + (m_Command.target << 2);
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if (m_PC == Section->m_Jump.TargetPC)
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{
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if (!DelaySlotEffectsCompare(m_PC, 31, 0))
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{
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Section->m_Jump.PermLoop = true;
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}
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}
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#endif
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break;
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case R4300i_J:
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m_NextInstruction = DELAY_SLOT;
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#ifdef CHECKED_BUILD
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if (Section->m_Jump.TargetPC != (m_PC & 0xF0000000) + (m_Command.target << 2))
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{
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g_Notify->BreakPoint(__FILE__, __LINE__);
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}
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if (m_PC == Section->m_Jump.TargetPC && !Section->m_Jump.PermLoop)
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{
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g_Notify->BreakPoint(__FILE__, __LINE__);
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}
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#endif
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break;
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case R4300i_BEQ:
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if (m_PC + ((int16_t)m_Command.offset << 2) + 4 != m_PC + 8)
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{
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m_NextInstruction = DELAY_SLOT;
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#ifdef CHECKED_BUILD
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if (m_Command.rs != 0 || m_Command.rt != 0)
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{
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if (Section->m_Cont.TargetPC != m_PC + 8 &&
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Section->m_ContinueSection != nullptr &&
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Section->m_Cont.TargetPC != (uint32_t)-1)
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{
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g_Notify->BreakPoint(__FILE__, __LINE__);
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}
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}
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else
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{
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if (Section->m_Cont.TargetPC != (uint32_t)-1)
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{
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//g_Notify->BreakPoint(__FILE__, __LINE__);
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}
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}
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if (Section->m_Jump.TargetPC != m_PC + ((int16_t)m_Command.offset << 2) + 4)
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{
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//g_Notify->BreakPoint(__FILE__, __LINE__);
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}
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if (m_PC == Section->m_Jump.TargetPC)
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{
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if (!DelaySlotEffectsCompare(m_PC, m_Command.rs, m_Command.rt) && !Section->m_Jump.PermLoop)
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{
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g_Notify->BreakPoint(__FILE__, __LINE__);
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}
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}
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#endif
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}
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break;
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case R4300i_BNE:
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case R4300i_BLEZ:
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case R4300i_BGTZ:
|
|
if (m_PC + ((int16_t)m_Command.offset << 2) + 4 != m_PC + 8)
|
|
{
|
|
m_NextInstruction = DELAY_SLOT;
|
|
#ifdef CHECKED_BUILD
|
|
if (Section->m_Cont.TargetPC != m_PC + 8 &&
|
|
Section->m_ContinueSection != nullptr &&
|
|
Section->m_Cont.TargetPC != (uint32_t)-1)
|
|
{
|
|
g_Notify->BreakPoint(__FILE__, __LINE__);
|
|
}
|
|
if (Section->m_Jump.TargetPC != m_PC + ((int16_t)m_Command.offset << 2) + 4 &&
|
|
Section->m_JumpSection != nullptr &&
|
|
Section->m_Jump.TargetPC != (uint32_t)-1)
|
|
{
|
|
g_Notify->BreakPoint(__FILE__, __LINE__);
|
|
}
|
|
if (m_PC == Section->m_Jump.TargetPC)
|
|
{
|
|
if (!DelaySlotEffectsCompare(m_PC, m_Command.rs, m_Command.rt) && !Section->m_Jump.PermLoop)
|
|
{
|
|
g_Notify->BreakPoint(__FILE__, __LINE__);
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
break;
|
|
case R4300i_ADDI:
|
|
case R4300i_ADDIU:
|
|
if (m_Command.rt == 0) { break; }
|
|
/*if (m_Command.rs == 0) {
|
|
m_Reg.GetMipsRegLo(m_Command.rt) = (int16_t)m_Command.immediate;
|
|
m_Reg.SetMipsRegState(m_Command.rt,CRegInfo::STATE_CONST_32_SIGN);
|
|
} else {*/
|
|
m_Reg.SetMipsRegState(m_Command.rt, CRegInfo::STATE_MODIFIED);
|
|
//}
|
|
break;
|
|
case R4300i_SLTI:
|
|
case R4300i_SLTIU:
|
|
if (m_Command.rt == 0) { break; }
|
|
m_Reg.SetMipsRegState(m_Command.rt, CRegInfo::STATE_MODIFIED);
|
|
break;
|
|
case R4300i_LUI:
|
|
if (m_Command.rt == 0) { break; }
|
|
if (!m_Reg.IsModified(m_Command.rt))
|
|
{
|
|
m_Reg.SetMipsRegLo(m_Command.rt, ((int16_t)m_Command.offset << 16));
|
|
m_Reg.SetMipsRegState(m_Command.rt, CRegInfo::STATE_CONST_32_SIGN);
|
|
}
|
|
break;
|
|
case R4300i_ANDI:
|
|
if (m_Command.rt == 0) { break; }
|
|
m_Reg.SetMipsRegState(m_Command.rt, CRegInfo::STATE_MODIFIED);
|
|
break;
|
|
case R4300i_ORI:
|
|
if (m_Command.rt == 0) { break; }
|
|
if (m_Command.rs == m_Command.rt)
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rt, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
if (m_Reg.IsConst(m_Command.rs)) {
|
|
m_Reg.SetMipsRegState(m_Command.rt, CRegInfo::STATE_CONST_32_SIGN);
|
|
m_Reg.SetMipsRegLo(m_Command.rt, m_Reg.GetMipsRegLo(m_Command.rs) | m_Command.immediate);
|
|
}
|
|
else {
|
|
m_Reg.SetMipsRegState(m_Command.rt, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
break;
|
|
case R4300i_XORI:
|
|
if (m_Command.rt == 0) { break; }
|
|
if (m_Command.rs == m_Command.rt)
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rt, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
if (m_Reg.IsConst(m_Command.rs))
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rt, CRegInfo::STATE_CONST_32_SIGN);
|
|
m_Reg.SetMipsRegLo(m_Command.rt, m_Reg.GetMipsRegLo(m_Command.rs) ^ m_Command.immediate);
|
|
}
|
|
else
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rt, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
break;
|
|
case R4300i_CP0:
|
|
switch (m_Command.rs)
|
|
{
|
|
case R4300i_COP0_MF:
|
|
if (m_Command.rt == 0) { break; }
|
|
m_Reg.SetMipsRegState(m_Command.rt, CRegInfo::STATE_MODIFIED);
|
|
break;
|
|
case R4300i_COP0_MT: break;
|
|
default:
|
|
if ((m_Command.rs & 0x10) != 0)
|
|
{
|
|
switch (m_Command.funct)
|
|
{
|
|
case R4300i_COP0_CO_TLBR: break;
|
|
case R4300i_COP0_CO_TLBWI: break;
|
|
case R4300i_COP0_CO_TLBWR: break;
|
|
case R4300i_COP0_CO_TLBP: break;
|
|
case R4300i_COP0_CO_ERET: m_NextInstruction = END_BLOCK; break;
|
|
default:
|
|
g_Notify->DisplayError(stdstr_f("Unhandled R4300i OpCode in FillSectionInfo\n%s", R4300iOpcodeName(m_Command.Hex, m_PC)).c_str());
|
|
m_NextInstruction = END_BLOCK;
|
|
m_PC -= 4;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
g_Notify->DisplayError(stdstr_f("Unhandled R4300i OpCode in FillSectionInfo 3\n%s", R4300iOpcodeName(m_Command.Hex, m_PC)).c_str());
|
|
m_NextInstruction = END_BLOCK;
|
|
m_PC -= 4;
|
|
}
|
|
}
|
|
break;
|
|
case R4300i_CP1:
|
|
switch (m_Command.fmt)
|
|
{
|
|
case R4300i_COP1_CF:
|
|
case R4300i_COP1_MF:
|
|
case R4300i_COP1_DMF:
|
|
if (m_Command.rt == 0) { break; }
|
|
m_Reg.SetMipsRegState(m_Command.rt, CRegInfo::STATE_MODIFIED);
|
|
break;
|
|
case R4300i_COP1_BC:
|
|
switch (m_Command.ft)
|
|
{
|
|
case R4300i_COP1_BC_BCFL:
|
|
case R4300i_COP1_BC_BCTL:
|
|
m_NextInstruction = LIKELY_DELAY_SLOT;
|
|
#ifdef CHECKED_BUILD
|
|
if (Section->m_Cont.TargetPC != m_PC + 8 &&
|
|
Section->m_ContinueSection != nullptr &&
|
|
Section->m_Cont.TargetPC != (uint32_t)-1)
|
|
{
|
|
g_Notify->BreakPoint(__FILE__, __LINE__);
|
|
}
|
|
if (m_PC == m_PC + ((int16_t)m_Command.offset << 2) + 4)
|
|
{
|
|
g_Notify->BreakPoint(__FILE__, __LINE__);
|
|
#ifdef legacycode
|
|
if (!DelaySlotEffectsCompare(m_PC, m_Command.rs, m_Command.rt))
|
|
{
|
|
if (!Section->m_Jump.PermLoop)
|
|
{
|
|
g_Notify->BreakPoint(__FILE__, __LINE__);
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
#endif
|
|
break;
|
|
case R4300i_COP1_BC_BCF:
|
|
case R4300i_COP1_BC_BCT:
|
|
m_NextInstruction = DELAY_SLOT;
|
|
#ifdef CHECKED_BUILD
|
|
if (Section->m_Cont.TargetPC != m_PC + 8 &&
|
|
Section->m_ContinueSection != nullptr &&
|
|
Section->m_Cont.TargetPC != (uint32_t)-1)
|
|
{
|
|
g_Notify->BreakPoint(__FILE__, __LINE__);
|
|
}
|
|
if (Section->m_Jump.TargetPC != m_PC + ((int16_t)m_Command.offset << 2) + 4)
|
|
{
|
|
g_Notify->BreakPoint(__FILE__, __LINE__);
|
|
}
|
|
if (m_PC == Section->m_Jump.TargetPC)
|
|
{
|
|
g_Notify->BreakPoint(__FILE__, __LINE__);
|
|
#ifdef legacycode
|
|
if (!DelaySlotEffectsCompare(m_PC, m_Command.rs, m_Command.rt)) {
|
|
Section->m_Jump.PermLoop = true;
|
|
}
|
|
#endif
|
|
}
|
|
#endif
|
|
break;
|
|
}
|
|
break;
|
|
case R4300i_COP1_MT: break;
|
|
case R4300i_COP1_DMT: break;
|
|
case R4300i_COP1_CT: break;
|
|
case R4300i_COP1_S: break;
|
|
case R4300i_COP1_D: break;
|
|
case R4300i_COP1_W: break;
|
|
case R4300i_COP1_L: break;
|
|
default:
|
|
g_Notify->DisplayError(stdstr_f("Unhandled R4300i OpCode in FillSectionInfo 2\n%s", R4300iOpcodeName(m_Command.Hex, m_PC)).c_str());
|
|
m_NextInstruction = END_BLOCK;
|
|
m_PC -= 4;
|
|
}
|
|
break;
|
|
case R4300i_BEQL:
|
|
case R4300i_BNEL:
|
|
case R4300i_BLEZL:
|
|
case R4300i_BGTZL:
|
|
m_NextInstruction = LIKELY_DELAY_SLOT;
|
|
#ifdef CHECKED_BUILD
|
|
if (Section->m_Cont.TargetPC != m_PC + 8 &&
|
|
Section->m_ContinueSection != nullptr &&
|
|
Section->m_Cont.TargetPC != (uint32_t)-1)
|
|
{
|
|
g_Notify->BreakPoint(__FILE__, __LINE__);
|
|
}
|
|
if (Section->m_Jump.TargetPC != m_PC + 4)
|
|
{
|
|
//g_Notify->BreakPoint(__FILE__, __LINE__);
|
|
}
|
|
/*if (Section->m_Jump.TargetPC != m_PC + ((int16_t)m_Command.offset << 2) + 4)
|
|
{
|
|
g_Notify->BreakPoint(__FILE__, __LINE__);
|
|
}*/
|
|
if (m_PC == m_PC + ((int16_t)m_Command.offset << 2) + 4)
|
|
{
|
|
if (!DelaySlotEffectsCompare(m_PC, m_Command.rs, m_Command.rt) && !Section->m_Jump.PermLoop)
|
|
{
|
|
g_Notify->BreakPoint(__FILE__, __LINE__);
|
|
}
|
|
}
|
|
#endif
|
|
break;
|
|
case R4300i_DADDI:
|
|
case R4300i_DADDIU:
|
|
if (m_Command.rt == 0) { break; }
|
|
if (m_Command.rs == m_Command.rt)
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rt, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
if (m_Reg.IsConst(m_Command.rs))
|
|
{
|
|
if (m_Reg.Is64Bit(m_Command.rs))
|
|
{
|
|
int imm32 = (int16_t)m_Command.immediate;
|
|
int64_t imm64 = imm32;
|
|
m_Reg.SetMipsReg_S(m_Command.rt, m_Reg.GetMipsRegLo_S(m_Command.rs) + imm64);
|
|
}
|
|
else
|
|
{
|
|
m_Reg.SetMipsReg_S(m_Command.rt, m_Reg.GetMipsRegLo_S(m_Command.rs) + (int16_t)m_Command.immediate);
|
|
}
|
|
m_Reg.SetMipsRegState(m_Command.rt, CRegInfo::STATE_CONST_64);
|
|
}
|
|
else
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rt, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
break;
|
|
case R4300i_LDR:
|
|
case R4300i_LDL:
|
|
case R4300i_LB:
|
|
case R4300i_LH:
|
|
case R4300i_LWL:
|
|
case R4300i_LW:
|
|
case R4300i_LWU:
|
|
case R4300i_LL:
|
|
case R4300i_LBU:
|
|
case R4300i_LHU:
|
|
case R4300i_LWR:
|
|
case R4300i_SC:
|
|
if (m_Command.rt == 0) { break; }
|
|
m_Reg.SetMipsRegState(m_Command.rt, CRegInfo::STATE_MODIFIED);
|
|
break;
|
|
case R4300i_SB: break;
|
|
case R4300i_SH: break;
|
|
case R4300i_SWL: break;
|
|
case R4300i_SW: break;
|
|
case R4300i_SWR: break;
|
|
case R4300i_SDL: break;
|
|
case R4300i_SDR: break;
|
|
case R4300i_CACHE: break;
|
|
case R4300i_LWC1: break;
|
|
case R4300i_SWC1: break;
|
|
case R4300i_LDC1: break;
|
|
case R4300i_LD:
|
|
if (m_Command.rt == 0) { break; }
|
|
m_Reg.SetMipsRegState(m_Command.rt, CRegInfo::STATE_MODIFIED);
|
|
break;
|
|
case R4300i_SDC1: break;
|
|
case R4300i_SD: break;
|
|
default:
|
|
m_NextInstruction = END_BLOCK;
|
|
m_PC -= 4;
|
|
if (m_Command.Hex == 0x7C1C97C0) { break; }
|
|
if (m_Command.Hex == 0x7FFFFFFF) { break; }
|
|
if (m_Command.Hex == 0xF1F3F5F7) { break; }
|
|
if (m_Command.Hex == 0xC1200000) { break; }
|
|
if (m_Command.Hex == 0x4C5A5353) { break; }
|
|
g_Notify->DisplayError(stdstr_f("Unhandled R4300i OpCode in FillSectionInfo 1\n%s\n%X", R4300iOpcodeName(m_Command.Hex, m_PC), m_Command.Hex).c_str());
|
|
}
|
|
|
|
CPU_Message(" %s state: %X value: %X", CRegName::GPR[5], m_Reg.GetMipsRegState(5), m_Reg.GetMipsRegLo(5));
|
|
|
|
if (Section->m_DelaySlot)
|
|
{
|
|
if (m_NextInstruction != NORMAL && m_NextInstruction != END_BLOCK)
|
|
{
|
|
g_Notify->BreakPoint(__FILE__, __LINE__);
|
|
}
|
|
m_NextInstruction = END_BLOCK;
|
|
SetJumpRegSet(Section, m_Reg);
|
|
}
|
|
else
|
|
{
|
|
switch (m_NextInstruction)
|
|
{
|
|
case NORMAL:
|
|
m_PC += 4;
|
|
break;
|
|
case DELAY_SLOT:
|
|
m_NextInstruction = DELAY_SLOT_DONE;
|
|
m_PC += 4;
|
|
if ((m_PC & 0xFFFFF000) != (m_EnterSection->m_EnterPC & 0xFFFFF000))
|
|
{
|
|
g_Notify->BreakPoint(__FILE__, __LINE__);
|
|
}
|
|
break;
|
|
case LIKELY_DELAY_SLOT:
|
|
SetContinueRegSet(Section, m_Reg);
|
|
SetJumpRegSet(Section, m_Reg);
|
|
m_NextInstruction = END_BLOCK;
|
|
break;
|
|
case DELAY_SLOT_DONE:
|
|
SetContinueRegSet(Section, m_Reg);
|
|
SetJumpRegSet(Section, m_Reg);
|
|
m_NextInstruction = END_BLOCK;
|
|
break;
|
|
case LIKELY_DELAY_SLOT_DONE:
|
|
g_Notify->BreakPoint(__FILE__, __LINE__);
|
|
m_NextInstruction = END_BLOCK;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (m_PC == ContinueSectionPC)
|
|
{
|
|
m_NextInstruction = END_BLOCK;
|
|
SetContinueRegSet(Section, m_Reg);
|
|
}
|
|
|
|
if ((m_PC & 0xFFFFF000) != (m_EnterSection->m_EnterPC & 0xFFFFF000))
|
|
{
|
|
if (m_NextInstruction != END_BLOCK && m_NextInstruction != NORMAL)
|
|
{
|
|
g_Notify->BreakPoint(__FILE__, __LINE__);
|
|
}
|
|
g_Notify->BreakPoint(__FILE__, __LINE__);
|
|
}
|
|
} while (m_NextInstruction != END_BLOCK);
|
|
|
|
if (!CheckLoopRegisterUsage(Section->m_ContinueSection)) { return false; }
|
|
if (!CheckLoopRegisterUsage(Section->m_JumpSection)) { return false; }
|
|
return true;
|
|
}
|
|
|
|
bool LoopAnalysis::SyncRegState(CRegInfo & RegSet, const CRegInfo& SyncReg)
|
|
{
|
|
bool bChanged = false;
|
|
for (int x = 0; x < 32; x++)
|
|
{
|
|
if (RegSet.GetMipsRegState(x) != SyncReg.GetMipsRegState(x))
|
|
{
|
|
CPU_Message("%s: Clear state %s RegEnter State: %X Jump Reg State: %X", __FUNCTION__, CRegName::GPR[x], RegSet.GetMipsRegState(x), SyncReg.GetMipsRegState(x));
|
|
RegSet.SetMipsRegState(x, CRegInfo::STATE_MODIFIED);
|
|
bChanged = true;
|
|
}
|
|
else if (RegSet.IsConst(x) && RegSet.Is32Bit(x) && RegSet.GetMipsRegLo(x) != SyncReg.GetMipsRegLo(x))
|
|
{
|
|
CPU_Message("%s: Clear state %s RegEnter State: %X Jump Reg State: %X", __FUNCTION__, CRegName::GPR[x], RegSet.GetMipsRegState(x), SyncReg.GetMipsRegState(x));
|
|
RegSet.SetMipsRegState(x, CRegInfo::STATE_MODIFIED);
|
|
bChanged = true;
|
|
}
|
|
else if (RegSet.IsConst(x) && RegSet.Is64Bit(x) && RegSet.GetMipsReg_S(x) != SyncReg.GetMipsReg_S(x))
|
|
{
|
|
g_Notify->BreakPoint(__FILE__, __LINE__);
|
|
}
|
|
}
|
|
return bChanged;
|
|
}
|
|
|
|
void LoopAnalysis::SetJumpRegSet(CCodeSection * Section, const CRegInfo &Reg)
|
|
{
|
|
RegisterMap::iterator itr = m_JumpRegisters.find(Section->m_SectionID);
|
|
if (itr != m_JumpRegisters.end())
|
|
{
|
|
*(itr->second) = Reg;
|
|
}
|
|
else
|
|
{
|
|
m_JumpRegisters.insert(RegisterMap::value_type(Section->m_SectionID, new CRegInfo(Reg)));
|
|
}
|
|
}
|
|
|
|
void LoopAnalysis::SetContinueRegSet(CCodeSection * Section, const CRegInfo &Reg)
|
|
{
|
|
RegisterMap::iterator itr = m_ContinueRegisters.find(Section->m_SectionID);
|
|
if (itr != m_ContinueRegisters.end())
|
|
{
|
|
*(itr->second) = Reg;
|
|
}
|
|
else
|
|
{
|
|
m_ContinueRegisters.insert(RegisterMap::value_type(Section->m_SectionID, new CRegInfo(Reg)));
|
|
}
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_SLL()
|
|
{
|
|
if (m_Command.rd == 0) { return; }
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_SRL()
|
|
{
|
|
if (m_Command.rd == 0) { return; }
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_SRA()
|
|
{
|
|
if (m_Command.rd == 0) { return; }
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_SLLV()
|
|
{
|
|
if (m_Command.rd == 0) { return; }
|
|
if (m_Command.rt == m_Command.rd || m_Command.rs == m_Command.rd)
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
if (m_Reg.IsConst(m_Command.rt) && m_Reg.IsConst(m_Command.rs))
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_CONST_32_SIGN);
|
|
m_Reg.SetMipsRegLo(m_Command.rd, m_Reg.GetMipsRegLo(m_Command.rt) << (m_Reg.GetMipsRegLo(m_Command.rs) & 0x1F));
|
|
}
|
|
else
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_SRLV()
|
|
{
|
|
if (m_Command.rd == 0) { return; }
|
|
if (m_Command.rt == m_Command.rd || m_Command.rs == m_Command.rd)
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
if (m_Reg.IsConst(m_Command.rt) && m_Reg.IsConst(m_Command.rs))
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_CONST_32_SIGN);
|
|
m_Reg.SetMipsRegLo(m_Command.rd, m_Reg.GetMipsRegLo(m_Command.rt) >> (m_Reg.GetMipsRegLo(m_Command.rs) & 0x1F));
|
|
}
|
|
else
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_SRAV()
|
|
{
|
|
if (m_Command.rd == 0) { return; }
|
|
if (m_Command.rt == m_Command.rd || m_Command.rs == m_Command.rd)
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
if (m_Reg.IsConst(m_Command.rt) && m_Reg.IsConst(m_Command.rs))
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_CONST_32_SIGN);
|
|
m_Reg.SetMipsRegLo(m_Command.rd, m_Reg.GetMipsRegLo_S(m_Command.rt) >> (m_Reg.GetMipsRegLo(m_Command.rs) & 0x1F));
|
|
}
|
|
else
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_JR()
|
|
{
|
|
g_Notify->BreakPoint(__FILE__, __LINE__);
|
|
#ifdef legacycode
|
|
if (m_Reg.IsConst(m_Command.rs))
|
|
{
|
|
Section->m_Jump.TargetPC = m_Reg.GetMipsRegLo(m_Command.rs);
|
|
}
|
|
else
|
|
{
|
|
Section->m_Jump.TargetPC = (uint32_t)-1;
|
|
}
|
|
#endif
|
|
m_NextInstruction = DELAY_SLOT;
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_JALR()
|
|
{
|
|
g_Notify->BreakPoint(__FILE__, __LINE__);
|
|
#ifdef legacycode
|
|
m_Reg.GetMipsRegLo(m_Command.rd) = m_PC + 8;
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_CONST_32_SIGN);
|
|
if (m_Reg.IsConst(m_Command.rs)) {
|
|
Section->m_Jump.TargetPC = m_Reg.GetMipsRegLo(m_Command.rs);
|
|
}
|
|
else
|
|
{
|
|
Section->m_Jump.TargetPC = (uint32_t)-1;
|
|
}
|
|
#endif
|
|
m_NextInstruction = DELAY_SLOT;
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_SYSCALL(CCodeSection * Section)
|
|
{
|
|
#ifdef CHECKED_BUILD
|
|
if (Section->m_ContinueSection != nullptr &&
|
|
Section->m_Cont.TargetPC != (uint32_t)-1)
|
|
{
|
|
g_Notify->BreakPoint(__FILE__, __LINE__);
|
|
}
|
|
if (Section->m_JumpSection != nullptr &&
|
|
Section->m_Jump.TargetPC != (uint32_t)-1)
|
|
{
|
|
g_Notify->BreakPoint(__FILE__, __LINE__);
|
|
}
|
|
#else
|
|
Section = Section;
|
|
#endif
|
|
m_NextInstruction = END_BLOCK;
|
|
m_PC -= 4;
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_BREAK(CCodeSection * Section)
|
|
{
|
|
#ifdef CHECKED_BUILD
|
|
if (Section->m_ContinueSection != nullptr &&
|
|
Section->m_Cont.TargetPC != (uint32_t)-1)
|
|
{
|
|
g_Notify->BreakPoint(__FILE__, __LINE__);
|
|
}
|
|
if (Section->m_JumpSection != nullptr &&
|
|
Section->m_Jump.TargetPC != (uint32_t)-1)
|
|
{
|
|
g_Notify->BreakPoint(__FILE__, __LINE__);
|
|
}
|
|
#else
|
|
Section = Section;
|
|
#endif
|
|
m_NextInstruction = END_BLOCK;
|
|
m_PC -= 4;
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_MFHI()
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_MTHI()
|
|
{
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_MFLO()
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_MTLO()
|
|
{
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_DSLLV()
|
|
{
|
|
if (m_Command.rd == 0) { return; }
|
|
if (m_Command.rt == m_Command.rd || m_Command.rs == m_Command.rd)
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
if (m_Reg.IsConst(m_Command.rt) && m_Reg.IsConst(m_Command.rs))
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_CONST_64);
|
|
m_Reg.SetMipsReg(m_Command.rd, m_Reg.Is64Bit(m_Command.rt) ? m_Reg.GetMipsReg(m_Command.rt) : (uint64_t)m_Reg.GetMipsRegLo_S(m_Command.rt) << (m_Reg.GetMipsRegLo(m_Command.rs) & 0x3F));
|
|
}
|
|
else
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_DSRLV()
|
|
{
|
|
if (m_Command.rd == 0) { return; }
|
|
if (m_Command.rt == m_Command.rd || m_Command.rs == m_Command.rd)
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
if (m_Reg.IsConst(m_Command.rt) && m_Reg.IsConst(m_Command.rs))
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_CONST_64);
|
|
m_Reg.SetMipsReg(m_Command.rd, m_Reg.Is64Bit(m_Command.rt) ? m_Reg.GetMipsReg(m_Command.rt) : (uint64_t)m_Reg.GetMipsRegLo_S(m_Command.rt) >> (m_Reg.GetMipsRegLo(m_Command.rs) & 0x3F));
|
|
}
|
|
else
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_DSRAV()
|
|
{
|
|
if (m_Command.rd == 0) { return; }
|
|
if (m_Command.rt == m_Command.rd || m_Command.rs == m_Command.rd)
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
if (m_Reg.IsConst(m_Command.rt) && m_Reg.IsConst(m_Command.rs)) {
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_CONST_64);
|
|
m_Reg.SetMipsReg(m_Command.rd, m_Reg.Is64Bit(m_Command.rt) ? m_Reg.GetMipsReg_S(m_Command.rt) : (int64_t)m_Reg.GetMipsRegLo_S(m_Command.rt) >> (m_Reg.GetMipsRegLo(m_Command.rs) & 0x3F));
|
|
}
|
|
else
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_ADD()
|
|
{
|
|
if (m_Command.rd == 0) { return; }
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_ADDU()
|
|
{
|
|
if (m_Command.rd == 0) { return; }
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_SUB()
|
|
{
|
|
if (m_Command.rd == 0) { return; }
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_SUBU()
|
|
{
|
|
if (m_Command.rd == 0) { return; }
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_AND()
|
|
{
|
|
if (m_Command.rd == 0) { return; }
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_OR()
|
|
{
|
|
if (m_Command.rd == 0) { return; }
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_XOR()
|
|
{
|
|
if (m_Command.rd == 0) { return; }
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_NOR()
|
|
{
|
|
if (m_Command.rd == 0) { return; }
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_SLT()
|
|
{
|
|
if (m_Command.rd == 0) { return; }
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_SLTU()
|
|
{
|
|
if (m_Command.rd == 0) { return; }
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_DADD()
|
|
{
|
|
if (m_Command.rd == 0) { return; }
|
|
if (m_Command.rt == m_Command.rd || m_Command.rs == m_Command.rd)
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
if (m_Reg.IsConst(m_Command.rt) && m_Reg.IsConst(m_Command.rs))
|
|
{
|
|
m_Reg.SetMipsReg(m_Command.rd,
|
|
(m_Reg.Is64Bit(m_Command.rs) ? m_Reg.GetMipsReg(m_Command.rs) : (int64_t)m_Reg.GetMipsRegLo_S(m_Command.rs)) +
|
|
(m_Reg.Is64Bit(m_Command.rt) ? m_Reg.GetMipsReg(m_Command.rt) : (int64_t)m_Reg.GetMipsRegLo_S(m_Command.rt))
|
|
);
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_CONST_64);
|
|
}
|
|
else
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_DADDU()
|
|
{
|
|
if (m_Command.rd == 0) { return; }
|
|
if (m_Command.rt == m_Command.rd || m_Command.rs == m_Command.rd)
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
if (m_Reg.IsConst(m_Command.rt) && m_Reg.IsConst(m_Command.rs))
|
|
{
|
|
m_Reg.SetMipsReg(m_Command.rd,
|
|
(m_Reg.Is64Bit(m_Command.rs) ? m_Reg.GetMipsReg(m_Command.rs) : (int64_t)m_Reg.GetMipsRegLo_S(m_Command.rs)) +
|
|
(m_Reg.Is64Bit(m_Command.rt) ? m_Reg.GetMipsReg(m_Command.rt) : (int64_t)m_Reg.GetMipsRegLo_S(m_Command.rt))
|
|
);
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_CONST_64);
|
|
}
|
|
else
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_DSUB()
|
|
{
|
|
if (m_Command.rd == 0) { return; }
|
|
if (m_Command.rt == m_Command.rd || m_Command.rs == m_Command.rd)
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
if (m_Reg.IsConst(m_Command.rt) && m_Reg.IsConst(m_Command.rs))
|
|
{
|
|
m_Reg.SetMipsReg(m_Command.rd,
|
|
(m_Reg.Is64Bit(m_Command.rs) ? m_Reg.GetMipsReg(m_Command.rs) : (int64_t)m_Reg.GetMipsRegLo_S(m_Command.rs)) -
|
|
(m_Reg.Is64Bit(m_Command.rt) ? m_Reg.GetMipsReg(m_Command.rt) : (int64_t)m_Reg.GetMipsRegLo_S(m_Command.rt))
|
|
);
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_CONST_64);
|
|
}
|
|
else
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_DSUBU()
|
|
{
|
|
if (m_Command.rd == 0) { return; }
|
|
if (m_Command.rt == m_Command.rd || m_Command.rs == m_Command.rd)
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
if (m_Reg.IsConst(m_Command.rt) && m_Reg.IsConst(m_Command.rs))
|
|
{
|
|
m_Reg.SetMipsReg(m_Command.rd,
|
|
(m_Reg.Is64Bit(m_Command.rs) ? m_Reg.GetMipsReg(m_Command.rs) : (int64_t)m_Reg.GetMipsRegLo_S(m_Command.rs)) -
|
|
(m_Reg.Is64Bit(m_Command.rt) ? m_Reg.GetMipsReg(m_Command.rt) : (int64_t)m_Reg.GetMipsRegLo_S(m_Command.rt))
|
|
);
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_CONST_64);
|
|
}
|
|
else
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_DSLL()
|
|
{
|
|
if (m_Command.rd == 0) { return; }
|
|
if (m_Command.rt == m_Command.rd)
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
if (m_Reg.IsConst(m_Command.rt))
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_CONST_64);
|
|
m_Reg.SetMipsReg(m_Command.rd, m_Reg.Is64Bit(m_Command.rt) ? m_Reg.GetMipsReg(m_Command.rt) : (int64_t)m_Reg.GetMipsRegLo_S(m_Command.rt) << m_Command.sa);
|
|
}
|
|
else
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_DSRL()
|
|
{
|
|
if (m_Command.rd == 0) { return; }
|
|
if (m_Command.rt == m_Command.rd)
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
if (m_Reg.IsConst(m_Command.rt))
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_CONST_64);
|
|
m_Reg.SetMipsReg(m_Command.rd, m_Reg.Is64Bit(m_Command.rt) ? m_Reg.GetMipsReg(m_Command.rt) : (uint64_t)m_Reg.GetMipsRegLo_S(m_Command.rt) >> m_Command.sa);
|
|
}
|
|
else
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_DSRA()
|
|
{
|
|
if (m_Command.rd == 0) { return; }
|
|
if (m_Command.rt == m_Command.rd)
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
if (m_Reg.IsConst(m_Command.rt))
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_CONST_64);
|
|
m_Reg.SetMipsReg_S(m_Command.rd, m_Reg.Is64Bit(m_Command.rt) ? m_Reg.GetMipsReg_S(m_Command.rt) : (int64_t)m_Reg.GetMipsRegLo_S(m_Command.rt) >> m_Command.sa);
|
|
}
|
|
else
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_DSLL32()
|
|
{
|
|
if (m_Command.rd == 0) { return; }
|
|
if (m_Command.rt == m_Command.rd)
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
if (m_Reg.IsConst(m_Command.rt))
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_CONST_64);
|
|
m_Reg.SetMipsReg(m_Command.rd, m_Reg.GetMipsRegLo(m_Command.rt) << (m_Command.sa + 32));
|
|
}
|
|
else
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_DSRL32()
|
|
{
|
|
if (m_Command.rd == 0) { return; }
|
|
if (m_Command.rt == m_Command.rd)
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
if (m_Reg.IsConst(m_Command.rt))
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_CONST_32_SIGN);
|
|
m_Reg.SetMipsRegLo(m_Command.rd, (uint32_t)(m_Reg.GetMipsReg(m_Command.rt) >> (m_Command.sa + 32)));
|
|
}
|
|
else
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
}
|
|
|
|
void LoopAnalysis::SPECIAL_DSRA32()
|
|
{
|
|
if (m_Command.rd == 0) { return; }
|
|
if (m_Command.rt == m_Command.rd)
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
if (m_Reg.IsConst(m_Command.rt))
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_CONST_32_SIGN);
|
|
m_Reg.SetMipsRegLo(m_Command.rd, (uint32_t)(m_Reg.GetMipsReg_S(m_Command.rt) >> (m_Command.sa + 32)));
|
|
}
|
|
else
|
|
{
|
|
m_Reg.SetMipsRegState(m_Command.rd, CRegInfo::STATE_MODIFIED);
|
|
}
|
|
} |