451 lines
15 KiB
C++
451 lines
15 KiB
C++
#pragma once
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#include <Common/Platform.h>
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#include <Project64-core\Logging.h>
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#include <Project64-core\N64System\MemoryHandler\AudioInterfaceHandler.h>
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#include <Project64-core\N64System\MemoryHandler\CartridgeDomain2Address1Handler.h>
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#include <Project64-core\N64System\MemoryHandler\DisplayControlRegHandler.h>
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#include <Project64-core\N64System\MemoryHandler\MIPSInterfaceHandler.h>
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#include <Project64-core\N64System\MemoryHandler\PeripheralInterfaceHandler.h>
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#include <Project64-core\N64System\MemoryHandler\RDRAMInterfaceHandler.h>
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#include <Project64-core\N64System\MemoryHandler\RDRAMRegistersHandler.h>
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#include <Project64-core\N64System\MemoryHandler\SPRegistersHandler.h>
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#include <Project64-core\N64System\MemoryHandler\SerialInterfaceHandler.h>
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#include <Project64-core\N64System\MemoryHandler\VideoInterfaceHandler.h>
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#include <Project64-core\N64System\N64Types.h>
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#include <Project64-core\Settings\DebugSettings.h>
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#include <Project64-core\Settings\GameSettings.h>
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#pragma warning(push)
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#pragma warning(disable : 4201) // Non-standard extension used: nameless struct/union
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union COP0Context
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{
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uint64_t Value;
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struct
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{
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unsigned : 4;
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unsigned BadVPN2 : 19;
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unsigned PTEBaseHi : 9;
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unsigned PTEBaseLo : 32;
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};
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};
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union COP0XContext
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{
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uint64_t Value;
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struct
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{
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uint64_t : 4;
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uint64_t BadVPN2 : 27;
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uint64_t R : 2;
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uint64_t PTEBase : 31;
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};
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};
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union FPStatusReg
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{
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uint32_t Value;
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struct
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{
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unsigned RoundingMode : 2;
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unsigned : 22;
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unsigned FlushSubnormals : 1;
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unsigned : 7;
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};
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struct
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{
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unsigned : 2;
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unsigned Inexact : 1;
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unsigned Underflow : 1;
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unsigned Overflow : 1;
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unsigned DivisionByZero : 1;
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unsigned InvalidOperation : 1;
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unsigned : 25;
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} Flags;
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struct
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{
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unsigned : 7;
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unsigned Inexact : 1;
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unsigned Underflow : 1;
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unsigned Overflow : 1;
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unsigned DivisionByZero : 1;
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unsigned InvalidOperation : 1;
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unsigned : 20;
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} Enable;
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struct
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{
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unsigned : 12;
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unsigned Inexact : 1;
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unsigned Underflow : 1;
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unsigned Overflow : 1;
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unsigned DivisionByZero : 1;
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unsigned InvalidOperation : 1;
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unsigned UnimplementedOperation : 1;
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unsigned : 14;
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} Cause;
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};
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#pragma warning(pop)
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// CPO registers by name
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class CP0registers
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{
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protected:
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CP0registers(uint64_t * _CP0);
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public:
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uint64_t & INDEX_REGISTER;
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uint64_t & RANDOM_REGISTER;
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uint64_t & ENTRYLO0_REGISTER;
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uint64_t & ENTRYLO1_REGISTER;
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COP0Context & CONTEXT_REGISTER;
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uint64_t & PAGE_MASK_REGISTER;
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uint64_t & WIRED_REGISTER;
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uint64_t & BAD_VADDR_REGISTER;
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uint64_t & COUNT_REGISTER;
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uint64_t & ENTRYHI_REGISTER;
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uint64_t & COMPARE_REGISTER;
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uint64_t & STATUS_REGISTER;
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uint64_t & CAUSE_REGISTER;
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uint64_t & EPC_REGISTER;
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uint64_t & PREVID_REGISTER;
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uint64_t & CONFIG_REGISTER;
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COP0XContext & XCONTEXT_REGISTER;
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uint64_t & TAGLO_REGISTER;
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uint64_t & TAGHI_REGISTER;
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uint64_t & ERROREPC_REGISTER;
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uint64_t & FAKE_CAUSE_REGISTER;
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private:
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CP0registers();
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CP0registers(const CP0registers &);
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CP0registers & operator=(const CP0registers &);
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};
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// CPO register flags
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enum
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{
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// Status register
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STATUS_IE = 0x00000001,
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STATUS_EXL = 0x00000002,
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STATUS_ERL = 0x00000004,
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STATUS_IP0 = 0x00000100,
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STATUS_IP1 = 0x00000200,
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STATUS_IP2 = 0x00000400,
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STATUS_IP3 = 0x00000800,
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STATUS_IP4 = 0x00001000,
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STATUS_IP5 = 0x00002000,
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STATUS_IP6 = 0x00004000,
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STATUS_IP7 = 0x00008000,
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STATUS_BEV = 0x00400000,
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STATUS_FR = 0x04000000,
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STATUS_CU0 = 0x10000000,
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STATUS_CU1 = 0x20000000,
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STATUS_CU2 = 0x40000000,
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STATUS_CU3 = 0x80000000,
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// Cause flags
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CAUSE_EXC_CODE = 0xFF,
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CAUSE_IP0 = 0x100,
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CAUSE_IP1 = 0x200,
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CAUSE_IP2 = 0x400,
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CAUSE_IP3 = 0x800,
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CAUSE_IP4 = 0x1000,
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CAUSE_IP5 = 0x2000,
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CAUSE_IP6 = 0x4000,
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CAUSE_IP7 = 0x8000,
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CAUSE_BD = 0x80000000,
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// Cause exception ID's
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EXC_INT = 0, // Interrupt
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EXC_MOD = 4, // TLB mod
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EXC_RMISS = 8, // Read TLB miss
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EXC_WMISS = 12, // Write TLB miss
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EXC_RADE = 16, // Read address error
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EXC_WADE = 20, // Write address error
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EXC_IBE = 24, // Instruction bus error
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EXC_DBE = 28, // Data bus error
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EXC_SYSCALL = 32, // Syscall
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EXC_BREAK = 36, // Breakpoint
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EXC_II = 40, // Illegal instruction
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EXC_CPU = 44, // Co-processor unusable
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EXC_OV = 48, // Overflow
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EXC_TRAP = 52, // Trap exception
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EXC_VCEI = 56, // Virtual coherency on instruction fetch
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EXC_FPE = 60, // Floating point exception
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EXC_WATCH = 92, // Watchpoint reference
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EXC_VCED = 124, // Virtual coherency on data read
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};
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// Float point control status register flags
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enum
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{
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FPCSR_FS = 0x01000000, // Flush denormalization to zero
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FPCSR_C = 0x00800000, // Condition bit
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FPCSR_CE = 0x00020000, // Cause: unimplemented operation
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FPCSR_CV = 0x00010000, // Cause: invalid operation
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FPCSR_CZ = 0x00008000, // Cause: division by zero
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FPCSR_CO = 0x00004000, // Cause: overflow
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FPCSR_CU = 0x00002000, // Cause: underflow
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FPCSR_CI = 0x00001000, // Cause: inexact operation
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FPCSR_EV = 0x00000800, // Enable: invalid operation
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FPCSR_EZ = 0x00000400, // Enable: division by zero
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FPCSR_EO = 0x00000200, // Enable: overflow
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FPCSR_EU = 0x00000100, // Enable: underflow
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FPCSR_EI = 0x00000080, // Enable: inexact operation
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FPCSR_FV = 0x00000040, // Flag: invalid operation
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FPCSR_FZ = 0x00000020, // Flag: division by zero
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FPCSR_FO = 0x00000010, // Flag: overflow
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FPCSR_FU = 0x00000008, // Flag: underflow
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FPCSR_FI = 0x00000004, // Flag: inexact operation
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FPCSR_RM_MASK = 0x00000003, // Rounding mode mask
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FPCSR_RM_RN = 0x00000000, // Round to nearest
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FPCSR_RM_RZ = 0x00000001, // Round to zero
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FPCSR_RM_RP = 0x00000002, // Round to positive infinity
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FPCSR_RM_RM = 0x00000003, // Round to negative infinity
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};
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// MIPS interface flags
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enum
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{
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MI_MODE_INIT = 0x0080, // Bit 7: Initialization mode
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MI_MODE_EBUS = 0x0100, // Bit 8: EBUS test mode
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MI_MODE_RDRAM = 0x0200, // Bit 9: RDRAM register mode
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MI_CLR_INIT = 0x0080, // Bit 7: Clear initialization mode
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MI_SET_INIT = 0x0100, // Bit 8: Set initialization mode
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MI_CLR_EBUS = 0x0200, // Bit 9: Clear EBUS test
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MI_SET_EBUS = 0x0400, // Bit 10: Set EBUS test mode
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MI_CLR_DP_INTR = 0x0800, // Bit 11: Clear DP interrupt
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MI_CLR_RDRAM = 0x1000, // Bit 12: Clear RDRAM register
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MI_SET_RDRAM = 0x2000, // Bit 13: Set RDRAM register mode
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// Flags for writing to MI_INTR_MASK_REG
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MI_INTR_MASK_CLR_SP = 0x0001, // Bit 0: Clear SP mask
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MI_INTR_MASK_SET_SP = 0x0002, // Bit 1: Set SP mask
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MI_INTR_MASK_CLR_SI = 0x0004, // Bit 2: Clear SI mask
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MI_INTR_MASK_SET_SI = 0x0008, // Bit 3: Set SI mask
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MI_INTR_MASK_CLR_AI = 0x0010, // Bit 4: Clear AI mask
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MI_INTR_MASK_SET_AI = 0x0020, // Bit 5: Set AI mask
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MI_INTR_MASK_CLR_VI = 0x0040, // Bit 6: Clear VI mask
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MI_INTR_MASK_SET_VI = 0x0080, // Bit 7: Set VI mask
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MI_INTR_MASK_CLR_PI = 0x0100, // Bit 8: Clear PI mask
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MI_INTR_MASK_SET_PI = 0x0200, // Bit 9: Set PI mask
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MI_INTR_MASK_CLR_DP = 0x0400, // Bit 10: Clear DP mask
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MI_INTR_MASK_SET_DP = 0x0800, // Bit 11: Set DP mask
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// Flags for reading from MI_INTR_MASK_REG
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MI_INTR_MASK_SP = 0x01, // Bit 0: SP INTR mask
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MI_INTR_MASK_SI = 0x02, // Bit 1: SI INTR mask
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MI_INTR_MASK_AI = 0x04, // Bit 2: AI INTR mask
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MI_INTR_MASK_VI = 0x08, // Bit 3: VI INTR mask
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MI_INTR_MASK_PI = 0x10, // Bit 4: PI INTR mask
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MI_INTR_MASK_DP = 0x20, // Bit 5: DP INTR mask
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MI_INTR_SP = 0x01, // Bit 0: SP INTR
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MI_INTR_SI = 0x02, // Bit 1: SI INTR
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MI_INTR_AI = 0x04, // Bit 2: AI INTR
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MI_INTR_VI = 0x08, // Bit 3: VI INTR
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MI_INTR_PI = 0x10, // Bit 4: PI INTR
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MI_INTR_DP = 0x20, // Bit 5: DP INTR
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};
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// Signal processor interface flags
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enum
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{
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SP_CLR_HALT = 0x00001, // Bit 0: Clear halt
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SP_SET_HALT = 0x00002, // Bit 1: Set halt
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SP_CLR_BROKE = 0x00004, // Bit 2: Clear broke
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SP_CLR_INTR = 0x00008, // Bit 3: Clear INTR
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SP_SET_INTR = 0x00010, // Bit 4: Set INTR
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SP_CLR_SSTEP = 0x00020, // Bit 5: Clear SSTEP
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SP_SET_SSTEP = 0x00040, // Bit 6: Set SSTEP
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SP_CLR_INTR_BREAK = 0x00080, // Bit 7: Clear INTR on break
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SP_SET_INTR_BREAK = 0x00100, // Bit 8: Set INTR on break
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SP_CLR_SIG0 = 0x00200, // Bit 9: Clear signal 0
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SP_SET_SIG0 = 0x00400, // Bit 10: Set signal 0
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SP_CLR_SIG1 = 0x00800, // Bit 11: Clear signal 1
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SP_SET_SIG1 = 0x01000, // Bit 12: Set signal 1
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SP_CLR_SIG2 = 0x02000, // Bit 13: Clear signal 2
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SP_SET_SIG2 = 0x04000, // Bit 14: Set signal 2
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SP_CLR_SIG3 = 0x08000, // Bit 15: Clear signal 3
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SP_SET_SIG3 = 0x10000, // Bit 16: Set signal 3
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SP_CLR_SIG4 = 0x20000, // Bit 17: Clear signal 4
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SP_SET_SIG4 = 0x40000, // Bit 18: Set signal 4
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SP_CLR_SIG5 = 0x80000, // Bit 19: Clear signal 5
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SP_SET_SIG5 = 0x100000, // Bit 20: Set signal 5
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SP_CLR_SIG6 = 0x200000, // Bit 21: Clear signal 6
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SP_SET_SIG6 = 0x400000, // Bit 22: Set signal 6
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SP_CLR_SIG7 = 0x800000, // Bit 23: Clear signal 7
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SP_SET_SIG7 = 0x1000000, // Bit 24: Set signal 7
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SP_STATUS_HALT = 0x001, // Bit 0: Halt
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SP_STATUS_BROKE = 0x002, // Bit 1: Broke
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SP_STATUS_DMA_BUSY = 0x004, // Bit 2: DMA busy
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SP_STATUS_DMA_FULL = 0x008, // Bit 3: DMA full
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SP_STATUS_IO_FULL = 0x010, // Bit 4: IO full
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SP_STATUS_SSTEP = 0x020, // Bit 5: Single step
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SP_STATUS_INTR_BREAK = 0x040, // Bit 6: Interrupt on break
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SP_STATUS_SIG0 = 0x080, // Bit 7: Signal 0 set
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SP_STATUS_SIG1 = 0x100, // Bit 8: Signal 1 set
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SP_STATUS_SIG2 = 0x200, // Bit 9: Signal 2 set
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SP_STATUS_SIG3 = 0x400, // Bit 10: Signal 3 set
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SP_STATUS_SIG4 = 0x800, // Bit 11: Signal 4 set
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SP_STATUS_SIG5 = 0x1000, // Bit 12: Signal 5 set
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SP_STATUS_SIG6 = 0x2000, // Bit 13: Signal 6 set
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SP_STATUS_SIG7 = 0x4000, // Bit 14: Signal 7 set
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};
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class CRegName
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{
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public:
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static const char * GPR[32];
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static const char * GPR_Hi[32];
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static const char * GPR_Lo[32];
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static const char * Cop0[32];
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static const char * FPR[32];
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static const char * FPR_Ctrl[32];
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};
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class CSystemRegisters
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{
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protected:
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static uint32_t * _PROGRAM_COUNTER;
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static MIPS_DWORD * _GPR;
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static MIPS_DWORD * _FPR;
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static uint64_t * _CP0;
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static MIPS_DWORD * _RegHI;
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static MIPS_DWORD * _RegLO;
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static float ** _FPR_S;
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static double ** _FPR_D;
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static uint32_t * _FPCR;
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static uint32_t * _LLBit;
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static int32_t * _RoundingModel;
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};
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class CN64System;
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class CSystemEvents;
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class CRegisters :
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public CLogging,
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private CDebugSettings,
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private CGameSettings,
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protected CSystemRegisters,
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public CP0registers,
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public RDRAMRegistersReg,
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public MIPSInterfaceReg,
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public VideoInterfaceReg,
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public AudioInterfaceReg,
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public PeripheralInterfaceReg,
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public RDRAMInterfaceReg,
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public SPRegistersReg,
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public DisplayControlReg,
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public SerialInterfaceReg,
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public DiskInterfaceReg
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{
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public:
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enum COP0Reg : uint32_t
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{
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COP0Reg_Index = 0,
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COP0Reg_Random = 1,
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COP0Reg_EntryLo0 = 2,
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COP0Reg_EntryLo1 = 3,
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COP0Reg_Context = 4,
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COP0Reg_PageMask = 5,
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COP0Reg_Wired = 6,
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COP0Reg_7 = 7,
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COP0Reg_BadVAddr = 8,
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COP0Reg_Count = 9,
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COP0Reg_EntryHi = 10,
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COP0Reg_Compare = 11,
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COP0Reg_Status = 12,
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COP0Reg_Cause = 13,
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COP0Reg_EPC = 14,
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COP0Reg_PRId = 15,
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COP0Reg_Config = 16,
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COP0Reg_LLAddr = 17,
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COP0Reg_WatchLo = 18,
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COP0Reg_WatchHi = 19,
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COP0Reg_XContext = 20,
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COP0Reg_21 = 21,
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COP0Reg_22 = 22,
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COP0Reg_23 = 23,
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COP0Reg_24 = 24,
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COP0Reg_25 = 25,
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COP0Reg_ParityError = 26,
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COP0Reg_CacheErr = 27,
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COP0Reg_TagLo = 28,
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COP0Reg_TagHi = 29,
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COP0Reg_ErrEPC = 30,
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COP0Reg_31 = 31,
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};
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CRegisters(CN64System * System, CSystemEvents * SystemEvents);
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void CheckInterrupts();
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void DoAddressError(bool DelaySlot, uint64_t BadVaddr, bool FromRead);
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void DoBreakException(bool DelaySlot);
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void DoFloatingPointException(bool DelaySlot);
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void DoTrapException(bool DelaySlot);
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void DoCopUnusableException(bool DelaySlot, int32_t Coprocessor);
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bool DoIntrException(bool DelaySlot);
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void DoIllegalInstructionException(bool DelaySlot);
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void DoOverflowException(bool DelaySlot);
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void DoTLBReadMiss(bool DelaySlot, uint64_t BadVaddr);
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void DoTLBWriteMiss(bool DelaySlot, uint64_t BadVaddr);
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void DoSysCallException(bool DelaySlot);
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void FixFpuLocations();
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void Reset();
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void SetAsCurrentSystem();
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uint64_t Cop0_MF(COP0Reg Reg);
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void Cop0_MT(COP0Reg Reg, uint64_t Value);
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void Cop1_CT(uint32_t Reg, uint32_t Value);
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// General registers
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uint32_t m_PROGRAM_COUNTER;
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MIPS_DWORD m_GPR[32];
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uint64_t m_CP0[33];
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uint64_t m_CP0Latch;
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MIPS_DWORD m_HI;
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MIPS_DWORD m_LO;
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uint32_t m_LLBit;
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// Floating point registers/information
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uint32_t m_FPCR[32];
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int32_t m_RoundingModel;
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MIPS_DWORD m_FPR[32];
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float * m_FPR_S[32];
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double * m_FPR_D[32];
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// Memory-mapped N64 registers
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uint32_t m_RDRAM_Registers[10];
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uint32_t m_SigProcessor_Interface[10];
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uint32_t m_Display_ControlReg[10];
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uint32_t m_Mips_Interface[4];
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uint32_t m_Video_Interface[14];
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uint32_t m_Audio_Interface[6];
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uint32_t m_Peripheral_Interface[13];
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uint32_t m_RDRAM_Interface[8];
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uint32_t m_SerialInterface[4];
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uint32_t m_DiskInterface[22];
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uint32_t m_AudioIntrReg;
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uint32_t m_GfxIntrReg;
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uint32_t m_RspIntrReg;
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private:
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CRegisters();
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CRegisters(const CRegisters &);
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CRegisters & operator=(const CRegisters &);
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bool m_FirstInterupt;
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CN64System * m_System;
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CSystemEvents * m_SystemEvents;
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};
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