554 lines
18 KiB
C++
554 lines
18 KiB
C++
#include "stdafx.h"
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const char * CRegName::GPR[32] = {"r0","at","v0","v1","a0","a1","a2","a3",
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"t0","t1","t2","t3","t4","t5","t6","t7",
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"s0","s1","s2","s3","s4","s5","s6","s7",
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"t8","t9","k0","k1","gp","sp","s8","ra"};
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const char *CRegName::GPR_Hi[32] = {"r0.HI","at.HI","v0.HI","v1.HI","a0.HI","a1.HI",
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"a2.HI","a3.HI","t0.HI","t1.HI","t2.HI","t3.HI",
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"t4.HI","t5.HI","t6.HI","t7.HI","s0.HI","s1.HI",
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"s2.HI","s3.HI","s4.HI","s5.HI","s6.HI","s7.HI",
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"t8.HI","t9.HI","k0.HI","k1.HI","gp.HI","sp.HI",
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"s8.HI","ra.HI"};
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const char *CRegName::GPR_Lo[32] = {"r0.LO","at.LO","v0.LO","v1.LO","a0.LO","a1.LO",
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"a2.LO","a3.LO","t0.LO","t1.LO","t2.LO","t3.LO",
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"t4.LO","t5.LO","t6.LO","t7.LO","s0.LO","s1.LO",
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"s2.LO","s3.LO","s4.LO","s5.LO","s6.LO","s7.LO",
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"t8.LO","t9.LO","k0.LO","k1.LO","gp.LO","sp.LO",
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"s8.LO","ra.LO"};
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const char * CRegName::Cop0[32] = {"Index","Random","EntryLo0","EntryLo1","Context","PageMask","Wired","",
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"BadVAddr","Count","EntryHi","Compare","Status","Cause","EPC","PRId",
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"Config","LLAddr","WatchLo","WatchHi","XContext","","","",
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"","","ECC","CacheErr","TagLo","TagHi","ErrEPC",""};
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const char * CRegName::FPR[32] = {"f0","f1","f2","f3","f4","f5","f6","f7",
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"f8","f9","f10","f11","f12","f13","f14","f15",
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"f16","f17","f18","f19","f20","f21","f22","f23",
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"f24","f25","f26","f27","f28","f29","f30","f31"};
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const char * CRegName::FPR_Ctrl[32] = {"Revision","Unknown","Unknown","Unknown","Unknown",
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"Unknown","Unknown","Unknown","Unknown","Unknown","Unknown",
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"Unknown","Unknown","Unknown","Unknown","Unknown","Unknown",
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"Unknown","Unknown","Unknown","Unknown","Unknown","Unknown",
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"Unknown","Unknown","Unknown","Unknown","Unknown","Unknown",
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"Unknown","Unknown","FCSR"};
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CP0registers::CP0registers(DWORD * _CP0) :
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INDEX_REGISTER(_CP0[0]),
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RANDOM_REGISTER(_CP0[1]),
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ENTRYLO0_REGISTER(_CP0[2]),
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ENTRYLO1_REGISTER(_CP0[3]),
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CONTEXT_REGISTER(_CP0[4]),
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PAGE_MASK_REGISTER(_CP0[5]),
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WIRED_REGISTER(_CP0[6]),
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BAD_VADDR_REGISTER(_CP0[8]),
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COUNT_REGISTER(_CP0[9]),
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ENTRYHI_REGISTER(_CP0[10]),
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COMPARE_REGISTER(_CP0[11]),
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STATUS_REGISTER(_CP0[12]),
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CAUSE_REGISTER(_CP0[13]),
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EPC_REGISTER(_CP0[14]),
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CONFIG_REGISTER(_CP0[16]),
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TAGLO_REGISTER(_CP0[28]),
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TAGHI_REGISTER(_CP0[29]),
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ERROREPC_REGISTER(_CP0[30]),
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FAKE_CAUSE_REGISTER(_CP0[32])
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{
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}
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Rdram_InterfaceReg::Rdram_InterfaceReg(DWORD * _RdramInterface) :
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RDRAM_CONFIG_REG(_RdramInterface[0]),
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RDRAM_DEVICE_TYPE_REG(_RdramInterface[0]),
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RDRAM_DEVICE_ID_REG(_RdramInterface[1]),
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RDRAM_DELAY_REG(_RdramInterface[2]),
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RDRAM_MODE_REG(_RdramInterface[3]),
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RDRAM_REF_INTERVAL_REG(_RdramInterface[4]),
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RDRAM_REF_ROW_REG(_RdramInterface[5]),
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RDRAM_RAS_INTERVAL_REG(_RdramInterface[6]),
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RDRAM_MIN_INTERVAL_REG(_RdramInterface[7]),
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RDRAM_ADDR_SELECT_REG(_RdramInterface[8]),
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RDRAM_DEVICE_MANUF_REG(_RdramInterface[9])
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{
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}
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Mips_InterfaceReg::Mips_InterfaceReg(DWORD * _MipsInterface) :
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MI_INIT_MODE_REG(_MipsInterface[0]),
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MI_MODE_REG(_MipsInterface[0]),
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MI_VERSION_REG(_MipsInterface[1]),
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MI_NOOP_REG(_MipsInterface[1]),
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MI_INTR_REG(_MipsInterface[2]),
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MI_INTR_MASK_REG(_MipsInterface[3])
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{
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}
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Video_InterfaceReg::Video_InterfaceReg(DWORD * _VideoInterface) :
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VI_STATUS_REG(_VideoInterface[0]),
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VI_CONTROL_REG(_VideoInterface[0]),
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VI_ORIGIN_REG(_VideoInterface[1]),
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VI_DRAM_ADDR_REG(_VideoInterface[1]),
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VI_WIDTH_REG(_VideoInterface[2]),
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VI_H_WIDTH_REG(_VideoInterface[2]),
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VI_INTR_REG(_VideoInterface[3]),
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VI_V_INTR_REG(_VideoInterface[3]),
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VI_CURRENT_REG(_VideoInterface[4]),
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VI_V_CURRENT_LINE_REG(_VideoInterface[4]),
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VI_BURST_REG(_VideoInterface[5]),
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VI_TIMING_REG(_VideoInterface[5]),
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VI_V_SYNC_REG(_VideoInterface[6]),
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VI_H_SYNC_REG(_VideoInterface[7]),
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VI_LEAP_REG(_VideoInterface[8]),
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VI_H_SYNC_LEAP_REG(_VideoInterface[8]),
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VI_H_START_REG(_VideoInterface[9]),
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VI_H_VIDEO_REG(_VideoInterface[9]),
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VI_V_START_REG(_VideoInterface[10]),
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VI_V_VIDEO_REG(_VideoInterface[10]),
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VI_V_BURST_REG(_VideoInterface[11]),
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VI_X_SCALE_REG(_VideoInterface[12]),
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VI_Y_SCALE_REG(_VideoInterface[13])
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{
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}
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AudioInterfaceReg::AudioInterfaceReg(DWORD * _AudioInterface) :
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AI_DRAM_ADDR_REG(_AudioInterface[0]),
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AI_LEN_REG(_AudioInterface[1]),
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AI_CONTROL_REG(_AudioInterface[2]),
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AI_STATUS_REG(_AudioInterface[3]),
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AI_DACRATE_REG(_AudioInterface[4]),
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AI_BITRATE_REG(_AudioInterface[5])
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{
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}
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PeripheralInterfaceReg::PeripheralInterfaceReg(DWORD * PeripheralInterface) :
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PI_DRAM_ADDR_REG(PeripheralInterface[0]),
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PI_CART_ADDR_REG(PeripheralInterface[1]),
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PI_RD_LEN_REG(PeripheralInterface[2]),
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PI_WR_LEN_REG(PeripheralInterface[3]),
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PI_STATUS_REG(PeripheralInterface[4]),
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PI_BSD_DOM1_LAT_REG(PeripheralInterface[5]),
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PI_DOMAIN1_REG(PeripheralInterface[5]),
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PI_BSD_DOM1_PWD_REG(PeripheralInterface[6]),
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PI_BSD_DOM1_PGS_REG(PeripheralInterface[7]),
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PI_BSD_DOM1_RLS_REG(PeripheralInterface[8]),
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PI_BSD_DOM2_LAT_REG(PeripheralInterface[9]),
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PI_DOMAIN2_REG(PeripheralInterface[9]),
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PI_BSD_DOM2_PWD_REG(PeripheralInterface[10]),
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PI_BSD_DOM2_PGS_REG(PeripheralInterface[11]),
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PI_BSD_DOM2_RLS_REG(PeripheralInterface[12])
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{
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}
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RDRAMInt_InterfaceReg::RDRAMInt_InterfaceReg(DWORD * RdramInterface) :
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RI_MODE_REG(RdramInterface[0]),
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RI_CONFIG_REG(RdramInterface[1]),
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RI_CURRENT_LOAD_REG(RdramInterface[2]),
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RI_SELECT_REG(RdramInterface[3]),
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RI_COUNT_REG(RdramInterface[4]),
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RI_REFRESH_REG(RdramInterface[4]),
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RI_LATENCY_REG(RdramInterface[5]),
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RI_RERROR_REG(RdramInterface[6]),
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RI_WERROR_REG(RdramInterface[7])
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{
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}
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DisplayControlReg::DisplayControlReg(DWORD * _DisplayProcessor) :
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DPC_START_REG(_DisplayProcessor[0]),
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DPC_END_REG(_DisplayProcessor[1]),
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DPC_CURRENT_REG(_DisplayProcessor[2]),
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DPC_STATUS_REG(_DisplayProcessor[3]),
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DPC_CLOCK_REG(_DisplayProcessor[4]),
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DPC_BUFBUSY_REG(_DisplayProcessor[5]),
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DPC_PIPEBUSY_REG(_DisplayProcessor[6]),
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DPC_TMEM_REG(_DisplayProcessor[7])
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{
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}
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SigProcessor_InterfaceReg::SigProcessor_InterfaceReg(DWORD * _SignalProcessorInterface) :
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SP_MEM_ADDR_REG(_SignalProcessorInterface[0]),
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SP_DRAM_ADDR_REG(_SignalProcessorInterface[1]),
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SP_RD_LEN_REG(_SignalProcessorInterface[2]),
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SP_WR_LEN_REG(_SignalProcessorInterface[3]),
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SP_STATUS_REG(_SignalProcessorInterface[4]),
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SP_DMA_FULL_REG(_SignalProcessorInterface[5]),
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SP_DMA_BUSY_REG(_SignalProcessorInterface[6]),
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SP_SEMAPHORE_REG(_SignalProcessorInterface[7]),
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SP_PC_REG(_SignalProcessorInterface[8]),
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SP_IBIST_REG(_SignalProcessorInterface[9])
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{
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}
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Serial_InterfaceReg::Serial_InterfaceReg(DWORD * SerialInterface) :
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SI_DRAM_ADDR_REG(SerialInterface[0]),
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SI_PIF_ADDR_RD64B_REG(SerialInterface[1]),
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SI_PIF_ADDR_WR64B_REG(SerialInterface[2]),
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SI_STATUS_REG(SerialInterface[3])
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{
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}
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CRegisters::CRegisters (void) :
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CP0registers(m_CP0),
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Rdram_InterfaceReg(m_RDRAM_Registers),
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Mips_InterfaceReg(m_Mips_Interface),
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Video_InterfaceReg(m_Video_Interface),
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AudioInterfaceReg(m_Audio_Interface),
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PeripheralInterfaceReg(m_Peripheral_Interface),
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RDRAMInt_InterfaceReg(m_RDRAM_Interface),
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SigProcessor_InterfaceReg(m_SigProcessor_Interface),
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DisplayControlReg(m_Display_ControlReg),
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Serial_InterfaceReg(m_SerialInterface)
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{
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memset(m_GPR,0,sizeof(m_GPR));
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memset(m_CP0,0,sizeof(m_CP0));
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memset(m_FPR,0,sizeof(m_FPR));
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memset(m_FPCR,0,sizeof(m_FPCR));
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m_HI.DW = 0;
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m_LO.DW = 0;
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//LLBit = 0;
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//LLAddr = 0;
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//Reset System Registers
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memset(m_RDRAM_Interface,0,sizeof(m_RDRAM_Interface));
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memset(m_RDRAM_Registers,0,sizeof(m_RDRAM_Registers));
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memset(m_Mips_Interface,0,sizeof(m_Mips_Interface));
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memset(m_Video_Interface,0,sizeof(m_Video_Interface));
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memset(m_Display_ControlReg,0,sizeof(m_Display_ControlReg));
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memset(m_Audio_Interface,0,sizeof(m_Audio_Interface));
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memset(m_SigProcessor_Interface,0,sizeof(m_SigProcessor_Interface));
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memset(m_Peripheral_Interface,0,sizeof(m_Peripheral_Interface));
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memset(m_SerialInterface,0,sizeof(m_SerialInterface));
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FixFpuLocations();
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}
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void CRegisters::FixFpuLocations ( void ) {
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if ((STATUS_REGISTER & STATUS_FR) == 0) {
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for (int count = 0; count < 32; count ++) {
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m_FPR_S[count] = &m_FPR[count >> 1].F[count & 1];
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m_FPR_D[count] = &m_FPR[count >> 1].D;
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}
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} else {
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for (int count = 0; count < 32; count ++) {
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m_FPR_S[count] = &m_FPR[count].F[1];
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m_FPR_D[count] = &m_FPR[count].D;
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}
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}
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}
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#ifdef toremove
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void CRegisters::InitalizeR4300iRegisters (CMipsMemory & MMU, bool PostPif, int Country, CICChip CIC_Chip)
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{
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//Reset General Registers
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memset(GPR,0,sizeof(GPR));
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memset(CP0,0,sizeof(CP0));
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memset(FPR,0,sizeof(FPR));
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memset(FPCR,0,sizeof(FPCR));
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HI.DW = 0;
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LO.DW = 0;
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LLBit = 0;
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LLAddr = 0;
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//Reset System Registers
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memset(RDRAM_Interface,0,sizeof(RDRAM_Interface));
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memset(RDRAM_Registers,0,sizeof(RDRAM_Registers));
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memset(Mips_Interface,0,sizeof(Mips_Interface));
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memset(Video_Interface,0,sizeof(Video_Interface));
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memset(Display_ControlReg,0,sizeof(Display_ControlReg));
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memset(Audio_Interface,0,sizeof(Audio_Interface));
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memset(SigProcessor_Interface,0,sizeof(SigProcessor_Interface));
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memset(Peripheral_Interface,0,sizeof(Peripheral_Interface));
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memset(SerialInterface,0,sizeof(SerialInterface));
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//COP0 Registers
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RANDOM_REGISTER = 0x1F;
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COUNT_REGISTER = 0x5000;
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MI_VERSION_REG = 0x02020102;
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SP_STATUS_REG = 0x00000001;
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CAUSE_REGISTER = 0x0000005C;
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CONTEXT_REGISTER = 0x007FFFF0;
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EPC_REGISTER = 0xFFFFFFFF;
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BAD_VADDR_REGISTER = 0xFFFFFFFF;
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ERROREPC_REGISTER = 0xFFFFFFFF;
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CONFIG_REGISTER = 0x0006E463;
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STATUS_REGISTER = 0x34000000;
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//REVISION_REGISTER = 0x00000511;
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ChangeTimerFixed(CompareTimer,COMPARE_REGISTER - COUNT_REGISTER);
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AudioIntrReg = 0;
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if (PostPif) {
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PROGRAM_COUNTER = 0xA4000040;
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GPR[0].DW=0x0000000000000000;
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GPR[6].DW=0xFFFFFFFFA4001F0C;
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GPR[7].DW=0xFFFFFFFFA4001F08;
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GPR[8].DW=0x00000000000000C0;
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GPR[9].DW=0x0000000000000000;
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GPR[10].DW=0x0000000000000040;
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GPR[11].DW=0xFFFFFFFFA4000040;
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GPR[16].DW=0x0000000000000000;
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GPR[17].DW=0x0000000000000000;
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GPR[18].DW=0x0000000000000000;
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GPR[19].DW=0x0000000000000000;
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GPR[21].DW=0x0000000000000000;
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GPR[26].DW=0x0000000000000000;
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GPR[27].DW=0x0000000000000000;
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GPR[28].DW=0x0000000000000000;
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GPR[29].DW=0xFFFFFFFFA4001FF0;
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GPR[30].DW=0x0000000000000000;
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switch (Country) {
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case Germany: case french: case Italian:
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case Europe: case Spanish: case Australia:
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case X_PAL: case Y_PAL:
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switch (CIC_Chip) {
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case CIC_NUS_6102:
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GPR[5].DW=0xFFFFFFFFC0F1D859;
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GPR[14].DW=0x000000002DE108EA;
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GPR[24].DW=0x0000000000000000;
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break;
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case CIC_NUS_6103:
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GPR[5].DW=0xFFFFFFFFD4646273;
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GPR[14].DW=0x000000001AF99984;
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GPR[24].DW=0x0000000000000000;
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break;
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case CIC_NUS_6105:
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MMU.SW_VAddr(0xA4001004,0xBDA807FC);
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GPR[5].DW=0xFFFFFFFFDECAAAD1;
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GPR[14].DW=0x000000000CF85C13;
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GPR[24].DW=0x0000000000000002;
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break;
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case CIC_NUS_6106:
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GPR[5].DW=0xFFFFFFFFB04DC903;
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GPR[14].DW=0x000000001AF99984;
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GPR[24].DW=0x0000000000000002;
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break;
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}
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GPR[20].DW=0x0000000000000000;
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GPR[23].DW=0x0000000000000006;
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GPR[31].DW=0xFFFFFFFFA4001554;
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break;
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case NTSC_BETA: case X_NTSC: case USA: case Japan:
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default:
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switch (CIC_Chip) {
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case CIC_NUS_6102:
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GPR[5].DW=0xFFFFFFFFC95973D5;
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GPR[14].DW=0x000000002449A366;
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break;
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case CIC_NUS_6103:
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GPR[5].DW=0xFFFFFFFF95315A28;
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GPR[14].DW=0x000000005BACA1DF;
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break;
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case CIC_NUS_6105:
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MMU.SW_VAddr(0xA4001004,0x8DA807FC);
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GPR[5].DW=0x000000005493FB9A;
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GPR[14].DW=0xFFFFFFFFC2C20384;
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case CIC_NUS_6106:
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GPR[5].DW=0xFFFFFFFFE067221F;
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GPR[14].DW=0x000000005CD2B70F;
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break;
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}
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GPR[20].DW=0x0000000000000001;
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GPR[23].DW=0x0000000000000000;
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GPR[24].DW=0x0000000000000003;
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GPR[31].DW=0xFFFFFFFFA4001550;
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}
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switch (CIC_Chip) {
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case CIC_NUS_6101:
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GPR[22].DW=0x000000000000003F;
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break;
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case CIC_NUS_6102:
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GPR[1].DW=0x0000000000000001;
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GPR[2].DW=0x000000000EBDA536;
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GPR[3].DW=0x000000000EBDA536;
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GPR[4].DW=0x000000000000A536;
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GPR[12].DW=0xFFFFFFFFED10D0B3;
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GPR[13].DW=0x000000001402A4CC;
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GPR[15].DW=0x000000003103E121;
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GPR[22].DW=0x000000000000003F;
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GPR[25].DW=0xFFFFFFFF9DEBB54F;
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break;
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case CIC_NUS_6103:
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GPR[1].DW=0x0000000000000001;
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GPR[2].DW=0x0000000049A5EE96;
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GPR[3].DW=0x0000000049A5EE96;
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GPR[4].DW=0x000000000000EE96;
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GPR[12].DW=0xFFFFFFFFCE9DFBF7;
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GPR[13].DW=0xFFFFFFFFCE9DFBF7;
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GPR[15].DW=0x0000000018B63D28;
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GPR[22].DW=0x0000000000000078;
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GPR[25].DW=0xFFFFFFFF825B21C9;
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break;
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case CIC_NUS_6105:
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MMU.SW_VAddr(0xA4001000,0x3C0DBFC0);
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MMU.SW_VAddr(0xA4001008,0x25AD07C0);
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MMU.SW_VAddr(0xA400100C,0x31080080);
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MMU.SW_VAddr(0xA4001010,0x5500FFFC);
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MMU.SW_VAddr(0xA4001014,0x3C0DBFC0);
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MMU.SW_VAddr(0xA4001018,0x8DA80024);
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MMU.SW_VAddr(0xA400101C,0x3C0BB000);
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GPR[1].DW=0x0000000000000000;
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GPR[2].DW=0xFFFFFFFFF58B0FBF;
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GPR[3].DW=0xFFFFFFFFF58B0FBF;
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GPR[4].DW=0x0000000000000FBF;
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GPR[12].DW=0xFFFFFFFF9651F81E;
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GPR[13].DW=0x000000002D42AAC5;
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GPR[15].DW=0x0000000056584D60;
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GPR[22].DW=0x0000000000000091;
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GPR[25].DW=0xFFFFFFFFCDCE565F;
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break;
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case CIC_NUS_6106:
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|
GPR[1].DW=0x0000000000000000;
|
|
GPR[2].DW=0xFFFFFFFFA95930A4;
|
|
GPR[3].DW=0xFFFFFFFFA95930A4;
|
|
GPR[4].DW=0x00000000000030A4;
|
|
GPR[12].DW=0xFFFFFFFFBCB59510;
|
|
GPR[13].DW=0xFFFFFFFFBCB59510;
|
|
GPR[15].DW=0x000000007A3C07F4;
|
|
GPR[22].DW=0x0000000000000085;
|
|
GPR[25].DW=0x00000000465E3F72;
|
|
break;
|
|
}
|
|
} else {
|
|
PROGRAM_COUNTER = 0xBFC00000;
|
|
/* PIF_Ram[36] = 0x00; PIF_Ram[39] = 0x3F; //common pif ram start values
|
|
|
|
switch (CIC_Chip) {
|
|
case CIC_NUS_6101: PIF_Ram[37] = 0x06; PIF_Ram[38] = 0x3F; break;
|
|
case CIC_NUS_6102: PIF_Ram[37] = 0x02; PIF_Ram[38] = 0x3F; break;
|
|
case CIC_NUS_6103: PIF_Ram[37] = 0x02; PIF_Ram[38] = 0x78; break;
|
|
case CIC_NUS_6105: PIF_Ram[37] = 0x02; PIF_Ram[38] = 0x91; break;
|
|
case CIC_NUS_6106: PIF_Ram[37] = 0x02; PIF_Ram[38] = 0x85; break;
|
|
}*/
|
|
}
|
|
FixFpuLocations();
|
|
}
|
|
#endif
|
|
|
|
#ifdef tofix
|
|
void CRegisters::CheckInterrupts ( void ) {
|
|
if ((MI_INTR_MASK_REG & MI_INTR_REG) != 0) {
|
|
FAKE_CAUSE_REGISTER |= CAUSE_IP2;
|
|
} else {
|
|
FAKE_CAUSE_REGISTER &= ~CAUSE_IP2;
|
|
}
|
|
|
|
if (( STATUS_REGISTER & STATUS_IE ) == 0 ) { return; }
|
|
if (( STATUS_REGISTER & STATUS_EXL ) != 0 ) { return; }
|
|
if (( STATUS_REGISTER & STATUS_ERL ) != 0 ) { return; }
|
|
|
|
if (( STATUS_REGISTER & FAKE_CAUSE_REGISTER & 0xFF00) != 0) {
|
|
_N64System->ExternalEvent(ExecuteInterrupt);
|
|
}
|
|
}
|
|
|
|
#ifdef toremove
|
|
|
|
void CRegisters::ExecuteInterruptException ( bool DelaySlot ) {
|
|
if (( STATUS_REGISTER & STATUS_IE ) == 0 ) { return; }
|
|
if (( STATUS_REGISTER & STATUS_EXL ) != 0 ) { return; }
|
|
if (( STATUS_REGISTER & STATUS_ERL ) != 0 ) { return; }
|
|
// TlbLog.Log("%08X: ExecuteInterruptException %X", PROGRAM_COUNTER,FAKE_CAUSE_REGISTER);
|
|
CAUSE_REGISTER = FAKE_CAUSE_REGISTER;
|
|
CAUSE_REGISTER |= EXC_INT;
|
|
if (DelaySlot) {
|
|
CAUSE_REGISTER |= CAUSE_BD;
|
|
EPC_REGISTER = PROGRAM_COUNTER - 4;
|
|
} else {
|
|
EPC_REGISTER = PROGRAM_COUNTER;
|
|
}
|
|
STATUS_REGISTER |= STATUS_EXL;
|
|
PROGRAM_COUNTER = 0x80000180;
|
|
}
|
|
|
|
void CRegisters::ExecuteCopUnusableException ( bool DelaySlot, int Coprocessor ) {
|
|
// TlbLog.Log("%08X: ExecuteCopUnusableException %X", PROGRAM_COUNTER,Coprocessor);
|
|
CAUSE_REGISTER = EXC_CPU;
|
|
if (Coprocessor == 1) { CAUSE_REGISTER |= 0x10000000; }
|
|
if (DelaySlot) {
|
|
CAUSE_REGISTER |= CAUSE_BD;
|
|
EPC_REGISTER = PROGRAM_COUNTER - 4;
|
|
} else {
|
|
EPC_REGISTER = PROGRAM_COUNTER;
|
|
}
|
|
STATUS_REGISTER |= STATUS_EXL;
|
|
PROGRAM_COUNTER = 0x80000180;
|
|
}
|
|
|
|
void CRegisters::ExecuteSysCallException ( bool DelaySlot) {
|
|
if (( STATUS_REGISTER & STATUS_EXL ) != 0 ) {
|
|
_Notify->DisplayError("EXL set in SysCall Exception");
|
|
}
|
|
if (( STATUS_REGISTER & STATUS_ERL ) != 0 ) {
|
|
_Notify->DisplayError("ERL set in SysCall Exception");
|
|
}
|
|
|
|
CAUSE_REGISTER = EXC_SYSCALL;
|
|
if (DelaySlot) {
|
|
CAUSE_REGISTER |= CAUSE_BD;
|
|
EPC_REGISTER = PROGRAM_COUNTER - 4;
|
|
} else {
|
|
EPC_REGISTER = PROGRAM_COUNTER;
|
|
}
|
|
STATUS_REGISTER |= STATUS_EXL;
|
|
PROGRAM_COUNTER = 0x80000180;
|
|
}
|
|
|
|
|
|
void CRegisters::ExecuteTLBMissException ( CMipsMemory * MMU, bool DelaySlot, DWORD BadVaddr ) {
|
|
//TlbLog.Log("ExecuteTLBMissException PC: %X BadVaddr: %X",PROGRAM_COUNTER,BadVaddr);
|
|
CAUSE_REGISTER = EXC_RMISS;
|
|
BAD_VADDR_REGISTER = BadVaddr;
|
|
CONTEXT_REGISTER &= 0xFF80000F;
|
|
CONTEXT_REGISTER |= (BadVaddr >> 9) & 0x007FFFF0;
|
|
ENTRYHI_REGISTER = (BadVaddr & 0xFFFFE000);
|
|
if ((STATUS_REGISTER & STATUS_EXL) == 0) {
|
|
if (DelaySlot) {
|
|
CAUSE_REGISTER |= CAUSE_BD;
|
|
EPC_REGISTER = PROGRAM_COUNTER - 4;
|
|
} else {
|
|
EPC_REGISTER = PROGRAM_COUNTER;
|
|
}
|
|
if (MMU->TLB_AddressDefined(BadVaddr)) {
|
|
PROGRAM_COUNTER = 0x80000180;
|
|
} else {
|
|
PROGRAM_COUNTER = 0x80000000;
|
|
}
|
|
STATUS_REGISTER |= STATUS_EXL;
|
|
} else {
|
|
_Notify->BreakPoint(__FILE__,__LINE__);
|
|
PROGRAM_COUNTER = 0x80000180;
|
|
}
|
|
}
|
|
|
|
void CRegisters::UpdateRegisterAfterOpcode (float StepIncrease) {
|
|
COUNT_REGISTER += (DWORD)StepIncrease;
|
|
// RANDOM_REGISTER -= 1;
|
|
// if ((int)RANDOM_REGISTER < (int)WIRED_REGISTER) { RANDOM_REGISTER = 31; }
|
|
UpdateTimer(StepIncrease);
|
|
}
|
|
|
|
void CRegisters::SetCurrentRoundingModel (ROUNDING_MODE RoundMode) {
|
|
switch (RoundMode) {
|
|
case ROUND_NEAR: _controlfp(_RC_NEAR,_MCW_RC); break;
|
|
case ROUND_CHOP: _controlfp(_RC_CHOP,_MCW_RC); break;
|
|
case ROUND_UP: _controlfp(_RC_UP, _MCW_RC); break;
|
|
case ROUND_DOWN: _controlfp(_RC_DOWN,_MCW_RC); break;
|
|
}
|
|
|
|
}
|
|
|
|
void CRegisters::ChangeDefaultRoundingModel (int Reg) {
|
|
switch((FPCR[Reg] & 3)) {
|
|
case 0: _RoundingModel = ROUND_NEAR; break;
|
|
case 1: _RoundingModel = ROUND_CHOP; break;
|
|
case 2: _RoundingModel = ROUND_UP; break;
|
|
case 3: _RoundingModel = ROUND_DOWN; break;
|
|
}
|
|
}
|
|
#endif
|
|
#endif |