525 lines
16 KiB
C++
525 lines
16 KiB
C++
//CPO registers by name
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class CP0registers
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{
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CP0registers (void);
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protected:
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CP0registers (DWORD * _CP0);
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public:
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DWORD & INDEX_REGISTER;
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DWORD & RANDOM_REGISTER;
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DWORD & ENTRYLO0_REGISTER;
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DWORD & ENTRYLO1_REGISTER;
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DWORD & CONTEXT_REGISTER;
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DWORD & PAGE_MASK_REGISTER;
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DWORD & WIRED_REGISTER;
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DWORD & BAD_VADDR_REGISTER;
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DWORD & COUNT_REGISTER;
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DWORD & ENTRYHI_REGISTER;
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DWORD & COMPARE_REGISTER;
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DWORD & STATUS_REGISTER;
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DWORD & CAUSE_REGISTER;
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DWORD & EPC_REGISTER;
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DWORD & CONFIG_REGISTER;
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DWORD & TAGLO_REGISTER;
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DWORD & TAGHI_REGISTER;
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DWORD & ERROREPC_REGISTER;
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DWORD & FAKE_CAUSE_REGISTER;
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};
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//CPO register flags
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enum {
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//Status Register
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STATUS_IE = 0x00000001, STATUS_EXL = 0x00000002, STATUS_ERL = 0x00000004,
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STATUS_IP0 = 0x00000100, STATUS_IP1 = 0x00000200, STATUS_IP2 = 0x00000400,
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STATUS_IP3 = 0x00000800, STATUS_IP4 = 0x00001000, STATUS_IP5 = 0x00002000,
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STATUS_IP6 = 0x00004000, STATUS_IP7 = 0x00008000, STATUS_BEV = 0x00400000,
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STATUS_FR = 0x04000000, STATUS_CU0 = 0x10000000, STATUS_CU1 = 0x20000000,
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//Cause Flags
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CAUSE_EXC_CODE = 0xFF,
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CAUSE_IP0 = 0x100,
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CAUSE_IP1 = 0x200,
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CAUSE_IP2 = 0x400,
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CAUSE_IP3 = 0x800,
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CAUSE_IP4 = 0x1000,
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CAUSE_IP5 = 0x2000,
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CAUSE_IP6 = 0x4000,
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CAUSE_IP7 = 0x8000,
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CAUSE_BD = 0x80000000,
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//Cause exception ID's
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EXC_INT = 0, /* interrupt */
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EXC_MOD = 4, /* TLB mod */
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EXC_RMISS = 8, /* Read TLB Miss */
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EXC_WMISS = 12, /* Write TLB Miss */
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EXC_RADE = 16, /* Read Address Error */
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EXC_WADE = 20, /* Write Address Error */
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EXC_IBE = 24, /* Instruction Bus Error */
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EXC_DBE = 28, /* Data Bus Error */
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EXC_SYSCALL = 32, /* SYSCALL */
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EXC_BREAK = 36, /* BREAKpoint */
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EXC_II = 40, /* Illegal Instruction */
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EXC_CPU = 44, /* CoProcessor Unusable */
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EXC_OV = 48, /* OVerflow */
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EXC_TRAP = 52, /* Trap exception */
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EXC_VCEI = 56, /* Virt. Coherency on Inst. fetch */
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EXC_FPE = 60, /* Floating Point Exception */
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EXC_WATCH = 92, /* Watchpoint reference */
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EXC_VCED = 124,/* Virt. Coherency on data read */
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};
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//Float point control status register flags
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enum {
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FPCSR_FS = 0x01000000, /* flush denorm to zero */
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FPCSR_C = 0x00800000, /* condition bit */
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FPCSR_CE = 0x00020000, /* cause: unimplemented operation */
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FPCSR_CV = 0x00010000, /* cause: invalid operation */
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FPCSR_CZ = 0x00008000, /* cause: division by zero */
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FPCSR_CO = 0x00004000, /* cause: overflow */
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FPCSR_CU = 0x00002000, /* cause: underflow */
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FPCSR_CI = 0x00001000, /* cause: inexact operation */
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FPCSR_EV = 0x00000800, /* enable: invalid operation */
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FPCSR_EZ = 0x00000400, /* enable: division by zero */
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FPCSR_EO = 0x00000200, /* enable: overflow */
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FPCSR_EU = 0x00000100, /* enable: underflow */
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FPCSR_EI = 0x00000080, /* enable: inexact operation */
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FPCSR_FV = 0x00000040, /* flag: invalid operation */
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FPCSR_FZ = 0x00000020, /* flag: division by zero */
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FPCSR_FO = 0x00000010, /* flag: overflow */
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FPCSR_FU = 0x00000008, /* flag: underflow */
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FPCSR_FI = 0x00000004, /* flag: inexact operation */
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FPCSR_RM_MASK = 0x00000003, /* rounding mode mask */
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FPCSR_RM_RN = 0x00000000, /* round to nearest */
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FPCSR_RM_RZ = 0x00000001, /* round to zero */
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FPCSR_RM_RP = 0x00000002, /* round to positive infinity */
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FPCSR_RM_RM = 0x00000003, /* round to negative infinity */
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};
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//Rdram Registers
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class Rdram_InterfaceReg
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{
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Rdram_InterfaceReg (void);
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protected:
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Rdram_InterfaceReg (DWORD * _RdramInterface);
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public:
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DWORD & RDRAM_CONFIG_REG;
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DWORD & RDRAM_DEVICE_TYPE_REG;
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DWORD & RDRAM_DEVICE_ID_REG;
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DWORD & RDRAM_DELAY_REG;
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DWORD & RDRAM_MODE_REG;
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DWORD & RDRAM_REF_INTERVAL_REG;
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DWORD & RDRAM_REF_ROW_REG;
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DWORD & RDRAM_RAS_INTERVAL_REG;
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DWORD & RDRAM_MIN_INTERVAL_REG;
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DWORD & RDRAM_ADDR_SELECT_REG;
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DWORD & RDRAM_DEVICE_MANUF_REG;
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};
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//Mips interface registers
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class Mips_InterfaceReg
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{
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Mips_InterfaceReg ();
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protected:
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Mips_InterfaceReg (DWORD * _MipsInterface);
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public:
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DWORD & MI_INIT_MODE_REG;
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DWORD & MI_MODE_REG;
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DWORD & MI_VERSION_REG;
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DWORD & MI_NOOP_REG;
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DWORD & MI_INTR_REG;
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DWORD & MI_INTR_MASK_REG;
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};
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//Mips interface flags
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enum {
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MI_MODE_INIT = 0x0080, /* Bit 7: init mode */
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MI_MODE_EBUS = 0x0100, /* Bit 8: ebus test mode */
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MI_MODE_RDRAM = 0x0200, /* Bit 9: RDRAM reg mode */
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MI_CLR_INIT = 0x0080, /* Bit 7: clear init mode */
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MI_SET_INIT = 0x0100, /* Bit 8: set init mode */
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MI_CLR_EBUS = 0x0200, /* Bit 9: clear ebus test */
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MI_SET_EBUS = 0x0400, /* Bit 10: set ebus test mode */
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MI_CLR_DP_INTR = 0x0800, /* Bit 11: clear dp interrupt */
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MI_CLR_RDRAM = 0x1000, /* Bit 12: clear RDRAM reg */
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MI_SET_RDRAM = 0x2000, /* Bit 13: set RDRAM reg mode */
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//Flags for writing to MI_INTR_MASK_REG
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MI_INTR_MASK_CLR_SP = 0x0001, /* Bit 0: clear SP mask */
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MI_INTR_MASK_SET_SP = 0x0002, /* Bit 1: set SP mask */
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MI_INTR_MASK_CLR_SI = 0x0004, /* Bit 2: clear SI mask */
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MI_INTR_MASK_SET_SI = 0x0008, /* Bit 3: set SI mask */
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MI_INTR_MASK_CLR_AI = 0x0010, /* Bit 4: clear AI mask */
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MI_INTR_MASK_SET_AI = 0x0020, /* Bit 5: set AI mask */
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MI_INTR_MASK_CLR_VI = 0x0040, /* Bit 6: clear VI mask */
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MI_INTR_MASK_SET_VI = 0x0080, /* Bit 7: set VI mask */
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MI_INTR_MASK_CLR_PI = 0x0100, /* Bit 8: clear PI mask */
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MI_INTR_MASK_SET_PI = 0x0200, /* Bit 9: set PI mask */
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MI_INTR_MASK_CLR_DP = 0x0400, /* Bit 10: clear DP mask */
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MI_INTR_MASK_SET_DP = 0x0800, /* Bit 11: set DP mask */
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//Flags for reading from MI_INTR_MASK_REG
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MI_INTR_MASK_SP = 0x01, /* Bit 0: SP intr mask */
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MI_INTR_MASK_SI = 0x02, /* Bit 1: SI intr mask */
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MI_INTR_MASK_AI = 0x04, /* Bit 2: AI intr mask */
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MI_INTR_MASK_VI = 0x08, /* Bit 3: VI intr mask */
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MI_INTR_MASK_PI = 0x10, /* Bit 4: PI intr mask */
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MI_INTR_MASK_DP = 0x20, /* Bit 5: DP intr mask */
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MI_INTR_SP = 0x01, /* Bit 0: SP intr */
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MI_INTR_SI = 0x02, /* Bit 1: SI intr */
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MI_INTR_AI = 0x04, /* Bit 2: AI intr */
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MI_INTR_VI = 0x08, /* Bit 3: VI intr */
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MI_INTR_PI = 0x10, /* Bit 4: PI intr */
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MI_INTR_DP = 0x20, /* Bit 5: DP intr */
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};
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//Mips interface registers
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class Video_InterfaceReg
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{
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Video_InterfaceReg (void);
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protected:
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Video_InterfaceReg (DWORD * _VideoInterface);
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public:
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DWORD & VI_STATUS_REG;
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DWORD & VI_CONTROL_REG;
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DWORD & VI_ORIGIN_REG;
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DWORD & VI_DRAM_ADDR_REG;
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DWORD & VI_WIDTH_REG;
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DWORD & VI_H_WIDTH_REG;
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DWORD & VI_INTR_REG;
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DWORD & VI_V_INTR_REG;
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DWORD & VI_CURRENT_REG;
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DWORD & VI_V_CURRENT_LINE_REG;
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DWORD & VI_BURST_REG;
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DWORD & VI_TIMING_REG;
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DWORD & VI_V_SYNC_REG;
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DWORD & VI_H_SYNC_REG;
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DWORD & VI_LEAP_REG;
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DWORD & VI_H_SYNC_LEAP_REG;
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DWORD & VI_H_START_REG;
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DWORD & VI_H_VIDEO_REG;
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DWORD & VI_V_START_REG;
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DWORD & VI_V_VIDEO_REG;
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DWORD & VI_V_BURST_REG;
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DWORD & VI_X_SCALE_REG;
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DWORD & VI_Y_SCALE_REG;
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};
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//Display Processor Control Registers
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class DisplayControlReg
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{
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DisplayControlReg (void);
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protected:
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DisplayControlReg (DWORD * _DisplayProcessor);
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public:
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DWORD & DPC_START_REG;
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DWORD & DPC_END_REG;
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DWORD & DPC_CURRENT_REG;
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DWORD & DPC_STATUS_REG;
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DWORD & DPC_CLOCK_REG;
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DWORD & DPC_BUFBUSY_REG;
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DWORD & DPC_PIPEBUSY_REG;
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DWORD & DPC_TMEM_REG;
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};
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enum {
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DPC_CLR_XBUS_DMEM_DMA = 0x0001, /* Bit 0: clear xbus_dmem_dma */
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DPC_SET_XBUS_DMEM_DMA = 0x0002, /* Bit 1: set xbus_dmem_dma */
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DPC_CLR_FREEZE = 0x0004, /* Bit 2: clear freeze */
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DPC_SET_FREEZE = 0x0008, /* Bit 3: set freeze */
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DPC_CLR_FLUSH = 0x0010, /* Bit 4: clear flush */
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DPC_SET_FLUSH = 0x0020, /* Bit 5: set flush */
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DPC_CLR_TMEM_CTR = 0x0040, /* Bit 6: clear tmem ctr */
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DPC_CLR_PIPE_CTR = 0x0080, /* Bit 7: clear pipe ctr */
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DPC_CLR_CMD_CTR = 0x0100, /* Bit 8: clear cmd ctr */
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DPC_CLR_CLOCK_CTR = 0x0200, /* Bit 9: clear clock ctr */
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DPC_STATUS_XBUS_DMEM_DMA = 0x001, /* Bit 0: xbus_dmem_dma */
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DPC_STATUS_FREEZE = 0x002, /* Bit 1: freeze */
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DPC_STATUS_FLUSH = 0x004, /* Bit 2: flush */
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DPC_STATUS_START_GCLK = 0x008, /* Bit 3: start gclk */
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DPC_STATUS_TMEM_BUSY = 0x010, /* Bit 4: tmem busy */
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DPC_STATUS_PIPE_BUSY = 0x020, /* Bit 5: pipe busy */
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DPC_STATUS_CMD_BUSY = 0x040, /* Bit 6: cmd busy */
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DPC_STATUS_CBUF_READY = 0x080, /* Bit 7: cbuf ready */
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DPC_STATUS_DMA_BUSY = 0x100, /* Bit 8: dma busy */
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DPC_STATUS_END_VALID = 0x200, /* Bit 9: end valid */
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DPC_STATUS_START_VALID = 0x400, /* Bit 10: start valid */
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};
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/*
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//Audio Interface registers;
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*/
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class AudioInterfaceReg
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{
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AudioInterfaceReg (void);
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protected:
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AudioInterfaceReg (DWORD * _AudioInterface);
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public:
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DWORD & AI_DRAM_ADDR_REG;
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DWORD & AI_LEN_REG;
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DWORD & AI_CONTROL_REG;
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DWORD & AI_STATUS_REG;
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DWORD & AI_DACRATE_REG;
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DWORD & AI_BITRATE_REG;
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};
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enum {
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AI_STATUS_FIFO_FULL = 0x80000000, /* Bit 31: full */
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AI_STATUS_DMA_BUSY = 0x40000000, /* Bit 30: busy */
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};
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//Audio Interface registers;
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class PeripheralInterfaceReg
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{
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PeripheralInterfaceReg (void);
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protected:
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PeripheralInterfaceReg (DWORD * PeripheralInterface);
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public:
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DWORD & PI_DRAM_ADDR_REG;
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DWORD & PI_CART_ADDR_REG;
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DWORD & PI_RD_LEN_REG;
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DWORD & PI_WR_LEN_REG;
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DWORD & PI_STATUS_REG;
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DWORD & PI_BSD_DOM1_LAT_REG;
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DWORD & PI_DOMAIN1_REG;
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DWORD & PI_BSD_DOM1_PWD_REG;
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DWORD & PI_BSD_DOM1_PGS_REG;
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DWORD & PI_BSD_DOM1_RLS_REG;
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DWORD & PI_BSD_DOM2_LAT_REG;
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DWORD & PI_DOMAIN2_REG;
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DWORD & PI_BSD_DOM2_PWD_REG;
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DWORD & PI_BSD_DOM2_PGS_REG;
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DWORD & PI_BSD_DOM2_RLS_REG;
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};
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class RDRAMInt_InterfaceReg
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{
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RDRAMInt_InterfaceReg (void);
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protected:
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RDRAMInt_InterfaceReg (DWORD * RdramInterface);
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public:
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DWORD & RI_MODE_REG;
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DWORD & RI_CONFIG_REG;
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DWORD & RI_CURRENT_LOAD_REG;
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DWORD & RI_SELECT_REG;
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DWORD & RI_COUNT_REG;
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DWORD & RI_REFRESH_REG;
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DWORD & RI_LATENCY_REG;
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DWORD & RI_RERROR_REG;
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DWORD & RI_WERROR_REG;
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};
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//Signal Processor Interface;
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class SigProcessor_InterfaceReg
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{
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protected:
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SigProcessor_InterfaceReg (DWORD * _SignalProcessorInterface);
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public:
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DWORD & SP_MEM_ADDR_REG;
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DWORD & SP_DRAM_ADDR_REG;
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DWORD & SP_RD_LEN_REG;
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DWORD & SP_WR_LEN_REG;
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DWORD & SP_STATUS_REG;
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DWORD & SP_DMA_FULL_REG;
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DWORD & SP_DMA_BUSY_REG;
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DWORD & SP_SEMAPHORE_REG;
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DWORD & SP_PC_REG;
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DWORD & SP_IBIST_REG;
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};
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//Signal Processor interface flags
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enum {
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SP_CLR_HALT = 0x00001, /* Bit 0: clear halt */
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SP_SET_HALT = 0x00002, /* Bit 1: set halt */
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SP_CLR_BROKE = 0x00004, /* Bit 2: clear broke */
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SP_CLR_INTR = 0x00008, /* Bit 3: clear intr */
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SP_SET_INTR = 0x00010, /* Bit 4: set intr */
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SP_CLR_SSTEP = 0x00020, /* Bit 5: clear sstep */
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SP_SET_SSTEP = 0x00040, /* Bit 6: set sstep */
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SP_CLR_INTR_BREAK = 0x00080, /* Bit 7: clear intr on break */
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SP_SET_INTR_BREAK = 0x00100, /* Bit 8: set intr on break */
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SP_CLR_SIG0 = 0x00200, /* Bit 9: clear signal 0 */
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SP_SET_SIG0 = 0x00400, /* Bit 10: set signal 0 */
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SP_CLR_SIG1 = 0x00800, /* Bit 11: clear signal 1 */
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SP_SET_SIG1 = 0x01000, /* Bit 12: set signal 1 */
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SP_CLR_SIG2 = 0x02000, /* Bit 13: clear signal 2 */
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SP_SET_SIG2 = 0x04000, /* Bit 14: set signal 2 */
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SP_CLR_SIG3 = 0x08000, /* Bit 15: clear signal 3 */
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SP_SET_SIG3 = 0x10000, /* Bit 16: set signal 3 */
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SP_CLR_SIG4 = 0x20000, /* Bit 17: clear signal 4 */
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SP_SET_SIG4 = 0x40000, /* Bit 18: set signal 4 */
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SP_CLR_SIG5 = 0x80000, /* Bit 19: clear signal 5 */
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SP_SET_SIG5 = 0x100000, /* Bit 20: set signal 5 */
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SP_CLR_SIG6 = 0x200000, /* Bit 21: clear signal 6 */
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SP_SET_SIG6 = 0x400000, /* Bit 22: set signal 6 */
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SP_CLR_SIG7 = 0x800000, /* Bit 23: clear signal 7 */
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SP_SET_SIG7 = 0x1000000, /* Bit 24: set signal 7 */
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SP_STATUS_HALT = 0x001, /* Bit 0: halt */
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SP_STATUS_BROKE = 0x002, /* Bit 1: broke */
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SP_STATUS_DMA_BUSY = 0x004, /* Bit 2: dma busy */
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SP_STATUS_DMA_FULL = 0x008, /* Bit 3: dma full */
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SP_STATUS_IO_FULL = 0x010, /* Bit 4: io full */
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SP_STATUS_SSTEP = 0x020, /* Bit 5: single step */
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SP_STATUS_INTR_BREAK = 0x040, /* Bit 6: interrupt on break */
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SP_STATUS_SIG0 = 0x080, /* Bit 7: signal 0 set */
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SP_STATUS_SIG1 = 0x100, /* Bit 8: signal 1 set */
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SP_STATUS_SIG2 = 0x200, /* Bit 9: signal 2 set */
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SP_STATUS_SIG3 = 0x400, /* Bit 10: signal 3 set */
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SP_STATUS_SIG4 = 0x800, /* Bit 11: signal 4 set */
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SP_STATUS_SIG5 = 0x1000, /* Bit 12: signal 5 set */
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SP_STATUS_SIG6 = 0x2000, /* Bit 13: signal 6 set */
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SP_STATUS_SIG7 = 0x4000, /* Bit 14: signal 7 set */
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};
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//Peripheral Interface flags
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enum {
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PI_STATUS_DMA_BUSY = 0x01,
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PI_STATUS_IO_BUSY = 0x02,
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PI_STATUS_ERROR = 0x04,
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PI_SET_RESET = 0x01,
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PI_CLR_INTR = 0x02,
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};
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class Serial_InterfaceReg
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{
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Serial_InterfaceReg (void);
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protected:
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Serial_InterfaceReg (DWORD * SerialInterface);
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public:
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DWORD & SI_DRAM_ADDR_REG;
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DWORD & SI_PIF_ADDR_RD64B_REG;
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DWORD & SI_PIF_ADDR_WR64B_REG;
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DWORD & SI_STATUS_REG;
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};
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//Serial Interface flags
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enum {
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SI_STATUS_DMA_BUSY = 0x0001,
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SI_STATUS_RD_BUSY = 0x0002,
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SI_STATUS_DMA_ERROR = 0x0008,
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SI_STATUS_INTERRUPT = 0x1000,
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};
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enum ROUNDING_MODE {
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ROUND_NEAR = _RC_NEAR,
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ROUND_DOWN = _RC_DOWN,
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ROUND_UP = _RC_UP,
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ROUND_CHOP = _RC_CHOP,
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};
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class CRegName {
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public:
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static const char *GPR[32];
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static const char *GPR_Hi[32];
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static const char *GPR_Lo[32];
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static const char *Cop0[32];
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static const char *FPR[32];
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static const char *FPR_Ctrl[32];
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};
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class CSystemRegisters
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{
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protected:
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static DWORD * _PROGRAM_COUNTER;
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static MIPS_DWORD * _GPR;
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static MIPS_DWORD * _FPR;
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static DWORD * _CP0;
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static MIPS_DWORD * _RegHI;
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static MIPS_DWORD * _RegLO;
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static float ** _FPR_S;
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static double ** _FPR_D;
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static DWORD * _FPCR;
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static DWORD * _LLBit;
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static ROUNDING_MODE * _RoundingModel;
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};
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class CRegisters:
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protected CSystemRegisters,
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protected CGameSettings,
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public CP0registers,
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public Rdram_InterfaceReg,
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public Mips_InterfaceReg,
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public Video_InterfaceReg,
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public AudioInterfaceReg,
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public PeripheralInterfaceReg,
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public RDRAMInt_InterfaceReg,
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public SigProcessor_InterfaceReg,
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public DisplayControlReg,
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public Serial_InterfaceReg
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{
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public:
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CRegisters();
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//General Registers
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DWORD m_PROGRAM_COUNTER;
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MIPS_DWORD m_GPR[32];
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DWORD m_CP0[33];
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MIPS_DWORD m_HI;
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MIPS_DWORD m_LO;
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DWORD m_LLBit;
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DWORD m_LLAddr;
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//Floating point registers/information
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DWORD m_FPCR[32];
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ROUNDING_MODE m_RoundingModel;
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MIPS_DWORD m_FPR[32];
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float * m_FPR_S[32];
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double * m_FPR_D[32];
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|
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//Memory Mapped N64 registers
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DWORD m_RDRAM_Registers[10];
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DWORD m_SigProcessor_Interface[10];
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DWORD m_Display_ControlReg[10];
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DWORD m_Mips_Interface[4];
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DWORD m_Video_Interface[14];
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DWORD m_Audio_Interface[6];
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DWORD m_Peripheral_Interface[13];
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DWORD m_RDRAM_Interface[8];
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DWORD m_SerialInterface[4];
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DWORD m_AudioIntrReg;
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DWORD m_GfxIntrReg;
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DWORD m_RspIntrReg;
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void CheckInterrupts ( void );
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void DoAddressError ( BOOL DelaySlot, DWORD BadVaddr, BOOL FromRead );
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void DoBreakException ( BOOL DelaySlot );
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void DoCopUnusableException ( BOOL DelaySlot, int Coprocessor );
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BOOL DoIntrException ( BOOL DelaySlot );
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void DoTLBReadMiss ( BOOL DelaySlot, DWORD BadVaddr );
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void DoSysCallException ( BOOL DelaySlot);
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void FixFpuLocations ( void );
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void Reset ( void );
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void SetAsCurrentSystem ( void );
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private:
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bool m_FirstInterupt;
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|
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};
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