248 lines
8.4 KiB
C
248 lines
8.4 KiB
C
#ifdef toremove
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/*
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* Project 64 - A Nintendo 64 emulator.
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*
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* (c) Copyright 2001 zilmar (zilmar@emulation64.com) and
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* Jabo (jabo@emulation64.com).
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*
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* pj64 homepage: www.pj64.net
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*
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* Permission to use, copy, modify and distribute Project64 in both binary and
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* source form, for non-commercial purposes, is hereby granted without fee,
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* providing that this license information and copyright notice appear with
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* all copies and any derived work.
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*
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* This software is provided 'as-is', without any express or implied
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* warranty. In no event shall the authors be held liable for any damages
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* arising from the use of this software.
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*
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* Project64 is freeware for PERSONAL USE only. Commercial users should
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* seek permission of the copyright holders first. Commercial use includes
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* charging money for Project64 or software derived from Project64.
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*
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* The copyright holders request that bug fixes and improvements to the code
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* should be forwarded to them so if they want them.
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*
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*/
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#define INDEX_REGISTER _CP0[0]
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#define RANDOM_REGISTER _CP0[1]
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#define ENTRYLO0_REGISTER _CP0[2]
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#define ENTRYLO1_REGISTER _CP0[3]
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#define CONTEXT_REGISTER _CP0[4]
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#define PAGE_MASK_REGISTER _CP0[5]
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#define WIRED_REGISTER _CP0[6]
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#define BAD_VADDR_REGISTER _CP0[8]
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#define COUNT_REGISTER _CP0[9]
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#define ENTRYHI_REGISTER _CP0[10]
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#define COMPARE_REGISTER _CP0[11]
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#define STATUS_REGISTER _CP0[12]
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#define CAUSE_REGISTER _CP0[13]
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#define EPC_REGISTER _CP0[14]
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#define CONFIG_REGISTER _CP0[16]
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#define TAGLO_REGISTER _CP0[28]
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#define TAGHI_REGISTER _CP0[29]
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#define ERROREPC_REGISTER _CP0[30]
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#define FAKE_CAUSE_REGISTER _CP0[32]
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#define COMPARE_REGISTER_NO 11
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#define STATUS_REGISTER_NO 12
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#define CAUSE_REGISTER_NO 13
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#define REVISION_REGISTER _FPCR[0]
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#define FSTATUS_REGISTER _FPCR[31]
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#define GPR_S0 _GPR[16]
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#define GPR_S1 _GPR[17]
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#define GPR_S2 _GPR[18]
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#define GPR_S3 _GPR[19]
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#define GPR_S4 _GPR[20]
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#define GPR_S5 _GPR[21]
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#define GPR_S6 _GPR[22]
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#define GPR_S7 _GPR[23]
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#define GPR_SP _GPR[29]
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#define GPR_RA _GPR[31]
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#define RDRAM_CONFIG_REG _RegRDRAM[0]
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#define RDRAM_DEVICE_TYPE_REG _RegRDRAM[0]
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#define RDRAM_DEVICE_ID_REG _RegRDRAM[1]
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#define RDRAM_DELAY_REG _RegRDRAM[2]
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#define RDRAM_MODE_REG _RegRDRAM[3]
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#define RDRAM_REF_INTERVAL_REG _RegRDRAM[4]
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#define RDRAM_REF_ROW_REG _RegRDRAM[5]
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#define RDRAM_RAS_INTERVAL_REG _RegRDRAM[6]
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#define RDRAM_MIN_INTERVAL_REG _RegRDRAM[7]
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#define RDRAM_ADDR_SELECT_REG _RegRDRAM[8]
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#define RDRAM_DEVICE_MANUF_REG _RegRDRAM[9]
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#define SP_MEM_ADDR_REG _RegSP[0]
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#define SP_DRAM_ADDR_REG _RegSP[1]
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#define SP_RD_LEN_REG _RegSP[2]
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#define SP_WR_LEN_REG _RegSP[3]
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#define SP_STATUS_REG _RegSP[4]
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#define SP_DMA_FULL_REG _RegSP[5]
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#define SP_DMA_BUSY_REG _RegSP[6]
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#define SP_SEMAPHORE_REG _RegSP[7]
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#define SP_PC_REG _RegSP[8]
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#define SP_IBIST_REG _RegSP[9]
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#define DPC_START_REG _RegDPC[0]
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#define DPC_END_REG _RegDPC[1]
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#define DPC_CURRENT_REG _RegDPC[2]
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#define DPC_STATUS_REG _RegDPC[3]
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#define DPC_CLOCK_REG _RegDPC[4]
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#define DPC_BUFBUSY_REG _RegDPC[5]
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#define DPC_PIPEBUSY_REG _RegDPC[6]
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#define DPC_TMEM_REG _RegDPC[7]
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#define MI_INIT_MODE_REG _RegMI[0]
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#define MI_MODE_REG _RegMI[0]
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#define MI_VERSION_REG _RegMI[1]
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#define MI_NOOP_REG _RegMI[1]
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#define MI_INTR_REG _RegMI[2]
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#define MI_INTR_MASK_REG _RegMI[3]
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#define VI_STATUS_REG _RegVI[0]
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#define VI_CONTROL_REG _RegVI[0]
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#define VI_ORIGIN_REG _RegVI[1]
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#define VI_DRAM_ADDR_REG _RegVI[1]
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#define VI_WIDTH_REG _RegVI[2]
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#define VI_H_WIDTH_REG _RegVI[2]
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#define VI_INTR_REG _RegVI[3]
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#define VI_V_INTR_REG _RegVI[3]
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#define VI_CURRENT_REG _RegVI[4]
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#define VI_V_CURRENT_LINE_REG _RegVI[4]
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#define VI_BURST_REG _RegVI[5]
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#define VI_TIMING_REG _RegVI[5]
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#define VI_V_SYNC_REG _RegVI[6]
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#define VI_H_SYNC_REG _RegVI[7]
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#define VI_LEAP_REG _RegVI[8]
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#define VI_H_SYNC_LEAP_REG _RegVI[8]
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#define VI_H_START_REG _RegVI[9]
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#define VI_H_VIDEO_REG _RegVI[9]
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#define VI_V_START_REG _RegVI[10]
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#define VI_V_VIDEO_REG _RegVI[10]
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#define VI_V_BURST_REG _RegVI[11]
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#define VI_X_SCALE_REG _RegVI[12]
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#define VI_Y_SCALE_REG _RegVI[13]
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#define AI_DRAM_ADDR_REG _RegAI[0]
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#define AI_LEN_REG _RegAI[1]
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#define AI_CONTROL_REG _RegAI[2]
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#define AI_STATUS_REG _RegAI[3]
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#define AI_DACRATE_REG _RegAI[4]
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#define AI_BITRATE_REG _RegAI[5]
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#define PI_DRAM_ADDR_REG _RegPI[0]
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#define PI_CART_ADDR_REG _RegPI[1]
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#define PI_RD_LEN_REG _RegPI[2]
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#define PI_WR_LEN_REG _RegPI[3]
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#define PI_STATUS_REG _RegPI[4]
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#define PI_BSD_DOM1_LAT_REG _RegPI[5]
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#define PI_DOMAIN1_REG _RegPI[5]
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#define PI_BSD_DOM1_PWD_REG _RegPI[6]
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#define PI_BSD_DOM1_PGS_REG _RegPI[7]
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#define PI_BSD_DOM1_RLS_REG _RegPI[8]
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#define PI_BSD_DOM2_LAT_REG _RegPI[9]
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#define PI_DOMAIN2_REG _RegPI[9]
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#define PI_BSD_DOM2_PWD_REG _RegPI[10]
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#define PI_BSD_DOM2_PGS_REG _RegPI[11]
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#define PI_BSD_DOM2_RLS_REG _RegPI[12]
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#define RI_MODE_REG _RegRI[0]
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#define RI_CONFIG_REG _RegRI[1]
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#define RI_CURRENT_LOAD_REG _RegRI[2]
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#define RI_SELECT_REG _RegRI[3]
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#define RI_COUNT_REG _RegRI[4]
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#define RI_REFRESH_REG _RegRI[4]
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#define RI_LATENCY_REG _RegRI[5]
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#define RI_RERROR_REG _RegRI[6]
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#define RI_WERROR_REG _RegRI[7]
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#define SI_DRAM_ADDR_REG _RegSI[0]
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#define SI_PIF_ADDR_RD64B_REG _RegSI[1]
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#define SI_PIF_ADDR_WR64B_REG _RegSI[2]
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#define SI_STATUS_REG _RegSI[3]
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enum
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{
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MI_MODE_INIT = 0x0080, /* Bit 7: init mode */
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MI_MODE_EBUS = 0x0100, /* Bit 8: ebus test mode */
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MI_MODE_RDRAM = 0x0200, /* Bit 9: RDRAM reg mode */
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};
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#define FPR_Type(Reg) (Reg) == R4300i_COP1_S ? "S" : (Reg) == R4300i_COP1_D ? "D" :\
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(Reg) == R4300i_COP1_W ? "W" : "L"
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typedef struct {
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DWORD PROGRAM_COUNTER;
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MIPS_DWORD GPR[32];
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MIPS_DWORD FPR[32];
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DWORD CP0[33];
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DWORD FPCR[32];
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MIPS_DWORD HI;
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MIPS_DWORD LO;
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DWORD RDRAM[10];
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DWORD SP[10];
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DWORD DPC[10];
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DWORD MI[4];
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DWORD VI[14];
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DWORD AI[6];
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DWORD PI[13];
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DWORD RI[8];
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DWORD SI[4];
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BYTE PIF_Ram[0x40];
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int DMAUsed;
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} N64_REGISTERS;
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#ifdef __cplusplus
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extern "C" {
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#endif
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extern char *GPR_Name[32], *GPR_NameHi[32], *GPR_NameLo[32], *FPR_Name[32], *FPR_NameHi[32],
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*FPR_NameLo[32],*FPR_Ctrl_Name[32];
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extern DWORD RegModValue;
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//extern DWORD RegModValue, ViFieldNumber, LLAddr;
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extern N64_REGISTERS Registers;
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/*enum FPU_Format {
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FPU_Unkown,FPU_Dword, FPU_Qword, FPU_Float, FPU_Double
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};*/
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void ChangeMiIntrMask ( void );
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void ChangeMiModeReg ( void );
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void ChangeSpStatus ( void );
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void InitalizeR4300iRegisters ( int UsePif, int Country, int CIC_Chip );
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void SetFpuLocations ( void );
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void SetupRegisters ( N64_REGISTERS * n64_Registers );
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#ifdef __cplusplus
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}
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#endif
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#endif
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BOOL Is8BitReg ( int x86Reg);
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void ChangeFPURegFormat ( CCodeSection * Section, int Reg, CRegInfo::FPU_STATE OldFormat, CRegInfo::FPU_STATE NewFormat, CRegInfo::FPU_ROUND RoundingModel );
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void Load_FPR_ToTop ( CCodeSection * Section, int Reg, int RegToLoad, CRegInfo::FPU_STATE Format);
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void Map_GPR_32bit ( CCodeSection * Section, int Reg, BOOL SignValue, int MipsRegToLoad );
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void Map_GPR_64bit ( CCodeSection * Section, int Reg, int MipsRegToLoad );
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int Map_MemoryStack ( CCodeSection * Section, int Reg, bool MapRegister );
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int Map_TempReg ( CCodeSection * Section, int x86Reg, int MipsReg, BOOL LoadHiWord );
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BOOL RegInStack ( CCodeSection * Section, int Reg, int Format );
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void ProtectGPR ( CCodeSection * Section, DWORD Reg );
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int StackPosition ( CCodeSection * Section, int Reg );
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void UnMap_AllFPRs ( CCodeSection * Section );
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void UnMap_FPR ( CCodeSection * Section, int Reg, int WriteBackValue );
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void UnMap_GPR ( CCodeSection * Section, DWORD Reg, int WriteBackValue );
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BOOL UnMap_X86reg ( CCodeSection * Section, DWORD x86Reg );
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void UnProtectGPR ( CCodeSection * Section, DWORD Reg );
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void WriteBackRegisters ( CCodeSection * Section );
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void FixRoundModel ( CCodeSection * Section, CRegInfo::FPU_ROUND RoundMethod );
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