Core: Fix N64 disk IPL load address check (#2401)

The IPL load address check always evaluated to false due
to a wrong operator.

Signed-off-by: Francois Berder <fberder@outlook.fr>

Source/Project64-core/N64System/N64Disk.cpp

@@ -191,7 +191,7 @@ bool CN64Disk::IsValidDiskImage(uint8_t Test[0x20])
 
     // IPL load address
     uint32_t ipl_load_addr = (Test[0x1C] << 24) | (Test[0x1D] << 16) | (Test[0x1E] << 8) | Test[0x1F];
-    if (ipl_load_addr < 0x80000000 && ipl_load_addr >= 0x80800000) return false;
+    if (ipl_load_addr < 0x80000000 || ipl_load_addr >= 0x80800000) return false;
 
     // Country code
     if (*((uint32_t *)&Test[0]) == 0x16D348E8)

Source/Project64-core/N64System/Recompiler/x86/x86RecompilerOps.cpp

@@ -8294,9 +8294,6 @@ void CX86RecompilerOps::COP1_S_CMP()
 // COP1: D functions
 void CX86RecompilerOps::COP1_D_ADD()
 {
-    uint32_t Reg1 = m_Opcode.ft == m_Opcode.fd ? m_Opcode.ft : m_Opcode.fs;
-    uint32_t Reg2 = m_Opcode.ft == m_Opcode.fd ? m_Opcode.fs : m_Opcode.ft;
-
     if (FpuExceptionInRecompiler())
     {
         COP1_D_Opcode(&CX86Ops::Fadd);
@@ -8305,6 +8302,9 @@ void CX86RecompilerOps::COP1_D_ADD()
     {
         CompileCop1Test();
 
+        uint32_t Reg1 = m_Opcode.ft == m_Opcode.fd ? m_Opcode.ft : m_Opcode.fs;
+        uint32_t Reg2 = m_Opcode.ft == m_Opcode.fd ? m_Opcode.fs : m_Opcode.ft;
+
         m_RegWorkingSet.Load_FPR_ToTop(m_Opcode.fd, Reg1, CRegInfo::FPU_Double);
         if (m_RegWorkingSet.RegInStack(Reg2, CRegInfo::FPU_Double))
         {
@@ -8323,9 +8323,6 @@ void CX86RecompilerOps::COP1_D_ADD()
 
 void CX86RecompilerOps::COP1_D_SUB()
 {
-    uint32_t Reg1 = m_Opcode.ft == m_Opcode.fd ? m_Opcode.ft : m_Opcode.fs;
-    uint32_t Reg2 = m_Opcode.ft == m_Opcode.fd ? m_Opcode.fs : m_Opcode.ft;
-
     if (FpuExceptionInRecompiler())
     {
         COP1_D_Opcode(&CX86Ops::Fsub);
@@ -8334,6 +8331,9 @@ void CX86RecompilerOps::COP1_D_SUB()
     {
         CompileCop1Test();
 
+        uint32_t Reg1 = m_Opcode.ft == m_Opcode.fd ? m_Opcode.ft : m_Opcode.fs;
+        uint32_t Reg2 = m_Opcode.ft == m_Opcode.fd ? m_Opcode.fs : m_Opcode.ft;
+
         if (m_Opcode.fd == m_Opcode.ft)
         {
             m_RegWorkingSet.UnMap_FPR(m_Opcode.fd, true);
@@ -8364,15 +8364,15 @@ void CX86RecompilerOps::COP1_D_SUB()
 
 void CX86RecompilerOps::COP1_D_MUL()
 {
-    uint32_t Reg1 = m_Opcode.ft == m_Opcode.fd ? m_Opcode.ft : m_Opcode.fs;
-    uint32_t Reg2 = m_Opcode.ft == m_Opcode.fd ? m_Opcode.fs : m_Opcode.ft;
-
     if (FpuExceptionInRecompiler())
     {
         COP1_D_Opcode(&CX86Ops::Fmul);
     }
     else
     {
+        uint32_t Reg1 = m_Opcode.ft == m_Opcode.fd ? m_Opcode.ft : m_Opcode.fs;
+        uint32_t Reg2 = m_Opcode.ft == m_Opcode.fd ? m_Opcode.fs : m_Opcode.ft;
+
         CompileCop1Test();
         m_RegWorkingSet.FixRoundModel(CRegInfo::RoundDefault);
 
@@ -8394,15 +8394,15 @@ void CX86RecompilerOps::COP1_D_MUL()
 
 void CX86RecompilerOps::COP1_D_DIV()
 {
-    uint32_t Reg1 = m_Opcode.ft == m_Opcode.fd ? m_Opcode.ft : m_Opcode.fs;
-    uint32_t Reg2 = m_Opcode.ft == m_Opcode.fd ? m_Opcode.fs : m_Opcode.ft;
-
     if (FpuExceptionInRecompiler())
     {
         COP1_D_Opcode(&CX86Ops::Fdiv);
     }
     else
     {
+        uint32_t Reg1 = m_Opcode.ft == m_Opcode.fd ? m_Opcode.ft : m_Opcode.fs;
+        uint32_t Reg2 = m_Opcode.ft == m_Opcode.fd ? m_Opcode.fs : m_Opcode.ft;
+
         CompileCop1Test();
 
         if (m_Opcode.fd == m_Opcode.ft)
@@ -8436,21 +8436,7 @@ void CX86RecompilerOps::COP1_D_ABS()
 {
     if (FpuExceptionInRecompiler())
     {
-        CompileInitFpuOperation(CRegInfo::RoundDefault);
+        COP1_D_Opcode(&CX86Ops::Fabs);
-        if (m_RegWorkingSet.RegInStack(m_Opcode.fs, CRegInfo::FPU_Any) ||
-            m_RegWorkingSet.RegInStack(m_Opcode.fd, CRegInfo::FPU_Any))
-        {
-            g_Notify->BreakPoint(__FILE__, __LINE__);
-            return;
-        }
-        asmjit::x86::Gp TempReg = m_RegWorkingSet.FPRValuePointer(m_Opcode.fs, CRegInfo::FPU_Double);
-        CompileCheckFPUInput(TempReg, FpuOpSize_64bit);
-        m_RegWorkingSet.PrepareFPTopToBe(m_Opcode.fd, m_Opcode.fs, CRegInfo::FPU_Double);
-        m_Assembler.fabs();
-        m_Assembler.mov(TempReg, (uint64_t)&m_TempValue64);
-        m_Assembler.fpuStoreQwordFromX86Reg(m_RegWorkingSet.StackTopPos(), TempReg, false);
-        CompileCheckFPUResult64(TempReg);
-        m_RegWorkingSet.SetFPTopAs(m_Opcode.fd);
     }
     else
     {
@@ -8461,31 +8447,24 @@ void CX86RecompilerOps::COP1_D_ABS()
 }
 
 void CX86RecompilerOps::COP1_D_NEG()
+{
+    if (FpuExceptionInRecompiler())
+    {
+        COP1_D_Opcode(&CX86Ops::Fchs);
+    }
+    else
     {
         CompileCop1Test();
         m_RegWorkingSet.Load_FPR_ToTop(m_Opcode.fd, m_Opcode.fs, CRegInfo::FPU_Double);
         m_Assembler.fchs();
     }
+}
 
 void CX86RecompilerOps::COP1_D_SQRT()
 {
     if (FpuExceptionInRecompiler())
     {
-        CompileInitFpuOperation(CRegInfo::RoundDefault);
+        COP1_D_Opcode(&CX86Ops::Fsqrt);
-        if (m_RegWorkingSet.RegInStack(m_Opcode.fs, CRegInfo::FPU_Any) ||
-            m_RegWorkingSet.RegInStack(m_Opcode.fd, CRegInfo::FPU_Any))
-        {
-            g_Notify->BreakPoint(__FILE__, __LINE__);
-            return;
-        }
-        asmjit::x86::Gp TempReg = m_RegWorkingSet.FPRValuePointer(m_Opcode.fs, CRegInfo::FPU_Double);
-        CompileCheckFPUInput(TempReg, FpuOpSize_64bit);
-        m_RegWorkingSet.PrepareFPTopToBe(m_Opcode.fd, m_Opcode.fs, CRegInfo::FPU_Double);
-        m_Assembler.fsqrt();
-        m_Assembler.mov(TempReg, (uint64_t)&m_TempValue64);
-        m_Assembler.fpuStoreQwordFromX86Reg(m_RegWorkingSet.StackTopPos(), TempReg, false);
-        CompileCheckFPUResult64(TempReg);
-        m_RegWorkingSet.SetFPTopAs(m_Opcode.fd);
     }
     else
     {
@@ -8499,6 +8478,7 @@ void CX86RecompilerOps::COP1_D_MOV()
 {
     if (FpuExceptionInRecompiler())
     {
+        CompileCop1Test();
         if (m_RegWorkingSet.RegInStack(m_Opcode.fs, CRegInfo::FPU_Any) || m_RegWorkingSet.RegInStack(m_Opcode.fd, CRegInfo::FPU_Any))
         {
             g_Notify->BreakPoint(__FILE__, __LINE__);
@@ -8577,6 +8557,12 @@ void CX86RecompilerOps::COP1_D_FLOOR_L()
 }
 
 void CX86RecompilerOps::COP1_D_ROUND_W()
+{
+    if (FpuExceptionInRecompiler())
+    {
+        COP1_S_CVT(CRegInfo::RoundNearest, CRegInfo::FPU_Double, CRegInfo::FPU_Dword);
+    }
+    else
     {
         CompileCop1Test();
         if (m_RegWorkingSet.RegInStack(m_Opcode.fs, CRegInfo::FPU_Double) || m_RegWorkingSet.RegInStack(m_Opcode.fs, CRegInfo::FPU_Qword))
@@ -8589,6 +8575,7 @@ void CX86RecompilerOps::COP1_D_ROUND_W()
         }
         m_RegWorkingSet.ChangeFPURegFormat(m_Opcode.fd, CRegInfo::FPU_Double, CRegInfo::FPU_Dword, CRegInfo::RoundNearest);
     }
+}
 
 void CX86RecompilerOps::COP1_D_TRUNC_W()
 {
@@ -8612,6 +8599,12 @@ void CX86RecompilerOps::COP1_D_TRUNC_W()
 }
 
 void CX86RecompilerOps::COP1_D_CEIL_W()
+{
+    if (FpuExceptionInRecompiler())
+    {
+        COP1_S_CVT(CRegInfo::RoundUp, CRegInfo::FPU_Double, CRegInfo::FPU_Dword);
+    }
+    else
     {
         CompileCop1Test();
         if (m_RegWorkingSet.RegInStack(m_Opcode.fs, CRegInfo::FPU_Double) || m_RegWorkingSet.RegInStack(m_Opcode.fs, CRegInfo::FPU_Qword))
@@ -8624,8 +8617,15 @@ void CX86RecompilerOps::COP1_D_CEIL_W()
         }
         m_RegWorkingSet.ChangeFPURegFormat(m_Opcode.fd, CRegInfo::FPU_Double, CRegInfo::FPU_Dword, CRegInfo::RoundUp);
     }
+}
 
 void CX86RecompilerOps::COP1_D_FLOOR_W()
+{
+    if (FpuExceptionInRecompiler())
+    {
+        COP1_S_CVT(CRegInfo::RoundDown, CRegInfo::FPU_Double, CRegInfo::FPU_Dword);
+    }
+    else
     {
         CompileCop1Test();
         if (m_RegWorkingSet.RegInStack(m_Opcode.fs, CRegInfo::FPU_Double) || m_RegWorkingSet.RegInStack(m_Opcode.fs, CRegInfo::FPU_Qword))
@@ -8638,8 +8638,15 @@ void CX86RecompilerOps::COP1_D_FLOOR_W()
         }
         m_RegWorkingSet.ChangeFPURegFormat(m_Opcode.fd, CRegInfo::FPU_Double, CRegInfo::FPU_Dword, CRegInfo::RoundDown);
     }
+}
 
 void CX86RecompilerOps::COP1_D_CVT_S()
+{
+    if (FpuExceptionInRecompiler())
+    {
+        COP1_S_CVT(CRegInfo::RoundDefault, CRegInfo::FPU_Double, CRegInfo::FPU_FloatLow);
+    }
+    else
     {
         CompileCop1Test();
         if (m_RegWorkingSet.RegInStack(m_Opcode.fd, CRegInfo::FPU_Double) || m_RegWorkingSet.RegInStack(m_Opcode.fd, CRegInfo::FPU_Qword))
@@ -8652,8 +8659,15 @@ void CX86RecompilerOps::COP1_D_CVT_S()
         }
         m_RegWorkingSet.ChangeFPURegFormat(m_Opcode.fd, CRegInfo::FPU_Double, CRegInfo::FPU_Float, CRegInfo::RoundDefault);
     }
+}
 
 void CX86RecompilerOps::COP1_D_CVT_W()
+{
+    if (FpuExceptionInRecompiler())
+    {
+        COP1_S_CVT(CRegInfo::RoundDefault, CRegInfo::FPU_Double, CRegInfo::FPU_Dword);
+    }
+    else
     {
         CompileCop1Test();
         if (m_RegWorkingSet.RegInStack(m_Opcode.fs, CRegInfo::FPU_Double) || m_RegWorkingSet.RegInStack(m_Opcode.fs, CRegInfo::FPU_Qword))
@@ -8666,6 +8680,7 @@ void CX86RecompilerOps::COP1_D_CVT_W()
         }
         m_RegWorkingSet.ChangeFPURegFormat(m_Opcode.fd, CRegInfo::FPU_Double, CRegInfo::FPU_Dword, CRegInfo::RoundDefault);
     }
+}
 
 void CX86RecompilerOps::COP1_D_CVT_L()
 {
@@ -9138,6 +9153,12 @@ void CX86RecompilerOps::CompileCheckFPUResult64(asmjit::x86::Gp RegPointer)
         m_Assembler.mov(RegPointerValue, RegPointer);
         RegPointer = RegPointerValue;
     }
+    bool RegPointerProtect = m_RegWorkingSet.GetX86Protected(GetIndexFromX86Reg(RegPointer));
+    if (!RegPointerProtect)
+    {
+        m_RegWorkingSet.SetX86Protected(GetIndexFromX86Reg(RegPointer), true);
+    }
+
     asmjit::x86::Gp TempReg2 = m_RegWorkingSet.Map_TempReg(x86Reg_Unknown, -1, false, false);
     m_Assembler.fnstsw(asmjit::x86::ax);
     m_Assembler.and_(asmjit::x86::ax, 0x3D);
@@ -9192,6 +9213,11 @@ void CX86RecompilerOps::CompileCheckFPUResult64(asmjit::x86::Gp RegPointer)
     CompileExit(m_CompilePC + 4, m_CompilePC + 4, ExitRegSet, ExitReason_Normal, false, &CX86Ops::JmpLabel);
     m_Assembler.bind(ValueSame);
     m_Assembler.bind(DoNoModify);
+
+    if (!RegPointerProtect)
+    {
+        m_RegWorkingSet.SetX86Protected(GetIndexFromX86Reg(RegPointer), false);
+    }
 }
 
 void CX86RecompilerOps::CompileCop1Test()
@@ -10872,6 +10898,26 @@ void CX86RecompilerOps::CompileStoreMemoryValue(asmjit::x86::Gp AddressReg, asmj
     }
 }
 
+void CX86RecompilerOps::COP1_D_Opcode(void (CX86Ops::*Instruction)(void))
+{
+    CompileInitFpuOperation(CRegInfo::RoundDefault);
+    if (m_RegWorkingSet.RegInStack(m_Opcode.fs, CRegInfo::FPU_Any) ||
+        m_RegWorkingSet.RegInStack(m_Opcode.fd, CRegInfo::FPU_Any))
+    {
+        g_Notify->BreakPoint(__FILE__, __LINE__);
+        return;
+    }
+    asmjit::x86::Gp TempReg = m_RegWorkingSet.FPRValuePointer(m_Opcode.fs, CRegInfo::FPU_Double);
+    CompileCheckFPUInput(TempReg, FpuOpSize_64bit);
+    m_RegWorkingSet.SetX86Protected(GetIndexFromX86Reg(TempReg), false);
+    m_RegWorkingSet.PrepareFPTopToBe(m_Opcode.fd, m_Opcode.fs, CRegInfo::FPU_Double);
+    (m_Assembler.*Instruction)();
+    m_Assembler.mov(TempReg, (uint64_t)&m_TempValue64);
+    m_Assembler.fpuStoreQwordFromX86Reg(m_RegWorkingSet.StackTopPos(), TempReg, false);
+    CompileCheckFPUResult64(TempReg);
+    m_RegWorkingSet.SetFPTopAs(m_Opcode.fd);
+}
+
 void CX86RecompilerOps::COP1_D_Opcode(void (CX86Ops::*Instruction)(const asmjit::x86::Mem &))
 {
     CompileInitFpuOperation(CRegInfo::RoundDefault);

Source/Project64-core/N64System/Recompiler/x86/x86RecompilerOps.h

@@ -270,6 +270,7 @@ private:
     asmjit::x86::Gp BaseOffsetAddress(bool UseBaseRegister);
     void CompileLoadMemoryValue(asmjit::x86::Gp & AddressReg, asmjit::x86::Gp ValueReg, const asmjit::x86::Gp & ValueRegHi, uint8_t ValueSize, bool SignExtend);
     void CompileStoreMemoryValue(asmjit::x86::Gp AddressReg, asmjit::x86::Gp ValueReg, const asmjit::x86::Gp & ValueRegHi, uint64_t Value, uint8_t ValueSize);
+    void COP1_D_Opcode(void (CX86Ops::*Instruction)(void));
     void COP1_D_Opcode(void (CX86Ops::*Instruction)(const asmjit::x86::Mem &));
 
     void SB_Const(uint32_t Value, uint32_t Addr);

Source/Project64-core/N64System/Recompiler/x86/x86ops.cpp

@@ -233,11 +233,21 @@ void CX86Ops::CompX86regToVariable(const asmjit::x86::Gp & Reg, void * Variable,
     }
 }
 
+void CX86Ops::Fabs(void)
+{
+    fabs();
+}
+
 void CX86Ops::Fadd(const asmjit::x86::Mem & Mem)
 {
     fadd(Mem);
 }
 
+void CX86Ops::Fchs(void)
+{
+    fchs();
+}
+
 void CX86Ops::Fdiv(const asmjit::x86::Mem & Mem)
 {
     fdiv(Mem);
@@ -248,6 +258,11 @@ void CX86Ops::Fmul(const asmjit::x86::Mem & Mem)
     fmul(Mem);
 }
 
+void CX86Ops::Fsqrt(void)
+{
+    fsqrt();
+}
+
 void CX86Ops::Fsub(const asmjit::x86::Mem & Mem)
 {
     fsub(Mem);

Source/Project64-core/N64System/Recompiler/x86/x86ops.h

@@ -44,9 +44,12 @@ public:
     void CompConstToVariable(void * Variable, const char * VariableName, uint32_t Const);
     void CompConstToX86reg(const asmjit::x86::Gp & Reg, uint32_t Const);
     void CompX86regToVariable(const asmjit::x86::Gp & Reg, void * Variable, const char * VariableName);
+    void Fabs(void);
     void Fadd(const asmjit::x86::Mem & Mem);
+    void Fchs(void);
     void Fdiv(const asmjit::x86::Mem & Mem);
     void Fmul(const asmjit::x86::Mem & Mem);
+    void Fsqrt(void);
     void Fsub(const asmjit::x86::Mem & Mem);
     void JaeLabel(const char * LabelName, asmjit::Label & JumpLabel);
     void JaLabel(const char * LabelName, asmjit::Label & JumpLabel);