zilmar
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c8e73ba18e
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Core: Handle unaligned SW exception in the recompiler
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2023-12-14 23:04:26 +10:30 |
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zilmar
|
972943cff7
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Core: Allow LW to R0 be able to generate an exception
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2023-12-14 17:21:52 +10:30 |
|
zilmar
|
89a6eaf9d1
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Core: Add RecordLLAddress for 32bit register pointer
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2023-12-14 13:52:15 +10:30 |
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zilmar
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67f5e4f854
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Core: in LL for recompiler handle storing the address in COP[17]
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2023-12-14 13:10:20 +10:30 |
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zilmar
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d5a5f4cdac
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Core: Have Store Instruc rdb and user rdb matching
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2023-12-14 12:21:03 +10:30 |
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zilmar
|
5fec3f8d31
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Core: remove the global of g_TLB
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2023-12-14 12:09:24 +10:30 |
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zilmar
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c67f3f0e97
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Core: Have UpdateSyncCPU use its Sync cpu instead of passing a cpu to it
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2023-12-14 11:18:07 +10:30 |
|
zilmar
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15175d3fe2
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Core: Fix bug in not creating save state correctly
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2023-12-07 17:43:48 +10:30 |
|
zilmar
|
de1288bdca
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Core: remove try/catch around Interpreter cpu
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2023-11-30 21:15:14 +10:30 |
|
zilmar
|
df56964c96
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Android: Remove unneeded log call
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2023-11-30 21:13:27 +10:30 |
|
zilmar
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5671f2b759
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Android: Update how Addu cause android studio was not sign extending result
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2023-11-30 21:12:53 +10:30 |
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zilmar
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01673dac8d
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Core: Change TriggerAddressException to SetVPN an R of entry hi in one call
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2023-11-23 14:20:48 +10:30 |
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zilmar
|
d47b49d4b5
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Core: Fix clang issue
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2023-11-16 18:24:47 +10:30 |
|
zilmar
|
542afc4514
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Core: remove some accidental added debug code
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2023-11-16 18:16:35 +10:30 |
|
zilmar
|
ee714e2462
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Core: On unmap base addresses reset to the correct address
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2023-11-16 18:14:15 +10:30 |
|
zilmar
|
8f4f434820
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Core: Get Fast tlb to just be 32bit
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2023-11-16 17:11:05 +10:30 |
|
zilmar
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dcb6969067
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Core: Have entryHI use functions to set/get parts
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2023-11-16 09:19:24 +10:30 |
|
zilmar
|
a0130ff896
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Core: Convert %I64U to %llx
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2023-11-16 09:03:32 +10:30 |
|
zilmar
|
296b7cf1cf
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Android: Force RSP to be interpret
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2023-11-09 12:45:36 +10:30 |
|
zilmar
|
e6edbc6c82
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Fix clang formatting
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2023-10-27 10:14:21 +10:30 |
|
zilmar
|
4770d29ec0
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Core: Get system events to be internal not global
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2023-10-26 19:59:11 +10:30 |
|
zilmar
|
8f062975c3
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Core: improve DisplayControlRegHandler::Write32
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2023-10-19 19:28:38 +10:30 |
|
zilmar
|
d6a2ae80c1
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Core: Remove SystemRegisters
|
2023-10-19 14:56:53 +10:30 |
|
zilmar
|
d58168bcb9
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Core: R4300iOp access the registers directly, not through CSystemRegisters
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2023-10-19 12:52:33 +10:30 |
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zilmar
|
4d78f56aa2
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Core: In R4300iOp have a member variable for system, reg, mmu
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2023-10-19 12:31:26 +10:30 |
|
zilmar
|
ae0097550f
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Core: Make R4300iOp opcodes not static
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2023-10-19 11:43:32 +10:30 |
|
zilmar
|
7f42f70283
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Core: Make R4300iOp::ExecuteCPU() and R4300iOp::ExecuteOps(int32_t Cycles) non static
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2023-10-19 10:28:25 +10:30 |
|
zilmar
|
d3edbf6dda
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Core: move CInterpreterCPU into R4300iOp
|
2023-10-19 09:32:42 +10:30 |
|
zilmar
|
d4dbc5a3f4
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Core: Have R4300iOp::COP1_D_SQRT inline asm version to only compile in Visual Studio
|
2023-10-14 11:53:35 +10:30 |
|
zilmar
|
00c5057b17
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Core: Make sure precision is correct for COP1_D_SQRT
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2023-10-13 00:16:14 +10:30 |
|
zilmar
|
3a68d3d92a
|
Core: LL/LLD store address
|
2023-10-12 19:55:29 +10:30 |
|
zilmar
|
a6405cfa2d
|
Core: Add masking around DPC_START_REG/DPC_END_REG
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2023-10-12 17:50:58 +10:30 |
|
zilmar
|
4e71221147
|
Core: Fix up FPU mode register location
|
2023-10-12 14:53:44 +10:30 |
|
zilmar
|
befa57924d
|
Core: Fix clang compile issues
|
2023-10-05 15:01:09 +10:30 |
|
zilmar
|
f73c3708a5
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Core: Fix up tlb Probe and call EXC_MOD when tlb is not dirty
|
2023-10-05 14:45:17 +10:30 |
|
zilmar
|
e74e8f6a23
|
Core: Have load/store ops be able to use 64bit addresses
|
2023-10-05 14:28:32 +10:30 |
|
zilmar
|
9f07fe2aac
|
Core: Get tlb addresses to be 64bit
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2023-10-05 13:42:31 +10:30 |
|
zilmar
|
4b844495b7
|
Core: Have save states handle COP0/TLB being 64bit now
Core: Clean up tlb class
|
2023-10-05 13:10:45 +10:30 |
|
zilmar
|
35105e814e
|
Core: Remove CRegisters::DoTLBReadMiss and CRegisters::DoTLBWriteMiss
|
2023-10-05 09:54:41 +10:30 |
|
zilmar
|
b7311cc611
|
Core: Change Non memory load/store to not use tlb
|
2023-10-05 09:32:45 +10:30 |
|
zilmar
|
46e6e54f24
|
RSP: improve running RSP multithreaded
|
2023-09-28 14:46:36 +09:30 |
|
zilmar
|
ac3e0f83d1
|
Rsp: Use RSP Register Handler
|
2023-09-28 11:52:06 +09:30 |
|
zilmar
|
bd1ec4ff0f
|
Core: Create a setting for RDRAM Size that plugins can read
|
2023-09-28 07:29:11 +09:30 |
|
zilmar
|
99417fc5d9
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Core: reset run event in CRSP_Plugin after rom close
|
2023-09-28 07:19:20 +09:30 |
|
zilmar
|
f817becf9c
|
Core: Create a handler for RSP registers that is accessible to the core and the RSP
|
2023-09-28 07:03:01 +09:30 |
|
zilmar
|
03e13455f9
|
Core: Update pipeline before sync in CX86RecompilerOps::OverflowDelaySlot
|
2023-09-28 06:39:39 +09:30 |
|
zilmar
|
2caa457d02
|
Core: reset pipeline stage after CompileLoadMemoryValue and CompileStoreMemoryValue
Update counter before mfc0 x, count
|
2023-09-22 11:01:46 +09:30 |
|
zilmar
|
10d2b77d7c
|
Core: Try to fix android build
|
2023-09-21 20:13:41 +09:30 |
|
zilmar
|
aadcca7528
|
Core: Fix clang issue
|
2023-09-21 18:40:27 +09:30 |
|
zilmar
|
6307888be4
|
Core: fix up exception generator functions
|
2023-09-21 18:07:56 +09:30 |