zilmar
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04c1c3d024
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Core: Fix up CX86RecompilerOps::SPECIAL_DADD
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2024-12-05 10:03:45 +10:30 |
|
zilmar
|
1f3ef6d505
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Core: CX86RecompilerOps::SPECIAL_NOR Ignore write to r0
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2024-11-28 15:54:36 +10:30 |
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zilmar
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95015302d6
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Core: Have CX86RecompilerOps::SPECIAL_XOR treat R0 as 64bit constant
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2024-11-28 15:38:54 +10:30 |
|
zilmar
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a3c777ed84
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Core: Have CX86RecompilerOps::SPECIAL_AND unmap the register on const write
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2024-11-28 15:14:26 +10:30 |
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zilmar
|
0de0bea07a
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Core: Ignore write in CX86RecompilerOps::SPECIAL_OR
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2024-11-28 12:37:42 +10:30 |
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zilmar
|
8d69671e93
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Core: CX86RecompilerOps::ADDIU should not ignore when not 32bit mapped
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2024-11-28 12:29:35 +10:30 |
|
zilmar
|
52d904702f
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Core: With CONST64 CX86RegInfo::WriteBackRegisters might not write the high 32bit correct
|
2024-11-28 11:39:41 +10:30 |
|
zilmar
|
d5367d9291
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Core: Better handling of SW with address not sign extended
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2024-11-28 11:02:38 +10:30 |
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zilmar
|
fd05d9f42f
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core: if lwl or lwr, in CX86RecompilerOps::CompileLoadMemoryValue, make sure that we are loading rt
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2024-11-21 21:33:42 +10:30 |
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zilmar
|
5e1a40fffb
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Core: fix CX86RecompilerOps::CompileLoadMemoryValue Map_GPR_32bit when called from LWC1
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2024-11-21 11:10:01 +10:30 |
|
zilmar
|
2ec9ed08a4
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Core: Improve LW with address not sign extended test in recompiler
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2024-11-14 17:02:18 +10:30 |
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zilmar
|
97b2579b4b
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Core: Have the recompiler just deal with the Program Counter as 32bit
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2024-11-07 17:05:16 +10:30 |
|
zilmar
|
e419508c2b
|
Core: On ExitReason_CheckPCAlignment make sure CompileSystemCheck is called
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2024-11-07 12:13:28 +10:30 |
|
zilmar
|
d06212e766
|
Core: CX86RecompilerOps::JAL stop double call to UpdateCounters
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2024-11-07 11:05:55 +10:30 |
|
zilmar
|
905254615d
|
Core: Change the handling of symbols inside asmjit usage
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2024-10-31 06:50:17 +10:30 |
|
zilmar
|
17c501fa08
|
Core: clean up some code related to CompileStoreMemoryValue, like the exit method being an exception
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2024-10-24 13:32:02 +10:30 |
|
zilmar
|
440894992a
|
Core: remove the BreakPoint in handling ExitReason_CheckPCAlignment
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2024-10-24 11:58:53 +10:30 |
|
zilmar
|
65ede5e3e8
|
Core: If jumping to an unaligned address then generate an exception
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2024-10-24 10:31:48 +10:30 |
|
zilmar
|
c39582b9ed
|
Core: Make sure CX86RecompilerOps::SPECIAL_AND can not write to R0
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2024-10-17 18:42:45 +10:30 |
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zilmar
|
45e52e1d2a
|
Core: in SPECIAL_SYSCALL, SPECIAL_BREAK only exit the block is the stage is PIPELINE_STAGE_NORMAL
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2024-10-17 14:12:46 +10:30 |
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zilmar
|
91f9cdaaa7
|
Core: Change the Program counter to be 64bit
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2024-06-06 14:09:12 +09:30 |
|
zilmar
|
77ac4744a5
|
Core: Make sure fpu stack is being cleared
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2024-05-23 11:52:58 +09:30 |
|
zilmar
|
ec714cd90d
|
Core: in CX86RecompilerOps::CompileCheckFPUResult64 protect RegPointer before Map_TempReg(asmjit::x86::eax)
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2024-05-23 11:41:15 +09:30 |
|
zilmar
|
3baaa829de
|
Core: Remove g_TLBLoadAddress, g_TLBStoreAddress global variables
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2024-05-16 16:34:17 +09:30 |
|
zilmar
|
13bd420b2a
|
Core: Sync FP status register in advanced block linking
|
2024-05-16 15:45:38 +09:30 |
|
zilmar
|
703a09d034
|
Core: Remove protecting memory option
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2024-05-09 17:56:28 +09:30 |
|
zilmar
|
f478f16269
|
Core: Clear FP Status flag in recompiler on BC1FL and BC1TL
|
2024-05-09 10:55:38 +09:30 |
|
zilmar
|
c786bc3251
|
Core: Force Fpu exception in recompiler
|
2024-05-02 16:34:13 +09:30 |
|
zilmar
|
b3e8b760e6
|
Core: get COP1_S_TRUNC_L, COP1_S_CEIL_L, COP1_S_FLOOR_L, COP1_W_CVT_S, COP1_W_CVT_D, COP1_L_CVT_S, COP1_L_CVT_D to use COP1_S_CVT function
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2024-05-02 15:48:43 +09:30 |
|
zilmar
|
dd0f7ad776
|
Core: Have CX86RecompilerOps::COP1_S_CVT be able to handle the old format of FPU_Dword and FPU_Qword
|
2024-05-02 15:46:03 +09:30 |
|
zilmar
|
046f27ce98
|
Core: fix up some bugs in CX86RecompilerOps::COP1_S_CVT
|
2024-04-25 20:47:02 +09:30 |
|
zilmar
|
627b4d6103
|
Core: Get CompileCheckFPUInput check InvalidValueMax, InvalidMinValue in conv
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2024-04-25 20:41:03 +09:30 |
|
zilmar
|
b92e6bd752
|
Core: get to COP1_S_ROUND_L and COP1_S_CVT_L to use COP1_S_CVT
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2024-04-25 20:22:47 +09:30 |
|
zilmar
|
d658477cf4
|
Core: get CX86RecompilerOps::Compile_Branch to clear status flags
|
2024-04-18 17:31:19 +09:30 |
|
zilmar
|
1172b6e04d
|
Core: get CX86RecompilerOps::SW_Const on 0x04300000 to call MIPSInterfaceHandler directly
|
2024-04-18 17:21:39 +09:30 |
|
zilmar
|
38738b783d
|
Core: get CX86RecompilerOps::COP1_S_CVT to handle NewFormat == CRegInfo::FPU_Qword
|
2024-04-18 17:11:45 +09:30 |
|
zilmar
|
7dc53e51cf
|
Core: Get CompileCheckFPUInput to better handle 64bit value check
|
2024-04-18 17:00:29 +09:30 |
|
zilmar
|
a9875b7d61
|
Core: Get COP1_D_CMP to map eax before CompileInitFpuOperation
|
2024-04-18 16:58:18 +09:30 |
|
zilmar
|
3203322d8b
|
Core: Get COP1_D_CVT_L to use COP1_S_CVT
|
2024-04-18 16:56:30 +09:30 |
|
zilmar
|
9e73771815
|
Core: Use the new COP1_S_CVT in COP1_D_ROUND_L, COP1_D_TRUNC_L, COP1_D_CEIL_L, COP1_D_FLOOR_L
|
2024-04-18 16:51:53 +09:30 |
|
zilmar
|
fe87142657
|
Core: CX86RecompilerOps::COP1_S_CMP should allocate eax before calling CompileInitFpuOperation
|
2024-04-18 16:42:48 +09:30 |
|
zilmar
|
0cf4c7dc11
|
Core: get COP1_D_CMP to work in recompiler
|
2024-04-11 18:14:44 +09:30 |
|
zilmar
|
9272ac05f6
|
Core: refactor S opcodes to one central function
|
2024-04-11 18:09:30 +09:30 |
|
zilmar
|
e7178dbdec
|
Core: Fix CX86RecompilerOps::COP1_D_CVT_S
|
2024-03-28 20:05:27 +10:30 |
|
zilmar
|
8bb2445263
|
Core: Have CX86RecompilerOps::CompileCheckFPUResult32 write to the high word
|
2024-03-28 20:02:24 +10:30 |
|
zilmar
|
45fb2ad965
|
Core: In X86RecompilerOps::CompileCheckFPUResult64 make sure RegPointer is protected
|
2024-03-21 17:44:53 +10:30 |
|
zilmar
|
2811b63ff0
|
Core: Update CX86RecompilerOps::COP1_D_CVT_S and CX86RecompilerOps::COP1_D_CVT_W
|
2024-03-21 17:41:29 +10:30 |
|
zilmar
|
33d2722841
|
Core: fix up CX86RecompilerOps::COP1_D_FLOOR_W
|
2024-03-21 17:40:14 +10:30 |
|
zilmar
|
9a9c2e5439
|
Core: Update CX86RecompilerOps::COP1_D_CEIL_W
|
2024-03-21 17:32:12 +10:30 |
|
zilmar
|
401efae0d9
|
Core: fix up CX86RecompilerOps::COP1_D_ROUND_W
|
2024-03-21 17:28:16 +10:30 |