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6,527 Commits 3 Branches 7 Tags 90 MiB
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617 Commits

Author SHA1 Message Date
zilmar bc3fe0fe16 Core: Handle FP Status Reg being mapped better 2024-01-25 18:46:39 +10:30
zilmar 7707f9c7b2 Core: Fix up mov.s and mov.d for correct behaviour in the recompiler 2024-01-25 16:25:06 +10:30
zilmar 272144dc37 Core: check timer on cop1 unusable 2024-01-25 16:23:03 +10:30
zilmar 7ed94b653e Core: Get CX86RecompilerOps::COP1_S_CVT_D to be able to work with exceptions 2024-01-18 17:09:27 +10:30
zilmar 4dc3e35bb4 Core: Update CX86RecompilerOps::COP1_S_SQRT to work with fpu exceptions 2024-01-04 16:51:11 +10:30
zilmar f8089f565e Core: Unmap FPU_Float with writing to m_FPR_UDW 2024-01-04 14:40:42 +10:30
zilmar 552b8f744a Core: update Format_Name to match FPU_STATE 2024-01-04 13:11:21 +10:30
zilmar 6ca8333d39 Core: Get CX86RecompilerOps::COP1_S_CMP to work with exceptions 2024-01-04 12:39:51 +10:30
zilmar c9d2bbd221 Core: CX86RecompilerOps::COP1_CF should be able use the mapped FPStatusReg if is mapped 2024-01-04 12:37:06 +10:30
zilmar 0998f0ff0e Core: Add being able to get FPU_FloatLow from CX86RegInfo::FPRValuePointer 2024-01-04 12:32:55 +10:30
zilmar 23cff4d7c5 Core: Add x86 asm opcode Jnp 2024-01-04 12:31:26 +10:30
zilmar 91a8a828d7 Core: CX86RegInfo::FPRValuePointer when the format is FPU_Dword it should be using m_FPR_UW 2024-01-04 12:01:21 +10:30
zilmar 320769d991 Core: CX86Ops::OrConstToVariable should be a dword_ptr not a word_ptr 2024-01-04 10:33:07 +10:30
zilmar dafa1fb24d Core: Have COP1_W_CVT_S handle the initialization of exceptions 2023-12-28 11:19:06 +10:30
zilmar 17288c90c0 Core: Reset pipeline in CX86RecompilerOps::CompileCheckFPUResult32 2023-12-28 10:23:18 +10:30
zilmar e2306e3541 Core: Get COP1_S_CVT_W to handle inexact 2023-12-28 09:21:53 +10:30
zilmar 8399fdb893 Core: Clear the Divide-by-zero flag 2023-12-21 21:24:33 +10:30
zilmar d14a639a62 Core: Implement COP1_S_DIV with fpu exceptions 2023-12-21 14:11:29 +10:30
zilmar 8e54ec8c8e Core: CompileCheckFPUInput32 and CompileCheckFPUResult32 should not be updating esp since using callthis 2023-12-21 14:10:21 +10:30
zilmar b263ee10b0 Core: In CX86RecompilerOps::CompileLoadMemoryValue instead of checking write to rt being 0 instead use WritesGPR() since LDC1 F0 rt is 0 but it is not writing to r0 2023-12-21 10:41:16 +10:30
zilmar 1810bfda5c Core: Handle unaligned CX86RecompilerOps::CompileLoadMemoryValue for 64bit ops 2023-12-21 10:38:49 +10:30
zilmar 2c1610cfe2 Core: fix up some of the commented out debugging code in CX86RecompilerOps::PreCompileOpcode 2023-12-21 10:37:27 +10:30
zilmar 6610ae3058 Core: Have R4300iInstruction in CRecompilerOpsBase 2023-12-21 10:34:03 +10:30
zilmar c8e73ba18e Core: Handle unaligned SW exception in the recompiler 2023-12-14 23:04:26 +10:30
zilmar 972943cff7 Core: Allow LW to R0 be able to generate an exception 2023-12-14 17:21:52 +10:30
zilmar 89a6eaf9d1 Core: Add RecordLLAddress for 32bit register pointer 2023-12-14 13:52:15 +10:30
zilmar 67f5e4f854 Core: in LL for recompiler handle storing the address in COP[17] 2023-12-14 13:10:20 +10:30
zilmar 5fec3f8d31 Core: remove the global of g_TLB 2023-12-14 12:09:24 +10:30
zilmar c67f3f0e97 Core: Have UpdateSyncCPU use its Sync cpu instead of passing a cpu to it 2023-12-14 11:18:07 +10:30
zilmar 4770d29ec0 Core: Get system events to be internal not global 2023-10-26 19:59:11 +10:30
zilmar d6a2ae80c1 Core: Remove SystemRegisters 2023-10-19 14:56:53 +10:30
zilmar 4d78f56aa2 Core: In R4300iOp have a member variable for system, reg, mmu 2023-10-19 12:31:26 +10:30
zilmar ae0097550f Core: Make R4300iOp opcodes not static 2023-10-19 11:43:32 +10:30
zilmar 7f42f70283 Core: Make R4300iOp::ExecuteCPU() and R4300iOp::ExecuteOps(int32_t Cycles) non static 2023-10-19 10:28:25 +10:30
zilmar d3edbf6dda Core: move CInterpreterCPU into R4300iOp 2023-10-19 09:32:42 +10:30
zilmar 4e71221147 Core: Fix up FPU mode register location 2023-10-12 14:53:44 +10:30
zilmar 35105e814e Core: Remove CRegisters::DoTLBReadMiss and CRegisters::DoTLBWriteMiss 2023-10-05 09:54:41 +10:30
zilmar b7311cc611 Core: Change Non memory load/store to not use tlb 2023-10-05 09:32:45 +10:30
zilmar f817becf9c Core: Create a handler for RSP registers that is accessible to the core and the RSP 2023-09-28 07:03:01 +09:30
zilmar 03e13455f9 Core: Update pipeline before sync in CX86RecompilerOps::OverflowDelaySlot 2023-09-28 06:39:39 +09:30
zilmar 2caa457d02 Core: reset pipeline stage after CompileLoadMemoryValue and CompileStoreMemoryValue 
Update counter before mfc0 x, count
 2023-09-22 11:01:46 +09:30
zilmar ae4af8746b Core: replace GenerateTLBReadException and void GenerateTLBWriteException with CRegisters::DoTLBReadMiss/CRegisters::DoTLBWriteMiss 2023-09-14 13:09:11 +09:30
zilmar a5a4873e84 Core: Have CRegisters::DoAddressError to not directly modify program counter 2023-09-14 11:37:21 +09:30
zilmar 5da5dab3c5 Core: Have CRegisters::DoTLBReadMiss set the target pipe line to jump, not directly modify the PC 2023-09-14 11:09:28 +09:30
zilmar fcd7257adc Core: Change COP0 Status register to a struct breaking up the bits 2023-09-14 10:23:36 +09:30
zilmar ab03916a70 Core: let the stack pointer equal end of rdram 2023-09-07 11:13:54 +09:30
zilmar 91d1c6e237 Core: Add fpu exceptions to COP1_S_MUL 2023-08-31 11:09:48 +09:30
zilmar 2f7a35613f Core: Add exception to COP1_S_SUB 2023-08-31 10:54:41 +09:30
zilmar c28c6bb4a1 Core: Add fpu exceptions to COP1_S_ADD 2023-08-31 10:08:49 +09:30
zilmar 416c85ecda Core: some code clean up of Load_FPR_ToTop 2023-08-31 09:30:05 +09:30
zilmar 2dcfcf250d Core: Do not force unmapping of fpr registers before CX86RegInfo::BeforeCallDirect(void) 2023-08-31 09:28:23 +09:30
zilmar e49438cdab Core: Add exit reason exception 2023-08-30 12:16:07 +09:30
zilmar 6884c8d2c9 Core: fix up how recompiler handles rounding 2023-08-17 15:24:57 +09:30
zilmar 187bd64915 Core: Update how exceptions are handled with the recompiler 2023-06-08 16:25:05 +09:30
zilmar e2eebe566d Core: fix up for clang 2023-05-18 18:05:54 +09:30
zilmar 3b8dfce64a Core: Convert DoBreakException to TriggerException 2023-05-18 11:47:00 +09:30
zilmar 0dfab78c88 Core: Convert DoCopUnusableException to TriggerException 2023-05-18 11:26:36 +09:30
zilmar 252f629e14 Core: Convert DoIllegalInstructionException to TriggerException 2023-05-18 11:13:22 +09:30
zilmar 59a1277bed Core: Convert GenerateOverflowException to TriggerException 2023-05-18 11:05:27 +09:30
zilmar 69fd74ba56 Core: Convert DoSysCallException to TriggerException 2023-05-18 10:56:06 +09:30
zilmar fa25b6d2af Core: clear FPU StatusReg cause in CX86RecompilerOps::COP1_S_ADD 2023-05-02 11:12:13 +09:30
zilmar 02a48566c0 Core: Remove helper functions from x86 Recompiler Ops 2023-05-02 10:50:49 +09:30
zilmar ab8b004b71 Core: Add a setting for fpu reg caching 2023-04-17 18:47:33 +09:30
zilmar 9a04293a67 Update arm/arm64 to use asmjit 2023-04-05 10:16:21 +09:30
zilmar 2c40d47a34 Start to look at x64 recompiler 2023-04-04 17:44:42 +09:30
zilmar fe35d950f3 x64: Change MemoryStackPos to be a pointer 2023-04-03 09:08:43 +09:30
zilmar ea70218d1c Clean up warnings 2023-02-28 10:09:08 +10:30
zilmar f802b18cdc Core: Change to using fenv.h instead of including the code directly 2023-01-30 10:07:51 +10:30
zilmar fb6bda321c Core: SW_Register needs to protect the register 2023-01-23 15:30:39 +10:30
zilmar 531a7df959 Core: Improve StoreInstruc 2023-01-09 14:26:35 +10:30
zilmar ccae22afc5 Core: Revert SPECIAL_SRA and SPECIAL_SRAV to old version when running as 32bit 2023-01-09 13:47:41 +10:30
zilmar b6629ac1d3 Android: Fix build warning with CX86Ops::CallThis 2023-01-03 14:49:35 +10:30
zilmar 811aaf9d36 Core: Fix up SPECIAL_SRAV for 64bit copy 2022-12-26 18:34:53 +10:30
zilmar c619b71b26 Core: get sra to handle 64bit shift 2022-12-26 18:13:45 +10:30
zilmar b217428fee Core: fix up masking in CX86RecompilerOps::COP1_CT 2022-12-26 17:35:58 +10:30
zilmar 0cc7ede816 Core: Fix up BGEZALL in recompiler 2022-12-26 17:19:32 +10:30
zilmar 2c6d3429b7 Core: Fix handling of BGEZAL ra in recompiler 2022-12-26 16:14:05 +10:30
zilmar f380d326fe Core: Start to handle jump in delay slot 2022-12-26 12:54:04 +10:30
zilmar 620aabcf9e Core: Add clang script and check on building release 2022-12-19 15:51:02 +10:30
zilmar bd1b1b4dbb Core: Missed file for code clean up 2022-12-19 15:36:08 +10:30
zilmar c0341bb759 Core: Code clean up for clang 2022-12-19 15:35:17 +10:30
zilmar ff56992542 Android: Some more core changes for asmjit 2022-12-07 09:04:55 +10:30
zilmar 6b04b908bf Core: Handle bgezal ra in the recompiler 2022-12-05 14:09:03 +10:30
zilmar 138868d9ac Core: Get x64 compiling 2022-11-30 17:19:15 +10:30
zilmar ed357e5d97 Core: Get recompiler to call PifRamHandler when in pif address space 2022-11-27 11:07:28 +10:30
zilmar 1e3fff2b41 Core: ignore memory stack pointer when stack pointer is reset 2022-11-25 09:34:54 +10:30
zilmar 79d749e33d Core: fix bug in CX86Ops::CallFunc when not logging opcodes 2022-11-24 09:10:15 +10:30
zilmar e3aa2514c1 Core: Fix bug in CX86RecompilerOps::SPECIAL_DIV 2022-11-23 20:16:38 +10:30
zilmar 8e94b3086b Core: Change recompiler to use asmjit 2022-11-23 14:46:55 +10:30
zilmar 2a6d3cd519 Core: remove #ifdef toremove block in CX86RecompilerOps::SPECIAL_DMULTU() 2022-11-21 08:55:51 +10:30
zilmar 9743f12b1d Core: Remvoe #ifdef LinkBlocks code block 2022-11-21 08:52:19 +10:30
zilmar 529812fdca Core: Switch to use asmjit registers in recompiler 2022-11-07 21:03:32 +10:30
zilmar a4c49a3567 Core: rearrange XorVariableToX86reg parameters 2022-11-07 16:30:09 +10:30
zilmar 2fcce6cdd5 Cote: TestVariable rearrange parameters 2022-11-07 16:25:54 +10:30
zilmar fe1f99ae1c Core: rearrange TestConstToX86Reg parameters 2022-11-07 16:22:51 +10:30
zilmar ce939100c5 Core: rearrange OrVariableToX86Reg parameters 2022-11-07 16:18:54 +10:30
zilmar 697397f1dd Core: Rearrange OrConstToX86Reg parameters 2022-11-07 16:03:45 +10:30
zilmar 40259d01ca Core: rearrange OrConstToVariable parameters 2022-11-07 15:55:19 +10:30
zilmar c95aae8e38 Core: rearrange MoveZxVariableToX86regHalf parameters 2022-11-07 15:48:39 +10:30
zilmar 96eed54a1d Core: rearrange MoveZxVariableToX86regByte parameters 2022-11-07 15:44:10 +10:30
zilmar 4570d9eab5 Core: rearrange MoveZxHalfX86regPointerToX86reg variables 2022-11-07 15:40:01 +10:30
zilmar 8a2197707b Core: rearrange MoveZxByteX86regPointerToX86reg parameters 2022-11-07 15:38:36 +10:30
zilmar 59892a266b Core: rearrange MoveX86regToVariable parameters 2022-11-07 15:30:25 +10:30
zilmar 91a192cead Core: rearrange MoveX86regToMemory parameters 2022-11-07 14:40:28 +10:30
zilmar 891d487fdd Core: rearrange MoveX86regPointerToX86regDisp8 parameters 2022-11-07 14:38:34 +10:30
zilmar d74694d16f Core: rearrange MoveX86regPointerToX86reg parameters 2022-11-07 14:36:11 +10:30
zilmar ebca0854d7 Core: rearrange MoveX86regHalfToX86regPointer parameters 2022-11-07 14:29:33 +10:30
zilmar efac334136 Rearrange MoveX86regHalfToVariable parameters 2022-11-07 14:26:06 +10:30
zilmar 1966b842f3 Core: rearrange MoveX86regByteToX86regPointer parameters 2022-11-07 14:24:22 +10:30
zilmar bb51c3d11d Core: rearrange MoveX86regByteToVariable parameters 2022-11-07 14:23:09 +10:30
zilmar d19fc10f0c Core: remove MoveVariableToX86regByte, MoveVariableToX86regHalf, MoveX86regByteToN64Mem 2022-11-07 14:21:26 +10:30
zilmar 8702e6b67c core: Rearrange MoveVariableDispToX86Reg parmeters 2022-11-07 14:18:15 +10:30
zilmar 10dd2c662a Core: rearrange MoveSxVariableToX86regHalf parameters 2022-11-07 14:08:23 +10:30
zilmar eb5d0ce363 Core: rearrange MoveSxVariableToX86regByte parameters 2022-11-07 14:05:08 +10:30
zilmar 1584d25cd9 Core: Rearrange MoveSxHalfX86regPointerToX86reg parameters 2022-11-07 13:41:49 +10:30
zilmar fe7b8afa92 Core: Rearrange MoveSxByteX86regPointerToX86reg parameters 2022-11-07 13:37:29 +10:30
zilmar 288fe4d222 Core: reorder MoveConstToX86regPointer parameters 2022-11-07 11:35:11 +10:30
zilmar b68caed6c4 Core: reorder MoveConstByteToX86regPointer parameters 2022-11-07 11:32:46 +10:30
zilmar eb0aa05a48 Core: remove x86 functions referencing n64mem 2022-11-07 11:30:51 +10:30
zilmar 40456f12db Core: Change order of MoveConstToVariable 2022-11-07 11:26:17 +10:30
zilmar 5c7390324a Core: reorder MoveConstToMemoryDisp parameters 2022-11-07 10:45:28 +10:30
zilmar 8272d18aa6 Reorder MoveConstHalfToX86regPointer parameters 2022-11-07 10:43:27 +10:30
zilmar 0123100233 Core: reorder MoveConstHalfToVariable parameters 2022-11-07 10:37:29 +10:30
zilmar bdb2d040f9 Core: reorder MoveConstByteToVariable parameters 2022-11-07 10:34:25 +10:30
zilmar eb8b36603b Core: remove MoveConstByteToN64Mem, MoveConstHalfToN64Mem, MoveConstToN64Mem, MoveConstToN64MemDisp 2022-11-07 10:27:22 +10:30
zilmar 9dd2df36d4 Core: remove CX86Ops::CompVariableToX86reg 2022-11-07 10:18:55 +10:30
zilmar 09fb90117e Core: reorder CompConstToVariable parameters 2022-11-07 10:11:55 +10:30
zilmar ade6787e6d Core: Reorder AndVariableToX86Reg parameters 2022-11-07 10:00:35 +10:30
zilmar 513ca57f46 Core: Reorder parameters for AndVariableDispToX86Reg 2022-11-07 09:51:41 +10:30
zilmar 897fd39a0e Core: reorder AndConstToVariable parameters 2022-11-07 09:40:12 +10:30
zilmar c13080d7c3 Core: Reorder AddX86regToVariable parameters 2022-11-07 09:34:34 +10:30
zilmar c7ac150b91 Core: Capitalize Reg in x86ops 2022-11-07 09:31:37 +10:30
zilmar dbd20dd993 Core: Reorder AddConstToVariable parameters 2022-11-07 09:29:06 +10:30
zilmar 6a69e2e86a Core: remove CX86Ops::AdcX86regToVariable 2022-11-07 09:25:31 +10:30
zilmar b3c6858b69 Core: Change COP0 registers to use an enum 2022-11-07 09:24:58 +10:30
zilmar 94247ce1a6 Core: handle better CX86RecompilerOps::ResetMemoryStack 2022-10-28 16:41:24 +10:30
zilmar 6c9237f603 Core: Get recompiler to handle RESERVED31 2022-10-24 16:50:12 +10:30
zilmar d06d1526d9 Core: Change the order of MoveVariableToX86reg parameters 2022-10-24 16:05:19 +10:30
zilmar af3c31b0ff Core: Change the order of MoveConstToX86Pointer 2022-10-24 15:09:24 +10:30
zilmar 538933e0a5 Core: reoder MoveConstToX86reg parameters 2022-10-24 15:05:31 +10:30
zilmar dd61a4351d Core: Reorder the order of MoveX86regToX86regPointer 2022-10-24 12:56:38 +10:30
zilmar fdbc31961f Core: Change the order of MoveX86RegToX86Reg 2022-10-24 12:48:51 +10:30
zilmar 8713878994 Core: Change order of MoveX86regToX86Pointer parameters 2022-10-24 12:13:48 +10:30
zilmar ef8067cf12 Android: Make a skeleton for arm to start over arm recompiler 2022-10-24 11:15:46 +10:30
zilmar ae6157427f Recompiler: Handle stack if it is in IMEM/DMEM 2022-10-21 10:03:33 +10:30
zilmar 96244cd6fd Core: Update NonMemory Access to pifram 2022-10-17 11:31:54 +10:30
zilmar c16307ec0f Core: Move Pifram code into PifRamHandler 2022-10-17 08:27:52 +10:30
zilmar 315231d439 Core: Writing to 0x0410000C was not calling AfterCallDirect() 2022-10-11 17:31:28 +10:30
zilmar 2199c9cd1f Core: Inherit STATE_CONST_64 in CX86RecompilerOps::InheritParentInfo 2022-10-11 17:24:06 +10:30
zilmar 801a3e29fc Core: Handle more with LW and invalid addresses 2022-10-10 20:25:16 +10:30