zilmar
|
3164caf2d0
|
Core: allow Store/load ops be forced to 32bit version
|
2024-12-08 11:15:39 +10:30 |
|
zilmar
|
315d5b9e66
|
Core: When running as recompiler in 32bit mode, if LW/SW are in delay slots on block boundaries use 32bit interpter functions
|
2024-11-21 19:13:56 +10:30 |
|
zilmar
|
5750d3df80
|
Core: Have only one function to do what R4300iOp::ExecuteOps and R4300iOp::ExecuteCPU was doing
|
2024-10-24 09:59:41 +10:30 |
|
zilmar
|
62bf10e505
|
Core: Have fpu ops check the input of fs and ft at the same time
|
2024-09-26 16:38:25 +09:30 |
|
zilmar
|
91f9cdaaa7
|
Core: Change the Program counter to be 64bit
|
2024-06-06 14:09:12 +09:30 |
|
zilmar
|
5fec3f8d31
|
Core: remove the global of g_TLB
|
2023-12-14 12:09:24 +10:30 |
|
zilmar
|
d58168bcb9
|
Core: R4300iOp access the registers directly, not through CSystemRegisters
|
2023-10-19 12:52:33 +10:30 |
|
zilmar
|
4d78f56aa2
|
Core: In R4300iOp have a member variable for system, reg, mmu
|
2023-10-19 12:31:26 +10:30 |
|
zilmar
|
ae0097550f
|
Core: Make R4300iOp opcodes not static
|
2023-10-19 11:43:32 +10:30 |
|
zilmar
|
7f42f70283
|
Core: Make R4300iOp::ExecuteCPU() and R4300iOp::ExecuteOps(int32_t Cycles) non static
|
2023-10-19 10:28:25 +10:30 |
|
zilmar
|
d3edbf6dda
|
Core: move CInterpreterCPU into R4300iOp
|
2023-10-19 09:32:42 +10:30 |
|
zilmar
|
c02858c7a0
|
Core: Add LLD opcode
|
2023-09-14 16:31:37 +09:30 |
|
zilmar
|
ae4af8746b
|
Core: replace GenerateTLBReadException and void GenerateTLBWriteException with CRegisters::DoTLBReadMiss/CRegisters::DoTLBWriteMiss
|
2023-09-14 13:09:11 +09:30 |
|
zilmar
|
7199096748
|
Core: Merge CheckFPUException into CheckFPUResult64
|
2023-08-31 18:52:34 +09:30 |
|
zilmar
|
6884c8d2c9
|
Core: fix up how recompiler handles rounding
|
2023-08-17 15:24:57 +09:30 |
|
zilmar
|
a39ebe7d37
|
Core: Create InitFpuOperation
|
2023-05-27 10:01:19 +09:30 |
|
zilmar
|
b438fddf2e
|
Core: Add CP2 handling
|
2023-05-18 18:04:41 +09:30 |
|
zilmar
|
59a1277bed
|
Core: Convert GenerateOverflowException to TriggerException
|
2023-05-18 11:05:27 +09:30 |
|
zilmar
|
5a23f48629
|
Core: remove Double_RoundToInteger32
|
2023-05-09 12:57:08 +09:30 |
|
zilmar
|
2c19c2c362
|
Core: Handle CPO1 unimplemented op
|
2023-05-09 11:28:59 +09:30 |
|
zilmar
|
49a385e743
|
Core: Split CheckFPUException into CheckFPUException and CheckFPUInvalidException
|
2023-05-09 08:06:15 +09:30 |
|
zilmar
|
5cfb80fcfc
|
Core: Improve R4300iOp::COP1_S_CVT_W
|
2023-04-24 19:02:00 +09:30 |
|
zilmar
|
71ef28fd55
|
Core: Add R4300iOp::COP1_W_CVT_W
|
2023-04-24 18:55:06 +09:30 |
|
zilmar
|
9297b1c4b8
|
Core: Improve COP1_S_CVT_D, COP1_W_CVT_D, COP1_D_CVT_S, COP1_W_CVT_S, COP1_L_CVT_S,
|
2023-04-11 16:20:24 +09:30 |
|
zilmar
|
9a04293a67
|
Update arm/arm64 to use asmjit
|
2023-04-05 10:16:21 +09:30 |
|
zilmar
|
2c40d47a34
|
Start to look at x64 recompiler
|
2023-04-04 17:44:42 +09:30 |
|
zilmar
|
306f21b5fa
|
Core: Improve accuracy of add.d
|
2023-03-06 18:28:32 +10:30 |
|
zilmar
|
1864adcb35
|
Core: improve the accuracy of COP1_S_ADD
|
2023-02-21 14:54:22 +10:30 |
|
zilmar
|
83a7d9e3f2
|
Core: Start to improve the accuracy of R4300iOp::COP1_S_ADD
|
2023-01-30 20:36:58 +10:30 |
|
zilmar
|
7affd514c0
|
Core: Convert TEST_COP1_USABLE_EXCEPTION from a macro to a function
|
2023-01-30 11:40:03 +10:30 |
|
zilmar
|
80aecdc5e3
|
Core: Improve R4300iOp::COP1_CT
|
2023-01-02 19:49:19 +10:30 |
|
zilmar
|
6c154f6547
|
Core: Add Cop2/Cop3 handling exception
|
2022-12-12 21:29:16 +10:30 |
|
zilmar
|
761a1ee52a
|
Code clean up
|
2022-10-10 10:52:17 +10:30 |
|
zilmar
|
a2981ff4d8
|
Core: Make Load/Store use 64bit vaddr
|
2022-09-19 21:36:36 +09:30 |
|
zilmar
|
1c77f6f0fd
|
Core: Make Cop0 64bit
|
2022-09-19 16:36:44 +09:30 |
|
zilmar
|
05d46c9487
|
Core: Handle reserve instruction 31
|
2022-09-19 12:12:08 +09:30 |
|
zilmar
|
18b9892bc7
|
Core: Add handling of overflow exception
|
2022-09-05 16:35:13 +09:30 |
|
zilmar
|
71ddfd885d
|
Core: Add BGEZALL to interrupter
|
2022-08-15 10:18:51 +09:30 |
|
zilmar
|
e724595ac2
|
Core: Add DADDI
|
2022-08-15 10:05:16 +09:30 |
|
zilmar
|
0419ba232e
|
Core: Add option to step code at break opcode
|
2022-08-01 11:43:17 +09:30 |
|
zilmar
|
7f3b8e3601
|
Core: Start to add R4300iInstruction to do analysis of an opcode
|
2022-07-18 18:01:00 +09:30 |
|
zilmar
|
86aa483a38
|
Core: Move memory exceptions out of interrupter ops and in to Memory Manager
|
2022-06-13 11:24:36 +09:30 |
|
zilmar
|
718d7e0359
|
[Core] Clean up load/store usage in MemoryVirtualMem
|
2022-05-09 10:06:10 +09:30 |
|
zilmar
|
7fd239cf82
|
Core: Change NextInstruction to PipelineStage
|
2022-01-18 18:17:21 +10:30 |
|
zilmar
|
ee864797ab
|
vgturtle127's Beautification 14 - Source\Project64-video directory and final cleanup
|
2021-05-18 21:21:36 +09:30 |
|
zilmar
|
c512a592a7
|
Move class out of file names
|
2021-04-14 15:04:15 +09:30 |
|
zilmar
|
5c60ea213f
|
Update copyright date
|
2021-03-02 12:43:17 +10:30 |
|
KrimtonZ
|
b9be612ac5
|
add remaining trap instructions, properly implement traps for the interpreter core
|
2019-12-16 14:15:26 -06:00 |
|
zilmar
|
9729fad9da
|
[Debugger] Add store breakpoints to recompiler
|
2018-02-13 18:16:53 +11:00 |
|
zilmar
|
076280b9ba
|
[Debugger] Add unaligned write breakpoints
|
2018-02-02 04:28:08 +11:00 |