From fd05d9f42fe38e92a32ac30b18f22cb3707ee8af Mon Sep 17 00:00:00 2001 From: zilmar Date: Thu, 21 Nov 2024 21:33:42 +1030 Subject: [PATCH] core: if lwl or lwr, in CX86RecompilerOps::CompileLoadMemoryValue, make sure that we are loading rt --- .../N64System/Recompiler/x86/x86RecompilerOps.cpp | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Source/Project64-core/N64System/Recompiler/x86/x86RecompilerOps.cpp b/Source/Project64-core/N64System/Recompiler/x86/x86RecompilerOps.cpp index 5daef0bde..4cd47fff2 100644 --- a/Source/Project64-core/N64System/Recompiler/x86/x86RecompilerOps.cpp +++ b/Source/Project64-core/N64System/Recompiler/x86/x86RecompilerOps.cpp @@ -9773,8 +9773,13 @@ void CX86RecompilerOps::CompileLoadMemoryValue(asmjit::x86::Gp & AddressReg, con { if (ValueSize == 32 && m_Instruction.WritesGPR() > 0) { + int32_t LoadReg = m_Opcode.rt == m_Opcode.base ? m_Opcode.base : -1; + if (m_Opcode.op == R4300i_LWL || m_Opcode.op == R4300i_LWR) + { + LoadReg = m_Opcode.rt; + } m_RegWorkingSet.ProtectGPR(m_Opcode.base); - m_RegWorkingSet.Map_GPR_32bit(m_Opcode.rt, true, m_Opcode.rt != m_Opcode.base ? -1 : m_Opcode.base); + m_RegWorkingSet.Map_GPR_32bit(m_Opcode.rt, true, LoadReg); } asmjit::Label Load64AddrDone; if (ValueSize == 32 && m_RegWorkingSet.IsMapped(m_Opcode.base) && m_RegWorkingSet.Is32Bit(m_Opcode.base) && !m_RegWorkingSet.IsSigned(m_Opcode.base))