Core: Change COP0 Status register to a struct breaking up the bits
This commit is contained in:
parent
9ffd87168a
commit
fcd7257adc
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@ -27,10 +27,10 @@ void CInterpreterCPU::BuildCPU()
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void CInterpreterCPU::InPermLoop()
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void CInterpreterCPU::InPermLoop()
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{
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{
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if (EndOnPermLoop() &&
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if (EndOnPermLoop() &&
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((g_Reg->STATUS_REGISTER & STATUS_IE) == 0 ||
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((g_Reg->STATUS_REGISTER.InterruptEnable) == 0 ||
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(g_Reg->STATUS_REGISTER & STATUS_EXL) != 0 ||
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(g_Reg->STATUS_REGISTER.ExceptionLevel) != 0 ||
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(g_Reg->STATUS_REGISTER & STATUS_ERL) != 0 ||
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(g_Reg->STATUS_REGISTER.ErrorLevel) != 0 ||
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(g_Reg->STATUS_REGISTER & 0xFF00) == 0))
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(g_Reg->STATUS_REGISTER.InterruptMask) == 0))
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{
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{
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if (g_Plugins->Gfx()->UpdateScreen != nullptr)
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if (g_Plugins->Gfx()->UpdateScreen != nullptr)
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{
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{
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@ -1869,15 +1869,15 @@ void R4300iOp::COP0_CO_TLBP()
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void R4300iOp::COP0_CO_ERET()
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void R4300iOp::COP0_CO_ERET()
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{
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{
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g_System->m_PipelineStage = PIPELINE_STAGE_JUMP;
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g_System->m_PipelineStage = PIPELINE_STAGE_JUMP;
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if ((g_Reg->STATUS_REGISTER & STATUS_ERL) != 0)
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if ((g_Reg->STATUS_REGISTER.ErrorLevel) != 0)
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{
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{
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g_System->m_JumpToLocation = (uint32_t)g_Reg->ERROREPC_REGISTER;
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g_System->m_JumpToLocation = (uint32_t)g_Reg->ERROREPC_REGISTER;
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g_Reg->STATUS_REGISTER &= ~STATUS_ERL;
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g_Reg->STATUS_REGISTER.ErrorLevel = 0;
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}
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}
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else
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else
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{
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{
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g_System->m_JumpToLocation = (uint32_t)g_Reg->EPC_REGISTER;
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g_System->m_JumpToLocation = (uint32_t)g_Reg->EPC_REGISTER;
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g_Reg->STATUS_REGISTER &= ~STATUS_EXL;
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g_Reg->STATUS_REGISTER.ExceptionLevel = 0;
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}
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}
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(*_LLBit) = 0;
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(*_LLBit) = 0;
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g_Reg->CheckInterrupts();
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g_Reg->CheckInterrupts();
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@ -2928,12 +2928,12 @@ void R4300iOp::COP1_L_CVT_D()
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// COP2 functions
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// COP2 functions
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void R4300iOp::CPO2_INVALID_OP(void)
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void R4300iOp::CPO2_INVALID_OP(void)
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{
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{
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g_Reg->TriggerException((g_Reg->STATUS_REGISTER & STATUS_CU2) == 0 ? EXC_CPU : EXC_II, 2);
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g_Reg->TriggerException(g_Reg->STATUS_REGISTER.CU2 == 0 ? EXC_CPU : EXC_II, 2);
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}
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}
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void R4300iOp::COP2_MF()
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void R4300iOp::COP2_MF()
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{
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{
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if ((g_Reg->STATUS_REGISTER & STATUS_CU2) == 0)
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if (g_Reg->STATUS_REGISTER.CU2 == 0)
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{
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{
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g_Reg->TriggerException(EXC_CPU, 2);
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g_Reg->TriggerException(EXC_CPU, 2);
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}
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}
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@ -2945,7 +2945,7 @@ void R4300iOp::COP2_MF()
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void R4300iOp::COP2_DMF()
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void R4300iOp::COP2_DMF()
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{
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{
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if ((g_Reg->STATUS_REGISTER & STATUS_CU2) == 0)
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if (g_Reg->STATUS_REGISTER.CU2 == 0)
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{
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{
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g_Reg->TriggerException(EXC_CPU, 2);
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g_Reg->TriggerException(EXC_CPU, 2);
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}
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}
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@ -2957,7 +2957,7 @@ void R4300iOp::COP2_DMF()
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void R4300iOp::COP2_CF()
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void R4300iOp::COP2_CF()
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{
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{
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if ((g_Reg->STATUS_REGISTER & STATUS_CU2) == 0)
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if (g_Reg->STATUS_REGISTER.CU2 == 0)
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{
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{
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g_Reg->TriggerException(EXC_CPU, 2);
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g_Reg->TriggerException(EXC_CPU, 2);
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}
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}
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@ -2969,7 +2969,7 @@ void R4300iOp::COP2_CF()
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void R4300iOp::COP2_MT()
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void R4300iOp::COP2_MT()
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{
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{
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if ((g_Reg->STATUS_REGISTER & STATUS_CU2) == 0)
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if (g_Reg->STATUS_REGISTER.CU2 == 0)
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{
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{
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g_Reg->TriggerException(EXC_CPU, 2);
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g_Reg->TriggerException(EXC_CPU, 2);
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}
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}
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@ -2981,7 +2981,7 @@ void R4300iOp::COP2_MT()
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void R4300iOp::COP2_DMT()
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void R4300iOp::COP2_DMT()
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{
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{
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if ((g_Reg->STATUS_REGISTER & STATUS_CU2) == 0)
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if (g_Reg->STATUS_REGISTER.CU2 == 0)
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{
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{
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g_Reg->TriggerException(EXC_CPU, 2);
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g_Reg->TriggerException(EXC_CPU, 2);
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}
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}
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@ -2993,7 +2993,7 @@ void R4300iOp::COP2_DMT()
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void R4300iOp::COP2_CT()
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void R4300iOp::COP2_CT()
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{
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{
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if ((g_Reg->STATUS_REGISTER & STATUS_CU2) == 0)
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if (g_Reg->STATUS_REGISTER.CU2 == 0)
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{
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{
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g_Reg->TriggerException(EXC_CPU, 2);
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g_Reg->TriggerException(EXC_CPU, 2);
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}
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}
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@ -3074,7 +3074,7 @@ void R4300iOp::GenerateTLBWriteException(uint64_t VAddr, const char * function)
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bool R4300iOp::TestCop1UsableException(void)
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bool R4300iOp::TestCop1UsableException(void)
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{
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{
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if ((g_Reg->STATUS_REGISTER & STATUS_CU1) == 0)
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if (g_Reg->STATUS_REGISTER.CU1 == 0)
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{
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{
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g_Reg->TriggerException(EXC_CPU, 1);
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g_Reg->TriggerException(EXC_CPU, 1);
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return true;
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return true;
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@ -239,7 +239,7 @@ CP0registers::CP0registers(uint64_t * _CP0) :
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COUNT_REGISTER(_CP0[9]),
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COUNT_REGISTER(_CP0[9]),
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ENTRYHI_REGISTER(_CP0[10]),
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ENTRYHI_REGISTER(_CP0[10]),
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COMPARE_REGISTER(_CP0[11]),
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COMPARE_REGISTER(_CP0[11]),
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STATUS_REGISTER(_CP0[12]),
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STATUS_REGISTER((COP0Status &)_CP0[12]),
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CAUSE_REGISTER((COP0Cause &)_CP0[13]),
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CAUSE_REGISTER((COP0Cause &)_CP0[13]),
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EPC_REGISTER(_CP0[14]),
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EPC_REGISTER(_CP0[14]),
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PREVID_REGISTER(_CP0[15]),
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PREVID_REGISTER(_CP0[15]),
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@ -411,8 +411,8 @@ void CRegisters::Cop0_MT(COP0Reg Reg, uint64_t Value)
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break;
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break;
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case COP0Reg_Status:
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case COP0Reg_Status:
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{
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{
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bool FRBitChanged = (m_CP0[Reg] & STATUS_FR) != (Value & STATUS_FR);
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bool FRBitChanged = STATUS_REGISTER.FR != ((COP0Status &)Value).FR;
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m_CP0[Reg] = Value & 0xFFF7FFFF;
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STATUS_REGISTER.Value = Value & 0xFFF7FFFF;
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if (FRBitChanged)
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if (FRBitChanged)
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{
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{
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FixFpuLocations();
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FixFpuLocations();
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@ -490,7 +490,7 @@ void CRegisters::Cop2_MT(uint32_t /*Reg*/, uint64_t Value)
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void CRegisters::CheckInterrupts()
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void CRegisters::CheckInterrupts()
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{
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{
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uint32_t mi_intr_reg = MI_INTR_REG, status_register;
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uint32_t mi_intr_reg = MI_INTR_REG;
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if (!m_System->bFixedAudio() && CpuType() != CPU_SyncCores)
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if (!m_System->bFixedAudio() && CpuType() != CPU_SyncCores)
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{
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{
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mi_intr_reg &= ~MI_INTR_AI;
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mi_intr_reg &= ~MI_INTR_AI;
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@ -507,22 +507,14 @@ void CRegisters::CheckInterrupts()
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CAUSE_REGISTER.PendingInterrupts &= ~CAUSE_IP2;
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CAUSE_REGISTER.PendingInterrupts &= ~CAUSE_IP2;
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}
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}
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MI_INTR_REG = mi_intr_reg;
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MI_INTR_REG = mi_intr_reg;
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status_register = (uint32_t)STATUS_REGISTER;
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COP0Status STATUS_REGISTER_Value = STATUS_REGISTER;
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if ((status_register & STATUS_IE) == 0)
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if (STATUS_REGISTER_Value.InterruptEnable == 0 || STATUS_REGISTER_Value.ExceptionLevel != 0 || STATUS_REGISTER_Value.ErrorLevel != 0)
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{
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return;
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}
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if ((status_register & STATUS_EXL) != 0)
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{
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return;
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}
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if ((status_register & STATUS_ERL) != 0)
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{
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{
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return;
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return;
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}
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}
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if ((status_register & CAUSE_REGISTER.Value & 0xFF00) != 0)
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if ((STATUS_REGISTER_Value.Value & CAUSE_REGISTER.Value & 0xFF00) != 0)
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{
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{
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if (m_FirstInterupt)
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if (m_FirstInterupt)
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{
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{
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@ -567,13 +559,13 @@ void CRegisters::DoAddressError(bool DelaySlot, uint64_t BadVaddr, bool FromRead
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CAUSE_REGISTER.BranchDelay = 0;
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CAUSE_REGISTER.BranchDelay = 0;
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EPC_REGISTER = (int32_t)m_PROGRAM_COUNTER;
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EPC_REGISTER = (int32_t)m_PROGRAM_COUNTER;
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}
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}
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STATUS_REGISTER |= STATUS_EXL;
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STATUS_REGISTER.ExceptionLevel = 1;
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m_PROGRAM_COUNTER = 0x80000180;
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m_PROGRAM_COUNTER = 0x80000180;
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}
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}
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void CRegisters::FixFpuLocations()
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void CRegisters::FixFpuLocations()
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{
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{
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if ((STATUS_REGISTER & STATUS_FR) == 0)
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if (STATUS_REGISTER.FR == 0)
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{
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{
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for (int count = 0; count < 32; count++)
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for (int count = 0; count < 32; count++)
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{
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{
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@ -593,7 +585,7 @@ void CRegisters::FixFpuLocations()
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bool CRegisters::DoIntrException()
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bool CRegisters::DoIntrException()
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{
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{
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if ((STATUS_REGISTER & STATUS_IE) == 0 || (STATUS_REGISTER & STATUS_EXL) != 0 || (STATUS_REGISTER & STATUS_ERL) != 0)
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if (STATUS_REGISTER.InterruptEnable == 0 || STATUS_REGISTER.ExceptionLevel != 0 || STATUS_REGISTER.ErrorLevel != 0)
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{
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{
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return false;
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return false;
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}
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}
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@ -608,7 +600,7 @@ void CRegisters::DoTLBReadMiss(bool DelaySlot, uint64_t BadVaddr)
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BAD_VADDR_REGISTER = BadVaddr;
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BAD_VADDR_REGISTER = BadVaddr;
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CONTEXT_REGISTER.BadVPN2 = BadVaddr >> 13;
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CONTEXT_REGISTER.BadVPN2 = BadVaddr >> 13;
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ENTRYHI_REGISTER = (BadVaddr & 0xFFFFE000);
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ENTRYHI_REGISTER = (BadVaddr & 0xFFFFE000);
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if ((STATUS_REGISTER & STATUS_EXL) == 0)
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if ((STATUS_REGISTER.ExceptionLevel) == 0)
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{
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{
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if (DelaySlot)
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if (DelaySlot)
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{
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{
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@ -628,7 +620,7 @@ void CRegisters::DoTLBReadMiss(bool DelaySlot, uint64_t BadVaddr)
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{
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{
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m_PROGRAM_COUNTER = 0x80000000;
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m_PROGRAM_COUNTER = 0x80000000;
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}
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}
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STATUS_REGISTER |= STATUS_EXL;
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STATUS_REGISTER.ExceptionLevel = 1;
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}
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}
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else
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else
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{
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{
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@ -647,7 +639,7 @@ void CRegisters::DoTLBWriteMiss(bool DelaySlot, uint64_t BadVaddr)
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BAD_VADDR_REGISTER = BadVaddr;
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BAD_VADDR_REGISTER = BadVaddr;
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CONTEXT_REGISTER.BadVPN2 = BadVaddr >> 13;
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CONTEXT_REGISTER.BadVPN2 = BadVaddr >> 13;
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ENTRYHI_REGISTER = (BadVaddr & 0xFFFFE000);
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ENTRYHI_REGISTER = (BadVaddr & 0xFFFFE000);
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if ((STATUS_REGISTER & STATUS_EXL) == 0)
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if ((STATUS_REGISTER.ExceptionLevel) == 0)
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{
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{
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if (DelaySlot)
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if (DelaySlot)
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{
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{
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@ -667,7 +659,7 @@ void CRegisters::DoTLBWriteMiss(bool DelaySlot, uint64_t BadVaddr)
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{
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{
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m_PROGRAM_COUNTER = 0x80000000;
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m_PROGRAM_COUNTER = 0x80000000;
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}
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}
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STATUS_REGISTER |= STATUS_EXL;
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STATUS_REGISTER.ExceptionLevel = 1;
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}
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}
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else
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else
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{
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{
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@ -697,7 +689,7 @@ void CRegisters::TriggerException(uint32_t ExceptionCode, uint32_t Coprocessor)
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CAUSE_REGISTER.CoprocessorUnitNumber = Coprocessor;
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CAUSE_REGISTER.CoprocessorUnitNumber = Coprocessor;
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CAUSE_REGISTER.BranchDelay = m_System->m_PipelineStage == PIPELINE_STAGE_JUMP;
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CAUSE_REGISTER.BranchDelay = m_System->m_PipelineStage == PIPELINE_STAGE_JUMP;
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EPC_REGISTER = (int64_t)((int32_t)m_PROGRAM_COUNTER - (CAUSE_REGISTER.BranchDelay ? 4 : 0));
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EPC_REGISTER = (int64_t)((int32_t)m_PROGRAM_COUNTER - (CAUSE_REGISTER.BranchDelay ? 4 : 0));
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STATUS_REGISTER |= STATUS_EXL;
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STATUS_REGISTER.ExceptionLevel = 1;
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m_System->m_PipelineStage = PIPELINE_STAGE_JUMP;
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m_System->m_PipelineStage = PIPELINE_STAGE_JUMP;
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m_System->m_JumpToLocation = 0x80000180;
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m_System->m_JumpToLocation = 0x80000180;
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}
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}
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@ -19,6 +19,46 @@
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#pragma warning(push)
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#pragma warning(push)
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#pragma warning(disable : 4201) // Non-standard extension used: nameless struct/union
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#pragma warning(disable : 4201) // Non-standard extension used: nameless struct/union
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enum PRIVILEGE_MODE : unsigned
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{
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PrivilegeMode_Kernel,
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PrivilegeMode_Supervisor,
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PrivilegeMode_User
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};
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union COP0Status
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{
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uint64_t Value;
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struct
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{
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unsigned InterruptEnable : 1;
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unsigned ExceptionLevel : 1;
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unsigned ErrorLevel : 1;
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PRIVILEGE_MODE PrivilegeMode : 2;
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unsigned UserExtendedAddressing : 1;
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unsigned SupervisorExtendedAddressing : 1;
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unsigned KernelExtendedAddressing : 1;
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unsigned InterruptMask : 8;
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unsigned DE : 1;
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unsigned CE : 1;
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unsigned CH : 1;
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unsigned NMI : 1;
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unsigned SR : 1;
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unsigned TS : 1;
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unsigned BEV : 1;
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unsigned : 1;
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unsigned : 1;
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unsigned RE : 1;
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unsigned FR : 1;
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unsigned RP : 1;
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unsigned CU0 : 1;
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unsigned CU1 : 1;
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unsigned CU2 : 1;
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unsigned CU3 : 1;
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};
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};
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union COP0Cause
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union COP0Cause
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{
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{
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uint64_t Value;
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uint64_t Value;
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@ -137,7 +177,7 @@ public:
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uint64_t & COUNT_REGISTER;
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uint64_t & COUNT_REGISTER;
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uint64_t & ENTRYHI_REGISTER;
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uint64_t & ENTRYHI_REGISTER;
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uint64_t & COMPARE_REGISTER;
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uint64_t & COMPARE_REGISTER;
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uint64_t & STATUS_REGISTER;
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COP0Status & STATUS_REGISTER;
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COP0Cause & CAUSE_REGISTER;
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COP0Cause & CAUSE_REGISTER;
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uint64_t & EPC_REGISTER;
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uint64_t & EPC_REGISTER;
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uint64_t & PREVID_REGISTER;
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uint64_t & PREVID_REGISTER;
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@ -897,7 +897,7 @@ void CN64System::PluginReset()
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void CN64System::ApplyGSButton(void)
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void CN64System::ApplyGSButton(void)
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{
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{
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if ((m_Reg.STATUS_REGISTER & STATUS_IE) != 0)
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if (m_Reg.STATUS_REGISTER.InterruptEnable != 0)
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{
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{
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g_Enhancements->ApplyGSButton(m_MMU_VM, !m_SyncSystem);
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g_Enhancements->ApplyGSButton(m_MMU_VM, !m_SyncSystem);
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}
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}
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@ -1037,7 +1037,7 @@ void CN64System::InitRegisters(bool bPostPif, CMipsMemoryVM & MMU)
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m_Reg.ERROREPC_REGISTER = 0xFFFFFFFFFFFFFFFF;
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m_Reg.ERROREPC_REGISTER = 0xFFFFFFFFFFFFFFFF;
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m_Reg.PREVID_REGISTER = 0x00000B22;
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m_Reg.PREVID_REGISTER = 0x00000B22;
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m_Reg.CONFIG_REGISTER = 0x7006E463;
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m_Reg.CONFIG_REGISTER = 0x7006E463;
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m_Reg.STATUS_REGISTER = 0x34000000;
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m_Reg.STATUS_REGISTER.Value = 0x34000000;
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// N64DD registers
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// N64DD registers
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||||||
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|
||||||
|
@ -1822,9 +1822,9 @@ bool CN64System::SaveState()
|
||||||
WriteTrace(TraceN64System, TraceDebug, "Start");
|
WriteTrace(TraceN64System, TraceDebug, "Start");
|
||||||
|
|
||||||
// if (!m_SystemTimer.SaveAllowed()) { return false; }
|
// if (!m_SystemTimer.SaveAllowed()) { return false; }
|
||||||
if ((m_Reg.STATUS_REGISTER & STATUS_EXL) != 0)
|
if (m_Reg.STATUS_REGISTER.ExceptionLevel != 0)
|
||||||
{
|
{
|
||||||
WriteTrace(TraceN64System, TraceDebug, "Done - STATUS_EXL set, can't save");
|
WriteTrace(TraceN64System, TraceDebug, "Done - ExceptionLevel set, can't save");
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -2639,7 +2639,7 @@ void CN64System::RefreshScreen()
|
||||||
m_CPU_Usage.ShowCPU_Usage();
|
m_CPU_Usage.ShowCPU_Usage();
|
||||||
m_CPU_Usage.StartTimer(CPU_UsageAddr != Timer_None ? CPU_UsageAddr : Timer_R4300);
|
m_CPU_Usage.StartTimer(CPU_UsageAddr != Timer_None ? CPU_UsageAddr : Timer_R4300);
|
||||||
}
|
}
|
||||||
if ((m_Reg.STATUS_REGISTER & STATUS_IE) != 0)
|
if (m_Reg.STATUS_REGISTER.InterruptEnable != 0)
|
||||||
{
|
{
|
||||||
g_Enhancements->ApplyActive(m_MMU_VM, g_BaseSystem->m_Plugins, !m_SyncSystem);
|
g_Enhancements->ApplyActive(m_MMU_VM, g_BaseSystem->m_Plugins, !m_SyncSystem);
|
||||||
}
|
}
|
||||||
|
|
|
@ -7409,15 +7409,15 @@ void CX86RecompilerOps::COP0_CO_TLBP(void)
|
||||||
|
|
||||||
void x86_compiler_COP0_CO_ERET()
|
void x86_compiler_COP0_CO_ERET()
|
||||||
{
|
{
|
||||||
if ((g_Reg->STATUS_REGISTER & STATUS_ERL) != 0)
|
if (g_Reg->STATUS_REGISTER.ErrorLevel != 0)
|
||||||
{
|
{
|
||||||
g_Reg->m_PROGRAM_COUNTER = (uint32_t)g_Reg->ERROREPC_REGISTER;
|
g_Reg->m_PROGRAM_COUNTER = (uint32_t)g_Reg->ERROREPC_REGISTER;
|
||||||
g_Reg->STATUS_REGISTER &= ~STATUS_ERL;
|
g_Reg->STATUS_REGISTER.ErrorLevel = 0;
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
g_Reg->m_PROGRAM_COUNTER = (uint32_t)g_Reg->EPC_REGISTER;
|
g_Reg->m_PROGRAM_COUNTER = (uint32_t)g_Reg->EPC_REGISTER;
|
||||||
g_Reg->STATUS_REGISTER &= ~STATUS_EXL;
|
g_Reg->STATUS_REGISTER.ExceptionLevel = 0;
|
||||||
}
|
}
|
||||||
g_Reg->m_LLBit = 0;
|
g_Reg->m_LLBit = 0;
|
||||||
g_Reg->CheckInterrupts();
|
g_Reg->CheckInterrupts();
|
||||||
|
|
|
@ -143,7 +143,7 @@ void CRegisterTabs::RefreshEdits()
|
||||||
m_COP0Edits[8].SetValue((uint32_t)g_Reg->COUNT_REGISTER, DisplayMode::ZeroExtend);
|
m_COP0Edits[8].SetValue((uint32_t)g_Reg->COUNT_REGISTER, DisplayMode::ZeroExtend);
|
||||||
m_COP0Edits[9].SetValue((uint32_t)g_Reg->ENTRYHI_REGISTER, DisplayMode::ZeroExtend);
|
m_COP0Edits[9].SetValue((uint32_t)g_Reg->ENTRYHI_REGISTER, DisplayMode::ZeroExtend);
|
||||||
m_COP0Edits[10].SetValue((uint32_t)g_Reg->COMPARE_REGISTER, DisplayMode::ZeroExtend);
|
m_COP0Edits[10].SetValue((uint32_t)g_Reg->COMPARE_REGISTER, DisplayMode::ZeroExtend);
|
||||||
m_COP0Edits[11].SetValue((uint32_t)g_Reg->STATUS_REGISTER, DisplayMode::ZeroExtend);
|
m_COP0Edits[11].SetValue((uint32_t)g_Reg->STATUS_REGISTER.Value, DisplayMode::ZeroExtend);
|
||||||
m_COP0Edits[12].SetValue((uint32_t)g_Reg->CAUSE_REGISTER.Value, DisplayMode::ZeroExtend);
|
m_COP0Edits[12].SetValue((uint32_t)g_Reg->CAUSE_REGISTER.Value, DisplayMode::ZeroExtend);
|
||||||
m_COP0Edits[13].SetValue((uint32_t)g_Reg->EPC_REGISTER, DisplayMode::ZeroExtend);
|
m_COP0Edits[13].SetValue((uint32_t)g_Reg->EPC_REGISTER, DisplayMode::ZeroExtend);
|
||||||
m_COP0Edits[14].SetValue((uint32_t)g_Reg->CONFIG_REGISTER, DisplayMode::ZeroExtend);
|
m_COP0Edits[14].SetValue((uint32_t)g_Reg->CONFIG_REGISTER, DisplayMode::ZeroExtend);
|
||||||
|
@ -322,7 +322,7 @@ void CRegisterTabs::RegisterChanged(HWND hDlg, TAB_ID srcTabId, WPARAM wParam)
|
||||||
case IDC_COP0_8_EDIT: g_Reg->COUNT_REGISTER = value; break;
|
case IDC_COP0_8_EDIT: g_Reg->COUNT_REGISTER = value; break;
|
||||||
case IDC_COP0_9_EDIT: g_Reg->ENTRYHI_REGISTER = value; break;
|
case IDC_COP0_9_EDIT: g_Reg->ENTRYHI_REGISTER = value; break;
|
||||||
case IDC_COP0_10_EDIT: g_Reg->COMPARE_REGISTER = value; break;
|
case IDC_COP0_10_EDIT: g_Reg->COMPARE_REGISTER = value; break;
|
||||||
case IDC_COP0_11_EDIT: g_Reg->STATUS_REGISTER = value; break;
|
case IDC_COP0_11_EDIT: g_Reg->STATUS_REGISTER.Value = value; break;
|
||||||
case IDC_COP0_12_EDIT: g_Reg->CAUSE_REGISTER.Value = value; break;
|
case IDC_COP0_12_EDIT: g_Reg->CAUSE_REGISTER.Value = value; break;
|
||||||
case IDC_COP0_13_EDIT: g_Reg->EPC_REGISTER = value; break;
|
case IDC_COP0_13_EDIT: g_Reg->EPC_REGISTER = value; break;
|
||||||
case IDC_COP0_14_EDIT: g_Reg->CONFIG_REGISTER = value; break;
|
case IDC_COP0_14_EDIT: g_Reg->CONFIG_REGISTER = value; break;
|
||||||
|
|
|
@ -630,7 +630,7 @@ void CDebuggerUI::CPUStepStarted()
|
||||||
|
|
||||||
if (pc == 0x80000000 || pc == 0x80000080 || pc == 0xA0000100 || pc == 0x80000180)
|
if (pc == 0x80000000 || pc == 0x80000080 || pc == 0xA0000100 || pc == 0x80000180)
|
||||||
{
|
{
|
||||||
if ((g_Reg->STATUS_REGISTER >> 1) & 3) // If EXL/ERL bits are set
|
if (g_Reg->STATUS_REGISTER.ExceptionLevel != 0 || g_Reg->STATUS_REGISTER.ErrorLevel != 0) // If EXL/ERL bits are set
|
||||||
{
|
{
|
||||||
HandleCPUException();
|
HandleCPUException();
|
||||||
}
|
}
|
||||||
|
|
Loading…
Reference in New Issue