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Core: Add DwordLower for cvt.w

This commit is contained in:
zilmar 2024-12-26 09:35:07 +10:30
parent 7e74b98d5b
commit fc79cb0344
3 changed files with 10 additions and 8 deletions
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6
Source/Project64-core/N64System/Recompiler/x86/x86RecompilerOps.cpp
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@ -8140,12 +8140,12 @@ void CX86RecompilerOps::COP1_D_CMP()
// COP1: W functions // COP1: W functions
void CX86RecompilerOps::COP1_W_CVT_S() void CX86RecompilerOps::COP1_W_CVT_S()
{ {
COP1_S_CVT(CRegInfo::RoundDefault, CRegInfo::FPU_Dword, CRegInfo::FPU_Float); COP1_S_CVT(CRegInfo::RoundDefault, CRegInfo::FPU_DwordLow, CRegInfo::FPU_Float);
} }
void CX86RecompilerOps::COP1_W_CVT_D() void CX86RecompilerOps::COP1_W_CVT_D()
{ {
COP1_S_CVT(CRegInfo::RoundDefault, CRegInfo::FPU_Dword, CRegInfo::FPU_Double); COP1_S_CVT(CRegInfo::RoundDefault, CRegInfo::FPU_DwordLow, CRegInfo::FPU_Double);
} }
// COP1: L functions // COP1: L functions
@ -11581,7 +11581,7 @@ void CX86RecompilerOps::COP1_S_CVT(CRegBase::FPU_ROUND RoundMethod, CRegInfo::FP
CompileCheckFPUInput(fsRegPointer, FpuOpSize_64bit, (NewFormat == CRegInfo::FPU_Dword || NewFormat == CRegInfo::FPU_Qword)); CompileCheckFPUInput(fsRegPointer, FpuOpSize_64bit, (NewFormat == CRegInfo::FPU_Dword || NewFormat == CRegInfo::FPU_Qword));
m_Assembler.fpuLoadQwordFromX86Reg(m_RegWorkingSet.StackTopPos(), fsRegPointer); m_Assembler.fpuLoadQwordFromX86Reg(m_RegWorkingSet.StackTopPos(), fsRegPointer);
} }
else if (OldFormat == CRegInfo::FPU_Dword) else if (OldFormat == CRegInfo::FPU_Dword || OldFormat == CRegInfo::FPU_DwordLow)
{ {
m_Assembler.fpuLoadIntegerDwordFromX86Reg(m_RegWorkingSet.StackTopPos(), fsRegPointer); m_Assembler.fpuLoadIntegerDwordFromX86Reg(m_RegWorkingSet.StackTopPos(), fsRegPointer);
} }

1
Source/Project64-core/N64System/Recompiler/x86/x86RegInfo.cpp
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@ -350,6 +350,7 @@ asmjit::x86::Gp CX86RegInfo::FPRValuePointer(int32_t Reg, FPU_STATE Format)
case FPU_UnsignedDoubleWord: case FPU_UnsignedDoubleWord:
m_Assembler.MoveVariableToX86reg(TempReg, &g_Reg->m_FPR_UDW[Reg], stdstr_f("m_FPR_UDW[%d]", Reg).c_str()); m_Assembler.MoveVariableToX86reg(TempReg, &g_Reg->m_FPR_UDW[Reg], stdstr_f("m_FPR_UDW[%d]", Reg).c_str());
break; break;
case FPU_DwordLow:
case FPU_FloatLow: case FPU_FloatLow:
m_Assembler.MoveVariableToX86reg(TempReg, &g_Reg->m_FPR_S_L[Reg], stdstr_f("m_FPR_S_L[%d]", Reg).c_str()); m_Assembler.MoveVariableToX86reg(TempReg, &g_Reg->m_FPR_S_L[Reg], stdstr_f("m_FPR_S_L[%d]", Reg).c_str());
break; break;

11
Source/Project64-core/N64System/Recompiler/x86/x86RegInfo.h
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@ -59,11 +59,12 @@ public:
FPU_Any = -1, FPU_Any = -1,
FPU_Unknown = 0, FPU_Unknown = 0,
FPU_Dword = 1, FPU_Dword = 1,
FPU_Qword = 2, FPU_DwordLow = 2,
FPU_Float = 3, FPU_Qword = 3,
FPU_FloatLow = 4, FPU_Float = 4,
FPU_Double = 5, FPU_FloatLow = 5,
FPU_UnsignedDoubleWord = 6, FPU_Double = 6,
FPU_UnsignedDoubleWord = 7,
}; };
CX86RegInfo(CCodeBlock & CodeBlock, CX86Ops & Assembler); CX86RegInfo(CCodeBlock & CodeBlock, CX86Ops & Assembler);