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Core: Add a look up table for Memory Reads or Writes

This commit is contained in:
zilmar 2022-04-04 10:30:27 +09:30
parent 1eda1bb243
commit fbf65bce12
4 changed files with 473 additions and 278 deletions
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24
Source/Project64-core/N64System/Mips/Dma.cpp
View File

@ -20,27 +20,27 @@ CDMA::CDMA(CFlashram & FlashRam, CSram & Sram) :
void CDMA::OnFirstDMA() void CDMA::OnFirstDMA()
{ {
int16_t offset; int16_t offset;
const uint32_t base = 0x00000000; const uint32_t base = 0x80000000;
const uint32_t rt = g_MMU->RdramSize(); const uint32_t rt = g_MMU->RdramSize();
switch (g_Rom->CicChipID()) switch (g_Rom->CicChipID())
{ {
case CIC_NUS_6101: offset = +0x0318; break; case CIC_NUS_6101: offset = 0x0318; break;
case CIC_NUS_5167: offset = +0x0318; break; case CIC_NUS_5167: offset = 0x0318; break;
case CIC_NUS_8303: offset = +0x0318; break; case CIC_NUS_8303: offset = 0x0318; break;
case CIC_NUS_DDUS: offset = +0x0318; break; case CIC_NUS_DDUS: offset = 0x0318; break;
case CIC_NUS_8401: offset = +0x0318; break; case CIC_NUS_8401: offset = 0x0318; break;
case CIC_UNKNOWN: case CIC_UNKNOWN:
case CIC_NUS_6102: offset = +0x0318; break; case CIC_NUS_6102: offset = 0x0318; break;
case CIC_NUS_6103: offset = +0x0318; break; case CIC_NUS_6103: offset = 0x0318; break;
case CIC_NUS_6105: offset = +0x03F0; break; case CIC_NUS_6105: offset = 0x03F0; break;
case CIC_NUS_6106: offset = +0x0318; break; case CIC_NUS_6106: offset = 0x0318; break;
case CIC_NUS_5101: offset = +0x0318; break; case CIC_NUS_5101: offset = 0x0318; break;
default: default:
g_Notify->DisplayError(stdstr_f("Unhandled CicChip(%d) in first DMA", g_Rom->CicChipID()).c_str()); g_Notify->DisplayError(stdstr_f("Unhandled CicChip(%d) in first DMA", g_Rom->CicChipID()).c_str());
return; return;
} }
g_MMU->SW_PAddr(base + offset, rt); g_MMU->SW_VAddr(base + offset, rt);
} }
void CDMA::PI_DMA_READ() void CDMA::PI_DMA_READ()

345
Source/Project64-core/N64System/Mips/MemoryVirtualMem.cpp
View File

@ -40,6 +40,8 @@ CMipsMemoryVM::CMipsMemoryVM(CN64System & System, bool SavesReadOnly) :
m_VideoInterfaceHandler(System, *this, System.m_Reg), m_VideoInterfaceHandler(System, *this, System.m_Reg),
m_Rom(nullptr), m_Rom(nullptr),
m_RomSize(0), m_RomSize(0),
m_MemoryReadMap(nullptr),
m_MemoryWriteMap(nullptr),
m_RomWrittenTo(false), m_RomWrittenTo(false),
m_RomWroteValue(0), m_RomWroteValue(0),
m_TLB_ReadMap(nullptr), m_TLB_ReadMap(nullptr),
@ -79,28 +81,61 @@ CMipsMemoryVM::~CMipsMemoryVM()
void CMipsMemoryVM::Reset(bool /*EraseMemory*/) void CMipsMemoryVM::Reset(bool /*EraseMemory*/)
{ {
if (m_MemoryReadMap != nullptr && m_MemoryWriteMap != nullptr)
{
memset(m_MemoryReadMap, -1, 0x100000 * sizeof(size_t));
memset(m_MemoryWriteMap, -1, 0x100000 * sizeof(size_t));
for (uint32_t i = 0; i < 2; i++)
{
uint32_t BaseAddress = i == 0 ? 0x80000000 : 0xA0000000;
for (size_t Address = BaseAddress; Address < BaseAddress + m_AllocatedRdramSize; Address += 0x1000)
{
m_MemoryReadMap[Address >> 12] = (size_t)((m_RDRAM + (Address & 0x1FFFFFFF)) - Address);
m_MemoryWriteMap[Address >> 12] = (size_t)((m_RDRAM + (Address & 0x1FFFFFFF)) - Address);
}
for (size_t Address = BaseAddress + 0x04000000; Address < (BaseAddress + 0x04001000); Address += 0x1000)
{
m_MemoryReadMap[Address >> 12] = (size_t)(m_DMEM - Address);
m_MemoryWriteMap[Address >> 12] = (size_t)(m_DMEM - Address);
}
for (size_t Address = BaseAddress + 0x04001000; Address < (BaseAddress + 0x04002000); Address += 0x1000)
{
m_MemoryReadMap[Address >> 12] = (size_t)(m_IMEM - Address);
m_MemoryWriteMap[Address >> 12] = (size_t)(m_IMEM - Address);
}
}
}
if (m_TLB_ReadMap) if (m_TLB_ReadMap)
{ {
size_t address;
memset(m_TLB_ReadMap, 0, 0xFFFFF * sizeof(size_t)); memset(m_TLB_ReadMap, 0, 0xFFFFF * sizeof(size_t));
memset(m_TLB_WriteMap, 0, 0xFFFFF * sizeof(size_t)); memset(m_TLB_WriteMap, 0, 0xFFFFF * sizeof(size_t));
for (address = 0x80000000; address < 0xC0000000; address += 0x1000) for (size_t Address = 0x80000000; Address < 0xC0000000; Address += 0x1000)
{ {
m_TLB_ReadMap[address >> 12] = ((size_t)m_RDRAM + (address & 0x1FFFFFFF)) - address; m_TLB_ReadMap[Address >> 12] = ((size_t)m_RDRAM + (Address & 0x1FFFFFFF)) - Address;
m_TLB_WriteMap[address >> 12] = ((size_t)m_RDRAM + (address & 0x1FFFFFFF)) - address; m_TLB_WriteMap[Address >> 12] = ((size_t)m_RDRAM + (Address & 0x1FFFFFFF)) - Address;
} }
if (g_Settings->LoadDword(Rdb_TLB_VAddrStart) != 0) if (g_Settings->LoadDword(Rdb_TLB_VAddrStart) != 0)
{ {
size_t Start = g_Settings->LoadDword(Rdb_TLB_VAddrStart); //0x7F000000; uint32_t Start = g_Settings->LoadDword(Rdb_TLB_VAddrStart); //0x7F000000;
size_t Len = g_Settings->LoadDword(Rdb_TLB_VAddrLen); //0x01000000; uint32_t Len = g_Settings->LoadDword(Rdb_TLB_VAddrLen); //0x01000000;
size_t PAddr = g_Settings->LoadDword(Rdb_TLB_PAddrStart); //0x10034b30; uint32_t PAddr = g_Settings->LoadDword(Rdb_TLB_PAddrStart); //0x10034b30;
size_t End = Start + Len; uint32_t End = Start + Len;
for (address = Start; address < End; address += 0x1000) for (uint32_t Address = Start; Address < End; Address += 0x1000)
{ {
m_TLB_ReadMap[address >> 12] = ((size_t)m_RDRAM + (address - Start + PAddr)) - address; uint32_t TargetAddress = (Address - Start + PAddr);
m_TLB_WriteMap[address >> 12] = ((size_t)m_RDRAM + (address - Start + PAddr)) - address; if (TargetAddress < m_AllocatedRdramSize)
{
m_MemoryReadMap[Address >> 12] = ((size_t)m_RDRAM + TargetAddress) - Address;
m_MemoryWriteMap[Address >> 12] = ((size_t)m_RDRAM + TargetAddress) - Address;
}
if (TargetAddress >= 0x10000000 && TargetAddress < (0x10000000 + m_RomSize))
{
m_MemoryReadMap[Address >> 12] = ((size_t)m_Rom + (TargetAddress - 0x10000000)) - Address;
}
m_TLB_ReadMap[Address >> 12] = ((size_t)m_RDRAM + TargetAddress) - Address;
m_TLB_WriteMap[Address >> 12] = ((size_t)m_RDRAM + TargetAddress) - Address;
} }
} }
} }
@ -222,6 +257,21 @@ bool CMipsMemoryVM::Initialize(bool SyncSystem)
CPifRam::Reset(); CPifRam::Reset();
m_MemoryReadMap = new size_t [0x100000];
if (m_MemoryReadMap == nullptr)
{
WriteTrace(TraceN64System, TraceError, "Failed to allocate m_MemoryReadMap (Size: 0x%X)", 0x100000 * sizeof(size_t));
FreeMemory();
return false;
}
m_MemoryWriteMap = new size_t [0x100000];
if (m_MemoryWriteMap == nullptr)
{
WriteTrace(TraceN64System, TraceError, "Failed to allocate m_MemoryWriteMap (Size: 0x%X)", 0x100000 * sizeof(size_t));
FreeMemory();
return false;
}
m_TLB_ReadMap = new size_t[0x100000]; m_TLB_ReadMap = new size_t[0x100000];
if (m_TLB_ReadMap == nullptr) if (m_TLB_ReadMap == nullptr)
{ {
@ -278,46 +328,37 @@ void CMipsMemoryVM::FreeMemory()
delete[] m_TLB_WriteMap; delete[] m_TLB_WriteMap;
m_TLB_WriteMap = nullptr; m_TLB_WriteMap = nullptr;
} }
if (m_MemoryReadMap)
{
delete[] m_MemoryReadMap;
m_MemoryReadMap = nullptr;
}
if (m_MemoryWriteMap)
{
delete[] m_MemoryWriteMap;
m_MemoryWriteMap = nullptr;
}
CPifRam::Reset(); CPifRam::Reset();
} }
uint8_t * CMipsMemoryVM::Rdram()
{
return m_RDRAM;
}
uint32_t CMipsMemoryVM::RdramSize()
{
return m_AllocatedRdramSize;
}
uint8_t * CMipsMemoryVM::Dmem()
{
return m_DMEM;
}
uint8_t * CMipsMemoryVM::Imem()
{
return m_IMEM;
}
uint8_t * CMipsMemoryVM::PifRam()
{
return m_PifRam;
}
CSram* CMipsMemoryVM::GetSram(void) CSram* CMipsMemoryVM::GetSram(void)
{ {
return dynamic_cast<CSram*>(this); return dynamic_cast<CSram*>(this);
} }
CFlashram* CMipsMemoryVM::GetFlashram() CFlashram* CMipsMemoryVM::GetFlashram()
{ {
return dynamic_cast<CFlashram*>(this); return dynamic_cast<CFlashram*>(this);
} }
bool CMipsMemoryVM::LB_VAddr(uint32_t VAddr, uint8_t& Value) bool CMipsMemoryVM::LB_VAddr(uint32_t VAddr, uint8_t& Value)
{ {
uint8_t * MemoryPtr = (uint8_t*)m_MemoryReadMap[VAddr >> 12];
if (MemoryPtr != (uint8_t*)-1)
{
Value = *(uint8_t*)(MemoryPtr + (VAddr ^ 3));
return true;
}
if (m_TLB_ReadMap[VAddr >> 12] == 0) if (m_TLB_ReadMap[VAddr >> 12] == 0)
{ {
return false; return false;
@ -329,6 +370,12 @@ bool CMipsMemoryVM::LB_VAddr(uint32_t VAddr, uint8_t& Value)
bool CMipsMemoryVM::LH_VAddr(uint32_t VAddr, uint16_t& Value) bool CMipsMemoryVM::LH_VAddr(uint32_t VAddr, uint16_t& Value)
{ {
uint8_t * MemoryPtr = (uint8_t*)m_MemoryReadMap[VAddr >> 12];
if (MemoryPtr != (uint8_t*)-1)
{
Value = *(uint16_t*)(MemoryPtr + (VAddr ^ 2));
return true;
}
if (m_TLB_ReadMap[VAddr >> 12] == 0) if (m_TLB_ReadMap[VAddr >> 12] == 0)
{ {
return false; return false;
@ -338,8 +385,14 @@ bool CMipsMemoryVM::LH_VAddr(uint32_t VAddr, uint16_t& Value)
return true; return true;
} }
bool CMipsMemoryVM::LW_VAddr(uint32_t VAddr, uint32_t& Value) bool CMipsMemoryVM::LW_VAddr(uint32_t VAddr, uint32_t & Value)
{ {
uint8_t * MemoryPtr = (uint8_t*)m_MemoryReadMap[VAddr >> 12];
if (MemoryPtr != (uint8_t *)-1)
{
Value = *(uint32_t*)(MemoryPtr + VAddr);
return true;
}
if (VAddr >= 0xA3F00000 && VAddr < 0xC0000000) if (VAddr >= 0xA3F00000 && VAddr < 0xC0000000)
{ {
if ((VAddr & 0xFFFFE000ul) != 0xA4000000ul) // !(A4000000 <= addr < A4002000) if ((VAddr & 0xFFFFE000ul) != 0xA4000000ul) // !(A4000000 <= addr < A4002000)
@ -358,19 +411,26 @@ bool CMipsMemoryVM::LW_VAddr(uint32_t VAddr, uint32_t& Value)
Value = *(uint32_t*)(BaseAddress + VAddr); Value = *(uint32_t*)(BaseAddress + VAddr);
// if (LookUpMode == FuncFind_ChangeMemory) // if (LookUpMode == FuncFind_ChangeMemory)
// { // {
// g_Notify->BreakPoint(__FILE__, __LINE__); // g_Notify->BreakPoint(__FILE__, __LINE__);
// if ( (Command.Hex >> 16) == 0x7C7C) // if ( (Command.Hex >> 16) == 0x7C7C)
// { // {
// Command.Hex = OrigMem[(Command.Hex & 0xFFFF)].OriginalValue; // Command.Hex = OrigMem[(Command.Hex & 0xFFFF)].OriginalValue;
// } // }
// } // }
return true; return true;
} }
bool CMipsMemoryVM::LD_VAddr(uint32_t VAddr, uint64_t& Value) bool CMipsMemoryVM::LD_VAddr(uint32_t VAddr, uint64_t& Value)
{ {
uint8_t * MemoryPtr = (uint8_t*)m_MemoryReadMap[VAddr >> 12];
if (MemoryPtr != (uint8_t *)-1)
{
*((uint32_t*)(&Value) + 1) = *(uint32_t*)(MemoryPtr + VAddr);
*((uint32_t*)(&Value) + 0) = *(uint32_t*)(MemoryPtr + VAddr + 4);
return true;
}
if (m_TLB_ReadMap[VAddr >> 12] == 0) if (m_TLB_ReadMap[VAddr >> 12] == 0)
{ {
return false; return false;
@ -381,77 +441,14 @@ bool CMipsMemoryVM::LD_VAddr(uint32_t VAddr, uint64_t& Value)
return true; return true;
} }
bool CMipsMemoryVM::LB_PAddr(uint32_t PAddr, uint8_t& Value)
{
if (PAddr < RdramSize())
{
Value = *(uint8_t*)(m_RDRAM + (PAddr ^ 3));
return true;
}
if (PAddr > 0x18000000)
{
return false;
}
g_Notify->BreakPoint(__FILE__, __LINE__);
return false;
}
bool CMipsMemoryVM::LH_PAddr(uint32_t PAddr, uint16_t& Value)
{
if (PAddr < RdramSize())
{
Value = *(uint16_t*)(m_RDRAM + (PAddr ^ 2));
return true;
}
if (PAddr > 0x18000000)
{
return false;
}
g_Notify->BreakPoint(__FILE__, __LINE__);
return false;
}
bool CMipsMemoryVM::LW_PAddr(uint32_t PAddr, uint32_t& Value)
{
if (PAddr < RdramSize())
{
Value = *(uint32_t*)(m_RDRAM + PAddr);
return true;
}
if (PAddr > 0x18000000)
{
return false;
}
g_Notify->BreakPoint(__FILE__, __LINE__);
return false;
}
bool CMipsMemoryVM::LD_PAddr(uint32_t PAddr, uint64_t& Value)
{
if (PAddr < RdramSize())
{
*((uint32_t*)(&Value) + 1) = *(uint32_t*)(m_RDRAM + PAddr);
*((uint32_t*)(&Value) + 0) = *(uint32_t*)(m_RDRAM + PAddr + 4);
return true;
}
if (PAddr > 0x18000000)
{
return false;
}
g_Notify->BreakPoint(__FILE__, __LINE__);
return false;
}
bool CMipsMemoryVM::SB_VAddr(uint32_t VAddr, uint8_t Value) bool CMipsMemoryVM::SB_VAddr(uint32_t VAddr, uint8_t Value)
{ {
uint8_t * MemoryPtr = (uint8_t*)m_MemoryWriteMap[VAddr >> 12];
if (MemoryPtr != (uint8_t *)-1)
{
*(uint8_t*)(MemoryPtr + (VAddr ^ 3)) = Value;
return true;
}
if (m_TLB_WriteMap[VAddr >> 12] == 0) if (m_TLB_WriteMap[VAddr >> 12] == 0)
{ {
return false; return false;
@ -463,6 +460,12 @@ bool CMipsMemoryVM::SB_VAddr(uint32_t VAddr, uint8_t Value)
bool CMipsMemoryVM::SH_VAddr(uint32_t VAddr, uint16_t Value) bool CMipsMemoryVM::SH_VAddr(uint32_t VAddr, uint16_t Value)
{ {
uint8_t * MemoryPtr = (uint8_t*)m_MemoryWriteMap[VAddr >> 12];
if (MemoryPtr != (uint8_t *)-1)
{
*(uint16_t*)(MemoryPtr + (VAddr ^ 2)) = Value;
return true;
}
if (m_TLB_WriteMap[VAddr >> 12] == 0) if (m_TLB_WriteMap[VAddr >> 12] == 0)
{ {
return false; return false;
@ -474,6 +477,12 @@ bool CMipsMemoryVM::SH_VAddr(uint32_t VAddr, uint16_t Value)
bool CMipsMemoryVM::SW_VAddr(uint32_t VAddr, uint32_t Value) bool CMipsMemoryVM::SW_VAddr(uint32_t VAddr, uint32_t Value)
{ {
uint8_t * MemoryPtr = (uint8_t*)m_MemoryWriteMap[VAddr >> 12];
if (MemoryPtr != (uint8_t *)-1)
{
*(uint32_t*)(MemoryPtr + VAddr) = Value;
return true;
}
if (VAddr >= 0xA3F00000 && VAddr < 0xC0000000) if (VAddr >= 0xA3F00000 && VAddr < 0xC0000000)
{ {
if ((VAddr & 0xFFFFE000ul) != 0xA4000000ul) // !(A4000000 <= addr < A4002000) if ((VAddr & 0xFFFFE000ul) != 0xA4000000ul) // !(A4000000 <= addr < A4002000)
@ -495,6 +504,13 @@ bool CMipsMemoryVM::SW_VAddr(uint32_t VAddr, uint32_t Value)
bool CMipsMemoryVM::SD_VAddr(uint32_t VAddr, uint64_t Value) bool CMipsMemoryVM::SD_VAddr(uint32_t VAddr, uint64_t Value)
{ {
uint8_t * MemoryPtr = (uint8_t*)m_MemoryWriteMap[VAddr >> 12];
if (MemoryPtr != (uint8_t *)-1)
{
*(uint32_t*)(MemoryPtr + VAddr + 0) = *((uint32_t*)(&Value) + 1);
*(uint32_t*)(MemoryPtr + VAddr + 4) = *((uint32_t*)(&Value));
return true;
}
if (m_TLB_WriteMap[VAddr >> 12] == 0) if (m_TLB_WriteMap[VAddr >> 12] == 0)
{ {
return false; return false;
@ -505,75 +521,6 @@ bool CMipsMemoryVM::SD_VAddr(uint32_t VAddr, uint64_t Value)
return true; return true;
} }
bool CMipsMemoryVM::SB_PAddr(uint32_t PAddr, uint8_t Value)
{
if (PAddr < RdramSize())
{
*(uint8_t*)(m_RDRAM + (PAddr ^ 3)) = Value;
return true;
}
if (PAddr > 0x18000000)
{
return false;
}
g_Notify->BreakPoint(__FILE__, __LINE__);
return false;
}
bool CMipsMemoryVM::SH_PAddr(uint32_t PAddr, uint16_t Value)
{
if (PAddr < RdramSize())
{
*(uint16_t*)(m_RDRAM + (PAddr ^ 2)) = Value;
return true;
}
if (PAddr > 0x18000000)
{
return false;
}
g_Notify->BreakPoint(__FILE__, __LINE__);
return false;
}
bool CMipsMemoryVM::SW_PAddr(uint32_t PAddr, uint32_t Value)
{
if (PAddr < RdramSize())
{
*(uint32_t*)(m_RDRAM + PAddr) = Value;
return true;
}
if (PAddr > 0x18000000)
{
return false;
}
g_Notify->BreakPoint(__FILE__, __LINE__);
return false;
}
bool CMipsMemoryVM::SD_PAddr(uint32_t PAddr, uint64_t Value)
{
if (PAddr < RdramSize())
{
*(uint32_t*)(m_RDRAM + PAddr + 0) = *((uint32_t*)(&Value) + 1);
*(uint32_t*)(m_RDRAM + PAddr + 4) = *((uint32_t*)(&Value));
return true;
}
if (PAddr > 0x18000000)
{
return false;
}
g_Notify->BreakPoint(__FILE__, __LINE__);
return false;
}
bool CMipsMemoryVM::ValidVaddr(uint32_t VAddr) const bool CMipsMemoryVM::ValidVaddr(uint32_t VAddr) const
{ {
return m_TLB_ReadMap[VAddr >> 12] != 0; return m_TLB_ReadMap[VAddr >> 12] != 0;
@ -852,28 +799,28 @@ const char * CMipsMemoryVM::LabelName(uint32_t Address) const
void CMipsMemoryVM::TLB_Mapped(uint32_t VAddr, uint32_t Len, uint32_t PAddr, bool bReadOnly) void CMipsMemoryVM::TLB_Mapped(uint32_t VAddr, uint32_t Len, uint32_t PAddr, bool bReadOnly)
{ {
size_t count, VEnd; uint32_t VEnd = VAddr + Len;
for (uint32_t Address = VAddr; Address < VEnd; Address += 0x1000)
VEnd = VAddr + Len;
for (count = VAddr; count < VEnd; count += 0x1000)
{ {
size_t Index = count >> 12; size_t Index = Address >> 12;
m_TLB_ReadMap[Index] = ((size_t)m_RDRAM + (count - VAddr + PAddr)) - count; m_MemoryReadMap[Index] = (size_t)((m_RDRAM + (Address - VAddr + PAddr)) - Address);
m_TLB_ReadMap[Index] = ((size_t)m_RDRAM + (Address - VAddr + PAddr)) - Address;
if (!bReadOnly) if (!bReadOnly)
{ {
m_TLB_WriteMap[Index] = ((size_t)m_RDRAM + (count - VAddr + PAddr)) - count; m_MemoryWriteMap[Index] = (size_t)((m_RDRAM + (Address - VAddr + PAddr)) - Address);
m_TLB_WriteMap[Index] = ((size_t)m_RDRAM + (Address - VAddr + PAddr)) - Address;
} }
} }
} }
void CMipsMemoryVM::TLB_Unmaped(uint32_t Vaddr, uint32_t Len) void CMipsMemoryVM::TLB_Unmaped(uint32_t Vaddr, uint32_t Len)
{ {
size_t count, End; uint32_t End = Vaddr + Len;
for (uint32_t Address = Vaddr; Address < End; Address += 0x1000)
End = Vaddr + Len;
for (count = Vaddr; count < End; count += 0x1000)
{ {
size_t Index = count >> 12; size_t Index = Address >> 12;
m_MemoryReadMap[Index] = (size_t)-1;
m_MemoryWriteMap[Index] = (size_t)-1;
m_TLB_ReadMap[Index] = 0; m_TLB_ReadMap[Index] = 0;
m_TLB_WriteMap[Index] = 0; m_TLB_WriteMap[Index] = 0;
} }
@ -1021,7 +968,7 @@ void CMipsMemoryVM::ChangeSpStatus()
} }
//if (*( uint32_t *)(DMEM + 0xFC0) == 1) //if (*( uint32_t *)(DMEM + 0xFC0) == 1)
//{ //{
// ChangeTimer(RspTimer,0x40000); // ChangeTimer(RspTimer,0x40000);
//} //}
//else //else
//{ //{

23
Source/Project64-core/N64System/Mips/MemoryVirtualMem.h
View File

@ -62,11 +62,12 @@ public:
bool Initialize(bool SyncSystem); bool Initialize(bool SyncSystem);
void Reset(bool EraseMemory); void Reset(bool EraseMemory);
uint8_t * Rdram(); uint8_t * Rdram() const { return m_RDRAM; }
uint32_t RdramSize(); uint32_t RdramSize() const { return m_AllocatedRdramSize; }
uint8_t * Dmem(); uint8_t * Dmem() const { return m_DMEM; }
uint8_t * Imem(); uint8_t * Imem() const { return m_IMEM; }
uint8_t * PifRam(); uint8_t * Rom() const { return m_Rom; }
uint8_t * PifRam() { return &m_PifRam[0]; }
CSram * GetSram(); CSram * GetSram();
CFlashram * GetFlashram(); CFlashram * GetFlashram();
@ -76,21 +77,11 @@ public:
bool LW_VAddr(uint32_t VAddr, uint32_t & Value); bool LW_VAddr(uint32_t VAddr, uint32_t & Value);
bool LD_VAddr(uint32_t VAddr, uint64_t & Value); bool LD_VAddr(uint32_t VAddr, uint64_t & Value);
bool LB_PAddr(uint32_t PAddr, uint8_t & Value);
bool LH_PAddr(uint32_t PAddr, uint16_t & Value);
bool LW_PAddr(uint32_t PAddr, uint32_t & Value);
bool LD_PAddr(uint32_t PAddr, uint64_t & Value);
bool SB_VAddr(uint32_t VAddr, uint8_t Value); bool SB_VAddr(uint32_t VAddr, uint8_t Value);
bool SH_VAddr(uint32_t VAddr, uint16_t Value); bool SH_VAddr(uint32_t VAddr, uint16_t Value);
bool SW_VAddr(uint32_t VAddr, uint32_t Value); bool SW_VAddr(uint32_t VAddr, uint32_t Value);
bool SD_VAddr(uint32_t VAddr, uint64_t Value); bool SD_VAddr(uint32_t VAddr, uint64_t Value);
bool SB_PAddr(uint32_t PAddr, uint8_t Value);
bool SH_PAddr(uint32_t PAddr, uint16_t Value);
bool SW_PAddr(uint32_t PAddr, uint32_t Value);
bool SD_PAddr(uint32_t PAddr, uint64_t Value);
int32_t MemoryFilter(uint32_t dwExptCode, void * lpExceptionPointer); int32_t MemoryFilter(uint32_t dwExptCode, void * lpExceptionPointer);
#ifndef _WIN32 #ifndef _WIN32
@ -199,6 +190,8 @@ private:
mutable char m_strLabelName[100]; mutable char m_strLabelName[100];
size_t * m_TLB_ReadMap; size_t * m_TLB_ReadMap;
size_t * m_TLB_WriteMap; size_t * m_TLB_WriteMap;
size_t * m_MemoryReadMap;
size_t * m_MemoryWriteMap;
static uint32_t m_MemLookupAddress; static uint32_t m_MemLookupAddress;
static MIPS_DWORD m_MemLookupValue; static MIPS_DWORD m_MemLookupValue;

359
Source/Project64-core/N64System/Recompiler/x86/x86RecompilerOps.cpp
View File

@ -2745,8 +2745,16 @@ void CX86RecompilerOps::LB_KnownAddress(x86Reg Reg, uint32_t VAddr, bool SignExt
MoveConstToX86reg(VAddr >> 12, TlbMappReg); MoveConstToX86reg(VAddr >> 12, TlbMappReg);
x86Reg AddrReg = Map_TempReg(x86_Any, -1, false); x86Reg AddrReg = Map_TempReg(x86_Any, -1, false);
MoveConstToX86reg(VAddr, AddrReg); MoveConstToX86reg(VAddr, AddrReg);
MoveVariableDispToX86Reg(g_MMU->m_MemoryReadMap, "MMU->m_MemoryReadMap", TlbMappReg, TlbMappReg, 4);
CompConstToX86reg(TlbMappReg, (uint32_t)-1);
JneLabel8(stdstr_f("MemoryReadMap_%X_Found", m_CompilePC).c_str(), 0);
uint8_t * JumpFound = (uint8_t *)(*g_RecompPos - 1);
MoveConstToX86reg(VAddr >> 12, TlbMappReg);
MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TlbMappReg, TlbMappReg, 4); MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TlbMappReg, TlbMappReg, 4);
CompileReadTLBMiss(AddrReg, TlbMappReg); CompileReadTLBMiss(AddrReg, TlbMappReg);
CPU_Message("");
CPU_Message(stdstr_f(" MemoryReadMap_%X_Found:", m_CompilePC).c_str());
SetJump8(JumpFound, *g_RecompPos);
if (SignExtend) if (SignExtend)
{ {
MoveSxByteX86regPointerToX86reg(AddrReg, TlbMappReg, Reg); MoveSxByteX86regPointerToX86reg(AddrReg, TlbMappReg, Reg);
@ -2810,8 +2818,16 @@ void CX86RecompilerOps::LH_KnownAddress(x86Reg Reg, uint32_t VAddr, bool SignExt
MoveConstToX86reg(VAddr >> 12, TlbMappReg); MoveConstToX86reg(VAddr >> 12, TlbMappReg);
x86Reg AddrReg = Map_TempReg(x86_Any, -1, false); x86Reg AddrReg = Map_TempReg(x86_Any, -1, false);
MoveConstToX86reg(VAddr, AddrReg); MoveConstToX86reg(VAddr, AddrReg);
MoveVariableDispToX86Reg(g_MMU->m_MemoryReadMap, "MMU->m_MemoryReadMap", TlbMappReg, TlbMappReg, 4);
CompConstToX86reg(TlbMappReg, (uint32_t)-1);
JneLabel8(stdstr_f("MemoryReadMap_%X_Found", m_CompilePC).c_str(), 0);
uint8_t * JumpFound = (uint8_t *)(*g_RecompPos - 1);
MoveConstToX86reg(VAddr >> 12, TlbMappReg);
MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TlbMappReg, TlbMappReg, 4); MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TlbMappReg, TlbMappReg, 4);
CompileReadTLBMiss(AddrReg, TlbMappReg); CompileReadTLBMiss(AddrReg, TlbMappReg);
CPU_Message("");
CPU_Message(stdstr_f(" MemoryReadMap_%X_Found:", m_CompilePC).c_str());
SetJump8(JumpFound, *g_RecompPos);
if (SignExtend) if (SignExtend)
{ {
MoveSxHalfX86regPointerToX86reg(AddrReg, TlbMappReg, Reg); MoveSxHalfX86regPointerToX86reg(AddrReg, TlbMappReg, Reg);
@ -2911,8 +2927,17 @@ void CX86RecompilerOps::LB()
TempReg2 = Map_TempReg(x86_Any, -1, false); TempReg2 = Map_TempReg(x86_Any, -1, false);
MoveX86RegToX86Reg(TempReg1, TempReg2); MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12); ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_MemoryReadMap, "MMU->m_MemoryReadMap", TempReg2, TempReg2, 4);
CompConstToX86reg(TempReg2, (uint32_t)-1);
JneLabel8(stdstr_f("MemoryReadMap_%X_Found", m_CompilePC).c_str(), 0);
uint8_t * JumpFound = (uint8_t *)(*g_RecompPos - 1);
MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4); MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4);
CompileReadTLBMiss(TempReg1, TempReg2); CompileReadTLBMiss(TempReg1, TempReg2);
CPU_Message("");
CPU_Message(stdstr_f(" MemoryReadMap_%X_Found:", m_CompilePC).c_str());
SetJump8(JumpFound, *g_RecompPos);
XorConstToX86Reg(TempReg1, 3); XorConstToX86Reg(TempReg1, 3);
Map_GPR_32bit(m_Opcode.rt, true, -1); Map_GPR_32bit(m_Opcode.rt, true, -1);
MoveSxByteX86regPointerToX86reg(TempReg1, TempReg2, GetMipsRegMapLo(m_Opcode.rt)); MoveSxByteX86regPointerToX86reg(TempReg1, TempReg2, GetMipsRegMapLo(m_Opcode.rt));
@ -2964,8 +2989,17 @@ void CX86RecompilerOps::LH()
x86Reg TempReg2 = Map_TempReg(x86_Any, -1, false); x86Reg TempReg2 = Map_TempReg(x86_Any, -1, false);
MoveX86RegToX86Reg(TempReg1, TempReg2); MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12); ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_MemoryReadMap, "MMU->m_MemoryReadMap", TempReg2, TempReg2, 4);
CompConstToX86reg(TempReg2, (uint32_t)-1);
JneLabel8(stdstr_f("MemoryReadMap_%X_Found", m_CompilePC).c_str(), 0);
uint8_t * JumpFound = (uint8_t *)(*g_RecompPos - 1);
MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4); MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4);
CompileReadTLBMiss(TempReg1, TempReg2); CompileReadTLBMiss(TempReg1, TempReg2);
CPU_Message("");
CPU_Message(stdstr_f(" MemoryReadMap_%X_Found:", m_CompilePC).c_str());
SetJump8(JumpFound, *g_RecompPos);
XorConstToX86Reg(TempReg1, 2); XorConstToX86Reg(TempReg1, 2);
Map_GPR_32bit(m_Opcode.rt, true, -1); Map_GPR_32bit(m_Opcode.rt, true, -1);
MoveSxHalfX86regPointerToX86reg(TempReg1, TempReg2, GetMipsRegMapLo(m_Opcode.rt)); MoveSxHalfX86regPointerToX86reg(TempReg1, TempReg2, GetMipsRegMapLo(m_Opcode.rt));
@ -3022,13 +3056,19 @@ void CX86RecompilerOps::LWL()
TempReg1 = Map_TempReg(x86_Any, m_Opcode.base, false); TempReg1 = Map_TempReg(x86_Any, m_Opcode.base, false);
AddConstToX86Reg(TempReg1, (int16_t)m_Opcode.immediate); AddConstToX86Reg(TempReg1, (int16_t)m_Opcode.immediate);
} }
x86Reg TempReg2 = x86_Unknown; x86Reg TempReg2 = Map_TempReg(x86_Any, -1, false);
TempReg2 = Map_TempReg(x86_Any, -1, false);
MoveX86RegToX86Reg(TempReg1, TempReg2); MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12); ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_MemoryReadMap, "MMU->m_MemoryReadMap", TempReg2, TempReg2, 4);
CompConstToX86reg(TempReg2, (uint32_t)-1);
JneLabel8(stdstr_f("MemoryReadMap_%X_Found", m_CompilePC).c_str(), 0);
uint8_t * JumpFound = (uint8_t *)(*g_RecompPos - 1);
MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4); MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4);
CompileReadTLBMiss(TempReg1, TempReg2); CompileReadTLBMiss(TempReg1, TempReg2);
CPU_Message("");
CPU_Message(stdstr_f(" MemoryReadMap_%X_Found:", m_CompilePC).c_str());
SetJump8(JumpFound, *g_RecompPos);
x86Reg OffsetReg = Map_TempReg(x86_Any, -1, false); x86Reg OffsetReg = Map_TempReg(x86_Any, -1, false);
MoveX86RegToX86Reg(TempReg1, OffsetReg); MoveX86RegToX86Reg(TempReg1, OffsetReg);
AndConstToX86Reg(OffsetReg, 3); AndConstToX86Reg(OffsetReg, 3);
@ -3114,8 +3154,17 @@ void CX86RecompilerOps::LW(bool ResultSigned, bool bRecordLLBit)
TempReg2 = Map_TempReg(x86_Any, -1, false); TempReg2 = Map_TempReg(x86_Any, -1, false);
MoveX86RegToX86Reg(TempReg1, TempReg2); MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12); ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_MemoryReadMap, "MMU->m_MemoryReadMap", TempReg2, TempReg2, 4);
CompConstToX86reg(TempReg2, (uint32_t)-1);
JneLabel8(stdstr_f("MemoryReadMap_%X_Found", m_CompilePC).c_str(), 0);
uint8_t * JumpFound = (uint8_t *)(*g_RecompPos - 1);
MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4); MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4);
CompileReadTLBMiss(TempReg1, TempReg2); CompileReadTLBMiss(TempReg1, TempReg2);
CPU_Message("");
CPU_Message(stdstr_f(" MemoryReadMap_%X_Found:", m_CompilePC).c_str());
SetJump8(JumpFound, *g_RecompPos);
Map_GPR_32bit(m_Opcode.rt, ResultSigned, -1); Map_GPR_32bit(m_Opcode.rt, ResultSigned, -1);
MoveX86regPointerToX86reg(TempReg1, TempReg2, GetMipsRegMapLo(m_Opcode.rt)); MoveX86regPointerToX86reg(TempReg1, TempReg2, GetMipsRegMapLo(m_Opcode.rt));
if (bRecordLLBit) if (bRecordLLBit)
@ -3139,9 +3188,18 @@ void CX86RecompilerOps::LW_KnownAddress(x86Reg Reg, uint32_t VAddr)
if (VAddr < 0x80000000 || VAddr >= 0xC0000000) if (VAddr < 0x80000000 || VAddr >= 0xC0000000)
{ {
x86Reg TlbMappReg = Map_TempReg(x86_Any, -1, false); x86Reg TlbMappReg = Map_TempReg(x86_Any, -1, false);
MoveConstToX86reg(VAddr >> 12, TlbMappReg);
MoveVariableDispToX86Reg(g_MMU->m_MemoryReadMap, "MMU->m_MemoryReadMap", TlbMappReg, TlbMappReg, 4);
CompConstToX86reg(TlbMappReg, (uint32_t)-1);
JneLabel8(stdstr_f("MemoryWriteMap_%X_Found", m_CompilePC).c_str(), 0);
uint8_t * JumpFound = (uint8_t *)(*g_RecompPos - 1);
MoveConstToX86reg(VAddr >> 12, TlbMappReg); MoveConstToX86reg(VAddr >> 12, TlbMappReg);
MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TlbMappReg, TlbMappReg, 4); MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TlbMappReg, TlbMappReg, 4);
CompileReadTLBMiss(VAddr, TlbMappReg); CompileReadTLBMiss(VAddr, TlbMappReg);
CPU_Message("");
CPU_Message(stdstr_f(" MemoryWriteMap_%X_Found:", m_CompilePC).c_str());
SetJump8(JumpFound, *g_RecompPos);
AddConstToX86Reg(TlbMappReg, VAddr); AddConstToX86Reg(TlbMappReg, VAddr);
MoveX86PointerToX86reg(Reg, TlbMappReg); MoveX86PointerToX86reg(Reg, TlbMappReg);
} }
@ -3362,8 +3420,8 @@ void CX86RecompilerOps::LW_KnownAddress(x86Reg Reg, uint32_t VAddr)
if ((PAddr & 0xF0000000) == 0x10000000 && (PAddr - 0x10000000) < g_Rom->GetRomSize()) if ((PAddr & 0xF0000000) == 0x10000000 && (PAddr - 0x10000000) < g_Rom->GetRomSize())
{ {
// Read from ROM // Read from ROM
sprintf(VarName, "RDRAM + %X", PAddr); sprintf(VarName, "Rom + %X", (PAddr - 0x10000000));
MoveVariableToX86reg(PAddr + g_MMU->Rdram(), VarName, Reg); MoveVariableToX86reg((PAddr - 0x10000000) + g_MMU->Rom(), VarName, Reg);
} }
else if (g_DDRom != nullptr && ((PAddr & 0xFF000000) == 0x06000000 && (PAddr - 0x06000000) < g_DDRom->GetRomSize())) else if (g_DDRom != nullptr && ((PAddr & 0xFF000000) == 0x06000000 && (PAddr - 0x06000000) < g_DDRom->GetRomSize()))
{ {
@ -3432,8 +3490,17 @@ void CX86RecompilerOps::LBU()
TempReg2 = Map_TempReg(x86_Any, -1, false); TempReg2 = Map_TempReg(x86_Any, -1, false);
MoveX86RegToX86Reg(TempReg1, TempReg2); MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12); ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_MemoryReadMap, "MMU->m_MemoryReadMap", TempReg2, TempReg2, 4);
CompConstToX86reg(TempReg2, (uint32_t)-1);
JneLabel8(stdstr_f("MemoryReadMap_%X_Found", m_CompilePC).c_str(), 0);
uint8_t * JumpFound = (uint8_t *)(*g_RecompPos - 1);
MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4); MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4);
CompileReadTLBMiss(TempReg1, TempReg2); CompileReadTLBMiss(TempReg1, TempReg2);
CPU_Message("");
CPU_Message(stdstr_f(" MemoryReadMap_%X_Found:", m_CompilePC).c_str());
SetJump8(JumpFound, *g_RecompPos);
XorConstToX86Reg(TempReg1, 3); XorConstToX86Reg(TempReg1, 3);
Map_GPR_32bit(m_Opcode.rt, false, -1); Map_GPR_32bit(m_Opcode.rt, false, -1);
MoveZxByteX86regPointerToX86reg(TempReg1, TempReg2, GetMipsRegMapLo(m_Opcode.rt)); MoveZxByteX86regPointerToX86reg(TempReg1, TempReg2, GetMipsRegMapLo(m_Opcode.rt));
@ -3487,8 +3554,17 @@ void CX86RecompilerOps::LHU()
TempReg2 = Map_TempReg(x86_Any, -1, false); TempReg2 = Map_TempReg(x86_Any, -1, false);
MoveX86RegToX86Reg(TempReg1, TempReg2); MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12); ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_MemoryReadMap, "MMU->m_MemoryReadMap", TempReg2, TempReg2, 4);
CompConstToX86reg(TempReg2, (uint32_t)-1);
JneLabel8(stdstr_f("MemoryReadMap_%X_Found", m_CompilePC).c_str(), 0);
uint8_t * JumpFound = (uint8_t *)(*g_RecompPos - 1);
MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4); MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4);
CompileReadTLBMiss(TempReg1, TempReg2); CompileReadTLBMiss(TempReg1, TempReg2);
CPU_Message("");
CPU_Message(stdstr_f(" MemoryReadMap_%X_Found:", m_CompilePC).c_str());
SetJump8(JumpFound, *g_RecompPos);
XorConstToX86Reg(TempReg1, 2); XorConstToX86Reg(TempReg1, 2);
Map_GPR_32bit(m_Opcode.rt, false, -1); Map_GPR_32bit(m_Opcode.rt, false, -1);
MoveZxHalfX86regPointerToX86reg(TempReg1, TempReg2, GetMipsRegMapLo(m_Opcode.rt)); MoveZxHalfX86regPointerToX86reg(TempReg1, TempReg2, GetMipsRegMapLo(m_Opcode.rt));
@ -3496,7 +3572,7 @@ void CX86RecompilerOps::LHU()
void CX86RecompilerOps::LWR() void CX86RecompilerOps::LWR()
{ {
x86Reg TempReg1 = x86_Unknown, TempReg2 = x86_Unknown, OffsetReg = x86_Unknown, shift = x86_Unknown; x86Reg TempReg1 = x86_Unknown, shift = x86_Unknown;
if (m_Opcode.rt == 0) if (m_Opcode.rt == 0)
{ {
@ -3548,13 +3624,22 @@ void CX86RecompilerOps::LWR()
} }
TestReadBreakpoint(TempReg1, (void *)x86TestReadBreakpoint32, "x86TestReadBreakpoint32"); TestReadBreakpoint(TempReg1, (void *)x86TestReadBreakpoint32, "x86TestReadBreakpoint32");
TempReg2 = Map_TempReg(x86_Any, -1, false); x86Reg TempReg2 = Map_TempReg(x86_Any, -1, false);
x86Reg OffsetReg = Map_TempReg(x86_Any, -1, false);
MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_MemoryReadMap, "MMU->m_MemoryReadMap", TempReg2, TempReg2, 4);
CompConstToX86reg(TempReg2, (uint32_t)-1);
JneLabel8(stdstr_f("MemoryReadMap_%X_Found", m_CompilePC).c_str(), 0);
uint8_t * JumpFound = (uint8_t *)(*g_RecompPos - 1);
MoveX86RegToX86Reg(TempReg1, TempReg2); MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12); ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4); MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4);
CompileReadTLBMiss(TempReg1, TempReg2); CompileReadTLBMiss(TempReg1, TempReg2);
OffsetReg = Map_TempReg(x86_Any, -1, false); CPU_Message("");
CPU_Message(stdstr_f(" MemoryReadMap_%X_Found:", m_CompilePC).c_str());
SetJump8(JumpFound, *g_RecompPos);
MoveX86RegToX86Reg(TempReg1, OffsetReg); MoveX86RegToX86Reg(TempReg1, OffsetReg);
AndConstToX86Reg(OffsetReg, 3); AndConstToX86Reg(OffsetReg, 3);
AndConstToX86Reg(TempReg1, (uint32_t)~3); AndConstToX86Reg(TempReg1, (uint32_t)~3);
@ -3629,11 +3714,27 @@ void CX86RecompilerOps::SB()
Compile_StoreInstructClean(TempReg1, 4); Compile_StoreInstructClean(TempReg1, 4);
TestWriteBreakpoint(TempReg1, (void *)x86TestWriteBreakpoint8, "x86TestWriteBreakpoint8"); TestWriteBreakpoint(TempReg1, (void *)x86TestWriteBreakpoint8, "x86TestWriteBreakpoint8");
x86Reg TempRtReg = IsUnknown(m_Opcode.rt) ? Map_TempReg(x86_Any8Bit, -1, false) : x86_Any8Bit;
if (IsMapped(m_Opcode.rt) && !Is8BitReg(GetMipsRegMapLo(m_Opcode.rt)))
{
UnProtectGPR(m_Opcode.rt);
TempRtReg = Map_TempReg(x86_Any8Bit, -1, false);
}
TempReg2 = Map_TempReg(x86_Any, -1, false); TempReg2 = Map_TempReg(x86_Any, -1, false);
MoveX86RegToX86Reg(TempReg1, TempReg2); MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12); ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_MemoryWriteMap, "MMU->m_MemoryWriteMap", TempReg2, TempReg2, 4);
CompConstToX86reg(TempReg2, (uint32_t)-1);
JneLabel8(stdstr_f("MemoryWriteMap_%X_Found", m_CompilePC).c_str(), 0);
uint8_t * JumpFound = (uint8_t *)(*g_RecompPos - 1);
MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4); MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4);
CompileWriteTLBMiss(TempReg1, TempReg2); CompileWriteTLBMiss(TempReg1, TempReg2);
CPU_Message("");
CPU_Message(stdstr_f(" MemoryWriteMap_%X_Found:", m_CompilePC).c_str());
SetJump8(JumpFound, *g_RecompPos);
XorConstToX86Reg(TempReg1, 3); XorConstToX86Reg(TempReg1, 3);
if (IsConst(m_Opcode.rt)) if (IsConst(m_Opcode.rt))
{ {
@ -3645,8 +3746,7 @@ void CX86RecompilerOps::SB()
} }
else else
{ {
UnProtectGPR(m_Opcode.rt); MoveX86regByteToX86regPointer(Map_TempReg(TempRtReg, m_Opcode.rt, false), TempReg1, TempReg2);
MoveX86regByteToX86regPointer(Map_TempReg(x86_Any8Bit, m_Opcode.rt, false), TempReg1, TempReg2);
} }
} }
@ -3705,11 +3805,25 @@ void CX86RecompilerOps::SH()
} }
TestWriteBreakpoint(TempReg1, (void *)x86TestWriteBreakpoint16, "x86TestWriteBreakpoint16"); TestWriteBreakpoint(TempReg1, (void *)x86TestWriteBreakpoint16, "x86TestWriteBreakpoint16");
x86Reg RtTemp = x86_Any;
if (!IsConst(m_Opcode.rt) && !IsMapped(m_Opcode.rt))
{
RtTemp = Map_TempReg(x86_Any, m_Opcode.rt, false);
}
TempReg2 = Map_TempReg(x86_Any, -1, false); TempReg2 = Map_TempReg(x86_Any, -1, false);
MoveX86RegToX86Reg(TempReg1, TempReg2); MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12); ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_MemoryWriteMap, "MMU->m_MemoryWriteMap", TempReg2, TempReg2, 4);
CompConstToX86reg(TempReg2, (uint32_t)-1);
JneLabel8(stdstr_f("MemoryWriteMap_%X_Found", m_CompilePC).c_str(), 0);
uint8_t * JumpFound = (uint8_t *)(*g_RecompPos - 1);
MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4); MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4);
CompileWriteTLBMiss(TempReg1, TempReg2); CompileWriteTLBMiss(TempReg1, TempReg2);
CPU_Message("");
CPU_Message(stdstr_f(" MemoryWriteMap_%X_Found:", m_CompilePC).c_str());
SetJump8(JumpFound, *g_RecompPos);
XorConstToX86Reg(TempReg1, 2); XorConstToX86Reg(TempReg1, 2);
if (IsConst(m_Opcode.rt)) if (IsConst(m_Opcode.rt))
{ {
@ -3721,7 +3835,7 @@ void CX86RecompilerOps::SH()
} }
else else
{ {
MoveX86regHalfToX86regPointer(Map_TempReg(x86_Any, m_Opcode.rt, false), TempReg1, TempReg2); MoveX86regHalfToX86regPointer(RtTemp, TempReg1, TempReg2);
} }
} }
@ -3771,19 +3885,25 @@ void CX86RecompilerOps::SWL()
} }
TestWriteBreakpoint(TempReg1, (void *)x86TestWriteBreakpoint32, "x86TestWriteBreakpoint32"); TestWriteBreakpoint(TempReg1, (void *)x86TestWriteBreakpoint32, "x86TestWriteBreakpoint32");
x86Reg TempReg2 = x86_Unknown; x86Reg TempReg2 = Map_TempReg(x86_Any, -1, false);
TempReg2 = Map_TempReg(x86_Any, -1, false); x86Reg OffsetReg = Map_TempReg(x86_Any, -1, false);
x86Reg Value = Map_TempReg(x86_Any, -1, false);
MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_MemoryReadMap, "MMU->m_MemoryReadMap", TempReg2, TempReg2, 4);
CompConstToX86reg(TempReg2, (uint32_t)-1);
JneLabel8(stdstr_f("MemoryReadMap_%X_Found", m_CompilePC).c_str(), 0);
uint8_t * JumpFound = (uint8_t *)(*g_RecompPos - 1);
MoveX86RegToX86Reg(TempReg1, TempReg2); MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12); ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4); MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4);
CompileReadTLBMiss(TempReg1, TempReg2); CompileReadTLBMiss(TempReg1, TempReg2);
CPU_Message("");
x86Reg OffsetReg = Map_TempReg(x86_Any, -1, false); CPU_Message(stdstr_f(" MemoryReadMap_%X_Found:", m_CompilePC).c_str());
SetJump8(JumpFound, *g_RecompPos);
MoveX86RegToX86Reg(TempReg1, OffsetReg); MoveX86RegToX86Reg(TempReg1, OffsetReg);
AndConstToX86Reg(OffsetReg, 3); AndConstToX86Reg(OffsetReg, 3);
AndConstToX86Reg(TempReg1, (uint32_t)~3); AndConstToX86Reg(TempReg1, (uint32_t)~3);
x86Reg Value = Map_TempReg(x86_Any, -1, false);
MoveX86regPointerToX86reg(TempReg1, TempReg2, Value); MoveX86regPointerToX86reg(TempReg1, TempReg2, Value);
AndVariableDispToX86Reg((void *)R4300iOp::SWL_MASK, "R4300iOp::SWL_MASK", Value, OffsetReg, Multip_x4); AndVariableDispToX86Reg((void *)R4300iOp::SWL_MASK, "R4300iOp::SWL_MASK", Value, OffsetReg, Multip_x4);
@ -3808,8 +3928,17 @@ void CX86RecompilerOps::SWL()
MoveX86RegToX86Reg(TempReg1, TempReg2); MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12); ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4);
MoveVariableDispToX86Reg(g_MMU->m_MemoryWriteMap, "MMU->m_MemoryWriteMap", TempReg2, TempReg2, 4);
CompConstToX86reg(TempReg2, (uint32_t)-1);
JneLabel8(stdstr_f("MemoryReadMap_%X_Found2", m_CompilePC).c_str(), 0);
uint8_t * JumpFound2 = (uint8_t *)(*g_RecompPos - 1);
MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4);
CPU_Message("");
CPU_Message(stdstr_f(" MemoryReadMap_%X_Found:", m_CompilePC).c_str());
SetJump8(JumpFound2, *g_RecompPos);
MoveX86regToX86regPointer(Value, TempReg1, TempReg2); MoveX86regToX86regPointer(Value, TempReg1, TempReg2);
} }
@ -3910,17 +4039,28 @@ void CX86RecompilerOps::SW(bool bCheckLLbit)
} }
Compile_StoreInstructClean(TempReg1, 4); Compile_StoreInstructClean(TempReg1, 4);
TestWriteBreakpoint(TempReg1, (void *)x86TestWriteBreakpoint32, "x86TestWriteBreakpoint32"); TestWriteBreakpoint(TempReg1, (void *)x86TestWriteBreakpoint32, "x86TestWriteBreakpoint32");
x86Reg TempRtReg = IsUnknown(m_Opcode.rt) ? Map_TempReg(x86_Any, -1, false) : x86_Any;
TempReg2 = Map_TempReg(x86_Any, -1, false); TempReg2 = Map_TempReg(x86_Any, -1, false);
MoveX86RegToX86Reg(TempReg1, TempReg2); MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12); ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_MemoryWriteMap, "MMU->m_MemoryWriteMap", TempReg2, TempReg2, 4);
CompConstToX86reg(TempReg2, (uint32_t)-1);
JneLabel8(stdstr_f("MemoryWriteMap_%X_Found", m_CompilePC).c_str(), 0);
uint8_t * JumpFound = (uint8_t *)(*g_RecompPos - 1);
MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4); MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4);
CompileWriteTLBMiss(TempReg1, TempReg2); CompileWriteTLBMiss(TempReg1, TempReg2);
uint8_t * Jump = nullptr; CPU_Message("");
CPU_Message(stdstr_f(" MemoryWriteMap_%X_Found:", m_CompilePC).c_str());
SetJump8(JumpFound, *g_RecompPos);
uint8_t * JumpLLBit = nullptr;
if (bCheckLLbit) if (bCheckLLbit)
{ {
CompConstToVariable(1, _LLBit, "_LLBit"); CompConstToVariable(1, _LLBit, "_LLBit");
JneLabel8("LLBit_Continue", 0); JneLabel8("LLBit_Continue", 0);
Jump = *g_RecompPos - 1; JumpLLBit = *g_RecompPos - 1;
} }
if (IsConst(m_Opcode.rt)) if (IsConst(m_Opcode.rt))
{ {
@ -3932,13 +4072,13 @@ void CX86RecompilerOps::SW(bool bCheckLLbit)
} }
else else
{ {
MoveX86regToX86regPointer(Map_TempReg(x86_Any, m_Opcode.rt, false), TempReg1, TempReg2); MoveX86regToX86regPointer(Map_TempReg(TempRtReg, m_Opcode.rt, false), TempReg1, TempReg2);
} }
if (bCheckLLbit) if (bCheckLLbit)
{ {
CPU_Message(" "); CPU_Message(" ");
CPU_Message(" LLBit_Continue:"); CPU_Message(" LLBit_Continue:");
SetJump8(Jump, *g_RecompPos); SetJump8(JumpLLBit, *g_RecompPos);
Map_GPR_32bit(m_Opcode.rt, false, -1); Map_GPR_32bit(m_Opcode.rt, false, -1);
MoveVariableToX86reg(_LLBit, "_LLBit", GetMipsRegMapLo(m_Opcode.rt)); MoveVariableToX86reg(_LLBit, "_LLBit", GetMipsRegMapLo(m_Opcode.rt));
} }
@ -3947,8 +4087,7 @@ void CX86RecompilerOps::SW(bool bCheckLLbit)
void CX86RecompilerOps::SWR() void CX86RecompilerOps::SWR()
{ {
x86Reg TempReg1 = x86_Unknown, TempReg2 = x86_Unknown, Value = x86_Unknown, x86Reg TempReg1 = x86_Unknown, shift = x86_Unknown;
OffsetReg = x86_Unknown, shift = x86_Unknown;
if (IsConst(m_Opcode.base)) if (IsConst(m_Opcode.base))
{ {
@ -3960,7 +4099,7 @@ void CX86RecompilerOps::SWR()
} }
uint32_t Offset = Address & 3; uint32_t Offset = Address & 3;
Value = Map_TempReg(x86_Any, -1, false); x86Reg Value = Map_TempReg(x86_Any, -1, false);
LW_KnownAddress(Value, (Address & ~3)); LW_KnownAddress(Value, (Address & ~3));
AndConstToX86Reg(Value, R4300iOp::SWR_MASK[Offset]); AndConstToX86Reg(Value, R4300iOp::SWR_MASK[Offset]);
TempReg1 = Map_TempReg(x86_Any, m_Opcode.rt, false); TempReg1 = Map_TempReg(x86_Any, m_Opcode.rt, false);
@ -3991,18 +4130,27 @@ void CX86RecompilerOps::SWR()
AddConstToX86Reg(TempReg1, (int16_t)m_Opcode.immediate); AddConstToX86Reg(TempReg1, (int16_t)m_Opcode.immediate);
} }
TestWriteBreakpoint(TempReg1, (void *)x86TestWriteBreakpoint32, "x86TestWriteBreakpoint32"); TestWriteBreakpoint(TempReg1, (void *)x86TestWriteBreakpoint32, "x86TestWriteBreakpoint32");
TempReg2 = Map_TempReg(x86_Any, -1, false); x86Reg TempReg2 = Map_TempReg(x86_Any, -1, false);
x86Reg OffsetReg = Map_TempReg(x86_Any, -1, false);
x86Reg Value = Map_TempReg(x86_Any, -1, false);
MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_MemoryReadMap, "MMU->m_MemoryReadMap", TempReg2, TempReg2, 4);
CompConstToX86reg(TempReg2, (uint32_t)-1);
JneLabel8(stdstr_f("MemoryReadMap_%X_Found", m_CompilePC).c_str(), 0);
uint8_t * JumpFound = (uint8_t *)(*g_RecompPos - 1);
MoveX86RegToX86Reg(TempReg1, TempReg2); MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12); ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4); MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4);
CompileReadTLBMiss(TempReg1, TempReg2); CompileReadTLBMiss(TempReg1, TempReg2);
CPU_Message("");
CPU_Message(stdstr_f(" MemoryReadMap_%X_Found:", m_CompilePC).c_str());
SetJump8(JumpFound, *g_RecompPos);
OffsetReg = Map_TempReg(x86_Any, -1, false);
MoveX86RegToX86Reg(TempReg1, OffsetReg); MoveX86RegToX86Reg(TempReg1, OffsetReg);
AndConstToX86Reg(OffsetReg, 3); AndConstToX86Reg(OffsetReg, 3);
AndConstToX86Reg(TempReg1, (uint32_t)~3); AndConstToX86Reg(TempReg1, (uint32_t)~3);
Value = Map_TempReg(x86_Any, -1, false);
MoveX86regPointerToX86reg(TempReg1, TempReg2, Value); MoveX86regPointerToX86reg(TempReg1, TempReg2, Value);
AndVariableDispToX86Reg((void *)R4300iOp::SWR_MASK, "R4300iOp::SWR_MASK", Value, OffsetReg, Multip_x4); AndVariableDispToX86Reg((void *)R4300iOp::SWR_MASK, "R4300iOp::SWR_MASK", Value, OffsetReg, Multip_x4);
@ -4025,9 +4173,18 @@ void CX86RecompilerOps::SWR()
AddX86RegToX86Reg(Value, OffsetReg); AddX86RegToX86Reg(Value, OffsetReg);
} }
MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_MemoryWriteMap, "MMU->m_MemoryWriteMap", TempReg2, TempReg2, 4);
CompConstToX86reg(TempReg2, (uint32_t)-1);
JneLabel8(stdstr_f("MemoryReadMap_%X_Found2", m_CompilePC).c_str(), 0);
uint8_t * JumpFound2 = (uint8_t *)(*g_RecompPos - 1);
MoveX86RegToX86Reg(TempReg1, TempReg2); MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12); ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4); MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4);
CPU_Message("");
CPU_Message(stdstr_f(" MemoryReadMap_%X_Found2:", m_CompilePC).c_str());
SetJump8(JumpFound2, *g_RecompPos);
MoveX86regToX86regPointer(Value, TempReg1, TempReg2); MoveX86regToX86regPointer(Value, TempReg1, TempReg2);
} }
@ -4140,13 +4297,22 @@ void CX86RecompilerOps::LWC1()
} }
} }
TestReadBreakpoint(TempReg1, (void *)x86TestReadBreakpoint32, "x86TestReadBreakpoint32"); TestReadBreakpoint(TempReg1, (void *)x86TestReadBreakpoint32, "x86TestReadBreakpoint32");
x86Reg TempReg2 = Map_TempReg(x86_Any, -1, false), TempReg3; x86Reg TempReg2 = Map_TempReg(x86_Any, -1, false);
x86Reg TempReg3 = Map_TempReg(x86_Any, -1, false);
MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_MemoryReadMap, "MMU->m_MemoryReadMap", TempReg2, TempReg2, 4);
CompConstToX86reg(TempReg2, (uint32_t)-1);
JneLabel8(stdstr_f("MemoryReadMap_%X_Found", m_CompilePC).c_str(), 0);
uint8_t * JumpFound = (uint8_t *)(*g_RecompPos - 1);
MoveX86RegToX86Reg(TempReg1, TempReg2); MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12); ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4); MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4);
CompileReadTLBMiss(TempReg1, TempReg2); CompileReadTLBMiss(TempReg1, TempReg2);
CPU_Message("");
CPU_Message(stdstr_f(" MemoryReadMap_%X_Found:", m_CompilePC).c_str());
SetJump8(JumpFound, *g_RecompPos);
TempReg3 = Map_TempReg(x86_Any, -1, false);
MoveX86regPointerToX86reg(TempReg1, TempReg2, TempReg3); MoveX86regPointerToX86reg(TempReg1, TempReg2, TempReg3);
sprintf(Name, "_FPR_S[%d]", m_Opcode.ft); sprintf(Name, "_FPR_S[%d]", m_Opcode.ft);
MoveVariableToX86reg(&_FPR_S[m_Opcode.ft], Name, TempReg2); MoveVariableToX86reg(&_FPR_S[m_Opcode.ft], Name, TempReg2);
@ -4227,11 +4393,20 @@ void CX86RecompilerOps::LDC1()
} }
TestReadBreakpoint(TempReg1, (void *)x86TestReadBreakpoint64, "x86TestReadBreakpoint64"); TestReadBreakpoint(TempReg1, (void *)x86TestReadBreakpoint64, "x86TestReadBreakpoint64");
TempReg2 = Map_TempReg(x86_Any, -1, false); TempReg2 = Map_TempReg(x86_Any, -1, false);
TempReg3 = Map_TempReg(x86_Any, -1, false);
MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_MemoryReadMap, "MMU->m_MemoryReadMap", TempReg2, TempReg2, 4);
CompConstToX86reg(TempReg2, (uint32_t)-1);
JneLabel8(stdstr_f("MemoryReadMap_%X_Found", m_CompilePC).c_str(), 0);
uint8_t * JumpFound = (uint8_t *)(*g_RecompPos - 1);
MoveX86RegToX86Reg(TempReg1, TempReg2); MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12); ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4); MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4);
CompileReadTLBMiss(TempReg1, TempReg2); CompileReadTLBMiss(TempReg1, TempReg2);
TempReg3 = Map_TempReg(x86_Any, -1, false); CPU_Message("");
CPU_Message(stdstr_f(" MemoryReadMap_%X_Found:", m_CompilePC).c_str());
SetJump8(JumpFound, *g_RecompPos);
MoveX86regPointerToX86reg(TempReg1, TempReg2, TempReg3); MoveX86regPointerToX86reg(TempReg1, TempReg2, TempReg3);
Push(TempReg2); Push(TempReg2);
sprintf(Name, "_FPR_S[%d]", m_Opcode.ft); sprintf(Name, "_FPR_S[%d]", m_Opcode.ft);
@ -4306,8 +4481,17 @@ void CX86RecompilerOps::LD()
TempReg2 = Map_TempReg(x86_Any, -1, false); TempReg2 = Map_TempReg(x86_Any, -1, false);
MoveX86RegToX86Reg(TempReg1, TempReg2); MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12); ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_MemoryReadMap, "MMU->m_MemoryReadMap", TempReg2, TempReg2, 4);
CompConstToX86reg(TempReg2, (uint32_t)-1);
JneLabel8(stdstr_f("MemoryReadMap_%X_Found", m_CompilePC).c_str(), 0);
uint8_t * JumpFound = (uint8_t *)(*g_RecompPos - 1);
MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4); MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4);
CompileReadTLBMiss(TempReg1, TempReg2); CompileReadTLBMiss(TempReg1, TempReg2);
CPU_Message("");
CPU_Message(stdstr_f(" MemoryReadMap_%X_Found:", m_CompilePC).c_str());
SetJump8(JumpFound, *g_RecompPos);
Map_GPR_64bit(m_Opcode.rt, -1); Map_GPR_64bit(m_Opcode.rt, -1);
MoveX86regPointerToX86reg(TempReg1, TempReg2, GetMipsRegMapHi(m_Opcode.rt)); MoveX86regPointerToX86reg(TempReg1, TempReg2, GetMipsRegMapHi(m_Opcode.rt));
MoveX86regPointerToX86regDisp8(TempReg1, TempReg2, GetMipsRegMapLo(m_Opcode.rt), 4); MoveX86regPointerToX86regDisp8(TempReg1, TempReg2, GetMipsRegMapLo(m_Opcode.rt), 4);
@ -4369,14 +4553,23 @@ void CX86RecompilerOps::SWC1()
AddConstToX86Reg(TempReg1, (int16_t)m_Opcode.immediate); AddConstToX86Reg(TempReg1, (int16_t)m_Opcode.immediate);
} }
TestWriteBreakpoint(TempReg1, (void *)x86TestWriteBreakpoint32, "x86TestWriteBreakpoint32"); TestWriteBreakpoint(TempReg1, (void *)x86TestWriteBreakpoint32, "x86TestWriteBreakpoint32");
UnMap_FPR(m_Opcode.ft, true);
x86Reg TempReg2 = Map_TempReg(x86_Any, -1, false); x86Reg TempReg2 = Map_TempReg(x86_Any, -1, false);
x86Reg TempReg3 = Map_TempReg(x86_Any, -1, false);
MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_MemoryWriteMap, "MMU->m_MemoryWriteMap", TempReg2, TempReg2, 4);
CompConstToX86reg(TempReg2, (uint32_t)-1);
JneLabel8(stdstr_f("MemoryWriteMap_%X_Found", m_CompilePC).c_str(), 0);
uint8_t * JumpFound = (uint8_t *)(*g_RecompPos - 1);
MoveX86RegToX86Reg(TempReg1, TempReg2); MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12); ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4); MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4);
CompileWriteTLBMiss(TempReg1, TempReg2); CompileWriteTLBMiss(TempReg1, TempReg2);
CPU_Message("");
CPU_Message(stdstr_f(" MemoryWriteMap_%X_Found:", m_CompilePC).c_str());
SetJump8(JumpFound, *g_RecompPos);
UnMap_FPR(m_Opcode.ft, true);
x86Reg TempReg3 = Map_TempReg(x86_Any, -1, false);
sprintf(Name, "_FPR_S[%d]", m_Opcode.ft); sprintf(Name, "_FPR_S[%d]", m_Opcode.ft);
MoveVariableToX86reg(&_FPR_S[m_Opcode.ft], Name, TempReg3); MoveVariableToX86reg(&_FPR_S[m_Opcode.ft], Name, TempReg3);
MoveX86PointerToX86reg(TempReg3, TempReg3); MoveX86PointerToX86reg(TempReg3, TempReg3);
@ -4433,12 +4626,22 @@ void CX86RecompilerOps::SDC1()
} }
TestWriteBreakpoint(TempReg1, (void *)x86TestWriteBreakpoint64, "x86TestWriteBreakpoint64"); TestWriteBreakpoint(TempReg1, (void *)x86TestWriteBreakpoint64, "x86TestWriteBreakpoint64");
x86Reg TempReg2 = Map_TempReg(x86_Any, -1, false); x86Reg TempReg2 = Map_TempReg(x86_Any, -1, false);
x86Reg TempReg3 = Map_TempReg(x86_Any, -1, false);
MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_MemoryWriteMap, "MMU->m_MemoryWriteMap", TempReg2, TempReg2, 4);
CompConstToX86reg(TempReg2, (uint32_t)-1);
JneLabel8(stdstr_f("MemoryWriteMap_%X_Found", m_CompilePC).c_str(), 0);
uint8_t * JumpFound = (uint8_t *)(*g_RecompPos - 1);
MoveX86RegToX86Reg(TempReg1, TempReg2); MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12); ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4); MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4);
CompileWriteTLBMiss(TempReg1, TempReg2); CompileWriteTLBMiss(TempReg1, TempReg2);
CPU_Message("");
CPU_Message(stdstr_f(" MemoryWriteMap_%X_Found:", m_CompilePC).c_str());
SetJump8(JumpFound, *g_RecompPos);
x86Reg TempReg3 = Map_TempReg(x86_Any, -1, false);
sprintf(Name, "_FPR_D[%d]", m_Opcode.ft); sprintf(Name, "_FPR_D[%d]", m_Opcode.ft);
MoveVariableToX86reg((uint8_t *)&_FPR_D[m_Opcode.ft], Name, TempReg3); MoveVariableToX86reg((uint8_t *)&_FPR_D[m_Opcode.ft], Name, TempReg3);
AddConstToX86Reg(TempReg3, 4); AddConstToX86Reg(TempReg3, 4);
@ -4512,11 +4715,21 @@ void CX86RecompilerOps::SD()
Compile_StoreInstructClean(TempReg1, 8); Compile_StoreInstructClean(TempReg1, 8);
TestWriteBreakpoint(TempReg1, (void *)x86TestWriteBreakpoint64, "x86TestWriteBreakpoint64"); TestWriteBreakpoint(TempReg1, (void *)x86TestWriteBreakpoint64, "x86TestWriteBreakpoint64");
x86Reg RtTempReg = IsUnknown(m_Opcode.rt) ? Map_TempReg(x86_Any, -1, false) : x86_Any;
TempReg2 = Map_TempReg(x86_Any, -1, false); TempReg2 = Map_TempReg(x86_Any, -1, false);
MoveX86RegToX86Reg(TempReg1, TempReg2); MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12); ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_MemoryWriteMap, "MMU->m_MemoryWriteMap", TempReg2, TempReg2, 4);
CompConstToX86reg(TempReg2, (uint32_t)-1);
JneLabel8(stdstr_f("MemoryWriteMap_%X_Found", m_CompilePC).c_str(), 0);
uint8_t * JumpFound = (uint8_t *)(*g_RecompPos - 1);
MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4); MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4);
CompileWriteTLBMiss(TempReg1, TempReg2); CompileWriteTLBMiss(TempReg1, TempReg2);
CPU_Message("");
CPU_Message(stdstr_f(" MemoryWriteMap_%X_Found:", m_CompilePC).c_str());
SetJump8(JumpFound, *g_RecompPos);
if (IsConst(m_Opcode.rt)) if (IsConst(m_Opcode.rt))
{ {
@ -4546,10 +4759,10 @@ void CX86RecompilerOps::SD()
} }
else else
{ {
x86Reg Reg = Map_TempReg(x86_Any, m_Opcode.rt, true); Map_TempReg(RtTempReg, m_Opcode.rt, true);
MoveX86regToX86regPointer(Reg, TempReg1, TempReg2); MoveX86regToX86regPointer(RtTempReg, TempReg1, TempReg2);
AddConstToX86Reg(TempReg1, 4); AddConstToX86Reg(TempReg1, 4);
MoveX86regToX86regPointer(Map_TempReg(Reg, m_Opcode.rt, false), TempReg1, TempReg2); MoveX86regToX86regPointer(Map_TempReg(RtTempReg, m_Opcode.rt, false), TempReg1, TempReg2);
} }
} }
} }
@ -9892,6 +10105,7 @@ void CX86RecompilerOps::CompileExit(uint32_t JumpPC, uint32_t TargetPC, CRegInfo
CompileSystemCheck((uint32_t)-1, ExitRegSet); CompileSystemCheck((uint32_t)-1, ExitRegSet);
} }
} }
#ifdef LinkBlocks
if (g_SyncSystem) if (g_SyncSystem)
{ {
#ifdef _MSC_VER #ifdef _MSC_VER
@ -9903,7 +10117,6 @@ void CX86RecompilerOps::CompileExit(uint32_t JumpPC, uint32_t TargetPC, CRegInfo
AddConstToX86Reg(x86_ESP, 4); AddConstToX86Reg(x86_ESP, 4);
#endif #endif
} }
#ifdef LinkBlocks
if (bSMM_ValidFunc == false) if (bSMM_ValidFunc == false)
{ {
if (LookUpMode() == FuncFind_ChangeMemory) if (LookUpMode() == FuncFind_ChangeMemory)
@ -10148,8 +10361,17 @@ void CX86RecompilerOps::SB_Const(uint8_t Value, uint32_t VAddr)
MoveConstToX86reg(VAddr, TempReg1); MoveConstToX86reg(VAddr, TempReg1);
MoveX86RegToX86Reg(TempReg1, TempReg2); MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12); ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_MemoryWriteMap, "MMU->m_MemoryWriteMap", TempReg2, TempReg2, 4);
CompConstToX86reg(TempReg2, (uint32_t)-1);
JneLabel8(stdstr_f("MemoryWriteMap_%X_Found", m_CompilePC).c_str(), 0);
uint8_t * JumpFound = (uint8_t *)(*g_RecompPos - 1);
MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4); MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4);
CompileWriteTLBMiss(TempReg1, TempReg2); CompileWriteTLBMiss(TempReg1, TempReg2);
CPU_Message("");
CPU_Message(stdstr_f(" MemoryWriteMap_%X_Found:", m_CompilePC).c_str());
SetJump8(JumpFound, *g_RecompPos);
MoveConstByteToX86regPointer(Value, TempReg1, TempReg2); MoveConstByteToX86regPointer(Value, TempReg1, TempReg2);
return; return;
} }
@ -10196,8 +10418,17 @@ void CX86RecompilerOps::SB_Register(x86Reg Reg, uint32_t VAddr)
MoveConstToX86reg(VAddr, TempReg1); MoveConstToX86reg(VAddr, TempReg1);
MoveX86RegToX86Reg(TempReg1, TempReg2); MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12); ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_MemoryWriteMap, "MMU->m_MemoryWriteMap", TempReg2, TempReg2, 4);
CompConstToX86reg(TempReg2, (uint32_t)-1);
JneLabel8(stdstr_f("MemoryWriteMap_%X_Found", m_CompilePC).c_str(), 0);
uint8_t * JumpFound = (uint8_t *)(*g_RecompPos - 1);
MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4); MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4);
CompileWriteTLBMiss(TempReg1, TempReg2); CompileWriteTLBMiss(TempReg1, TempReg2);
CPU_Message("");
CPU_Message(stdstr_f(" MemoryWriteMap_%X_Found:", m_CompilePC).c_str());
SetJump8(JumpFound, *g_RecompPos);
MoveX86regByteToX86regPointer(Reg, TempReg1, TempReg2); MoveX86regByteToX86regPointer(Reg, TempReg1, TempReg2);
return; return;
} }
@ -10245,8 +10476,17 @@ void CX86RecompilerOps::SH_Const(uint16_t Value, uint32_t VAddr)
MoveConstToX86reg(VAddr, TempReg1); MoveConstToX86reg(VAddr, TempReg1);
MoveX86RegToX86Reg(TempReg1, TempReg2); MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12); ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_MemoryWriteMap, "MMU->m_MemoryWriteMap", TempReg2, TempReg2, 4);
CompConstToX86reg(TempReg2, (uint32_t)-1);
JneLabel8(stdstr_f("MemoryWriteMap_%X_Found", m_CompilePC).c_str(), 0);
uint8_t * JumpFound = (uint8_t *)(*g_RecompPos - 1);
MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4); MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4);
CompileWriteTLBMiss(TempReg1, TempReg2); CompileWriteTLBMiss(TempReg1, TempReg2);
CPU_Message("");
CPU_Message(stdstr_f(" MemoryWriteMap_%X_Found:", m_CompilePC).c_str());
SetJump8(JumpFound, *g_RecompPos);
MoveConstHalfToX86regPointer(Value, TempReg1, TempReg2); MoveConstHalfToX86regPointer(Value, TempReg1, TempReg2);
return; return;
} }
@ -10296,8 +10536,17 @@ void CX86RecompilerOps::SH_Register(x86Reg Reg, uint32_t VAddr)
MoveConstToX86reg(VAddr, TempReg1); MoveConstToX86reg(VAddr, TempReg1);
MoveX86RegToX86Reg(TempReg1, TempReg2); MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12); ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_MemoryWriteMap, "MMU->m_MemoryWriteMap", TempReg2, TempReg2, 4);
CompConstToX86reg(TempReg2, (uint32_t)-1);
JneLabel8(stdstr_f("MemoryWriteMap_%X_Found", m_CompilePC).c_str(), 0);
uint8_t * JumpFound = (uint8_t *)(*g_RecompPos - 1);
MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4); MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4);
CompileWriteTLBMiss(TempReg1, TempReg2); CompileWriteTLBMiss(TempReg1, TempReg2);
CPU_Message("");
CPU_Message(stdstr_f(" MemoryWriteMap_%X_Found:", m_CompilePC).c_str());
SetJump8(JumpFound, *g_RecompPos);
MoveX86regHalfToX86regPointer(Reg, TempReg1, TempReg2); MoveX86regHalfToX86regPointer(Reg, TempReg1, TempReg2);
return; return;
} }
@ -10346,8 +10595,17 @@ void CX86RecompilerOps::SW_Const(uint32_t Value, uint32_t VAddr)
MoveConstToX86reg(VAddr, TempReg1); MoveConstToX86reg(VAddr, TempReg1);
MoveX86RegToX86Reg(TempReg1, TempReg2); MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12); ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_MemoryWriteMap, "MMU->m_MemoryWriteMap", TempReg2, TempReg2, 4);
CompConstToX86reg(TempReg2, (uint32_t)-1);
JneLabel8(stdstr_f("MemoryWriteMap_%X_Found", m_CompilePC).c_str(), 0);
uint8_t * JumpFound = (uint8_t *)(*g_RecompPos - 1);
MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4); MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4);
CompileWriteTLBMiss(TempReg1, TempReg2); CompileWriteTLBMiss(TempReg1, TempReg2);
CPU_Message("");
CPU_Message(stdstr_f(" MemoryWriteMap_%X_Found:", m_CompilePC).c_str());
SetJump8(JumpFound, *g_RecompPos);
MoveConstToX86regPointer(Value, TempReg1, TempReg2); MoveConstToX86regPointer(Value, TempReg1, TempReg2);
return; return;
} }
@ -10914,8 +11172,17 @@ void CX86RecompilerOps::SW_Register(x86Reg Reg, uint32_t VAddr)
MoveConstToX86reg(VAddr, TempReg1); MoveConstToX86reg(VAddr, TempReg1);
MoveX86RegToX86Reg(TempReg1, TempReg2); MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12); ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_MemoryWriteMap, "MMU->m_MemoryWriteMap", TempReg2, TempReg2, 4);
CompConstToX86reg(TempReg2, (uint32_t)-1);
JneLabel8(stdstr_f("MemoryWriteMap_%X_Found", m_CompilePC).c_str(), 0);
uint8_t * JumpFound = (uint8_t *)(*g_RecompPos - 1);
MoveX86RegToX86Reg(TempReg1, TempReg2);
ShiftRightUnsignImmed(TempReg2, 12);
MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4); MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4);
CompileWriteTLBMiss(TempReg1, TempReg2); CompileWriteTLBMiss(TempReg1, TempReg2);
CPU_Message("");
CPU_Message(stdstr_f(" MemoryWriteMap_%X_Found:", m_CompilePC).c_str());
SetJump8(JumpFound, *g_RecompPos);
MoveX86regToX86regPointer(Reg, TempReg1, TempReg2); MoveX86regToX86regPointer(Reg, TempReg1, TempReg2);
return; return;
} }
@ -10952,6 +11219,7 @@ void CX86RecompilerOps::SW_Register(x86Reg Reg, uint32_t VAddr)
case 0x04040000: MoveX86regToVariable(Reg, &g_Reg->SP_MEM_ADDR_REG, "SP_MEM_ADDR_REG"); break; case 0x04040000: MoveX86regToVariable(Reg, &g_Reg->SP_MEM_ADDR_REG, "SP_MEM_ADDR_REG"); break;
case 0x04040004: MoveX86regToVariable(Reg, &g_Reg->SP_DRAM_ADDR_REG, "SP_DRAM_ADDR_REG"); break; case 0x04040004: MoveX86regToVariable(Reg, &g_Reg->SP_DRAM_ADDR_REG, "SP_DRAM_ADDR_REG"); break;
case 0x04040008: case 0x04040008:
case 0x0404000C:
m_RegWorkingSet.BeforeCallDirect(); m_RegWorkingSet.BeforeCallDirect();
PushImm32(0xFFFFFFFF); PushImm32(0xFFFFFFFF);
Push(Reg); Push(Reg);
@ -10963,19 +11231,6 @@ void CX86RecompilerOps::SW_Register(x86Reg Reg, uint32_t VAddr)
PushImm32((uint32_t)&g_MMU->m_SPRegistersHandler); PushImm32((uint32_t)&g_MMU->m_SPRegistersHandler);
Call_Direct(AddressOf(&SPRegistersHandler::Write32), "SPRegistersHandler::Write32"); Call_Direct(AddressOf(&SPRegistersHandler::Write32), "SPRegistersHandler::Write32");
AddConstToX86Reg(x86_ESP, 16); AddConstToX86Reg(x86_ESP, 16);
#endif
m_RegWorkingSet.AfterCallDirect();
break;
case 0x0404000C:
MoveX86regToVariable(Reg, &g_Reg->SP_WR_LEN_REG, "SP_WR_LEN_REG");
m_RegWorkingSet.BeforeCallDirect();
#ifdef _MSC_VER
MoveConstToX86reg((uint32_t)((CDMA *)g_MMU), x86_ECX);
Call_Direct(AddressOf(&CDMA::SP_DMA_WRITE), "CDMA::SP_DMA_WRITE");
#else
PushImm32((uint32_t)((CDMA *)g_MMU));
Call_Direct(AddressOf(&CDMA::SP_DMA_WRITE), "CDMA::SP_DMA_WRITE");
AddConstToX86Reg(x86_ESP, 4);
#endif #endif
m_RegWorkingSet.AfterCallDirect(); m_RegWorkingSet.AfterCallDirect();
break; break;
@ -11417,7 +11672,7 @@ void CX86RecompilerOps::ResetMemoryStack()
TempReg = Map_TempReg(x86_Any, -1, false); TempReg = Map_TempReg(x86_Any, -1, false);
MoveX86RegToX86Reg(Reg, TempReg); MoveX86RegToX86Reg(Reg, TempReg);
ShiftRightUnsignImmed(TempReg, 12); ShiftRightUnsignImmed(TempReg, 12);
MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg, TempReg, 4); MoveVariableDispToX86Reg(g_MMU->m_MemoryReadMap, "MMU->m_MemoryReadMap", TempReg, TempReg, 4);
AddX86RegToX86Reg(Reg, TempReg); AddX86RegToX86Reg(Reg, TempReg);
MoveX86regToVariable(Reg, &(g_Recompiler->MemoryStackPos()), "MemoryStack"); MoveX86regToVariable(Reg, &(g_Recompiler->MemoryStackPos()), "MemoryStack");
} }