[Android] Handle exception from strhne and strh

Source/Project64-core/MemoryExceptionFilter.cpp

@@ -536,6 +536,34 @@ bool CMipsMemoryVM::FilterArmException(uint32_t MemAddress, mcontext_t & context
         return true;
     }
 
+    if (OpCode32->reg_cond_imm8.opcode == 0 && OpCode32->reg_cond_imm8.opcode1 == 1 && OpCode32->reg_cond_imm8.opcode2 == 0 && OpCode32->reg_cond_imm8.opcode3 == 0xB)
+    {
+        //11c020b0 	strhne	r2, [r0]
+        if (!g_MMU->SH_NonMemory(MemAddress, *ArmRegisters[OpCode32->reg_cond_imm8.rt]))
+        {
+            if (g_Settings->LoadDword(Debugger_ShowUnhandledMemory))
+            {
+                g_Notify->DisplayError(stdstr_f("Failed to store half word\n\nMIPS Address: %08X\nPC Address: %08X", MemAddress, context.arm_pc).c_str());
+            }
+        }
+        context.arm_pc = context.arm_pc + 4;
+        return true;
+    }
+
+    if (OpCode->Imm5.opcode == 0x10)
+    {
+        // 00 80 strh	r0, [r0, #0]
+        if (!g_MMU->SH_NonMemory(MemAddress, *ArmRegisters[OpCode->Imm5.rt]))
+        {
+            if (g_Settings->LoadDword(Debugger_ShowUnhandledMemory))
+            {
+                g_Notify->DisplayError(stdstr_f("Failed to store half word\n\nMIPS Address: %08X\nPC Address: %08X", MemAddress, context.arm_pc).c_str());
+            }
+        }
+        context.arm_pc = context.arm_pc + 2;
+        return true;
+    }
+
     if (OpCode->Reg.opcode == 0x29)
     {
         // 14 52 strh	r4, [r2, r0]

Source/Project64-core/N64System/Recompiler/Arm/ArmOpCode.h

@@ -273,6 +273,22 @@ union Arm32Opcode
         unsigned cond : 4;
     } reg_cond_imm5;
 
+    struct
+    {
+        unsigned imm4l : 4;
+        unsigned opcode3 : 4;
+        unsigned imm4h : 4;
+        unsigned rt : 4;
+        unsigned rn : 4;
+        unsigned opcode2 : 1;
+        unsigned w : 1;
+        unsigned opcode1 : 1;
+        unsigned u : 1;
+        unsigned p : 1;
+        unsigned opcode : 3;
+        unsigned cond : 4;
+    } reg_cond_imm8;
+
     struct
     {
         unsigned imm12 : 12;