Update Recompiler Sections.c
Fix typos, punctuation, abbreviations, convert multi line comments into single line comments, fix some formatting
This commit is contained in:
Derek "Turtle" Roe
parent
77e502b99d
commit
e3009170c6
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@ -12,15 +12,12 @@
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#include "x86.h"
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#include "Types.h"
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#pragma warning(disable : 4152) // nonstandard extension, function/data pointer conversion in expression
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#pragma warning(disable : 4152) // Non-standard extension, function/data pointer conversion in expression
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void RSP_Sections_VMUDH ( OPCODE RspOp, DWORD AccumStyle ) {
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char Reg[256];
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/*****************************************
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** VMUDH
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** - affects the upper 32-bits
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******************************************/
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// VMUDH - affects the upper 32-bits
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if (AccumStyle == Low16BitAccum) {
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MmxXorRegToReg(x86_MM0, x86_MM0);
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@ -30,13 +27,13 @@ void RSP_Sections_VMUDH ( OPCODE RspOp, DWORD AccumStyle ) {
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RSPOpC = RspOp;
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/**** Load source registers ****/
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// Load source registers
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sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rd);
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MmxMoveQwordVariableToReg(x86_MM0, &RSP_Vect[RspOp.rd].HW[0], Reg);
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sprintf(Reg, "RSP_Vect[%i].HW[4]", RspOp.rd);
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MmxMoveQwordVariableToReg(x86_MM1, &RSP_Vect[RspOp.rd].HW[4], Reg);
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/******* VMUDH *******/
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// VMUDH
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if ((RspOp.rs & 0x0f) < 2) {
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sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rt);
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MmxMoveQwordVariableToReg(x86_MM2, &RSP_Vect[RspOp.rt].HW[0], Reg);
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@ -74,10 +71,7 @@ void RSP_Sections_VMUDH ( OPCODE RspOp, DWORD AccumStyle ) {
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void RSP_Sections_VMADH ( OPCODE RspOp, DWORD AccumStyle ) {
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char Reg[256];
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/*****************************************
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** VMADH
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** - affects the upper 32-bits
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******************************************/
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// VMADH - affects the upper 32-bits
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if (AccumStyle == Low16BitAccum) {
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return;
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@ -85,13 +79,13 @@ void RSP_Sections_VMADH ( OPCODE RspOp, DWORD AccumStyle ) {
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RSPOpC = RspOp;
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/**** Load source registers ****/
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// Load source registers
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sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rd);
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MmxMoveQwordVariableToReg(x86_MM0 + 2, &RSP_Vect[RspOp.rd].HW[0], Reg);
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sprintf(Reg, "RSP_Vect[%i].HW[4]", RspOp.rd);
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MmxMoveQwordVariableToReg(x86_MM1 + 2, &RSP_Vect[RspOp.rd].HW[4], Reg);
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/******* VMUDH *******/
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// VMUDH
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if ((RspOp.rs & 0x0f) < 2) {
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sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rt);
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MmxMoveQwordVariableToReg(x86_MM2 + 2, &RSP_Vect[RspOp.rt].HW[0], Reg);
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@ -132,10 +126,7 @@ void RSP_Sections_VMADH ( OPCODE RspOp, DWORD AccumStyle ) {
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void RSP_Sections_VMUDL ( OPCODE RspOp, DWORD AccumStyle ) {
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char Reg[256];
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/*****************************************
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** VMUDL
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** - affects the lower 16-bits
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******************************************/
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// VMUDL - affects the lower 16-bits
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if (AccumStyle != Low16BitAccum) {
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MmxXorRegToReg(x86_MM0, x86_MM0);
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@ -145,13 +136,13 @@ void RSP_Sections_VMUDL ( OPCODE RspOp, DWORD AccumStyle ) {
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RSPOpC = RspOp;
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/**** Load source registers ****/
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// Load source registers
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sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rd);
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MmxMoveQwordVariableToReg(x86_MM0, &RSP_Vect[RspOp.rd].HW[0], Reg);
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sprintf(Reg, "RSP_Vect[%i].HW[4]", RspOp.rd);
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MmxMoveQwordVariableToReg(x86_MM1, &RSP_Vect[RspOp.rd].HW[4], Reg);
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/******* VMUDL *******/
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// VMUDL
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if ((RspOp.rs & 0x0f) < 2) {
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sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rt);
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MmxMoveQwordVariableToReg(x86_MM2, &RSP_Vect[RspOp.rt].HW[0], Reg);
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@ -174,10 +165,7 @@ void RSP_Sections_VMUDL ( OPCODE RspOp, DWORD AccumStyle ) {
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void RSP_Sections_VMADL ( OPCODE RspOp, DWORD AccumStyle ) {
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char Reg[256];
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/*****************************************
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** VMADL
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** - affects the lower 16-bits
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******************************************/
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// VMADL - affects the lower 16-bits
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if (AccumStyle != Low16BitAccum) {
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return;
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@ -185,13 +173,13 @@ void RSP_Sections_VMADL ( OPCODE RspOp, DWORD AccumStyle ) {
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RSPOpC = RspOp;
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/**** Load source registers ****/
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// Load source registers
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sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rd);
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MmxMoveQwordVariableToReg(x86_MM0 + 2, &RSP_Vect[RspOp.rd].HW[0], Reg);
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sprintf(Reg, "RSP_Vect[%i].HW[4]", RspOp.rd);
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MmxMoveQwordVariableToReg(x86_MM1 + 2, &RSP_Vect[RspOp.rd].HW[4], Reg);
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/******* VMADL *******/
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// VMADL
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if ((RspOp.rs & 0x0f) < 2) {
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sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rt);
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MmxMoveQwordVariableToReg(x86_MM2 + 2, &RSP_Vect[RspOp.rt].HW[0], Reg);
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@ -217,10 +205,7 @@ void RSP_Sections_VMADL ( OPCODE RspOp, DWORD AccumStyle ) {
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void RSP_Sections_VMUDM ( OPCODE RspOp, DWORD AccumStyle ) {
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char Reg[256];
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/*****************************************
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** VMUDM
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** - affects the middle 32-bits, s16*u16
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******************************************/
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// VMUDM - affects the middle 32-bits, s16*u16
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if (AccumStyle == High16BitAccum) {
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MmxXorRegToReg(x86_MM0, x86_MM0);
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@ -230,13 +215,13 @@ void RSP_Sections_VMUDM ( OPCODE RspOp, DWORD AccumStyle ) {
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RSPOpC = RspOp;
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/**** Load source registers ****/
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// Load source registers
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sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rd);
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MmxMoveQwordVariableToReg(x86_MM0, &RSP_Vect[RspOp.rd].HW[0], Reg);
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sprintf(Reg, "RSP_Vect[%i].HW[4]", RspOp.rd);
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MmxMoveQwordVariableToReg(x86_MM1, &RSP_Vect[RspOp.rd].HW[4], Reg);
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/******* VMUDM *******/
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// VMUDM
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if (AccumStyle != Middle16BitAccum) {
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if ((RspOp.rs & 0x0f) < 2) {
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sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rt);
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@ -262,7 +247,7 @@ void RSP_Sections_VMUDM ( OPCODE RspOp, DWORD AccumStyle ) {
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sprintf(Reg, "RSP_Vect[%i].UHW[4]", RSPOpC.rt);
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MmxMoveQwordVariableToReg(x86_MM5, &RSP_Vect[RSPOpC.rt].UHW[4], Reg);
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/* Copy the signed portion */
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// Copy the signed portion
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MmxMoveRegToReg(x86_MM2, x86_MM0);
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MmxMoveRegToReg(x86_MM3, x86_MM1);
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@ -278,7 +263,7 @@ void RSP_Sections_VMUDM ( OPCODE RspOp, DWORD AccumStyle ) {
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} else if ((RSPOpC.rs & 0xF) >= 8) {
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RSP_Element2Mmx(x86_MM4);
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/* Copy the signed portion */
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// Copy the signed portion
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MmxMoveRegToReg(x86_MM2, x86_MM0);
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MmxMoveRegToReg(x86_MM3, x86_MM1);
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@ -294,7 +279,7 @@ void RSP_Sections_VMUDM ( OPCODE RspOp, DWORD AccumStyle ) {
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} else {
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RSP_MultiElement2Mmx(x86_MM4, x86_MM5);
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/* Copy the signed portion */
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// Copy the signed portion
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MmxMoveRegToReg(x86_MM2, x86_MM0);
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MmxMoveRegToReg(x86_MM3, x86_MM1);
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@ -309,7 +294,7 @@ void RSP_Sections_VMUDM ( OPCODE RspOp, DWORD AccumStyle ) {
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MmxPmullwRegToReg(x86_MM3, x86_MM5);
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}
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/* Add them up */
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// Add them up
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MmxPaddwRegToReg(x86_MM0, x86_MM2);
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MmxPaddwRegToReg(x86_MM1, x86_MM3);
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}
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@ -318,10 +303,7 @@ void RSP_Sections_VMUDM ( OPCODE RspOp, DWORD AccumStyle ) {
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void RSP_Sections_VMADM ( OPCODE RspOp, DWORD AccumStyle ) {
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char Reg[256];
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/*****************************************
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** VMADM
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** - affects the middle 32-bits, s16*u16
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******************************************/
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// VMADM - affects the middle 32-bits, s16*u16
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if (AccumStyle == High16BitAccum) {
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MmxXorRegToReg(x86_MM0, x86_MM0);
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@ -331,13 +313,13 @@ void RSP_Sections_VMADM ( OPCODE RspOp, DWORD AccumStyle ) {
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RSPOpC = RspOp;
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/**** Load source registers ****/
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// Load source registers
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sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rd);
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MmxMoveQwordVariableToReg(x86_MM0 + 2, &RSP_Vect[RspOp.rd].HW[0], Reg);
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sprintf(Reg, "RSP_Vect[%i].HW[4]", RspOp.rd);
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MmxMoveQwordVariableToReg(x86_MM1 + 2, &RSP_Vect[RspOp.rd].HW[4], Reg);
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/******* VMADM *******/
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// VMADM
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if (AccumStyle != Middle16BitAccum) {
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if ((RspOp.rs & 0x0f) < 2) {
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sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rt);
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@ -363,7 +345,7 @@ void RSP_Sections_VMADM ( OPCODE RspOp, DWORD AccumStyle ) {
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sprintf(Reg, "RSP_Vect[%i].UHW[4]", RSPOpC.rt);
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MmxMoveQwordVariableToReg(x86_MM5 + 2, &RSP_Vect[RSPOpC.rt].UHW[4], Reg);
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/* Copy the signed portion */
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// Copy the signed portion
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MmxMoveRegToReg(x86_MM2 + 2, x86_MM0 + 2);
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MmxMoveRegToReg(x86_MM3 + 2, x86_MM1 + 2);
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@ -379,7 +361,7 @@ void RSP_Sections_VMADM ( OPCODE RspOp, DWORD AccumStyle ) {
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} else if ((RSPOpC.rs & 0xF) >= 8) {
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RSP_Element2Mmx(x86_MM4 + 2);
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/* Copy the signed portion */
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// Copy the signed portion
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MmxMoveRegToReg(x86_MM2 + 2, x86_MM0 + 2);
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MmxMoveRegToReg(x86_MM3 + 2, x86_MM1 + 2);
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@ -395,7 +377,7 @@ void RSP_Sections_VMADM ( OPCODE RspOp, DWORD AccumStyle ) {
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} else {
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RSP_MultiElement2Mmx(x86_MM4 + 2, x86_MM5 + 2);
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/* Copy the signed portion */
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// Copy the signed portion
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MmxMoveRegToReg(x86_MM2 + 2, x86_MM0 + 2);
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MmxMoveRegToReg(x86_MM3 + 2, x86_MM1 + 2);
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@ -410,7 +392,7 @@ void RSP_Sections_VMADM ( OPCODE RspOp, DWORD AccumStyle ) {
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MmxPmullwRegToReg(x86_MM3 + 2, x86_MM5 + 2);
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}
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/* Add them up */
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// Add them up
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MmxPaddwRegToReg(x86_MM0 + 2, x86_MM2 + 2);
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MmxPaddwRegToReg(x86_MM1 + 2, x86_MM3 + 2);
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}
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@ -422,10 +404,7 @@ void RSP_Sections_VMADM ( OPCODE RspOp, DWORD AccumStyle ) {
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void RSP_Sections_VMUDN ( OPCODE RspOp, DWORD AccumStyle ) {
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char Reg[256];
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/*****************************************
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** VMUDN
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** - affects the middle 32-bits, u16*s16
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******************************************/
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// VMUDN - affects the middle 32-bits, u16*s16
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if (AccumStyle == High16BitAccum) {
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MmxXorRegToReg(x86_MM0, x86_MM0);
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@ -435,10 +414,10 @@ void RSP_Sections_VMUDN ( OPCODE RspOp, DWORD AccumStyle ) {
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RSPOpC = RspOp;
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/******* VMUDN *******/
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// VMUDN
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if (AccumStyle != Middle16BitAccum) {
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/**** Load source registers ****/
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// Load source registers
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sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rd);
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MmxMoveQwordVariableToReg(x86_MM0, &RSP_Vect[RspOp.rd].HW[0], Reg);
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sprintf(Reg, "RSP_Vect[%i].HW[4]", RspOp.rd);
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@ -465,12 +444,10 @@ void RSP_Sections_VMUDN ( OPCODE RspOp, DWORD AccumStyle ) {
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}
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} else {
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/***
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** NOTE: for code clarity, this is the same as VMUDM,
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** just the mmx registers are swapped, this is easier
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****/
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// NOTE: for code clarity, this is the same as VMUDM,
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// just the MMX registers are swapped, this is easier
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/**** Load source registers ****/
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// Load source registers
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sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rd);
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MmxMoveQwordVariableToReg(x86_MM4, &RSP_Vect[RspOp.rd].HW[0], Reg);
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sprintf(Reg, "RSP_Vect[%i].HW[4]", RspOp.rd);
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@ -488,7 +465,7 @@ void RSP_Sections_VMUDN ( OPCODE RspOp, DWORD AccumStyle ) {
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RSP_MultiElement2Mmx(x86_MM0, x86_MM1);
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}
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/* Copy the signed portion */
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// Copy the signed portion
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MmxMoveRegToReg(x86_MM2, x86_MM0);
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MmxMoveRegToReg(x86_MM3, x86_MM1);
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@ -502,7 +479,7 @@ void RSP_Sections_VMUDN ( OPCODE RspOp, DWORD AccumStyle ) {
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MmxPmullwRegToReg(x86_MM2, x86_MM4);
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MmxPmullwRegToReg(x86_MM3, x86_MM5);
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/* Add them up */
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// Add them up
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MmxPaddwRegToReg(x86_MM0, x86_MM2);
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MmxPaddwRegToReg(x86_MM1, x86_MM3);
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}
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@ -511,10 +488,7 @@ void RSP_Sections_VMUDN ( OPCODE RspOp, DWORD AccumStyle ) {
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void RSP_Sections_VMADN ( OPCODE RspOp, DWORD AccumStyle ) {
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char Reg[256];
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/*****************************************
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** VMADN
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** - affects the middle 32-bits, u16*s16
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******************************************/
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// VMADN - affects the middle 32-bits, u16*s16
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if (AccumStyle == High16BitAccum) {
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return;
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@ -522,9 +496,9 @@ void RSP_Sections_VMADN ( OPCODE RspOp, DWORD AccumStyle ) {
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RSPOpC = RspOp;
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/******* VMADN *******/
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// VMADN
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if (AccumStyle != Middle16BitAccum) {
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/**** Load source registers ****/
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// Load source registers
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sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rd);
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MmxMoveQwordVariableToReg(x86_MM0 + 2, &RSP_Vect[RspOp.rd].HW[0], Reg);
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sprintf(Reg, "RSP_Vect[%i].HW[4]", RspOp.rd);
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@ -551,12 +525,10 @@ void RSP_Sections_VMADN ( OPCODE RspOp, DWORD AccumStyle ) {
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}
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} else {
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/*
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** NOTE: for code clarity, this is the same as VMADM,
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** just the mmx registers are swapped, this is easier
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*/
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// NOTE: for code clarity, this is the same as VMADM,
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// just the MMX registers are swapped, this is easier
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/**** Load source registers ****/
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// Load source registers
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sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rd);
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MmxMoveQwordVariableToReg(x86_MM4 + 2, &RSP_Vect[RspOp.rd].HW[0], Reg);
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sprintf(Reg, "RSP_Vect[%i].HW[4]", RspOp.rd);
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@ -574,7 +546,7 @@ void RSP_Sections_VMADN ( OPCODE RspOp, DWORD AccumStyle ) {
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RSP_MultiElement2Mmx(x86_MM0 + 2, x86_MM1 + 2);
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}
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/* Copy the signed portion */
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// Copy the signed portion
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MmxMoveRegToReg(x86_MM2 + 2, x86_MM0 + 2);
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MmxMoveRegToReg(x86_MM3 + 2, x86_MM1 + 2);
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@ -588,15 +560,14 @@ void RSP_Sections_VMADN ( OPCODE RspOp, DWORD AccumStyle ) {
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MmxPmullwRegToReg(x86_MM2 + 2, x86_MM4 + 2);
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MmxPmullwRegToReg(x86_MM3 + 2, x86_MM5 + 2);
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/* Add them up */
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// Add them up
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MmxPaddwRegToReg(x86_MM0 + 2, x86_MM2 + 2);
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MmxPaddwRegToReg(x86_MM1 + 2, x86_MM3 + 2);
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}
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/*
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** only thing is when we are responsible for clamping
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||||
** so we adopt unsigned here?
|
||||
*/
|
||||
// Only thing is when we are responsible for clamping
|
||||
// So we adopt unsigned here?
|
||||
|
||||
MmxPaddswRegToReg(x86_MM0, x86_MM0 + 2);
|
||||
MmxPaddswRegToReg(x86_MM1, x86_MM1 + 2);
|
||||
|
||||
|
|
@ -605,10 +576,7 @@ void RSP_Sections_VMADN ( OPCODE RspOp, DWORD AccumStyle ) {
|
|||
void RSP_Sections_VMULF ( OPCODE RspOp, DWORD AccumStyle ) {
|
||||
char Reg[256];
|
||||
|
||||
/*****************************************
|
||||
** VMULF
|
||||
** - affects the middle 32-bits, s16*s16*2
|
||||
******************************************/
|
||||
// VMULF - affects the middle 32-bits, s16*s16*2
|
||||
|
||||
if (AccumStyle == High16BitAccum) {
|
||||
MmxXorRegToReg(x86_MM0, x86_MM0);
|
||||
|
|
@ -618,13 +586,13 @@ void RSP_Sections_VMULF ( OPCODE RspOp, DWORD AccumStyle ) {
|
|||
|
||||
RSPOpC = RspOp;
|
||||
|
||||
/**** Load source registers ****/
|
||||
// Load source registers
|
||||
sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rd);
|
||||
MmxMoveQwordVariableToReg(x86_MM0, &RSP_Vect[RspOp.rd].HW[0], Reg);
|
||||
sprintf(Reg, "RSP_Vect[%i].HW[4]", RspOp.rd);
|
||||
MmxMoveQwordVariableToReg(x86_MM1, &RSP_Vect[RspOp.rd].HW[4], Reg);
|
||||
|
||||
/******* VMULF *******/
|
||||
// VMULF
|
||||
if ((RspOp.rs & 0x0f) < 2) {
|
||||
sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rt);
|
||||
MmxMoveQwordVariableToReg(x86_MM2, &RSP_Vect[RspOp.rt].HW[0], Reg);
|
||||
|
|
@ -665,10 +633,7 @@ void RSP_Sections_VMULF ( OPCODE RspOp, DWORD AccumStyle ) {
|
|||
void RSP_Sections_VMACF ( OPCODE RspOp, DWORD AccumStyle ) {
|
||||
char Reg[256];
|
||||
|
||||
/*****************************************
|
||||
** VMACF
|
||||
** - affects the upper 32-bits, s16*s16*2
|
||||
******************************************/
|
||||
// VMACF - affects the upper 32-bits, s16*s16*2
|
||||
|
||||
if (AccumStyle == High16BitAccum) {
|
||||
return;
|
||||
|
|
@ -676,13 +641,13 @@ void RSP_Sections_VMACF ( OPCODE RspOp, DWORD AccumStyle ) {
|
|||
|
||||
RSPOpC = RspOp;
|
||||
|
||||
/**** Load source registers ****/
|
||||
// Load source registers
|
||||
sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rd);
|
||||
MmxMoveQwordVariableToReg(x86_MM0 + 2, &RSP_Vect[RspOp.rd].HW[0], Reg);
|
||||
sprintf(Reg, "RSP_Vect[%i].HW[4]", RspOp.rd);
|
||||
MmxMoveQwordVariableToReg(x86_MM1 + 2, &RSP_Vect[RspOp.rd].HW[4], Reg);
|
||||
|
||||
/******* VMACF *******/
|
||||
// VMACF
|
||||
if ((RspOp.rs & 0x0f) < 2) {
|
||||
sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rt);
|
||||
MmxMoveQwordVariableToReg(x86_MM2 + 2, &RSP_Vect[RspOp.rt].HW[0], Reg);
|
||||
|
|
@ -722,9 +687,9 @@ void RSP_Sections_VMACF ( OPCODE RspOp, DWORD AccumStyle ) {
|
|||
MmxPaddswRegToReg(x86_MM1, x86_MM1 + 2);
|
||||
}
|
||||
|
||||
/******************** Microcode Sections *********************/
|
||||
// Microcode sections
|
||||
|
||||
static DWORD Section_000_VMADN; /* Yah i know, but leave it */
|
||||
static DWORD Section_000_VMADN; // Yeah I know, but leave it
|
||||
|
||||
Boolean Check_Section_000(void)
|
||||
{
|
||||
|
|
@ -733,13 +698,9 @@ Boolean Check_Section_000(void)
|
|||
|
||||
RSP_LW_IMEM(CompilePC + 0x00, &op0.Hex);
|
||||
|
||||
/************************************
|
||||
** Example: (mario audio microcode)
|
||||
**
|
||||
** 0x574 VMUDN $v30, $v3, $v23
|
||||
** 0x578 VMADN $v30, $v4, $v23
|
||||
**
|
||||
*************************************/
|
||||
// Example: (Mario audio microcode)
|
||||
// 0x574 VMUDN $v30, $v3, $v23
|
||||
// 0x578 VMADN $v30, $v4, $v23
|
||||
|
||||
if (!(op0.op == RSP_CP2 && (op0.rs & 0x10) != 0 && op0.funct == RSP_VECTOR_VMUDN)) {
|
||||
return FALSE;
|
||||
|
|
@ -760,12 +721,12 @@ Boolean Check_Section_000(void)
|
|||
}
|
||||
}
|
||||
|
||||
/* We need at least 1 VMADN */
|
||||
// We need at least 1 VMADN
|
||||
if (Section_000_VMADN == 0) {
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
/* FIXME: check dest & flushes */
|
||||
// TODO: check destination and flushes
|
||||
if (TRUE == WriteToAccum(7, CompilePC + 0x4 + (Section_000_VMADN * 4) - 0x4)) {
|
||||
return FALSE;
|
||||
}
|
||||
|
|
@ -838,12 +799,9 @@ Boolean Check_Section_001(void)
|
|||
|
||||
RSP_LW_IMEM(CompilePC + 0x00, &op0.Hex);
|
||||
|
||||
/************************************
|
||||
** Example: (mario audio microcode)
|
||||
**
|
||||
** 0xCC0 VMULF $v28, $v28, $v10 [6]
|
||||
** 0xCC4 VMACF $v28, $v17, $v16
|
||||
*************************************/
|
||||
// Example: (Mario audio microcode)
|
||||
// 0xCC0 VMULF $v28, $v28, $v10 [6]
|
||||
// 0xCC4 VMACF $v28, $v17, $v16
|
||||
|
||||
if (!(op0.op == RSP_CP2 && (op0.rs & 0x10) != 0 && op0.funct == RSP_VECTOR_VMULF)) {
|
||||
return FALSE;
|
||||
|
|
@ -864,7 +822,7 @@ Boolean Check_Section_001(void)
|
|||
}
|
||||
}
|
||||
|
||||
/* We need at least 1 VMACF */
|
||||
// We need at least 1 VMACF
|
||||
if (Section_001_VMACF == 0) {
|
||||
return FALSE;
|
||||
}
|
||||
|
|
@ -873,7 +831,7 @@ Boolean Check_Section_001(void)
|
|||
return FALSE;
|
||||
}
|
||||
|
||||
/* dests are checked elsewhere, this is fine */
|
||||
// Destinations are checked elsewhere, this is fine
|
||||
if (TRUE == WriteToAccum(7, CompilePC + 0x4 + (Section_001_VMACF * 4) - 0x4)) {
|
||||
return FALSE;
|
||||
}
|
||||
|
|
@ -931,9 +889,8 @@ Boolean Check_Section_002(void)
|
|||
RSP_LW_IMEM(CompilePC + (Count * 0x04), &op[Count].Hex);
|
||||
}
|
||||
|
||||
/************************************
|
||||
** Example: (mario audio microcode)
|
||||
**
|
||||
/*
|
||||
** Example: (Mario audio microcode)
|
||||
** 5F4 VMUDH $v2, $v21, $v27 [6]
|
||||
** 5F8 VMADH $v2, $v20, $v27 [7]
|
||||
** 5FC VMADH $v2, $v19, $v30 [0]
|
||||
|
|
@ -946,7 +903,7 @@ Boolean Check_Section_002(void)
|
|||
** 618 VMADH $v2, $v30, $v31 [5]
|
||||
** 61C VSAW $v26 [9], $v7, $v28
|
||||
** 620 VSAW $v28 [8], $v7, $v28
|
||||
************************************/
|
||||
*/
|
||||
|
||||
if (IsMmxEnabled == FALSE) {
|
||||
return FALSE;
|
||||
|
|
@ -1004,12 +961,12 @@ void Compile_Section_002 ( void ) {
|
|||
vmudh = op[0];
|
||||
RSP_Sections_VMUDH(vmudh, High16BitAccum);
|
||||
|
||||
/******* VMADHs *******/
|
||||
// VMADHs
|
||||
for (Count = 1; Count < 10; Count++) {
|
||||
RSP_Sections_VMADH(op[Count], High16BitAccum);
|
||||
}
|
||||
|
||||
/***** VSAWs *****/
|
||||
// VSAWs
|
||||
vsaw = op[10];
|
||||
MmxXorRegToReg(x86_MM4, x86_MM4);
|
||||
sprintf(Reg, "RSP_Vect[%i].HW[0]", RSPOpC.sa);
|
||||
|
|
@ -1037,14 +994,12 @@ Boolean Check_Section_003(void)
|
|||
RSP_LW_IMEM(CompilePC + (Count * 0x04), &op[Count].Hex);
|
||||
}
|
||||
|
||||
/************************************
|
||||
** Example: (zelda audio microcode)
|
||||
**
|
||||
** VMUDM $v23, $v31, $v23 [7]
|
||||
** VMADH $v23, $v31, $v22 [7]
|
||||
** VMADM $v22, $v25, $v18 [4]
|
||||
** VMADN $v23, $v31, $v30 [0]
|
||||
************************************/
|
||||
|
||||
// Example: (Zelda audio microcode)
|
||||
// VMUDM $v23, $v31, $v23 [7]
|
||||
// VMADH $v23, $v31, $v22 [7]
|
||||
// VMADM $v22, $v25, $v18 [4]
|
||||
// VMADN $v23, $v31, $v30 [0]
|
||||
|
||||
if (op[0].Hex == 0x4BF7FDC5 && op[1].Hex == 0x4BF6FDCF && op[2].Hex == 0x4B92CD8D && op[3].Hex == 0x4B1EFDCE) {
|
||||
if (TRUE == WriteToAccum(7, CompilePC + 0xc))
|
||||
|
|
|
|||
Loading…
Reference in New Issue