diff --git a/Source/Glide64/Main.cpp b/Source/Glide64/Main.cpp index 3678a5b2f..89b8c36dd 100644 --- a/Source/Glide64/Main.cpp +++ b/Source/Glide64/Main.cpp @@ -47,6 +47,7 @@ #include #include #include +#include #include "Config.h" #include "Util.h" @@ -281,7 +282,7 @@ void ConfigWrapper() #else g_settings->wrpResolution, g_settings->wrpVRAM * 1024 * 1024, g_settings->wrpFBO, g_settings->wrpAnisotropic #endif - ); + ); } void UseUnregisteredSetting(int /*SettingID*/) @@ -1093,7 +1094,6 @@ void ReleaseGfx() rdp.window_changed = TRUE; } - #ifdef _WIN32 CriticalSection * g_ProcessDListCS = NULL; @@ -1417,7 +1417,7 @@ int CALL InitiateGFX(GFX_INFO Gfx_Info) #else g_settings->wrpResolution, g_settings->wrpVRAM * 1024 * 1024, g_settings->wrpFBO, g_settings->wrpAnisotropic #endif - ); + ); grGlideInit(); grSstSelect(0); @@ -2127,7 +2127,7 @@ void newSwapBuffers() info.size = sizeof(GrLfbInfo_t); if (grLfbLock(GR_LFB_READ_ONLY, GR_BUFFER_BACKBUFFER, GR_LFBWRITEMODE_565, GR_ORIGIN_UPPER_LEFT, FXFALSE, &info)) { - std::auto_ptr ssimg_buffer(new uint8_t[image_width * image_height * 3]); + AUTO_PTR ssimg_buffer(new uint8_t[image_width * image_height * 3]); uint8_t * ssimg = ssimg_buffer.get(); int sspos = 0; uint32_t offset_src = info.strideInBytes * offset_y; @@ -2442,4 +2442,4 @@ void Android_JNI_SwapWindow() { gfx.SwapBuffers(); } -#endif +#endif \ No newline at end of file diff --git a/Source/Project64-core/N64System/Mips/GBCart.cpp b/Source/Project64-core/N64System/Mips/GBCart.cpp index 4390001af..b73d955e2 100644 --- a/Source/Project64-core/N64System/Mips/GBCart.cpp +++ b/Source/Project64-core/N64System/Mips/GBCart.cpp @@ -11,6 +11,7 @@ * * ****************************************************************************/ #include "stdafx.h" +#include #include "GBCart.h" #include @@ -18,221 +19,220 @@ static void read_gb_cart_normal(struct gb_cart* gb_cart, uint16_t address, uint8_t* data) { - uint16_t offset; + uint16_t offset; - if ((address >= 0x0000) && (address <= 0x7FFF)) - { - //Read GB Cart - if (address >= gb_cart->rom_size) - { - //If address is larger then our rome size, bail out - return; - } - memcpy(data, &gb_cart->rom[address], 0x20); - } - else if ((address >= 0xA000) && (address <= 0xBFFF)) - { - //Read from RAM - if (gb_cart->ram == NULL) - { - //No RAM to write to - return; - } + if ((address >= 0x0000) && (address <= 0x7FFF)) + { + //Read GB Cart + if (address >= gb_cart->rom_size) + { + //If address is larger then our rome size, bail out + return; + } + memcpy(data, &gb_cart->rom[address], 0x20); + } + else if ((address >= 0xA000) && (address <= 0xBFFF)) + { + //Read from RAM + if (gb_cart->ram == NULL) + { + //No RAM to write to + return; + } - offset = address - 0xA000; - if (offset >= gb_cart->ram_size) - { - //Offset is larger then our ram size - return; - } + offset = address - 0xA000; + if (offset >= gb_cart->ram_size) + { + //Offset is larger then our ram size + return; + } - memcpy(&gb_cart->ram[offset], data, 0x20); - memcpy(data, &gb_cart->ram[offset], 0x20); - } + memcpy(&gb_cart->ram[offset], data, 0x20); + memcpy(data, &gb_cart->ram[offset], 0x20); + } } static void write_gb_cart_normal(struct gb_cart* gb_cart, uint16_t address, const uint8_t* data) { - uint16_t offset; - if ((address >= 0xA000) && (address <= 0xBFFF)) - { - //Write to RAM - if (gb_cart->ram == NULL) - { - //No RAM to write to - return; - } + uint16_t offset; + if ((address >= 0xA000) && (address <= 0xBFFF)) + { + //Write to RAM + if (gb_cart->ram == NULL) + { + //No RAM to write to + return; + } - offset = address - 0xa000; - if (offset >= gb_cart->ram_size) - { - //Offset is larger then our ram size - return; - } - - memcpy(&gb_cart->ram[offset], data, 0x20); - } + offset = address - 0xa000; + if (offset >= gb_cart->ram_size) + { + //Offset is larger then our ram size + return; + } + memcpy(&gb_cart->ram[offset], data, 0x20); + } } static void read_gb_cart_mbc1(struct gb_cart* gb_cart, uint16_t address, uint8_t* data) { - size_t offset; - - if ((address >= 0x0000) && (address <= 0x3FFF)) //No nbanked memory - { - memcpy(data, &gb_cart->rom[address], 0x20); - } - else if ((address >= 0x4000) && (address <= 0x7FFF)) //Read from ROM - { - offset = (address - 0x4000) + (gb_cart->rom_bank * 0x4000); - if (offset < gb_cart->rom_size) - { - memcpy(data, &gb_cart->rom[offset], 0x20); - } - } - else if ((address >= 0xA000) && (address <= 0xBFFF)) //Read from RAM - { - if (gb_cart->ram != NULL) - { - offset = (address - 0xA000) + (gb_cart->ram_bank * 0x2000); - if (offset < gb_cart->ram_size) - { - memcpy(data, &gb_cart->ram[offset], 0x20); - } - } - } + size_t offset; + + if ((address >= 0x0000) && (address <= 0x3FFF)) //No nbanked memory + { + memcpy(data, &gb_cart->rom[address], 0x20); + } + else if ((address >= 0x4000) && (address <= 0x7FFF)) //Read from ROM + { + offset = (address - 0x4000) + (gb_cart->rom_bank * 0x4000); + if (offset < gb_cart->rom_size) + { + memcpy(data, &gb_cart->rom[offset], 0x20); + } + } + else if ((address >= 0xA000) && (address <= 0xBFFF)) //Read from RAM + { + if (gb_cart->ram != NULL) + { + offset = (address - 0xA000) + (gb_cart->ram_bank * 0x2000); + if (offset < gb_cart->ram_size) + { + memcpy(data, &gb_cart->ram[offset], 0x20); + } + } + } } static void write_gb_cart_mbc1(struct gb_cart* gb_cart, uint16_t address, const uint8_t* data) { - size_t offset; + size_t offset; - if ((address >= 0x0000) && (address <= 0x1FFF)) // RAM enable - { - //Enable/disable RAM - gb_cart->ram_enabled = (data[0] & 0x0F) == 0x0A; - } - else if ((address >= 0x2000) && (address <= 0x3FFF)) // ROM bank select - { - gb_cart->rom_bank &= 0x60; // keep MSB - gb_cart->rom_bank |= data[0] & 0x1F; - - // emulate quirk: 0x00 -> 0x01, 0x20 -> 0x21, 0x40->0x41, 0x60 -> 0x61 - if ((gb_cart->rom_bank & 0x1F) == 0) - { - gb_cart->rom_bank |= 0x01; - } - } - else if ((address >= 0x4000) && (address <= 0x5FFF)) // RAM bank select - { - if (gb_cart->ram_bank_mode) - { - gb_cart->ram_bank = data[0] & 0x03; - } - else - { - gb_cart->rom_bank &= 0x1F; - gb_cart->rom_bank |= ((data[0] & 0x03) << 5); // set bits 5 and 6 of ROM bank - } - } - else if ((address >= 0x6000) && (address <= 0x7FFF)) // MBC1 mode select - { - // this is overly complicated, but it keeps us from having to do bitwise math later - // Basically we shuffle the 2 "magic bits" between rom_bank and ram_bank as necessary. - if (gb_cart->ram_bank_mode != (data[0] & 0x01)) - { - // we should only alter the ROM and RAM bank numbers if we have changed modes - gb_cart->ram_bank_mode = data[0] & 0x01; - if (gb_cart->ram_bank_mode) - { - gb_cart->ram_bank = gb_cart->rom_bank >> 5; // set the ram bank to the "magic bits" - gb_cart->rom_bank &= 0x1F; // zero out bits 5 and 6 to keep consistency - } - else - { - gb_cart->rom_bank &= 0x1F; - gb_cart->rom_bank |= (gb_cart->ram_bank << 5); - gb_cart->ram_bank = 0x00; // we can only reach RAM page 0 - } - } - } - else if ((address >= 0xA000) && (address <= 0xBFFF)) // Write to RAM - { - if (gb_cart->ram != NULL) - { - offset = (address - 0xA000) + (gb_cart->ram_bank * 0x2000); - if (offset < gb_cart->ram_size) - { - memcpy(&gb_cart->ram[offset], data, 0x20); - } - } - } + if ((address >= 0x0000) && (address <= 0x1FFF)) // RAM enable + { + //Enable/disable RAM + gb_cart->ram_enabled = (data[0] & 0x0F) == 0x0A; + } + else if ((address >= 0x2000) && (address <= 0x3FFF)) // ROM bank select + { + gb_cart->rom_bank &= 0x60; // keep MSB + gb_cart->rom_bank |= data[0] & 0x1F; + + // emulate quirk: 0x00 -> 0x01, 0x20 -> 0x21, 0x40->0x41, 0x60 -> 0x61 + if ((gb_cart->rom_bank & 0x1F) == 0) + { + gb_cart->rom_bank |= 0x01; + } + } + else if ((address >= 0x4000) && (address <= 0x5FFF)) // RAM bank select + { + if (gb_cart->ram_bank_mode) + { + gb_cart->ram_bank = data[0] & 0x03; + } + else + { + gb_cart->rom_bank &= 0x1F; + gb_cart->rom_bank |= ((data[0] & 0x03) << 5); // set bits 5 and 6 of ROM bank + } + } + else if ((address >= 0x6000) && (address <= 0x7FFF)) // MBC1 mode select + { + // this is overly complicated, but it keeps us from having to do bitwise math later + // Basically we shuffle the 2 "magic bits" between rom_bank and ram_bank as necessary. + if (gb_cart->ram_bank_mode != (data[0] & 0x01)) + { + // we should only alter the ROM and RAM bank numbers if we have changed modes + gb_cart->ram_bank_mode = data[0] & 0x01; + if (gb_cart->ram_bank_mode) + { + gb_cart->ram_bank = gb_cart->rom_bank >> 5; // set the ram bank to the "magic bits" + gb_cart->rom_bank &= 0x1F; // zero out bits 5 and 6 to keep consistency + } + else + { + gb_cart->rom_bank &= 0x1F; + gb_cart->rom_bank |= (gb_cart->ram_bank << 5); + gb_cart->ram_bank = 0x00; // we can only reach RAM page 0 + } + } + } + else if ((address >= 0xA000) && (address <= 0xBFFF)) // Write to RAM + { + if (gb_cart->ram != NULL) + { + offset = (address - 0xA000) + (gb_cart->ram_bank * 0x2000); + if (offset < gb_cart->ram_size) + { + memcpy(&gb_cart->ram[offset], data, 0x20); + } + } + } } static void read_gb_cart_mbc2(struct gb_cart* gb_cart, uint16_t address, uint8_t* data) { - size_t offset; + size_t offset; - if ((address < 0x4000)) //Rom Bank 0 - { - memcpy(data, &gb_cart->rom[address], 0x20); - } - else if ((address >= 0x4000) && (address < 0x8000)) //Switchable Rom Bank - { - offset = (address - 0x4000) + (gb_cart->rom_bank * 0x4000); - if (offset < gb_cart->rom_size) - { - memcpy(data, &gb_cart->rom[offset], 0x20); - } - } - else if ((address >= 0xA000) && (address <= 0xC000)) //Upper Bounds of memory map - { - if (gb_cart->ram != NULL) - { - offset = (address - 0xA000) + (gb_cart->ram_bank * 0x2000); - if (offset < gb_cart->ram_size) - { - memcpy(data, &gb_cart->ram[offset], 0x20); - } - } - } + if ((address < 0x4000)) //Rom Bank 0 + { + memcpy(data, &gb_cart->rom[address], 0x20); + } + else if ((address >= 0x4000) && (address < 0x8000)) //Switchable Rom Bank + { + offset = (address - 0x4000) + (gb_cart->rom_bank * 0x4000); + if (offset < gb_cart->rom_size) + { + memcpy(data, &gb_cart->rom[offset], 0x20); + } + } + else if ((address >= 0xA000) && (address <= 0xC000)) //Upper Bounds of memory map + { + if (gb_cart->ram != NULL) + { + offset = (address - 0xA000) + (gb_cart->ram_bank * 0x2000); + if (offset < gb_cart->ram_size) + { + memcpy(data, &gb_cart->ram[offset], 0x20); + } + } + } } static void write_gb_cart_mbc2(struct gb_cart* gb_cart, uint16_t address, const uint8_t* data) { - size_t offset; + size_t offset; - if ((address >= 0x0000) && (address <= 0x1FFF)) // We shouldn't be able to read/write to RAM unless this is toggled on - { - gb_cart->ram_enabled = (data[0] & 0x0F) == 0x0A; - } - else if ((address >= 0x2000) && (address <= 0x3FFF)) // ROM bank select - { - gb_cart->rom_bank = data[0] & 0x0F; - if (gb_cart->rom_bank == 0) - { - gb_cart->rom_bank = 1; - } - } - else if ((address >= 0x4000) && (address <= 0x5FFF)) // RAM bank select - { - if (gb_cart->ram != NULL) - { - gb_cart->ram_bank = data[0] & 0x07; - } - } - else if ((address >= 0xA000) && (address <= 0xBFFF)) // Write to RAM - { - if (gb_cart->ram != NULL) - { - offset = (address - 0xA000) + (gb_cart->ram_bank * 0x2000); - if (offset < gb_cart->ram_size) - { - memcpy(&gb_cart->ram[offset], data, 0x20); - } - } - } + if ((address >= 0x0000) && (address <= 0x1FFF)) // We shouldn't be able to read/write to RAM unless this is toggled on + { + gb_cart->ram_enabled = (data[0] & 0x0F) == 0x0A; + } + else if ((address >= 0x2000) && (address <= 0x3FFF)) // ROM bank select + { + gb_cart->rom_bank = data[0] & 0x0F; + if (gb_cart->rom_bank == 0) + { + gb_cart->rom_bank = 1; + } + } + else if ((address >= 0x4000) && (address <= 0x5FFF)) // RAM bank select + { + if (gb_cart->ram != NULL) + { + gb_cart->ram_bank = data[0] & 0x07; + } + } + else if ((address >= 0xA000) && (address <= 0xBFFF)) // Write to RAM + { + if (gb_cart->ram != NULL) + { + offset = (address - 0xA000) + (gb_cart->ram_bank * 0x2000); + if (offset < gb_cart->ram_size) + { + memcpy(&gb_cart->ram[offset], data, 0x20); + } + } + } } void memoryUpdateMBC3Clock(struct gb_cart* gb_cart) @@ -261,7 +261,6 @@ void memoryUpdateMBC3Clock(struct gb_cart* gb_cart) gb_cart->rtc_data[3]++; } diff /= 24; - gb_cart->rtc_data[3] += (int)(diff & 0xFFFFFFFF); if (gb_cart->rtc_data[3] > 255) { @@ -269,7 +268,7 @@ void memoryUpdateMBC3Clock(struct gb_cart* gb_cart) gb_cart->rtc_data[3] %= 512; gb_cart->rtc_data[3] |= 0x80; } - gb_cart->rtc_data[4] = (gb_cart->rtc_data[4] & 0xFE) | (gb_cart->rtc_data[3]>255 ? 1 : 0); + gb_cart->rtc_data[4] = (gb_cart->rtc_data[4] & 0xFE) | (gb_cart->rtc_data[3] > 255 ? 1 : 0); } } gb_cart->rtc_last_time = now; @@ -277,34 +276,34 @@ void memoryUpdateMBC3Clock(struct gb_cart* gb_cart) static void read_gb_cart_mbc3(struct gb_cart* gb_cart, uint16_t address, uint8_t* data) { - size_t offset; + size_t offset; - if ((address < 0x4000)) //Rom Bank 0 - { - memcpy(data, &gb_cart->rom[address], 0x20); - } - else if ((address >= 0x4000) && (address < 0x8000)) //Switchable Rom Bank - { - offset = (address - 0x4000) + (gb_cart->rom_bank * 0x4000); - if (offset < gb_cart->rom_size) - { - memcpy(data, &gb_cart->rom[offset], 0x20); - } - } - else if ((address >= 0xA000) && (address <= 0xC000)) //Upper Bounds of memory map - { - if (gb_cart->ram != NULL) - { - if (gb_cart->ram_bank >= 0x00 && gb_cart->ram_bank <= 0x03) - { + if ((address < 0x4000)) //Rom Bank 0 + { + memcpy(data, &gb_cart->rom[address], 0x20); + } + else if ((address >= 0x4000) && (address < 0x8000)) //Switchable Rom Bank + { + offset = (address - 0x4000) + (gb_cart->rom_bank * 0x4000); + if (offset < gb_cart->rom_size) + { + memcpy(data, &gb_cart->rom[offset], 0x20); + } + } + else if ((address >= 0xA000) && (address <= 0xC000)) //Upper Bounds of memory map + { + if (gb_cart->ram != NULL) + { + if (gb_cart->ram_bank >= 0x00 && gb_cart->ram_bank <= 0x03) + { offset = (address - 0xA000) + (gb_cart->ram_bank * 0x2000); if (offset < gb_cart->ram_size) { memcpy(data, &gb_cart->ram[offset], 0x20); } - } - else if (gb_cart->has_rtc) - { + } + else if (gb_cart->has_rtc) + { if (gb_cart->rtc_latch) { for (int i = 0; i < 32; i++) @@ -320,28 +319,28 @@ static void read_gb_cart_mbc3(struct gb_cart* gb_cart, uint16_t address, uint8_t data[i] = gb_cart->rtc_data[gb_cart->ram_bank - 0x08]; } } - } - } - } + } + } + } } static void write_gb_cart_mbc3(struct gb_cart* gb_cart, uint16_t address, const uint8_t* data) { - uint8_t bank; - size_t offset; + uint8_t bank; + size_t offset; - if ((address >= 0x0000) && (address <= 0x1FFF)) // We shouldn't be able to read/write to RAM unless this is toggled on - { - //Enable / Disable RAM -- NOT WORKING -- FIXME - gb_cart->ram_enabled = (data[0] & 0x0F) == 0x0A; - } - else if ((address >= 0x2000) && (address <= 0x3FFF)) // ROM bank select - { + if ((address >= 0x0000) && (address <= 0x1FFF)) // We shouldn't be able to read/write to RAM unless this is toggled on + { + //Enable / Disable RAM -- NOT WORKING -- FIXME + gb_cart->ram_enabled = (data[0] & 0x0F) == 0x0A; + } + else if ((address >= 0x2000) && (address <= 0x3FFF)) // ROM bank select + { bank = data[0] & 0x7F; - gb_cart->rom_bank = (bank == 0) ? 1 : bank; - } - else if ((address >= 0x4000) && (address <= 0x5FFF)) // RAM/Clock bank select - { + gb_cart->rom_bank = (bank == 0) ? 1 : bank; + } + else if ((address >= 0x4000) && (address <= 0x5FFF)) // RAM/Clock bank select + { if (gb_cart->ram != NULL) { bank = data[0]; @@ -355,10 +354,10 @@ static void write_gb_cart_mbc3(struct gb_cart* gb_cart, uint16_t address, const gb_cart->ram_bank = bank & 0x03; } } - } - else if ((address >= 0x6000) && (address <= 0x7FFF)) // Latch timer data - { - //Implement RTC timer / latch + } + else if ((address >= 0x6000) && (address <= 0x7FFF)) // Latch timer data + { + //Implement RTC timer / latch if (gb_cart->rtc_latch == 0 && data[0] == 1) { //Update time @@ -369,9 +368,9 @@ static void write_gb_cart_mbc3(struct gb_cart* gb_cart, uint16_t address, const } } gb_cart->rtc_latch = data[0]; - } - else if ((address >= 0xA000) && (address <= 0xBFFF)) // Write to RAM - { + } + else if ((address >= 0xA000) && (address <= 0xBFFF)) // Write to RAM + { if (gb_cart->ram != NULL) { if (gb_cart->ram_bank >= 0x00 && gb_cart->ram_bank <= 0x03) @@ -388,7 +387,7 @@ static void write_gb_cart_mbc3(struct gb_cart* gb_cart, uint16_t address, const gb_cart->rtc_data[gb_cart->ram_bank - 0x08] = data[0]; } } - } + } } static void read_gb_cart_mbc4(struct gb_cart* gb_cart, uint16_t address, uint8_t* data) @@ -405,100 +404,99 @@ static void read_gb_cart_mbc5(struct gb_cart* gb_cart, uint16_t address, uint8_t { size_t offset; - if ((address < 0x4000)) //Rom Bank 0 - { - memcpy(data, &gb_cart->rom[address], 0x20); - } - else if ((address >= 0x4000) && (address < 0x8000)) //Switchable ROM BANK - { - offset = (address - 0x4000) + (gb_cart->rom_bank * 0x4000); - if (offset < gb_cart->rom_size) - { - memcpy(data, &gb_cart->rom[offset], 0x20); - } - } - else if ((address >= 0xA000) && (address <= 0xC000)) //Upper bounds of memory map - { - if (gb_cart->ram != NULL) - { - offset = (address - 0xA000) + (gb_cart->ram_bank * 0x2000); - if (offset < gb_cart->ram_size) - { - memcpy(data, &gb_cart->ram[offset], 0x20); - } - } - } + if ((address < 0x4000)) //Rom Bank 0 + { + memcpy(data, &gb_cart->rom[address], 0x20); + } + else if ((address >= 0x4000) && (address < 0x8000)) //Switchable ROM BANK + { + offset = (address - 0x4000) + (gb_cart->rom_bank * 0x4000); + if (offset < gb_cart->rom_size) + { + memcpy(data, &gb_cart->rom[offset], 0x20); + } + } + else if ((address >= 0xA000) && (address <= 0xC000)) //Upper bounds of memory map + { + if (gb_cart->ram != NULL) + { + offset = (address - 0xA000) + (gb_cart->ram_bank * 0x2000); + if (offset < gb_cart->ram_size) + { + memcpy(data, &gb_cart->ram[offset], 0x20); + } + } + } } static void write_gb_cart_mbc5(struct gb_cart* gb_cart, uint16_t address, const uint8_t* data) { - size_t offset; - - if ((address >= 0x0000) && (address <= 0x1FFF)) // We shouldn't be able to read/write to RAM unless this is toggled on - { - //Enable / Disable RAM -- NOT WORKING -- CHECK ME - gb_cart->ram_enabled = (data[0] & 0x0F) == 0x0A; - } - else if ((address >= 0x2000) && (address <= 0x2FFF)) // ROM bank select, low bits - { - gb_cart->rom_bank &= 0xff00; - gb_cart->rom_bank |= data[0]; - } - else if ((address >= 0x3000) && (address <= 0x3FFF)) // ROM bank select, high bit - { - gb_cart->rom_bank &= 0x00ff; - gb_cart->rom_bank |= (data[0] & 0x01) << 8; - } - else if ((address >= 0x4000) && (address <= 0x5FFF)) // RAM bank select - { - if (gb_cart->ram != NULL) - { - gb_cart->ram_bank = data[0] & 0x0f; - } - } - else if ((address >= 0xA000) && (address <= 0xBFFF)) // Write to RAM - { - if (gb_cart->ram != NULL) - { - offset = (address - 0xA000) + (gb_cart->ram_bank * 0x2000); - if (offset < gb_cart->ram_size) - { - memcpy(&gb_cart->ram[offset], data, 0x20); - } - } - } + size_t offset; + if ((address >= 0x0000) && (address <= 0x1FFF)) // We shouldn't be able to read/write to RAM unless this is toggled on + { + //Enable / Disable RAM -- NOT WORKING -- CHECK ME + gb_cart->ram_enabled = (data[0] & 0x0F) == 0x0A; + } + else if ((address >= 0x2000) && (address <= 0x2FFF)) // ROM bank select, low bits + { + gb_cart->rom_bank &= 0xff00; + gb_cart->rom_bank |= data[0]; + } + else if ((address >= 0x3000) && (address <= 0x3FFF)) // ROM bank select, high bit + { + gb_cart->rom_bank &= 0x00ff; + gb_cart->rom_bank |= (data[0] & 0x01) << 8; + } + else if ((address >= 0x4000) && (address <= 0x5FFF)) // RAM bank select + { + if (gb_cart->ram != NULL) + { + gb_cart->ram_bank = data[0] & 0x0f; + } + } + else if ((address >= 0xA000) && (address <= 0xBFFF)) // Write to RAM + { + if (gb_cart->ram != NULL) + { + offset = (address - 0xA000) + (gb_cart->ram_bank * 0x2000); + if (offset < gb_cart->ram_size) + { + memcpy(&gb_cart->ram[offset], data, 0x20); + } + } + } } static void read_gb_cart_mmm01(struct gb_cart* gb_cart, uint16_t address, uint8_t* data) { - g_Notify->BreakPoint(__FILE__, __LINE__); + g_Notify->BreakPoint(__FILE__, __LINE__); } static void write_gb_cart_mmm01(struct gb_cart* gb_cart, uint16_t address, const uint8_t* data) { - g_Notify->BreakPoint(__FILE__, __LINE__); + g_Notify->BreakPoint(__FILE__, __LINE__); } static void read_gb_cart_pocket_cam(struct gb_cart* gb_cart, uint16_t address, uint8_t* data) { - size_t offset; + size_t offset; - if ((address < 0x4000)) //Rom Bank 0 - { - memcpy(data, &gb_cart->rom[address], 0x20); - } - else if ((address >= 0x4000) && (address < 0x8000)) //Switchable ROM BANK - { - offset = (address - 0x4000) + (gb_cart->rom_bank * 0x4000); - if (offset < gb_cart->rom_size) - { - memcpy(data, &gb_cart->rom[offset], 0x20); - } - } - else if ((address >= 0xA000) && (address <= 0xC000)) //Upper bounds of memory map - { - //Check to see if where currently in register mode + if ((address < 0x4000)) //Rom Bank 0 + { + memcpy(data, &gb_cart->rom[address], 0x20); + } + else if ((address >= 0x4000) && (address < 0x8000)) //Switchable ROM BANK + { + offset = (address - 0x4000) + (gb_cart->rom_bank * 0x4000); + if (offset < gb_cart->rom_size) + { + memcpy(data, &gb_cart->rom[offset], 0x20); + } + } + else if ((address >= 0xA000) && (address <= 0xC000)) //Upper bounds of memory map + { + //Check to see if where currently in register mode if (gb_cart->ram != NULL) { if (gb_cart->ram_bank & 0x10) @@ -517,25 +515,25 @@ static void read_gb_cart_pocket_cam(struct gb_cart* gb_cart, uint16_t address, u } } } - } + } } static void write_gb_cart_pocket_cam(struct gb_cart* gb_cart, uint16_t address, const uint8_t* data) { - size_t offset; + size_t offset; - if ((address >= 0x0000) && (address <= 0x1FFF)) // We shouldn't be able to read/write to RAM unless this is toggled on - { - //Enable / Disable RAM - gb_cart->ram_enabled = (data[0] & 0x0F) == 0x0A; - } - else if ((address >= 0x2000) && (address <= 0x2FFF)) // ROM bank select, low bits - { - gb_cart->rom_bank &= 0xFF00; - gb_cart->rom_bank |= data[0]; - } - else if ((address >= 0x4000) && (address <= 0x4FFF)) // Camera Register & RAM bank select - { + if ((address >= 0x0000) && (address <= 0x1FFF)) // We shouldn't be able to read/write to RAM unless this is toggled on + { + //Enable / Disable RAM + gb_cart->ram_enabled = (data[0] & 0x0F) == 0x0A; + } + else if ((address >= 0x2000) && (address <= 0x2FFF)) // ROM bank select, low bits + { + gb_cart->rom_bank &= 0xFF00; + gb_cart->rom_bank |= data[0]; + } + else if ((address >= 0x4000) && (address <= 0x4FFF)) // Camera Register & RAM bank select + { if (gb_cart->ram != NULL) { if (data[0] & 0x10) @@ -549,9 +547,9 @@ static void write_gb_cart_pocket_cam(struct gb_cart* gb_cart, uint16_t address, gb_cart->ram_bank = data[0] & 0x0F; } } - } - else if ((address >= 0xA000) && (address <= 0xBFFF)) // Write to RAM - { + } + else if ((address >= 0xA000) && (address <= 0xBFFF)) // Write to RAM + { if (gb_cart->ram != NULL) { if (gb_cart->ram_bank & 0x10) @@ -568,134 +566,133 @@ static void write_gb_cart_pocket_cam(struct gb_cart* gb_cart, uint16_t address, } } } - } + } } static void read_gb_cart_bandai_tama5(struct gb_cart* gb_cart, uint16_t address, uint8_t* data) { - g_Notify->BreakPoint(__FILE__, __LINE__); + g_Notify->BreakPoint(__FILE__, __LINE__); } static void write_gb_cart_bandai_tama5(struct gb_cart* gb_cart, uint16_t address, const uint8_t* data) { - g_Notify->BreakPoint(__FILE__, __LINE__); + g_Notify->BreakPoint(__FILE__, __LINE__); } static void read_gb_cart_huc1(struct gb_cart* gb_cart, uint16_t address, uint8_t* data) { - g_Notify->BreakPoint(__FILE__, __LINE__); + g_Notify->BreakPoint(__FILE__, __LINE__); } static void write_gb_cart_huc1(struct gb_cart* gb_cart, uint16_t address, const uint8_t* data) { - g_Notify->BreakPoint(__FILE__, __LINE__); + g_Notify->BreakPoint(__FILE__, __LINE__); } static void read_gb_cart_huc3(struct gb_cart* gb_cart, uint16_t address, uint8_t* data) { - g_Notify->BreakPoint(__FILE__, __LINE__); + g_Notify->BreakPoint(__FILE__, __LINE__); } static void write_gb_cart_huc3(struct gb_cart* gb_cart, uint16_t address, const uint8_t* data) { - g_Notify->BreakPoint(__FILE__, __LINE__); + g_Notify->BreakPoint(__FILE__, __LINE__); } enum gbcart_extra_devices { - GED_NONE = 0x00, - GED_RAM = 0x01, - GED_BATTERY = 0x02, - GED_RTC = 0x04, - GED_RUMBLE = 0x08 + GED_NONE = 0x00, + GED_RAM = 0x01, + GED_BATTERY = 0x02, + GED_RTC = 0x04, + GED_RUMBLE = 0x08 }; struct parsed_cart_type { - void(*read_gb_cart)(struct gb_cart*, uint16_t, uint8_t*); - void(*write_gb_cart)(struct gb_cart*, uint16_t, const uint8_t*); - unsigned int extra_devices; + void(*read_gb_cart)(struct gb_cart*, uint16_t, uint8_t*); + void(*write_gb_cart)(struct gb_cart*, uint16_t, const uint8_t*); + unsigned int extra_devices; }; static const struct parsed_cart_type* parse_cart_type(uint8_t cart_type) { #define MBC(x) read_gb_cart_ ## x, write_gb_cart_ ## x - static const struct parsed_cart_type GB_CART_TYPES[] = - { - { MBC(normal), GED_NONE }, - { MBC(mbc1), GED_NONE }, - { MBC(mbc1), GED_RAM }, - { MBC(mbc1), GED_RAM | GED_BATTERY }, - { MBC(mbc2), GED_NONE }, - { MBC(mbc2), GED_BATTERY }, - { MBC(normal), GED_RAM }, - { MBC(normal), GED_RAM | GED_BATTERY }, - { MBC(mmm01), GED_NONE }, - { MBC(mmm01), GED_RAM }, - { MBC(mmm01), GED_RAM | GED_BATTERY }, - { MBC(mbc3), GED_BATTERY | GED_RTC }, - { MBC(mbc3), GED_RAM | GED_BATTERY | GED_RTC }, - { MBC(mbc3), GED_NONE }, - { MBC(mbc3), GED_RAM }, - { MBC(mbc3), GED_RAM | GED_BATTERY }, - { MBC(mbc4), GED_NONE }, - { MBC(mbc4), GED_RAM }, - { MBC(mbc4), GED_RAM | GED_BATTERY }, - { MBC(mbc5), GED_NONE }, - { MBC(mbc5), GED_RAM }, - { MBC(mbc5), GED_RAM | GED_BATTERY }, - { MBC(mbc5), GED_RUMBLE }, - { MBC(mbc5), GED_RAM | GED_RUMBLE }, - { MBC(mbc5), GED_RAM | GED_BATTERY | GED_RUMBLE }, - { MBC(pocket_cam), GED_NONE }, - { MBC(bandai_tama5), GED_NONE }, - { MBC(huc3), GED_NONE }, - { MBC(huc1), GED_RAM | GED_BATTERY } - }; + static const struct parsed_cart_type GB_CART_TYPES[] = + { + { MBC(normal), GED_NONE }, + { MBC(mbc1), GED_NONE }, + { MBC(mbc1), GED_RAM }, + { MBC(mbc1), GED_RAM | GED_BATTERY }, + { MBC(mbc2), GED_NONE }, + { MBC(mbc2), GED_BATTERY }, + { MBC(normal), GED_RAM }, + { MBC(normal), GED_RAM | GED_BATTERY }, + { MBC(mmm01), GED_NONE }, + { MBC(mmm01), GED_RAM }, + { MBC(mmm01), GED_RAM | GED_BATTERY }, + { MBC(mbc3), GED_BATTERY | GED_RTC }, + { MBC(mbc3), GED_RAM | GED_BATTERY | GED_RTC }, + { MBC(mbc3), GED_NONE }, + { MBC(mbc3), GED_RAM }, + { MBC(mbc3), GED_RAM | GED_BATTERY }, + { MBC(mbc4), GED_NONE }, + { MBC(mbc4), GED_RAM }, + { MBC(mbc4), GED_RAM | GED_BATTERY }, + { MBC(mbc5), GED_NONE }, + { MBC(mbc5), GED_RAM }, + { MBC(mbc5), GED_RAM | GED_BATTERY }, + { MBC(mbc5), GED_RUMBLE }, + { MBC(mbc5), GED_RAM | GED_RUMBLE }, + { MBC(mbc5), GED_RAM | GED_BATTERY | GED_RUMBLE }, + { MBC(pocket_cam), GED_NONE }, + { MBC(bandai_tama5), GED_NONE }, + { MBC(huc3), GED_NONE }, + { MBC(huc1), GED_RAM | GED_BATTERY } + }; #undef MBC - - switch (cart_type) - { - case 0x00: return &GB_CART_TYPES[0]; - case 0x01: return &GB_CART_TYPES[1]; - case 0x02: return &GB_CART_TYPES[2]; - case 0x03: return &GB_CART_TYPES[3]; - case 0x05: return &GB_CART_TYPES[4]; - case 0x06: return &GB_CART_TYPES[5]; - case 0x08: return &GB_CART_TYPES[6]; - case 0x09: return &GB_CART_TYPES[7]; - case 0x0B: return &GB_CART_TYPES[8]; - case 0x0C: return &GB_CART_TYPES[9]; - case 0x0D: return &GB_CART_TYPES[10]; - case 0x0F: return &GB_CART_TYPES[11]; - case 0x10: return &GB_CART_TYPES[12]; - case 0x11: return &GB_CART_TYPES[13]; - case 0x12: return &GB_CART_TYPES[14]; - case 0x13: return &GB_CART_TYPES[15]; - case 0x15: return &GB_CART_TYPES[16]; - case 0x16: return &GB_CART_TYPES[17]; - case 0x17: return &GB_CART_TYPES[18]; - case 0x19: return &GB_CART_TYPES[19]; - case 0x1A: return &GB_CART_TYPES[20]; - case 0x1B: return &GB_CART_TYPES[21]; - case 0x1C: return &GB_CART_TYPES[22]; - case 0x1D: return &GB_CART_TYPES[23]; - case 0x1E: return &GB_CART_TYPES[24]; - case 0xFC: return &GB_CART_TYPES[25]; - case 0xFD: return &GB_CART_TYPES[26]; - case 0xFE: return &GB_CART_TYPES[27]; - case 0xFF: return &GB_CART_TYPES[28]; - default: return NULL; - } + switch (cart_type) + { + case 0x00: return &GB_CART_TYPES[0]; + case 0x01: return &GB_CART_TYPES[1]; + case 0x02: return &GB_CART_TYPES[2]; + case 0x03: return &GB_CART_TYPES[3]; + case 0x05: return &GB_CART_TYPES[4]; + case 0x06: return &GB_CART_TYPES[5]; + case 0x08: return &GB_CART_TYPES[6]; + case 0x09: return &GB_CART_TYPES[7]; + case 0x0B: return &GB_CART_TYPES[8]; + case 0x0C: return &GB_CART_TYPES[9]; + case 0x0D: return &GB_CART_TYPES[10]; + case 0x0F: return &GB_CART_TYPES[11]; + case 0x10: return &GB_CART_TYPES[12]; + case 0x11: return &GB_CART_TYPES[13]; + case 0x12: return &GB_CART_TYPES[14]; + case 0x13: return &GB_CART_TYPES[15]; + case 0x15: return &GB_CART_TYPES[16]; + case 0x16: return &GB_CART_TYPES[17]; + case 0x17: return &GB_CART_TYPES[18]; + case 0x19: return &GB_CART_TYPES[19]; + case 0x1A: return &GB_CART_TYPES[20]; + case 0x1B: return &GB_CART_TYPES[21]; + case 0x1C: return &GB_CART_TYPES[22]; + case 0x1D: return &GB_CART_TYPES[23]; + case 0x1E: return &GB_CART_TYPES[24]; + case 0xFC: return &GB_CART_TYPES[25]; + case 0xFD: return &GB_CART_TYPES[26]; + case 0xFE: return &GB_CART_TYPES[27]; + case 0xFF: return &GB_CART_TYPES[28]; + default: return NULL; + } } bool GBCart::init_gb_cart(struct gb_cart* gb_cart, const char* gb_file) { - const struct parsed_cart_type* type; - std::auto_ptr rom; + const struct parsed_cart_type* type; + AUTO_PTR rom; size_t rom_size = 0; - std::auto_ptr ram; + AUTO_PTR ram; size_t ram_size = 0; CFile tempFile; @@ -712,39 +709,39 @@ bool GBCart::init_gb_cart(struct gb_cart* gb_cart, const char* gb_file) tempFile.Read(rom.get(), rom_size); tempFile.Close(); - if (rom_size < 0x8000) - { + if (rom_size < 0x8000) + { return false; - } + } - /* get and parse cart type */ - uint8_t cart_type = rom.get()[0x147]; - type = parse_cart_type(cart_type); - if (type == NULL) - { + /* get and parse cart type */ + uint8_t cart_type = rom.get()[0x147]; + type = parse_cart_type(cart_type); + if (type == NULL) + { return false; - } + } - /* load ram (if present) */ - if (type->extra_devices & GED_RAM) - { - ram_size = 0; - switch (rom.get()[0x149]) - { - case 0x01: ram_size = 1 * 0x800; break; - case 0x02: ram_size = 4 * 0x800; break; - case 0x03: ram_size = 16 * 0x800; break; - case 0x04: ram_size = 64 * 0x800; break; - case 0x05: ram_size = 32 * 0x800; break; - } + /* load ram (if present) */ + if (type->extra_devices & GED_RAM) + { + ram_size = 0; + switch (rom.get()[0x149]) + { + case 0x01: ram_size = 1 * 0x800; break; + case 0x02: ram_size = 4 * 0x800; break; + case 0x03: ram_size = 16 * 0x800; break; + case 0x04: ram_size = 64 * 0x800; break; + case 0x05: ram_size = 32 * 0x800; break; + } - if (ram_size != 0) - { + if (ram_size != 0) + { ram.reset(new uint8_t[ram_size]); - if (ram.get() == NULL) - { + if (ram.get() == NULL) + { return false; - } + } if (!tempFile.Open(g_Settings->LoadStringVal(Game_Transferpak_Sav).c_str(), CFileBase::modeRead)) { @@ -753,38 +750,38 @@ bool GBCart::init_gb_cart(struct gb_cart* gb_cart, const char* gb_file) } tempFile.Read(ram.get(), ram_size); - } - + } + //If we have RTC we need to load in the data, we assume the save will use the VBA-M format if (type->extra_devices & GED_RTC) { - tempFile.Read(&gb_cart->rtc_data[0], 4); - tempFile.Read(&gb_cart->rtc_data[1], 4); - tempFile.Read(&gb_cart->rtc_data[2], 4); - tempFile.Read(&gb_cart->rtc_data[3], 4); - tempFile.Read(&gb_cart->rtc_data[4], 4); + tempFile.Read(&gb_cart->rtc_data[0], 4); + tempFile.Read(&gb_cart->rtc_data[1], 4); + tempFile.Read(&gb_cart->rtc_data[2], 4); + tempFile.Read(&gb_cart->rtc_data[3], 4); + tempFile.Read(&gb_cart->rtc_data[4], 4); tempFile.Read(&gb_cart->rtc_latch_data[0], 4); tempFile.Read(&gb_cart->rtc_latch_data[1], 4); tempFile.Read(&gb_cart->rtc_latch_data[2], 4); tempFile.Read(&gb_cart->rtc_latch_data[3], 4); tempFile.Read(&gb_cart->rtc_latch_data[4], 4); - tempFile.Read(&gb_cart->rtc_last_time, 8); + tempFile.Read(&gb_cart->rtc_last_time, 8); memoryUpdateMBC3Clock(gb_cart); } tempFile.Close(); - } + } - /* update gb_cart */ + /* update gb_cart */ gb_cart->rom = rom.release(); gb_cart->ram = ram.release(); - gb_cart->rom_size = rom_size; - gb_cart->ram_size = ram_size; - gb_cart->rom_bank = 1; - gb_cart->ram_bank = 0; - gb_cart->has_rtc = (type->extra_devices & GED_RTC) ? 1 : 0; - gb_cart->read_gb_cart = type->read_gb_cart; - gb_cart->write_gb_cart = type->write_gb_cart; - return true; + gb_cart->rom_size = rom_size; + gb_cart->ram_size = ram_size; + gb_cart->rom_bank = 1; + gb_cart->ram_bank = 0; + gb_cart->has_rtc = (type->extra_devices & GED_RTC) ? 1 : 0; + gb_cart->read_gb_cart = type->read_gb_cart; + gb_cart->write_gb_cart = type->write_gb_cart; + return true; } void GBCart::save_gb_cart(struct gb_cart* gb_cart) @@ -795,17 +792,17 @@ void GBCart::save_gb_cart(struct gb_cart* gb_cart) if (gb_cart->has_rtc) { - ramFile.Write(&gb_cart->rtc_data[0], 4); - ramFile.Write(&gb_cart->rtc_data[1], 4); - ramFile.Write(&gb_cart->rtc_data[2], 4); - ramFile.Write(&gb_cart->rtc_data[3], 4); - ramFile.Write(&gb_cart->rtc_data[4], 4); + ramFile.Write(&gb_cart->rtc_data[0], 4); + ramFile.Write(&gb_cart->rtc_data[1], 4); + ramFile.Write(&gb_cart->rtc_data[2], 4); + ramFile.Write(&gb_cart->rtc_data[3], 4); + ramFile.Write(&gb_cart->rtc_data[4], 4); ramFile.Write(&gb_cart->rtc_latch_data[0], 4); ramFile.Write(&gb_cart->rtc_latch_data[1], 4); ramFile.Write(&gb_cart->rtc_latch_data[2], 4); ramFile.Write(&gb_cart->rtc_latch_data[3], 4); ramFile.Write(&gb_cart->rtc_latch_data[4], 4); - ramFile.Write(&gb_cart->rtc_last_time, 8); + ramFile.Write(&gb_cart->rtc_last_time, 8); } ramFile.Close(); @@ -813,22 +810,21 @@ void GBCart::save_gb_cart(struct gb_cart* gb_cart) void GBCart::release_gb_cart(struct gb_cart* gb_cart) { - if (gb_cart->rom != NULL) - delete gb_cart->rom; + if (gb_cart->rom != NULL) + delete gb_cart->rom; if (gb_cart->ram != NULL) delete gb_cart->ram; - memset(gb_cart, 0, sizeof(*gb_cart)); + memset(gb_cart, 0, sizeof(*gb_cart)); } - void GBCart::read_gb_cart(struct gb_cart* gb_cart, uint16_t address, uint8_t* data) { - gb_cart->read_gb_cart(gb_cart, address, data); + gb_cart->read_gb_cart(gb_cart, address, data); } void GBCart::write_gb_cart(struct gb_cart* gb_cart, uint16_t address, const uint8_t* data) { - gb_cart->write_gb_cart(gb_cart, address, data); -} + gb_cart->write_gb_cart(gb_cart, address, data); +} \ No newline at end of file diff --git a/Source/Project64-core/N64System/N64DiskClass.cpp b/Source/Project64-core/N64System/N64DiskClass.cpp index ef5b4869e..28cf5e1e4 100644 --- a/Source/Project64-core/N64System/N64DiskClass.cpp +++ b/Source/Project64-core/N64System/N64DiskClass.cpp @@ -12,6 +12,7 @@ #include "N64DiskClass.h" #include "SystemGlobals.h" #include +#include #include #include #include @@ -122,7 +123,7 @@ bool CN64Disk::IsValidDiskImage(uint8_t Test[4]) bool CN64Disk::AllocateDiskImage(uint32_t DiskFileSize) { WriteTrace(TraceN64System, TraceDebug, "Allocating memory for disk"); - std::auto_ptr ImageBase(new uint8_t[DiskFileSize + 0x1000]); + AUTO_PTR ImageBase(new uint8_t[DiskFileSize + 0x1000]); if (ImageBase.get() == NULL) { SetError(MSG_MEM_ALLOC_ERROR); @@ -493,7 +494,7 @@ void CN64Disk::ConvertDiskFormatBack() //SDK DISK RAM WriteTrace(TraceN64System, TraceDebug, "Allocating memory for disk SDK format"); - std::auto_ptr ImageBase(new uint8_t[SDKFormatSize + 0x1000]); + AUTO_PTR ImageBase(new uint8_t[SDKFormatSize + 0x1000]); if (ImageBase.get() == NULL) { SetError(MSG_MEM_ALLOC_ERROR); @@ -515,7 +516,7 @@ void CN64Disk::ConvertDiskFormatBack() memcpy(&SystemData, m_DiskImage, 0xE8); disktype = SystemData[5] & 0xF; - + //Prepare Input Offsets for (zone = 1; zone < 16; zone++) { @@ -528,7 +529,7 @@ void CN64Disk::ConvertDiskFormatBack() { OutStart[zone] = OutStart[zone - 1] + ZONESIZE(zone - 1); } - + //Copy Head 0 for (zone = 0; zone < 8; zone++) { @@ -567,7 +568,7 @@ void CN64Disk::ConvertDiskFormatBack() } } } - + //Copy Head 1 for (zone = 8; zone < 16; zone++) { @@ -606,13 +607,13 @@ void CN64Disk::ConvertDiskFormatBack() } } } - + if (!m_DiskFile.Write(s_DiskImage, SDKFormatSize)) { m_DiskFile.Close(); WriteTrace(TraceN64System, TraceError, "Failed to write file"); } - + WriteTrace(TraceN64System, TraceDebug, "Unallocating disk SDK format memory"); delete[] s_DiskImageBase; s_DiskImageBase = NULL; diff --git a/Source/Project64-core/N64System/N64RomClass.cpp b/Source/Project64-core/N64System/N64RomClass.cpp index 15fd5b9ee..859c36166 100644 --- a/Source/Project64-core/N64System/N64RomClass.cpp +++ b/Source/Project64-core/N64System/N64RomClass.cpp @@ -15,6 +15,7 @@ #include #include #include +#include #include #ifdef _WIN32 @@ -38,7 +39,7 @@ CN64Rom::~CN64Rom() bool CN64Rom::AllocateRomImage(uint32_t RomFileSize) { WriteTrace(TraceN64System, TraceDebug, "Allocating memory for rom"); - std::auto_ptr ImageBase(new uint8_t[RomFileSize + 0x1000]); + AUTO_PTR ImageBase(new uint8_t[RomFileSize + 0x1000]); if (ImageBase.get() == NULL) { SetError(MSG_MEM_ALLOC_ERROR);