From 87dc96752d62193ced1ccff48548287b6e2651f3 Mon Sep 17 00:00:00 2001 From: LegendOfDragoon Date: Fri, 9 Oct 2015 11:39:46 -0700 Subject: [PATCH 1/4] Implement Recompiler version of LBV --- Source/RSP/Recompiler Ops.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/Source/RSP/Recompiler Ops.c b/Source/RSP/Recompiler Ops.c index c49fa6449..2bf2fe1f2 100644 --- a/Source/RSP/Recompiler Ops.c +++ b/Source/RSP/Recompiler Ops.c @@ -98,6 +98,7 @@ DWORD BranchCompare = 0; # define CompileVnand #endif #ifdef RSP_VectorLoads +# define CompileLbv # define CompileSqv /* Verified 12/17/2000 - Jabo */ # define CompileSdv /* Verified 12/17/2000 - Jabo */ # define CompileSsv /* Verified 12/17/2000 - Jabo */ @@ -5042,7 +5043,24 @@ void Compile_Vector_VNOOP ( void ) { /************************** lc2 functions **************************/ void Compile_Opcode_LBV ( void ) { - Cheat_r4300iOpcode(RSP_Opcode_LBV,"RSP_Opcode_LBV"); + char Reg[256]; + int offset = RSPOpC.voffset << 0; + + #ifndef CompileLbv + Cheat_r4300iOpcode(RSP_Opcode_LBV,"RSP_Opcode_LBV"); return; + #endif + + CPU_Message(" %X %s", CompilePC, RSPOpcodeName(RSPOpC.Hex, CompilePC)); + + MoveVariableToX86reg(&RSP_GPR[RSPOpC.base].UW, GPR_Name(RSPOpC.base), x86_EBX); + if (offset != 0) + AddConstToX86Reg(x86_EBX, offset); + + AndConstToX86Reg(x86_EBX, 0x0FFF); + XorConstToX86Reg(x86_EBX, 3); + MoveN64MemToX86regByte(x86_ECX, x86_EBX); + sprintf(Reg, "RSP_Vect[%i].B[%i]", RSPOpC.rt, 15 - RSPOpC.del); + MoveX86regByteToVariable(x86_ECX, &RSP_Vect[RSPOpC.rt].B[15 - RSPOpC.del], Reg); } void Compile_Opcode_LSV ( void ) { From 0fca9e65a45cb1dd2016f2bad0b469182bc817c8 Mon Sep 17 00:00:00 2001 From: LegendOfDragoon Date: Fri, 9 Oct 2015 11:49:03 -0700 Subject: [PATCH 2/4] Implement Recompiler version of LPV --- Source/RSP/Recompiler Ops.c | 108 +++++++++++++++++++++++++++++++++++- 1 file changed, 107 insertions(+), 1 deletion(-) diff --git a/Source/RSP/Recompiler Ops.c b/Source/RSP/Recompiler Ops.c index 2bf2fe1f2..3e12778ef 100644 --- a/Source/RSP/Recompiler Ops.c +++ b/Source/RSP/Recompiler Ops.c @@ -99,6 +99,7 @@ DWORD BranchCompare = 0; #endif #ifdef RSP_VectorLoads # define CompileLbv +# define CompileLpv # define CompileSqv /* Verified 12/17/2000 - Jabo */ # define CompileSdv /* Verified 12/17/2000 - Jabo */ # define CompileSsv /* Verified 12/17/2000 - Jabo */ @@ -5469,7 +5470,112 @@ void Compile_Opcode_LRV ( void ) { } void Compile_Opcode_LPV ( void ) { - Cheat_r4300iOpcode(RSP_Opcode_LPV,"RSP_Opcode_LPV"); + char Reg[256]; + int offset = (RSPOpC.voffset << 3); + + #ifndef CompileLpv + Cheat_r4300iOpcode(RSP_Opcode_LPV,"RSP_Opcode_LPV"); return; + #endif + + CPU_Message(" %X %s", CompilePC, RSPOpcodeName(RSPOpC.Hex, CompilePC)); + + MoveVariableToX86reg(&RSP_GPR[RSPOpC.base].UW, GPR_Name(RSPOpC.base), x86_EBX); + if (offset != 0) { + AddConstToX86Reg(x86_EBX, offset); + } + MoveX86RegToX86Reg(x86_EBX, x86_ESI); + MoveX86RegToX86Reg(x86_EBX, x86_EDI); + + AddConstToX86Reg(x86_ESI, (0x10 - RSPOpC.del + 0) & 0xF ); + AddConstToX86Reg(x86_EDI, (0x10 - RSPOpC.del + 1) & 0xF ); + + XorConstToX86Reg(x86_ESI, 3); + XorConstToX86Reg(x86_EDI, 3); + + AndConstToX86Reg(x86_ESI, 0x0fff); + AndConstToX86Reg(x86_EDI, 0x0fff); + + MoveZxN64MemToX86regByte(x86_ECX, x86_ESI); + MoveZxN64MemToX86regByte(x86_EDX, x86_EDI); + + ShiftLeftSignImmed(x86_ECX, 8); + ShiftLeftSignImmed(x86_EDX, 8); + + sprintf(Reg, "RSP_Vect[%i].HW[7]", RSPOpC.rt); + MoveX86regHalfToVariable(x86_ECX, &RSP_Vect[RSPOpC.rt].HW[7], Reg); + sprintf(Reg, "RSP_Vect[%i].HW[6]", RSPOpC.rt); + MoveX86regHalfToVariable(x86_EDX, &RSP_Vect[RSPOpC.rt].HW[6], Reg); + + + MoveX86RegToX86Reg(x86_EBX, x86_ESI); + MoveX86RegToX86Reg(x86_EBX, x86_EDI); + + AddConstToX86Reg(x86_ESI, (0x10 - RSPOpC.del + 2) & 0xF ); + AddConstToX86Reg(x86_EDI, (0x10 - RSPOpC.del + 3) & 0xF ); + + XorConstToX86Reg(x86_ESI, 3); + XorConstToX86Reg(x86_EDI, 3); + + AndConstToX86Reg(x86_ESI, 0x0fff); + AndConstToX86Reg(x86_EDI, 0x0fff); + + MoveZxN64MemToX86regByte(x86_ECX, x86_ESI); + MoveZxN64MemToX86regByte(x86_EDX, x86_EDI); + + ShiftLeftSignImmed(x86_ECX, 8); + ShiftLeftSignImmed(x86_EDX, 8); + + sprintf(Reg, "RSP_Vect[%i].HW[5]", RSPOpC.rt); + MoveX86regHalfToVariable(x86_ECX, &RSP_Vect[RSPOpC.rt].HW[5], Reg); + sprintf(Reg, "RSP_Vect[%i].HW[4]", RSPOpC.rt); + MoveX86regHalfToVariable(x86_EDX, &RSP_Vect[RSPOpC.rt].HW[4], Reg); + + + MoveX86RegToX86Reg(x86_EBX, x86_ESI); + MoveX86RegToX86Reg(x86_EBX, x86_EDI); + + AddConstToX86Reg(x86_ESI, (0x10 - RSPOpC.del + 4) & 0xF ); + AddConstToX86Reg(x86_EDI, (0x10 - RSPOpC.del + 5) & 0xF ); + + XorConstToX86Reg(x86_ESI, 3); + XorConstToX86Reg(x86_EDI, 3); + + AndConstToX86Reg(x86_ESI, 0x0fff); + AndConstToX86Reg(x86_EDI, 0x0fff); + + MoveZxN64MemToX86regByte(x86_ECX, x86_ESI); + MoveZxN64MemToX86regByte(x86_EDX, x86_EDI); + + ShiftLeftSignImmed(x86_ECX, 8); + ShiftLeftSignImmed(x86_EDX, 8); + + sprintf(Reg, "RSP_Vect[%i].HW[3]", RSPOpC.rt); + MoveX86regHalfToVariable(x86_ECX, &RSP_Vect[RSPOpC.rt].HW[3], Reg); + sprintf(Reg, "RSP_Vect[%i].HW[2]", RSPOpC.rt); + MoveX86regHalfToVariable(x86_EDX, &RSP_Vect[RSPOpC.rt].HW[2], Reg); + + + MoveX86RegToX86Reg(x86_EBX, x86_ESI); + + AddConstToX86Reg(x86_ESI, (0x10 - RSPOpC.del + 6) & 0xF ); + AddConstToX86Reg(x86_EBX, (0x10 - RSPOpC.del + 7) & 0xF ); + + XorConstToX86Reg(x86_ESI, 3); + XorConstToX86Reg(x86_EBX, 3); + + AndConstToX86Reg(x86_ESI, 0x0fff); + AndConstToX86Reg(x86_EBX, 0x0fff); + + MoveZxN64MemToX86regByte(x86_ECX, x86_ESI); + MoveZxN64MemToX86regByte(x86_EDX, x86_EBX); + + ShiftLeftSignImmed(x86_ECX, 8); + ShiftLeftSignImmed(x86_EDX, 8); + + sprintf(Reg, "RSP_Vect[%i].HW[1]", RSPOpC.rt); + MoveX86regHalfToVariable(x86_ECX, &RSP_Vect[RSPOpC.rt].HW[1], Reg); + sprintf(Reg, "RSP_Vect[%i].HW[0]", RSPOpC.rt); + MoveX86regHalfToVariable(x86_EDX, &RSP_Vect[RSPOpC.rt].HW[0], Reg); } void Compile_Opcode_LUV ( void ) { From 221c4d1d4dced66af23b64ab02cc9cb9e2550dbe Mon Sep 17 00:00:00 2001 From: LegendOfDragoon Date: Fri, 9 Oct 2015 11:51:39 -0700 Subject: [PATCH 3/4] Implement Recompiler version of LUV --- Source/RSP/Recompiler Ops.c | 108 +++++++++++++++++++++++++++++++++++- 1 file changed, 107 insertions(+), 1 deletion(-) diff --git a/Source/RSP/Recompiler Ops.c b/Source/RSP/Recompiler Ops.c index 3e12778ef..e0f8b8556 100644 --- a/Source/RSP/Recompiler Ops.c +++ b/Source/RSP/Recompiler Ops.c @@ -100,6 +100,7 @@ DWORD BranchCompare = 0; #ifdef RSP_VectorLoads # define CompileLbv # define CompileLpv +# define CompileLuv # define CompileSqv /* Verified 12/17/2000 - Jabo */ # define CompileSdv /* Verified 12/17/2000 - Jabo */ # define CompileSsv /* Verified 12/17/2000 - Jabo */ @@ -5579,7 +5580,112 @@ void Compile_Opcode_LPV ( void ) { } void Compile_Opcode_LUV ( void ) { - Cheat_r4300iOpcode(RSP_Opcode_LUV,"RSP_Opcode_LUV"); + char Reg[256]; + int offset = (RSPOpC.voffset << 3); + + #ifndef CompileLuv + Cheat_r4300iOpcode(RSP_Opcode_LUV,"RSP_Opcode_LUV"); return; + #endif + + CPU_Message(" %X %s", CompilePC, RSPOpcodeName(RSPOpC.Hex, CompilePC)); + + MoveVariableToX86reg(&RSP_GPR[RSPOpC.base].UW, GPR_Name(RSPOpC.base), x86_EBX); + if (offset != 0) { + AddConstToX86Reg(x86_EBX, offset); + } + MoveX86RegToX86Reg(x86_EBX, x86_ESI); + MoveX86RegToX86Reg(x86_EBX, x86_EDI); + + AddConstToX86Reg(x86_ESI, (0x10 - RSPOpC.del + 0) & 0xF ); + AddConstToX86Reg(x86_EDI, (0x10 - RSPOpC.del + 1) & 0xF); + + XorConstToX86Reg(x86_ESI, 3); + XorConstToX86Reg(x86_EDI, 3); + + AndConstToX86Reg(x86_ESI, 0x0fff); + AndConstToX86Reg(x86_EDI, 0x0fff); + + MoveZxN64MemToX86regByte(x86_ECX, x86_ESI); + MoveZxN64MemToX86regByte(x86_EDX, x86_EDI); + + ShiftLeftSignImmed(x86_ECX, 7); + ShiftLeftSignImmed(x86_EDX, 7); + + sprintf(Reg, "RSP_Vect[%i].HW[7]", RSPOpC.rt); + MoveX86regHalfToVariable(x86_ECX, &RSP_Vect[RSPOpC.rt].HW[7], Reg); + sprintf(Reg, "RSP_Vect[%i].HW[6]", RSPOpC.rt); + MoveX86regHalfToVariable(x86_EDX, &RSP_Vect[RSPOpC.rt].HW[6], Reg); + + + MoveX86RegToX86Reg(x86_EBX, x86_ESI); + MoveX86RegToX86Reg(x86_EBX, x86_EDI); + + AddConstToX86Reg(x86_ESI, (0x10 - RSPOpC.del + 2) & 0xF); + AddConstToX86Reg(x86_EDI, (0x10 - RSPOpC.del + 3) & 0xF); + + XorConstToX86Reg(x86_ESI, 3); + XorConstToX86Reg(x86_EDI, 3); + + AndConstToX86Reg(x86_ESI, 0x0fff); + AndConstToX86Reg(x86_EDI, 0x0fff); + + MoveZxN64MemToX86regByte(x86_ECX, x86_ESI); + MoveZxN64MemToX86regByte(x86_EDX, x86_EDI); + + ShiftLeftSignImmed(x86_ECX, 7); + ShiftLeftSignImmed(x86_EDX, 7); + + sprintf(Reg, "RSP_Vect[%i].HW[5]", RSPOpC.rt); + MoveX86regHalfToVariable(x86_ECX, &RSP_Vect[RSPOpC.rt].HW[5], Reg); + sprintf(Reg, "RSP_Vect[%i].HW[4]", RSPOpC.rt); + MoveX86regHalfToVariable(x86_EDX, &RSP_Vect[RSPOpC.rt].HW[4], Reg); + + + MoveX86RegToX86Reg(x86_EBX, x86_ESI); + MoveX86RegToX86Reg(x86_EBX, x86_EDI); + + AddConstToX86Reg(x86_ESI, (0x10 - RSPOpC.del + 4) & 0xF); + AddConstToX86Reg(x86_EDI, (0x10 - RSPOpC.del + 5) & 0xF); + + XorConstToX86Reg(x86_ESI, 3); + XorConstToX86Reg(x86_EDI, 3); + + AndConstToX86Reg(x86_ESI, 0x0fff); + AndConstToX86Reg(x86_EDI, 0x0fff); + + MoveZxN64MemToX86regByte(x86_ECX, x86_ESI); + MoveZxN64MemToX86regByte(x86_EDX, x86_EDI); + + ShiftLeftSignImmed(x86_ECX, 7); + ShiftLeftSignImmed(x86_EDX, 7); + + sprintf(Reg, "RSP_Vect[%i].HW[3]", RSPOpC.rt); + MoveX86regHalfToVariable(x86_ECX, &RSP_Vect[RSPOpC.rt].HW[3], Reg); + sprintf(Reg, "RSP_Vect[%i].HW[2]", RSPOpC.rt); + MoveX86regHalfToVariable(x86_EDX, &RSP_Vect[RSPOpC.rt].HW[2], Reg); + + + MoveX86RegToX86Reg(x86_EBX, x86_ESI); + + AddConstToX86Reg(x86_ESI, (0x10 - RSPOpC.del + 6) & 0xF); + AddConstToX86Reg(x86_EBX, (0x10 - RSPOpC.del + 7) & 0xF); + + XorConstToX86Reg(x86_ESI, 3); + XorConstToX86Reg(x86_EBX, 3); + + AndConstToX86Reg(x86_ESI, 0x0fff); + AndConstToX86Reg(x86_EBX, 0x0fff); + + MoveZxN64MemToX86regByte(x86_ECX, x86_ESI); + MoveZxN64MemToX86regByte(x86_EDX, x86_EBX); + + ShiftLeftSignImmed(x86_ECX, 7); + ShiftLeftSignImmed(x86_EDX, 7); + + sprintf(Reg, "RSP_Vect[%i].HW[1]", RSPOpC.rt); + MoveX86regHalfToVariable(x86_ECX, &RSP_Vect[RSPOpC.rt].HW[1], Reg); + sprintf(Reg, "RSP_Vect[%i].HW[0]", RSPOpC.rt); + MoveX86regHalfToVariable(x86_EDX, &RSP_Vect[RSPOpC.rt].HW[0], Reg); } From 0cefcf16fb940931606fc94c565e2bdc3613910c Mon Sep 17 00:00:00 2001 From: LegendOfDragoon Date: Fri, 9 Oct 2015 11:54:27 -0700 Subject: [PATCH 4/4] Implement Recompiler version of LHV --- Source/RSP/Recompiler Ops.c | 108 +++++++++++++++++++++++++++++++++++- 1 file changed, 107 insertions(+), 1 deletion(-) diff --git a/Source/RSP/Recompiler Ops.c b/Source/RSP/Recompiler Ops.c index e0f8b8556..594f3c925 100644 --- a/Source/RSP/Recompiler Ops.c +++ b/Source/RSP/Recompiler Ops.c @@ -101,6 +101,7 @@ DWORD BranchCompare = 0; # define CompileLbv # define CompileLpv # define CompileLuv +# define CompileLhv # define CompileSqv /* Verified 12/17/2000 - Jabo */ # define CompileSdv /* Verified 12/17/2000 - Jabo */ # define CompileSsv /* Verified 12/17/2000 - Jabo */ @@ -5690,7 +5691,112 @@ void Compile_Opcode_LUV ( void ) { void Compile_Opcode_LHV ( void ) { - Cheat_r4300iOpcode(RSP_Opcode_LHV,"RSP_Opcode_LHV"); + char Reg[256]; + int offset = (RSPOpC.voffset << 4); + + #ifndef CompileLhv + Cheat_r4300iOpcode(RSP_Opcode_LHV,"RSP_Opcode_LHV"); return; + #endif + + CPU_Message(" %X %s", CompilePC, RSPOpcodeName(RSPOpC.Hex, CompilePC)); + + MoveVariableToX86reg(&RSP_GPR[RSPOpC.base].UW, GPR_Name(RSPOpC.base), x86_EBX); + if (offset != 0) { + AddConstToX86Reg(x86_EBX, offset); + } + MoveX86RegToX86Reg(x86_EBX, x86_ESI); + MoveX86RegToX86Reg(x86_EBX, x86_EDI); + + AddConstToX86Reg(x86_ESI, (0x10 - RSPOpC.del + 0) & 0xF); + AddConstToX86Reg(x86_EDI, (0x10 - RSPOpC.del + 2) & 0xF); + + XorConstToX86Reg(x86_ESI, 3); + XorConstToX86Reg(x86_EDI, 3); + + AndConstToX86Reg(x86_ESI, 0x0fff); + AndConstToX86Reg(x86_EDI, 0x0fff); + + MoveZxN64MemToX86regByte(x86_ECX, x86_ESI); + MoveZxN64MemToX86regByte(x86_EDX, x86_EDI); + + ShiftLeftSignImmed(x86_ECX, 7); + ShiftLeftSignImmed(x86_EDX, 7); + + sprintf(Reg, "RSP_Vect[%i].HW[7]", RSPOpC.rt); + MoveX86regHalfToVariable(x86_ECX, &RSP_Vect[RSPOpC.rt].HW[7], Reg); + sprintf(Reg, "RSP_Vect[%i].HW[6]", RSPOpC.rt); + MoveX86regHalfToVariable(x86_EDX, &RSP_Vect[RSPOpC.rt].HW[6], Reg); + + + MoveX86RegToX86Reg(x86_EBX, x86_ESI); + MoveX86RegToX86Reg(x86_EBX, x86_EDI); + + AddConstToX86Reg(x86_ESI, (0x10 - RSPOpC.del + 4) & 0xF); + AddConstToX86Reg(x86_EDI, (0x10 - RSPOpC.del + 6) & 0xF); + + XorConstToX86Reg(x86_ESI, 3); + XorConstToX86Reg(x86_EDI, 3); + + AndConstToX86Reg(x86_ESI, 0x0fff); + AndConstToX86Reg(x86_EDI, 0x0fff); + + MoveZxN64MemToX86regByte(x86_ECX, x86_ESI); + MoveZxN64MemToX86regByte(x86_EDX, x86_EDI); + + ShiftLeftSignImmed(x86_ECX, 7); + ShiftLeftSignImmed(x86_EDX, 7); + + sprintf(Reg, "RSP_Vect[%i].HW[5]", RSPOpC.rt); + MoveX86regHalfToVariable(x86_ECX, &RSP_Vect[RSPOpC.rt].HW[5], Reg); + sprintf(Reg, "RSP_Vect[%i].HW[4]", RSPOpC.rt); + MoveX86regHalfToVariable(x86_EDX, &RSP_Vect[RSPOpC.rt].HW[4], Reg); + + + MoveX86RegToX86Reg(x86_EBX, x86_ESI); + MoveX86RegToX86Reg(x86_EBX, x86_EDI); + + AddConstToX86Reg(x86_ESI, (0x10 - RSPOpC.del + 8) & 0xF); + AddConstToX86Reg(x86_EDI, (0x10 - RSPOpC.del + 10) & 0xF); + + XorConstToX86Reg(x86_ESI, 3); + XorConstToX86Reg(x86_EDI, 3); + + AndConstToX86Reg(x86_ESI, 0x0fff); + AndConstToX86Reg(x86_EDI, 0x0fff); + + MoveZxN64MemToX86regByte(x86_ECX, x86_ESI); + MoveZxN64MemToX86regByte(x86_EDX, x86_EDI); + + ShiftLeftSignImmed(x86_ECX, 7); + ShiftLeftSignImmed(x86_EDX, 7); + + sprintf(Reg, "RSP_Vect[%i].HW[3]", RSPOpC.rt); + MoveX86regHalfToVariable(x86_ECX, &RSP_Vect[RSPOpC.rt].HW[3], Reg); + sprintf(Reg, "RSP_Vect[%i].HW[2]", RSPOpC.rt); + MoveX86regHalfToVariable(x86_EDX, &RSP_Vect[RSPOpC.rt].HW[2], Reg); + + + MoveX86RegToX86Reg(x86_EBX, x86_ESI); + + AddConstToX86Reg(x86_ESI, (0x10 - RSPOpC.del + 12) & 0xF); + AddConstToX86Reg(x86_EBX, (0x10 - RSPOpC.del + 14) & 0xF); + + XorConstToX86Reg(x86_ESI, 3); + XorConstToX86Reg(x86_EBX, 3); + + AndConstToX86Reg(x86_ESI, 0x0fff); + AndConstToX86Reg(x86_EBX, 0x0fff); + + MoveZxN64MemToX86regByte(x86_ECX, x86_ESI); + MoveZxN64MemToX86regByte(x86_EDX, x86_EBX); + + ShiftLeftSignImmed(x86_ECX, 7); + ShiftLeftSignImmed(x86_EDX, 7); + + sprintf(Reg, "RSP_Vect[%i].HW[1]", RSPOpC.rt); + MoveX86regHalfToVariable(x86_ECX, &RSP_Vect[RSPOpC.rt].HW[1], Reg); + sprintf(Reg, "RSP_Vect[%i].HW[0]", RSPOpC.rt); + MoveX86regHalfToVariable(x86_EDX, &RSP_Vect[RSPOpC.rt].HW[0], Reg); }