diff --git a/Source/RSP/Recompiler Ops.c b/Source/RSP/Recompiler Ops.c
index c49fa6449..594f3c925 100644
--- a/Source/RSP/Recompiler Ops.c	
+++ b/Source/RSP/Recompiler Ops.c	
@@ -98,6 +98,10 @@ DWORD BranchCompare = 0;
 #	define CompileVnand
 #endif
 #ifdef RSP_VectorLoads
+#	define CompileLbv
+#	define CompileLpv
+#	define CompileLuv
+#	define CompileLhv
 #	define CompileSqv		/* Verified 12/17/2000 - Jabo */
 #	define CompileSdv		/* Verified 12/17/2000 - Jabo */
 #	define CompileSsv		/* Verified 12/17/2000 - Jabo */
@@ -5042,7 +5046,24 @@ void Compile_Vector_VNOOP ( void ) {
 /************************** lc2 functions **************************/
 
 void Compile_Opcode_LBV ( void ) {
-	Cheat_r4300iOpcode(RSP_Opcode_LBV,"RSP_Opcode_LBV");
+	char Reg[256];
+	int offset = RSPOpC.voffset << 0;
+
+	#ifndef CompileLbv
+	Cheat_r4300iOpcode(RSP_Opcode_LBV,"RSP_Opcode_LBV"); return;
+	#endif
+
+	CPU_Message("  %X %s", CompilePC, RSPOpcodeName(RSPOpC.Hex, CompilePC));
+
+	MoveVariableToX86reg(&RSP_GPR[RSPOpC.base].UW, GPR_Name(RSPOpC.base), x86_EBX);
+	if (offset != 0)
+		AddConstToX86Reg(x86_EBX, offset);
+
+	AndConstToX86Reg(x86_EBX, 0x0FFF);
+	XorConstToX86Reg(x86_EBX, 3);
+	MoveN64MemToX86regByte(x86_ECX, x86_EBX);
+	sprintf(Reg, "RSP_Vect[%i].B[%i]", RSPOpC.rt, 15 - RSPOpC.del);
+	MoveX86regByteToVariable(x86_ECX, &RSP_Vect[RSPOpC.rt].B[15 - RSPOpC.del], Reg);
 }
 
 void Compile_Opcode_LSV ( void ) {
@@ -5451,16 +5472,331 @@ void Compile_Opcode_LRV ( void ) {
 }
 
 void Compile_Opcode_LPV ( void ) {
-	Cheat_r4300iOpcode(RSP_Opcode_LPV,"RSP_Opcode_LPV");
+	char Reg[256];
+	int offset = (RSPOpC.voffset << 3);
+
+	#ifndef CompileLpv
+	Cheat_r4300iOpcode(RSP_Opcode_LPV,"RSP_Opcode_LPV"); return;
+	#endif
+	
+	CPU_Message("  %X %s", CompilePC, RSPOpcodeName(RSPOpC.Hex, CompilePC));
+	
+	MoveVariableToX86reg(&RSP_GPR[RSPOpC.base].UW, GPR_Name(RSPOpC.base), x86_EBX);
+	if (offset != 0) {
+		AddConstToX86Reg(x86_EBX, offset);
+	}
+	MoveX86RegToX86Reg(x86_EBX, x86_ESI);
+	MoveX86RegToX86Reg(x86_EBX, x86_EDI);
+	
+	AddConstToX86Reg(x86_ESI, (0x10 - RSPOpC.del + 0) & 0xF );			
+	AddConstToX86Reg(x86_EDI, (0x10 - RSPOpC.del + 1) & 0xF );
+
+	XorConstToX86Reg(x86_ESI, 3);
+	XorConstToX86Reg(x86_EDI, 3);
+
+	AndConstToX86Reg(x86_ESI, 0x0fff);
+	AndConstToX86Reg(x86_EDI, 0x0fff);
+
+	MoveZxN64MemToX86regByte(x86_ECX, x86_ESI);
+	MoveZxN64MemToX86regByte(x86_EDX, x86_EDI);
+
+	ShiftLeftSignImmed(x86_ECX, 8);
+	ShiftLeftSignImmed(x86_EDX, 8);
+
+	sprintf(Reg, "RSP_Vect[%i].HW[7]", RSPOpC.rt);
+	MoveX86regHalfToVariable(x86_ECX, &RSP_Vect[RSPOpC.rt].HW[7], Reg);
+	sprintf(Reg, "RSP_Vect[%i].HW[6]", RSPOpC.rt);
+	MoveX86regHalfToVariable(x86_EDX, &RSP_Vect[RSPOpC.rt].HW[6], Reg);
+
+
+	MoveX86RegToX86Reg(x86_EBX, x86_ESI);
+	MoveX86RegToX86Reg(x86_EBX, x86_EDI);
+
+	AddConstToX86Reg(x86_ESI, (0x10 - RSPOpC.del + 2) & 0xF );			
+	AddConstToX86Reg(x86_EDI, (0x10 - RSPOpC.del + 3) & 0xF );
+
+	XorConstToX86Reg(x86_ESI, 3);
+	XorConstToX86Reg(x86_EDI, 3);
+
+	AndConstToX86Reg(x86_ESI, 0x0fff);
+	AndConstToX86Reg(x86_EDI, 0x0fff);
+
+	MoveZxN64MemToX86regByte(x86_ECX, x86_ESI);
+	MoveZxN64MemToX86regByte(x86_EDX, x86_EDI);
+
+	ShiftLeftSignImmed(x86_ECX, 8);
+	ShiftLeftSignImmed(x86_EDX, 8);
+
+	sprintf(Reg, "RSP_Vect[%i].HW[5]", RSPOpC.rt);
+	MoveX86regHalfToVariable(x86_ECX, &RSP_Vect[RSPOpC.rt].HW[5], Reg);
+	sprintf(Reg, "RSP_Vect[%i].HW[4]", RSPOpC.rt);
+	MoveX86regHalfToVariable(x86_EDX, &RSP_Vect[RSPOpC.rt].HW[4], Reg);
+
+
+	MoveX86RegToX86Reg(x86_EBX, x86_ESI);
+	MoveX86RegToX86Reg(x86_EBX, x86_EDI);
+
+	AddConstToX86Reg(x86_ESI, (0x10 - RSPOpC.del + 4) & 0xF );			
+	AddConstToX86Reg(x86_EDI, (0x10 - RSPOpC.del + 5) & 0xF );
+
+	XorConstToX86Reg(x86_ESI, 3);
+	XorConstToX86Reg(x86_EDI, 3);
+
+	AndConstToX86Reg(x86_ESI, 0x0fff);
+	AndConstToX86Reg(x86_EDI, 0x0fff);
+
+	MoveZxN64MemToX86regByte(x86_ECX, x86_ESI);
+	MoveZxN64MemToX86regByte(x86_EDX, x86_EDI);
+
+	ShiftLeftSignImmed(x86_ECX, 8);
+	ShiftLeftSignImmed(x86_EDX, 8);
+
+	sprintf(Reg, "RSP_Vect[%i].HW[3]", RSPOpC.rt);
+	MoveX86regHalfToVariable(x86_ECX, &RSP_Vect[RSPOpC.rt].HW[3], Reg);
+	sprintf(Reg, "RSP_Vect[%i].HW[2]", RSPOpC.rt);
+	MoveX86regHalfToVariable(x86_EDX, &RSP_Vect[RSPOpC.rt].HW[2], Reg);
+
+
+	MoveX86RegToX86Reg(x86_EBX, x86_ESI);
+
+	AddConstToX86Reg(x86_ESI, (0x10 - RSPOpC.del + 6) & 0xF );			
+	AddConstToX86Reg(x86_EBX, (0x10 - RSPOpC.del + 7) & 0xF );
+
+	XorConstToX86Reg(x86_ESI, 3);
+	XorConstToX86Reg(x86_EBX, 3);
+
+	AndConstToX86Reg(x86_ESI, 0x0fff);
+	AndConstToX86Reg(x86_EBX, 0x0fff);
+
+	MoveZxN64MemToX86regByte(x86_ECX, x86_ESI);
+	MoveZxN64MemToX86regByte(x86_EDX, x86_EBX);
+
+	ShiftLeftSignImmed(x86_ECX, 8);
+	ShiftLeftSignImmed(x86_EDX, 8);
+
+	sprintf(Reg, "RSP_Vect[%i].HW[1]", RSPOpC.rt);
+	MoveX86regHalfToVariable(x86_ECX, &RSP_Vect[RSPOpC.rt].HW[1], Reg);
+	sprintf(Reg, "RSP_Vect[%i].HW[0]", RSPOpC.rt);
+	MoveX86regHalfToVariable(x86_EDX, &RSP_Vect[RSPOpC.rt].HW[0], Reg);
 }
 
 void Compile_Opcode_LUV ( void ) {
-	Cheat_r4300iOpcode(RSP_Opcode_LUV,"RSP_Opcode_LUV");
+	char Reg[256];
+	int offset = (RSPOpC.voffset << 3);
+
+	#ifndef CompileLuv
+	Cheat_r4300iOpcode(RSP_Opcode_LUV,"RSP_Opcode_LUV"); return;
+	#endif
+
+	CPU_Message("  %X %s", CompilePC, RSPOpcodeName(RSPOpC.Hex, CompilePC));
+
+	MoveVariableToX86reg(&RSP_GPR[RSPOpC.base].UW, GPR_Name(RSPOpC.base), x86_EBX);
+	if (offset != 0) {
+		AddConstToX86Reg(x86_EBX, offset);
+	}
+	MoveX86RegToX86Reg(x86_EBX, x86_ESI);
+	MoveX86RegToX86Reg(x86_EBX, x86_EDI);
+
+	AddConstToX86Reg(x86_ESI, (0x10 - RSPOpC.del + 0) & 0xF );			
+	AddConstToX86Reg(x86_EDI, (0x10 - RSPOpC.del + 1) & 0xF);
+
+	XorConstToX86Reg(x86_ESI, 3);
+	XorConstToX86Reg(x86_EDI, 3);
+
+	AndConstToX86Reg(x86_ESI, 0x0fff);
+	AndConstToX86Reg(x86_EDI, 0x0fff);
+
+	MoveZxN64MemToX86regByte(x86_ECX, x86_ESI);
+	MoveZxN64MemToX86regByte(x86_EDX, x86_EDI);
+
+	ShiftLeftSignImmed(x86_ECX, 7);
+	ShiftLeftSignImmed(x86_EDX, 7);
+
+	sprintf(Reg, "RSP_Vect[%i].HW[7]", RSPOpC.rt);
+	MoveX86regHalfToVariable(x86_ECX, &RSP_Vect[RSPOpC.rt].HW[7], Reg);
+	sprintf(Reg, "RSP_Vect[%i].HW[6]", RSPOpC.rt);
+	MoveX86regHalfToVariable(x86_EDX, &RSP_Vect[RSPOpC.rt].HW[6], Reg);
+
+
+	MoveX86RegToX86Reg(x86_EBX, x86_ESI);
+	MoveX86RegToX86Reg(x86_EBX, x86_EDI);
+
+	AddConstToX86Reg(x86_ESI, (0x10 - RSPOpC.del + 2) & 0xF);
+	AddConstToX86Reg(x86_EDI, (0x10 - RSPOpC.del + 3) & 0xF);
+
+	XorConstToX86Reg(x86_ESI, 3);
+	XorConstToX86Reg(x86_EDI, 3);
+
+	AndConstToX86Reg(x86_ESI, 0x0fff);
+	AndConstToX86Reg(x86_EDI, 0x0fff);
+
+	MoveZxN64MemToX86regByte(x86_ECX, x86_ESI);
+	MoveZxN64MemToX86regByte(x86_EDX, x86_EDI);
+
+	ShiftLeftSignImmed(x86_ECX, 7);
+	ShiftLeftSignImmed(x86_EDX, 7);
+
+	sprintf(Reg, "RSP_Vect[%i].HW[5]", RSPOpC.rt);
+	MoveX86regHalfToVariable(x86_ECX, &RSP_Vect[RSPOpC.rt].HW[5], Reg);
+	sprintf(Reg, "RSP_Vect[%i].HW[4]", RSPOpC.rt);
+	MoveX86regHalfToVariable(x86_EDX, &RSP_Vect[RSPOpC.rt].HW[4], Reg);
+
+
+	MoveX86RegToX86Reg(x86_EBX, x86_ESI);
+	MoveX86RegToX86Reg(x86_EBX, x86_EDI);
+
+	AddConstToX86Reg(x86_ESI, (0x10 - RSPOpC.del + 4) & 0xF);
+	AddConstToX86Reg(x86_EDI, (0x10 - RSPOpC.del + 5) & 0xF);
+
+	XorConstToX86Reg(x86_ESI, 3);
+	XorConstToX86Reg(x86_EDI, 3);
+
+	AndConstToX86Reg(x86_ESI, 0x0fff);
+	AndConstToX86Reg(x86_EDI, 0x0fff);
+
+	MoveZxN64MemToX86regByte(x86_ECX, x86_ESI);
+	MoveZxN64MemToX86regByte(x86_EDX, x86_EDI);
+
+	ShiftLeftSignImmed(x86_ECX, 7);
+	ShiftLeftSignImmed(x86_EDX, 7);
+
+	sprintf(Reg, "RSP_Vect[%i].HW[3]", RSPOpC.rt);
+	MoveX86regHalfToVariable(x86_ECX, &RSP_Vect[RSPOpC.rt].HW[3], Reg);
+	sprintf(Reg, "RSP_Vect[%i].HW[2]", RSPOpC.rt);
+	MoveX86regHalfToVariable(x86_EDX, &RSP_Vect[RSPOpC.rt].HW[2], Reg);
+
+
+	MoveX86RegToX86Reg(x86_EBX, x86_ESI);
+
+	AddConstToX86Reg(x86_ESI, (0x10 - RSPOpC.del + 6) & 0xF);
+	AddConstToX86Reg(x86_EBX, (0x10 - RSPOpC.del + 7) & 0xF);
+
+	XorConstToX86Reg(x86_ESI, 3);
+	XorConstToX86Reg(x86_EBX, 3);
+
+	AndConstToX86Reg(x86_ESI, 0x0fff);
+	AndConstToX86Reg(x86_EBX, 0x0fff);
+
+	MoveZxN64MemToX86regByte(x86_ECX, x86_ESI);
+	MoveZxN64MemToX86regByte(x86_EDX, x86_EBX);
+
+	ShiftLeftSignImmed(x86_ECX, 7);
+	ShiftLeftSignImmed(x86_EDX, 7);
+
+	sprintf(Reg, "RSP_Vect[%i].HW[1]", RSPOpC.rt);
+	MoveX86regHalfToVariable(x86_ECX, &RSP_Vect[RSPOpC.rt].HW[1], Reg);
+	sprintf(Reg, "RSP_Vect[%i].HW[0]", RSPOpC.rt);
+	MoveX86regHalfToVariable(x86_EDX, &RSP_Vect[RSPOpC.rt].HW[0], Reg);
 }
 
 
 void Compile_Opcode_LHV ( void ) {
-	Cheat_r4300iOpcode(RSP_Opcode_LHV,"RSP_Opcode_LHV");
+	char Reg[256];
+	int offset = (RSPOpC.voffset << 4);
+
+	#ifndef CompileLhv
+	Cheat_r4300iOpcode(RSP_Opcode_LHV,"RSP_Opcode_LHV"); return;
+	#endif
+
+	CPU_Message("  %X %s", CompilePC, RSPOpcodeName(RSPOpC.Hex, CompilePC));
+
+	MoveVariableToX86reg(&RSP_GPR[RSPOpC.base].UW, GPR_Name(RSPOpC.base), x86_EBX);
+	if (offset != 0) {
+		AddConstToX86Reg(x86_EBX, offset);
+	}
+	MoveX86RegToX86Reg(x86_EBX, x86_ESI);
+	MoveX86RegToX86Reg(x86_EBX, x86_EDI);
+
+	AddConstToX86Reg(x86_ESI, (0x10 - RSPOpC.del + 0) & 0xF);
+	AddConstToX86Reg(x86_EDI, (0x10 - RSPOpC.del + 2) & 0xF);
+
+	XorConstToX86Reg(x86_ESI, 3);
+	XorConstToX86Reg(x86_EDI, 3);
+
+	AndConstToX86Reg(x86_ESI, 0x0fff);
+	AndConstToX86Reg(x86_EDI, 0x0fff);
+
+	MoveZxN64MemToX86regByte(x86_ECX, x86_ESI);
+	MoveZxN64MemToX86regByte(x86_EDX, x86_EDI);
+
+	ShiftLeftSignImmed(x86_ECX, 7);
+	ShiftLeftSignImmed(x86_EDX, 7);
+
+	sprintf(Reg, "RSP_Vect[%i].HW[7]", RSPOpC.rt);
+	MoveX86regHalfToVariable(x86_ECX, &RSP_Vect[RSPOpC.rt].HW[7], Reg);
+	sprintf(Reg, "RSP_Vect[%i].HW[6]", RSPOpC.rt);
+	MoveX86regHalfToVariable(x86_EDX, &RSP_Vect[RSPOpC.rt].HW[6], Reg);
+
+
+	MoveX86RegToX86Reg(x86_EBX, x86_ESI);
+	MoveX86RegToX86Reg(x86_EBX, x86_EDI);
+
+	AddConstToX86Reg(x86_ESI, (0x10 - RSPOpC.del + 4) & 0xF);
+	AddConstToX86Reg(x86_EDI, (0x10 - RSPOpC.del + 6) & 0xF);
+
+	XorConstToX86Reg(x86_ESI, 3);
+	XorConstToX86Reg(x86_EDI, 3);
+
+	AndConstToX86Reg(x86_ESI, 0x0fff);
+	AndConstToX86Reg(x86_EDI, 0x0fff);
+
+	MoveZxN64MemToX86regByte(x86_ECX, x86_ESI);
+	MoveZxN64MemToX86regByte(x86_EDX, x86_EDI);
+
+	ShiftLeftSignImmed(x86_ECX, 7);
+	ShiftLeftSignImmed(x86_EDX, 7);
+
+	sprintf(Reg, "RSP_Vect[%i].HW[5]", RSPOpC.rt);
+	MoveX86regHalfToVariable(x86_ECX, &RSP_Vect[RSPOpC.rt].HW[5], Reg);
+	sprintf(Reg, "RSP_Vect[%i].HW[4]", RSPOpC.rt);
+	MoveX86regHalfToVariable(x86_EDX, &RSP_Vect[RSPOpC.rt].HW[4], Reg);
+
+
+	MoveX86RegToX86Reg(x86_EBX, x86_ESI);
+	MoveX86RegToX86Reg(x86_EBX, x86_EDI);
+
+	AddConstToX86Reg(x86_ESI, (0x10 - RSPOpC.del + 8) & 0xF);
+	AddConstToX86Reg(x86_EDI, (0x10 - RSPOpC.del + 10) & 0xF);
+
+	XorConstToX86Reg(x86_ESI, 3);
+	XorConstToX86Reg(x86_EDI, 3);
+
+	AndConstToX86Reg(x86_ESI, 0x0fff);
+	AndConstToX86Reg(x86_EDI, 0x0fff);
+
+	MoveZxN64MemToX86regByte(x86_ECX, x86_ESI);
+	MoveZxN64MemToX86regByte(x86_EDX, x86_EDI);
+
+	ShiftLeftSignImmed(x86_ECX, 7);
+	ShiftLeftSignImmed(x86_EDX, 7);
+
+	sprintf(Reg, "RSP_Vect[%i].HW[3]", RSPOpC.rt);
+	MoveX86regHalfToVariable(x86_ECX, &RSP_Vect[RSPOpC.rt].HW[3], Reg);
+	sprintf(Reg, "RSP_Vect[%i].HW[2]", RSPOpC.rt);
+	MoveX86regHalfToVariable(x86_EDX, &RSP_Vect[RSPOpC.rt].HW[2], Reg);
+
+
+	MoveX86RegToX86Reg(x86_EBX, x86_ESI);
+
+	AddConstToX86Reg(x86_ESI, (0x10 - RSPOpC.del + 12) & 0xF);
+	AddConstToX86Reg(x86_EBX, (0x10 - RSPOpC.del + 14) & 0xF);
+
+	XorConstToX86Reg(x86_ESI, 3);
+	XorConstToX86Reg(x86_EBX, 3);
+
+	AndConstToX86Reg(x86_ESI, 0x0fff);
+	AndConstToX86Reg(x86_EBX, 0x0fff);
+
+	MoveZxN64MemToX86regByte(x86_ECX, x86_ESI);
+	MoveZxN64MemToX86regByte(x86_EDX, x86_EBX);
+
+	ShiftLeftSignImmed(x86_ECX, 7);
+	ShiftLeftSignImmed(x86_EDX, 7);
+
+	sprintf(Reg, "RSP_Vect[%i].HW[1]", RSPOpC.rt);
+	MoveX86regHalfToVariable(x86_ECX, &RSP_Vect[RSPOpC.rt].HW[1], Reg);
+	sprintf(Reg, "RSP_Vect[%i].HW[0]", RSPOpC.rt);
+	MoveX86regHalfToVariable(x86_EDX, &RSP_Vect[RSPOpC.rt].HW[0], Reg);
 }