From db50dac063ecec03472901be723eb6e7b07b8757 Mon Sep 17 00:00:00 2001 From: zilmar Date: Mon, 21 Feb 2022 21:56:25 +1030 Subject: [PATCH] Core: Add DisplayControlRegHandler --- Source/Project64-core/Logging.cpp | 34 +--- .../DisplayControlRegHandler.cpp | 146 ++++++++++++++++++ .../MemoryHandler/DisplayControlRegHandler.h | 80 ++++++++++ .../PeripheralInterfaceHandler.h | 1 + .../MemoryHandler/SPRegistersHandler.cpp | 2 +- .../N64System/Mips/MemoryVirtualMem.cpp | 90 +---------- .../N64System/Mips/MemoryVirtualMem.h | 4 +- .../Project64-core/N64System/Mips/Register.h | 49 +----- Source/Project64-core/Project64-core.vcxproj | 2 + .../Project64-core.vcxproj.filters | 6 + 10 files changed, 244 insertions(+), 170 deletions(-) create mode 100644 Source/Project64-core/N64System/MemoryHandler/DisplayControlRegHandler.cpp create mode 100644 Source/Project64-core/N64System/MemoryHandler/DisplayControlRegHandler.h diff --git a/Source/Project64-core/Logging.cpp b/Source/Project64-core/Logging.cpp index aebf55f3a..88984c917 100644 --- a/Source/Project64-core/Logging.cpp +++ b/Source/Project64-core/Logging.cpp @@ -51,23 +51,7 @@ void CLogging::Log_LW(uint32_t PC, uint32_t VAddr) } if (VAddr >= 0xA4100000 && VAddr <= 0xA410001C) { - if (!LogDPCRegisters()) - { - return; - } - g_MMU->LW_VAddr(VAddr, Value); - - switch (VAddr) - { - case 0xA4100000: LogMessage("%08X: read from DPC_START_REG (%08X)", PC, Value); return; - case 0xA4100004: LogMessage("%08X: read from DPC_END_REG (%08X)", PC, Value); return; - case 0xA4100008: LogMessage("%08X: read from DPC_CURRENT_REG (%08X)", PC, Value); return; - case 0xA410000C: LogMessage("%08X: read from DPC_STATUS_REG (%08X)", PC, Value); return; - case 0xA4100010: LogMessage("%08X: read from DPC_CLOCK_REG (%08X)", PC, Value); return; - case 0xA4100014: LogMessage("%08X: read from DPC_BUFBUSY_REG (%08X)", PC, Value); return; - case 0xA4100018: LogMessage("%08X: read from DPC_PIPEBUSY_REG (%08X)", PC, Value); return; - case 0xA410001C: LogMessage("%08X: read from DPC_TMEM_REG (%08X)", PC, Value); return; - } + return; } if (VAddr >= 0xA4300000 && VAddr <= 0xA430000C) { @@ -257,21 +241,7 @@ void CLogging::Log_SW(uint32_t PC, uint32_t VAddr, uint32_t Value) if (VAddr >= 0xA4100000 && VAddr <= 0xA410001C) { - if (!LogDPCRegisters()) - { - return; - } - switch (VAddr) - { - case 0xA4100000: LogMessage("%08X: Writing 0x%08X to DPC_START_REG", PC, Value); return; - case 0xA4100004: LogMessage("%08X: Writing 0x%08X to DPC_END_REG", PC, Value); return; - case 0xA4100008: LogMessage("%08X: Writing 0x%08X to DPC_CURRENT_REG", PC, Value); return; - case 0xA410000C: LogMessage("%08X: Writing 0x%08X to DPC_STATUS_REG", PC, Value); return; - case 0xA4100010: LogMessage("%08X: Writing 0x%08X to DPC_CLOCK_REG", PC, Value); return; - case 0xA4100014: LogMessage("%08X: Writing 0x%08X to DPC_BUFBUSY_REG", PC, Value); return; - case 0xA4100018: LogMessage("%08X: Writing 0x%08X to DPC_PIPEBUSY_REG", PC, Value); return; - case 0xA410001C: LogMessage("%08X: Writing 0x%08X to DPC_TMEM_REG", PC, Value); return; - } + return; } if (VAddr >= 0xA4200000 && VAddr <= 0xA420000C) diff --git a/Source/Project64-core/N64System/MemoryHandler/DisplayControlRegHandler.cpp b/Source/Project64-core/N64System/MemoryHandler/DisplayControlRegHandler.cpp new file mode 100644 index 000000000..a1034b96f --- /dev/null +++ b/Source/Project64-core/N64System/MemoryHandler/DisplayControlRegHandler.cpp @@ -0,0 +1,146 @@ +#include "stdafx.h" +#include +#include +#include +#include +#include +#include +#include "SPRegistersHandler.h" + +DisplayControlRegHandler::DisplayControlRegHandler(CN64System & N64System, CPlugins * Plugins, CRegisters & Reg) : + DisplayControlReg(Reg.m_Display_ControlReg), + SPRegistersReg(Reg.m_SigProcessor_Interface), + m_System(N64System), + m_Plugins(Plugins), + m_PC(Reg.m_PROGRAM_COUNTER) +{ +} + +bool DisplayControlRegHandler::Read32(uint32_t Address, uint32_t & Value) +{ + switch (Address & 0x1FFFFFFF) + { + case 0x0410000C: Value = DPC_STATUS_REG; break; + case 0x04100010: Value = DPC_CLOCK_REG; break; + case 0x04100014: Value = DPC_BUFBUSY_REG; break; + case 0x04100018: Value = DPC_PIPEBUSY_REG; break; + case 0x0410001C: Value = DPC_TMEM_REG; break; + default: + Value = 0; + if (HaveDebugger()) + { + g_Notify->BreakPoint(__FILE__, __LINE__); + } + } + + if (GenerateLog() && LogDPCRegisters()) + { + switch (Address & 0x1FFFFFFF) + { + case 0x04100000: LogMessage("%08X: read from DPC_START_REG (%08X)", m_PC, Value); break; + case 0x04100004: LogMessage("%08X: read from DPC_END_REG (%08X)", m_PC, Value); break; + case 0x04100008: LogMessage("%08X: read from DPC_CURRENT_REG (%08X)", m_PC, Value); break; + case 0x0410000C: LogMessage("%08X: read from DPC_STATUS_REG (%08X)", m_PC, Value); break; + case 0x04100010: LogMessage("%08X: read from DPC_CLOCK_REG (%08X)", m_PC, Value); break; + case 0x04100014: LogMessage("%08X: read from DPC_BUFBUSY_REG (%08X)", m_PC, Value); break; + case 0x04100018: LogMessage("%08X: read from DPC_PIPEBUSY_REG (%08X)", m_PC, Value); break; + case 0x0410001C: LogMessage("%08X: read from DPC_TMEM_REG (%08X)", m_PC, Value); break; + default: + if (HaveDebugger()) + { + g_Notify->BreakPoint(__FILE__, __LINE__); + } + } + } + return true; +} + +bool DisplayControlRegHandler::Write32(uint32_t Address, uint32_t Value, uint32_t Mask) +{ + if (GenerateLog() && LogDPCRegisters()) + { + switch (Address & 0x1FFFFFFF) + { + case 0x04100000: LogMessage("%08X: Writing 0x%08X (Mask: 0x%08X) to DPC_START_REG", m_PC, Value, Mask); break; + case 0x04100004: LogMessage("%08X: Writing 0x%08X (Mask: 0x%08X) to DPC_END_REG", m_PC, Value, Mask); break; + case 0x04100008: LogMessage("%08X: Writing 0x%08X (Mask: 0x%08X) to DPC_CURRENT_REG", m_PC, Value, Mask); break; + case 0x0410000C: LogMessage("%08X: Writing 0x%08X (Mask: 0x%08X) to DPC_STATUS_REG", m_PC, Value, Mask); break; + case 0x04100010: LogMessage("%08X: Writing 0x%08X (Mask: 0x%08X) to DPC_CLOCK_REG", m_PC, Value, Mask); break; + case 0x04100014: LogMessage("%08X: Writing 0x%08X (Mask: 0x%08X) to DPC_BUFBUSY_REG", m_PC, Value, Mask); break; + case 0x04100018: LogMessage("%08X: Writing 0x%08X (Mask: 0x%08X) to DPC_PIPEBUSY_REG", m_PC, Value, Mask); break; + case 0x0410001C: LogMessage("%08X: Writing 0x%08X (Mask: 0x%08X) to DPC_TMEM_REG", m_PC, Value, Mask); break; + default: + if (HaveDebugger()) + { + g_Notify->BreakPoint(__FILE__, __LINE__); + } + } + } + + uint32_t MaskedValue = Value & Mask; + switch (Address & 0x1FFFFFFF) + { + case 0x04100000: + DPC_START_REG = MaskedValue; + DPC_CURRENT_REG = MaskedValue; + break; + case 0x04100004: + DPC_END_REG = MaskedValue; + if (m_Plugins->Gfx()->ProcessRDPList) + { + m_Plugins->Gfx()->ProcessRDPList(); + } + break; + //case 0x04100008: g_Reg->DPC_CURRENT_REG = Value; break; + case 0x0410000C: + if ((MaskedValue & DPC_CLR_XBUS_DMEM_DMA) != 0) + { + DPC_STATUS_REG &= ~DPC_STATUS_XBUS_DMEM_DMA; + } + if ((MaskedValue & DPC_SET_XBUS_DMEM_DMA) != 0) + { + DPC_STATUS_REG |= DPC_STATUS_XBUS_DMEM_DMA; + } + if ((MaskedValue & DPC_CLR_FREEZE) != 0) + { + DPC_STATUS_REG &= ~DPC_STATUS_FREEZE; + } + if ((MaskedValue & DPC_SET_FREEZE) != 0) + { + DPC_STATUS_REG |= DPC_STATUS_FREEZE; + } + if ((MaskedValue & DPC_CLR_FLUSH) != 0) + { + DPC_STATUS_REG &= ~DPC_STATUS_FLUSH; + } + if ((MaskedValue & DPC_SET_FLUSH) != 0) + { + DPC_STATUS_REG |= DPC_STATUS_FLUSH; + } + if ((MaskedValue & DPC_CLR_FREEZE) != 0) + { + if ((SP_STATUS_REG & SP_STATUS_HALT) == 0) + { + if ((SP_STATUS_REG & SP_STATUS_BROKE) == 0) + { + __except_try() + { + m_System.RunRSP(); + } + __except_catch() + { + g_Notify->BreakPoint(__FILE__, __LINE__); + } + } + } + } + break; + default: + if (HaveDebugger()) + { + g_Notify->BreakPoint(__FILE__, __LINE__); + } + } + return true; +} + diff --git a/Source/Project64-core/N64System/MemoryHandler/DisplayControlRegHandler.h b/Source/Project64-core/N64System/MemoryHandler/DisplayControlRegHandler.h new file mode 100644 index 000000000..25a155c35 --- /dev/null +++ b/Source/Project64-core/N64System/MemoryHandler/DisplayControlRegHandler.h @@ -0,0 +1,80 @@ +#pragma once +#include +#include +#include "SPRegistersHandler.h" +#include "MemoryHandler.h" +#include + +enum +{ + DPC_CLR_XBUS_DMEM_DMA = 0x0001, // Bit 0: Clear xbus_dmem_dma + DPC_SET_XBUS_DMEM_DMA = 0x0002, // Bit 1: Set xbus_dmem_dma + DPC_CLR_FREEZE = 0x0004, // Bit 2: Clear freeze + DPC_SET_FREEZE = 0x0008, // Bit 3: Set freeze + DPC_CLR_FLUSH = 0x0010, // Bit 4: Clear flush + DPC_SET_FLUSH = 0x0020, // Bit 5: Set flush + DPC_CLR_TMEM_CTR = 0x0040, // Bit 6: Clear TMEM CTR + DPC_CLR_PIPE_CTR = 0x0080, // Bit 7: Clear pipe CTR + DPC_CLR_CMD_CTR = 0x0100, // Bit 8: Clear CMD CTR + DPC_CLR_CLOCK_CTR = 0x0200, // Bit 9: Clear clock CTR + + DPC_STATUS_XBUS_DMEM_DMA = 0x001, // Bit 0: xbus_dmem_dma + DPC_STATUS_FREEZE = 0x002, // Bit 1: Freeze + DPC_STATUS_FLUSH = 0x004, // Bit 2: Flush + DPC_STATUS_START_GCLK = 0x008, // Bit 3: Start GCLK + DPC_STATUS_TMEM_BUSY = 0x010, // Bit 4: TMEM busy + DPC_STATUS_PIPE_BUSY = 0x020, // Bit 5: Pipe busy + DPC_STATUS_CMD_BUSY = 0x040, // Bit 6: CMD busy + DPC_STATUS_CBUF_READY = 0x080, // Bit 7: CBUF ready + DPC_STATUS_DMA_BUSY = 0x100, // Bit 8: DMA busy + DPC_STATUS_END_VALID = 0x200, // Bit 9: End valid + DPC_STATUS_START_VALID = 0x400, // Bit 10: Start valid +}; + +class DisplayControlReg +{ +protected: + DisplayControlReg(uint32_t * _DisplayProcessor); + +public: + uint32_t & DPC_START_REG; + uint32_t & DPC_END_REG; + uint32_t & DPC_CURRENT_REG; + uint32_t & DPC_STATUS_REG; + uint32_t & DPC_CLOCK_REG; + uint32_t & DPC_BUFBUSY_REG; + uint32_t & DPC_PIPEBUSY_REG; + uint32_t & DPC_TMEM_REG; + +private: + DisplayControlReg(); + DisplayControlReg(const DisplayControlReg&); + DisplayControlReg& operator=(const DisplayControlReg&); +}; + +class CN64System; +class CPlugins; +class CRegisters; + +class DisplayControlRegHandler : + public MemoryHandler, + private CDebugSettings, + private CLogging, + private DisplayControlReg, + private SPRegistersReg +{ +public: + DisplayControlRegHandler(CN64System & N64System, CPlugins * Plugins, CRegisters & Reg); + + bool Read32(uint32_t Address, uint32_t & Value); + bool Write32(uint32_t Address, uint32_t Value, uint32_t Mask); + +private: + DisplayControlRegHandler(); + DisplayControlRegHandler(const DisplayControlRegHandler &); + DisplayControlRegHandler & operator=(const DisplayControlRegHandler &); + + CN64System & m_System; + CPlugins * m_Plugins; + uint32_t & m_PC; +}; \ No newline at end of file diff --git a/Source/Project64-core/N64System/MemoryHandler/PeripheralInterfaceHandler.h b/Source/Project64-core/N64System/MemoryHandler/PeripheralInterfaceHandler.h index b59898b97..7b9243ac5 100644 --- a/Source/Project64-core/N64System/MemoryHandler/PeripheralInterfaceHandler.h +++ b/Source/Project64-core/N64System/MemoryHandler/PeripheralInterfaceHandler.h @@ -45,6 +45,7 @@ class PeripheralInterfaceHandler : { public: PeripheralInterfaceHandler(CMipsMemoryVM & MMU, CRegisters & Reg); + bool Read32(uint32_t Address, uint32_t & Value); bool Write32(uint32_t Address, uint32_t Value, uint32_t Mask); diff --git a/Source/Project64-core/N64System/MemoryHandler/SPRegistersHandler.cpp b/Source/Project64-core/N64System/MemoryHandler/SPRegistersHandler.cpp index 9ae617734..110955f4a 100644 --- a/Source/Project64-core/N64System/MemoryHandler/SPRegistersHandler.cpp +++ b/Source/Project64-core/N64System/MemoryHandler/SPRegistersHandler.cpp @@ -74,7 +74,7 @@ bool SPRegistersHandler::Read32(uint32_t Address, uint32_t & Value) bool SPRegistersHandler::Write32(uint32_t Address, uint32_t Value, uint32_t Mask) { - if (LogSPRegisters()) + if (GenerateLog() && LogSPRegisters()) { switch (Address & 0x1FFFFFFF) { diff --git a/Source/Project64-core/N64System/Mips/MemoryVirtualMem.cpp b/Source/Project64-core/N64System/Mips/MemoryVirtualMem.cpp index e1894ed3d..fa859c2e7 100755 --- a/Source/Project64-core/N64System/Mips/MemoryVirtualMem.cpp +++ b/Source/Project64-core/N64System/Mips/MemoryVirtualMem.cpp @@ -29,6 +29,7 @@ CMipsMemoryVM::CMipsMemoryVM(CN64System & System, CRegisters & Reg, bool SavesRe m_Reg(Reg), m_RDRAMRegistersHandler(Reg), m_RomMapped(false), + m_DPCommandRegistersHandler(System, System.GetPlugins(), Reg), m_PeripheralInterfaceHandler(*this, Reg), m_RDRAMInterfaceHandler(Reg), m_SPRegistersHandler(System, *this, Reg), @@ -642,7 +643,7 @@ bool CMipsMemoryVM::LW_NonMemory(uint32_t PAddr, uint32_t* Value) { case 0x03F00000: m_RDRAMRegistersHandler.Read32(PAddr, m_MemLookupValue.UW[0]); break; case 0x04000000: m_SPRegistersHandler.Read32(PAddr, m_MemLookupValue.UW[0]); break; - case 0x04100000: Load32DPCommand(); break; + case 0x04100000: m_DPCommandRegistersHandler.Read32(PAddr, m_MemLookupValue.UW[0]); break; case 0x04300000: Load32MIPSInterface(); break; case 0x04400000: Load32VideoInterface(); break; case 0x04500000: Load32AudioInterface(); break; @@ -762,7 +763,7 @@ bool CMipsMemoryVM::SW_NonMemory(uint32_t PAddr, uint32_t Value) m_SPRegistersHandler.Write32(PAddr, Value, 0xFFFFFFFF); } break; - case 0x04100000: Write32DPCommandRegisters(); break; + case 0x04100000: m_DPCommandRegistersHandler.Write32(PAddr, Value, 0xFFFFFFFF); break; case 0x04300000: Write32MIPSInterface(); break; case 0x04400000: Write32VideoInterface(); break; case 0x04500000: Write32AudioInterface(); break; @@ -1119,24 +1120,6 @@ void CMipsMemoryVM::ChangeMiIntrMask() } } -void CMipsMemoryVM::Load32DPCommand(void) -{ - switch (m_MemLookupAddress & 0x1FFFFFFF) - { - case 0x0410000C: m_MemLookupValue.UW[0] = g_Reg->DPC_STATUS_REG; break; - case 0x04100010: m_MemLookupValue.UW[0] = g_Reg->DPC_CLOCK_REG; break; - case 0x04100014: m_MemLookupValue.UW[0] = g_Reg->DPC_BUFBUSY_REG; break; - case 0x04100018: m_MemLookupValue.UW[0] = g_Reg->DPC_PIPEBUSY_REG; break; - case 0x0410001C: m_MemLookupValue.UW[0] = g_Reg->DPC_TMEM_REG; break; - default: - m_MemLookupValue.UW[0] = 0; - if (HaveDebugger()) - { - g_Notify->BreakPoint(__FILE__, __LINE__); - } - } -} - void CMipsMemoryVM::Load32MIPSInterface(void) { switch (m_MemLookupAddress & 0x1FFFFFFF) @@ -1383,73 +1366,6 @@ void CMipsMemoryVM::Load32Rom(void) } } -void CMipsMemoryVM::Write32DPCommandRegisters(void) -{ - switch ((m_MemLookupAddress & 0xFFFFFFF)) - { - case 0x04100000: - g_Reg->DPC_START_REG = m_MemLookupValue.UW[0]; - g_Reg->DPC_CURRENT_REG = m_MemLookupValue.UW[0]; - break; - case 0x04100004: - g_Reg->DPC_END_REG = m_MemLookupValue.UW[0]; - if (g_Plugins->Gfx()->ProcessRDPList) - { - g_Plugins->Gfx()->ProcessRDPList(); - } - break; - //case 0x04100008: g_Reg->DPC_CURRENT_REG = Value; break; - case 0x0410000C: - if ((m_MemLookupValue.UW[0] & DPC_CLR_XBUS_DMEM_DMA) != 0) - { - g_Reg->DPC_STATUS_REG &= ~DPC_STATUS_XBUS_DMEM_DMA; - } - if ((m_MemLookupValue.UW[0] & DPC_SET_XBUS_DMEM_DMA) != 0) - { - g_Reg->DPC_STATUS_REG |= DPC_STATUS_XBUS_DMEM_DMA; - } - if ((m_MemLookupValue.UW[0] & DPC_CLR_FREEZE) != 0) - { - g_Reg->DPC_STATUS_REG &= ~DPC_STATUS_FREEZE; - } - if ((m_MemLookupValue.UW[0] & DPC_SET_FREEZE) != 0) - { - g_Reg->DPC_STATUS_REG |= DPC_STATUS_FREEZE; - } - if ((m_MemLookupValue.UW[0] & DPC_CLR_FLUSH) != 0) - { - g_Reg->DPC_STATUS_REG &= ~DPC_STATUS_FLUSH; - } - if ((m_MemLookupValue.UW[0] & DPC_SET_FLUSH) != 0) - { - g_Reg->DPC_STATUS_REG |= DPC_STATUS_FLUSH; - } - if ((m_MemLookupValue.UW[0] & DPC_CLR_FREEZE) != 0) - { - if ((g_Reg->SP_STATUS_REG & SP_STATUS_HALT) == 0) - { - if ((g_Reg->SP_STATUS_REG & SP_STATUS_BROKE) == 0) - { - __except_try() - { - g_System->RunRSP(); - } - __except_catch() - { - g_Notify->BreakPoint(__FILE__, __LINE__); - } - } - } - } - break; - default: - if (HaveDebugger()) - { - g_Notify->BreakPoint(__FILE__, __LINE__); - } - } -} - void CMipsMemoryVM::Write32MIPSInterface(void) { switch ((m_MemLookupAddress & 0xFFFFFFF)) diff --git a/Source/Project64-core/N64System/Mips/MemoryVirtualMem.h b/Source/Project64-core/N64System/Mips/MemoryVirtualMem.h index 25b000b08..edfe7d1b5 100644 --- a/Source/Project64-core/N64System/Mips/MemoryVirtualMem.h +++ b/Source/Project64-core/N64System/Mips/MemoryVirtualMem.h @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -135,7 +136,6 @@ private: bool SH_NonMemory(uint32_t PAddr, uint16_t Value); bool SW_NonMemory(uint32_t PAddr, uint32_t Value); - static void Load32DPCommand(void); static void Load32MIPSInterface(void); static void Load32VideoInterface(void); static void Load32AudioInterface(void); @@ -147,7 +147,6 @@ private: static void Load32PifRam(void); static void Load32Rom(void); - static void Write32DPCommandRegisters(void); static void Write32MIPSInterface(void); static void Write32VideoInterface(void); static void Write32AudioInterface(void); @@ -182,6 +181,7 @@ private: static uint8_t * m_Reserve1, *m_Reserve2; CRegisters & m_Reg; + DisplayControlRegHandler m_DPCommandRegistersHandler; PeripheralInterfaceHandler m_PeripheralInterfaceHandler; RDRAMInterfaceHandler m_RDRAMInterfaceHandler; RDRAMRegistersHandler m_RDRAMRegistersHandler; diff --git a/Source/Project64-core/N64System/Mips/Register.h b/Source/Project64-core/N64System/Mips/Register.h index 321abc479..a073db087 100644 --- a/Source/Project64-core/N64System/Mips/Register.h +++ b/Source/Project64-core/N64System/Mips/Register.h @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -216,54 +217,6 @@ private: Video_InterfaceReg& operator=(const Video_InterfaceReg&); }; -// Display processor control registers -class DisplayControlReg -{ -protected: - DisplayControlReg (uint32_t * _DisplayProcessor); - -public: - uint32_t & DPC_START_REG; - uint32_t & DPC_END_REG; - uint32_t & DPC_CURRENT_REG; - uint32_t & DPC_STATUS_REG; - uint32_t & DPC_CLOCK_REG; - uint32_t & DPC_BUFBUSY_REG; - uint32_t & DPC_PIPEBUSY_REG; - uint32_t & DPC_TMEM_REG; - -private: - DisplayControlReg(); - DisplayControlReg(const DisplayControlReg&); - DisplayControlReg& operator=(const DisplayControlReg&); -}; - -enum -{ - DPC_CLR_XBUS_DMEM_DMA = 0x0001, // Bit 0: Clear xbus_dmem_dma - DPC_SET_XBUS_DMEM_DMA = 0x0002, // Bit 1: Set xbus_dmem_dma - DPC_CLR_FREEZE = 0x0004, // Bit 2: Clear freeze - DPC_SET_FREEZE = 0x0008, // Bit 3: Set freeze - DPC_CLR_FLUSH = 0x0010, // Bit 4: Clear flush - DPC_SET_FLUSH = 0x0020, // Bit 5: Set flush - DPC_CLR_TMEM_CTR = 0x0040, // Bit 6: Clear TMEM CTR - DPC_CLR_PIPE_CTR = 0x0080, // Bit 7: Clear pipe CTR - DPC_CLR_CMD_CTR = 0x0100, // Bit 8: Clear CMD CTR - DPC_CLR_CLOCK_CTR = 0x0200, // Bit 9: Clear clock CTR - - DPC_STATUS_XBUS_DMEM_DMA = 0x001, // Bit 0: xbus_dmem_dma - DPC_STATUS_FREEZE = 0x002, // Bit 1: Freeze - DPC_STATUS_FLUSH = 0x004, // Bit 2: Flush - DPC_STATUS_START_GCLK = 0x008, // Bit 3: Start GCLK - DPC_STATUS_TMEM_BUSY = 0x010, // Bit 4: TMEM busy - DPC_STATUS_PIPE_BUSY = 0x020, // Bit 5: Pipe busy - DPC_STATUS_CMD_BUSY = 0x040, // Bit 6: CMD busy - DPC_STATUS_CBUF_READY = 0x080, // Bit 7: CBUF ready - DPC_STATUS_DMA_BUSY = 0x100, // Bit 8: DMA busy - DPC_STATUS_END_VALID = 0x200, // Bit 9: End valid - DPC_STATUS_START_VALID = 0x400, // Bit 10: Start valid -}; - // Audio interface registers class AudioInterfaceReg { diff --git a/Source/Project64-core/Project64-core.vcxproj b/Source/Project64-core/Project64-core.vcxproj index 13ce58597..957c94312 100644 --- a/Source/Project64-core/Project64-core.vcxproj +++ b/Source/Project64-core/Project64-core.vcxproj @@ -53,6 +53,7 @@ + @@ -152,6 +153,7 @@ + diff --git a/Source/Project64-core/Project64-core.vcxproj.filters b/Source/Project64-core/Project64-core.vcxproj.filters index 21b6e19ab..244f67ffd 100644 --- a/Source/Project64-core/Project64-core.vcxproj.filters +++ b/Source/Project64-core/Project64-core.vcxproj.filters @@ -369,6 +369,9 @@ Source Files\N64 System\MemoryHandler + + Source Files\N64 System\MemoryHandler + @@ -704,6 +707,9 @@ Header Files\N64 System\MemoryHandler + + Header Files\N64 System\MemoryHandler +