Core: Improve R4300iOp::COP1_D_CMP
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@ -2841,6 +2841,7 @@ void R4300iOp::COP1_D_CMP()
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{
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return;
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}
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_FPCR[31] &= ~0x0003F000;
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MIPS_DWORD Temp0, Temp1;
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Temp0.DW = *(int64_t *)_FPR_D[m_Opcode.fs];
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@ -2852,7 +2853,20 @@ void R4300iOp::COP1_D_CMP()
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less = false;
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equal = false;
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unorded = true;
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if ((m_Opcode.funct & 8) != 0)
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bool QuietNan = false;
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if ((*(uint64_t *)_FPR_D[m_Opcode.fs] >= 0x7FF8000000000000 && *(uint64_t *)_FPR_D[m_Opcode.fs] <= 0x7FFFFFFFFFFFFFFF) ||
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(*(uint64_t *)_FPR_D[m_Opcode.fs] >= 0xFFF8000000000000 && *(uint64_t *)_FPR_D[m_Opcode.fs] <= 0xFFFFFFFFFFFFFFFF))
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{
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QuietNan = true;
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}
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else if ((*(uint64_t *)_FPR_D[m_Opcode.ft] >= 0x7FF8000000000000 && *(uint64_t *)_FPR_D[m_Opcode.ft] <= 0x7FFFFFFFFFFFFFFF) ||
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(*(uint64_t *)_FPR_D[m_Opcode.ft] >= 0xFFF8000000000000 && *(uint64_t *)_FPR_D[m_Opcode.ft] <= 0xFFFFFFFFFFFFFFFF))
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{
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QuietNan = true;
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}
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if ((m_Opcode.funct & 8) != 0 || QuietNan)
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{
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FPStatusReg & StatusReg = (FPStatusReg &)_FPCR[31];
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StatusReg.Cause.InvalidOperation = 1;
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