{Project64] Cleanup MemoryVirtualMem.cpp
This commit is contained in:
zilmar
parent
abcfe60a51
commit
d8a4b4810b
|
|
@ -24,22 +24,22 @@ uint8_t * CMipsMemoryVM::m_Reserve2 = NULL;
|
|||
|
||||
CMipsMemoryVM::CMipsMemoryVM(CMipsMemory_CallBack * CallBack, bool SavesReadOnly) :
|
||||
|
||||
CPifRam(SavesReadOnly),
|
||||
CFlashram(SavesReadOnly),
|
||||
CSram(SavesReadOnly),
|
||||
CDMA(*this, *this),
|
||||
m_CBClass(CallBack),
|
||||
m_RomMapped(false),
|
||||
m_Rom(NULL),
|
||||
m_RomSize(0),
|
||||
m_RomWrittenTo(false),
|
||||
m_RomWroteValue(0),
|
||||
m_HalfLine(0),
|
||||
m_HalfLineCheck(false),
|
||||
m_FieldSerration(0),
|
||||
m_TempValue(0),
|
||||
m_TLB_ReadMap(NULL),
|
||||
m_TLB_WriteMap(NULL)
|
||||
CPifRam(SavesReadOnly),
|
||||
CFlashram(SavesReadOnly),
|
||||
CSram(SavesReadOnly),
|
||||
CDMA(*this, *this),
|
||||
m_CBClass(CallBack),
|
||||
m_RomMapped(false),
|
||||
m_Rom(NULL),
|
||||
m_RomSize(0),
|
||||
m_RomWrittenTo(false),
|
||||
m_RomWroteValue(0),
|
||||
m_HalfLine(0),
|
||||
m_HalfLineCheck(false),
|
||||
m_FieldSerration(0),
|
||||
m_TempValue(0),
|
||||
m_TLB_ReadMap(NULL),
|
||||
m_TLB_WriteMap(NULL)
|
||||
{
|
||||
g_Settings->RegisterChangeCB(Game_RDRamSize, this, (CSettings::SettingChangedFunc)RdramChanged);
|
||||
m_RDRAM = NULL;
|
||||
|
|
@ -777,17 +777,17 @@ void CMipsMemoryVM::Compile_LW(x86Reg Reg, uint32_t VAddr)
|
|||
}
|
||||
break;
|
||||
case 0x04100000:
|
||||
{
|
||||
static uint32_t TempValue = 0;
|
||||
BeforeCallDirect(m_RegWorkingSet);
|
||||
PushImm32("TempValue", (uint32_t)&TempValue);
|
||||
PushImm32(PAddr);
|
||||
MoveConstToX86reg((ULONG)((CMipsMemoryVM *)this), x86_ECX);
|
||||
Call_Direct(AddressOf(&CMipsMemoryVM::LW_NonMemory), "CMipsMemoryVM::LW_NonMemory");
|
||||
AfterCallDirect(m_RegWorkingSet);
|
||||
MoveVariableToX86reg(&TempValue, "TempValue", Reg);
|
||||
}
|
||||
break;
|
||||
{
|
||||
static uint32_t TempValue = 0;
|
||||
BeforeCallDirect(m_RegWorkingSet);
|
||||
PushImm32("TempValue", (uint32_t)&TempValue);
|
||||
PushImm32(PAddr);
|
||||
MoveConstToX86reg((ULONG)((CMipsMemoryVM *)this), x86_ECX);
|
||||
Call_Direct(AddressOf(&CMipsMemoryVM::LW_NonMemory), "CMipsMemoryVM::LW_NonMemory");
|
||||
AfterCallDirect(m_RegWorkingSet);
|
||||
MoveVariableToX86reg(&TempValue, "TempValue", Reg);
|
||||
}
|
||||
break;
|
||||
case 0x04300000:
|
||||
switch (PAddr)
|
||||
{
|
||||
|
|
@ -1227,19 +1227,19 @@ void CMipsMemoryVM::Compile_SW_Const(uint32_t Value, uint32_t VAddr)
|
|||
AfterCallDirect(m_RegWorkingSet);
|
||||
break;
|
||||
case 0x04040010:
|
||||
{
|
||||
m_RegWorkingSet.SetBlockCycleCount(m_RegWorkingSet.GetBlockCycleCount() - g_System->CountPerOp());
|
||||
UpdateCounters(m_RegWorkingSet, false, true);
|
||||
m_RegWorkingSet.SetBlockCycleCount(m_RegWorkingSet.GetBlockCycleCount() + g_System->CountPerOp());
|
||||
{
|
||||
m_RegWorkingSet.SetBlockCycleCount(m_RegWorkingSet.GetBlockCycleCount() - g_System->CountPerOp());
|
||||
UpdateCounters(m_RegWorkingSet, false, true);
|
||||
m_RegWorkingSet.SetBlockCycleCount(m_RegWorkingSet.GetBlockCycleCount() + g_System->CountPerOp());
|
||||
|
||||
BeforeCallDirect(m_RegWorkingSet);
|
||||
PushImm32(Value);
|
||||
PushImm32(PAddr);
|
||||
MoveConstToX86reg((ULONG)((CMipsMemoryVM *)this), x86_ECX);
|
||||
Call_Direct(AddressOf(&CMipsMemoryVM::SW_NonMemory), "CMipsMemoryVM::SW_NonMemory");
|
||||
AfterCallDirect(m_RegWorkingSet);
|
||||
}
|
||||
break;
|
||||
BeforeCallDirect(m_RegWorkingSet);
|
||||
PushImm32(Value);
|
||||
PushImm32(PAddr);
|
||||
MoveConstToX86reg((ULONG)((CMipsMemoryVM *)this), x86_ECX);
|
||||
Call_Direct(AddressOf(&CMipsMemoryVM::SW_NonMemory), "CMipsMemoryVM::SW_NonMemory");
|
||||
AfterCallDirect(m_RegWorkingSet);
|
||||
}
|
||||
break;
|
||||
case 0x0404001C: MoveConstToVariable(0, &g_Reg->SP_SEMAPHORE_REG, "SP_SEMAPHORE_REG"); break;
|
||||
case 0x04080000: MoveConstToVariable(Value & 0xFFC, &g_Reg->SP_PC_REG, "SP_PC_REG"); break;
|
||||
default:
|
||||
|
|
@ -1271,113 +1271,113 @@ void CMipsMemoryVM::Compile_SW_Const(uint32_t Value, uint32_t VAddr)
|
|||
switch (PAddr)
|
||||
{
|
||||
case 0x04300000:
|
||||
{
|
||||
uint32_t ModValue;
|
||||
ModValue = 0x7F;
|
||||
if ((Value & MI_CLR_INIT) != 0)
|
||||
{
|
||||
uint32_t ModValue;
|
||||
ModValue = 0x7F;
|
||||
if ((Value & MI_CLR_INIT) != 0)
|
||||
{
|
||||
ModValue |= MI_MODE_INIT;
|
||||
}
|
||||
if ((Value & MI_CLR_EBUS) != 0)
|
||||
{
|
||||
ModValue |= MI_MODE_EBUS;
|
||||
}
|
||||
if ((Value & MI_CLR_RDRAM) != 0)
|
||||
{
|
||||
ModValue |= MI_MODE_RDRAM;
|
||||
}
|
||||
if (ModValue != 0)
|
||||
{
|
||||
AndConstToVariable(~ModValue, &g_Reg->MI_MODE_REG, "MI_MODE_REG");
|
||||
}
|
||||
|
||||
ModValue = (Value & 0x7F);
|
||||
if ((Value & MI_SET_INIT) != 0)
|
||||
{
|
||||
ModValue |= MI_MODE_INIT;
|
||||
}
|
||||
if ((Value & MI_SET_EBUS) != 0)
|
||||
{
|
||||
ModValue |= MI_MODE_EBUS;
|
||||
}
|
||||
if ((Value & MI_SET_RDRAM) != 0)
|
||||
{
|
||||
ModValue |= MI_MODE_RDRAM;
|
||||
}
|
||||
if (ModValue != 0) {
|
||||
OrConstToVariable(ModValue, &g_Reg->MI_MODE_REG, "MI_MODE_REG");
|
||||
}
|
||||
if ((Value & MI_CLR_DP_INTR) != 0)
|
||||
{
|
||||
AndConstToVariable((uint32_t)~MI_INTR_DP, &g_Reg->MI_INTR_REG, "MI_INTR_REG");
|
||||
AndConstToVariable((uint32_t)~MI_INTR_DP, &g_Reg->m_GfxIntrReg, "m_GfxIntrReg");
|
||||
}
|
||||
ModValue |= MI_MODE_INIT;
|
||||
}
|
||||
break;
|
||||
if ((Value & MI_CLR_EBUS) != 0)
|
||||
{
|
||||
ModValue |= MI_MODE_EBUS;
|
||||
}
|
||||
if ((Value & MI_CLR_RDRAM) != 0)
|
||||
{
|
||||
ModValue |= MI_MODE_RDRAM;
|
||||
}
|
||||
if (ModValue != 0)
|
||||
{
|
||||
AndConstToVariable(~ModValue, &g_Reg->MI_MODE_REG, "MI_MODE_REG");
|
||||
}
|
||||
|
||||
ModValue = (Value & 0x7F);
|
||||
if ((Value & MI_SET_INIT) != 0)
|
||||
{
|
||||
ModValue |= MI_MODE_INIT;
|
||||
}
|
||||
if ((Value & MI_SET_EBUS) != 0)
|
||||
{
|
||||
ModValue |= MI_MODE_EBUS;
|
||||
}
|
||||
if ((Value & MI_SET_RDRAM) != 0)
|
||||
{
|
||||
ModValue |= MI_MODE_RDRAM;
|
||||
}
|
||||
if (ModValue != 0) {
|
||||
OrConstToVariable(ModValue, &g_Reg->MI_MODE_REG, "MI_MODE_REG");
|
||||
}
|
||||
if ((Value & MI_CLR_DP_INTR) != 0)
|
||||
{
|
||||
AndConstToVariable((uint32_t)~MI_INTR_DP, &g_Reg->MI_INTR_REG, "MI_INTR_REG");
|
||||
AndConstToVariable((uint32_t)~MI_INTR_DP, &g_Reg->m_GfxIntrReg, "m_GfxIntrReg");
|
||||
}
|
||||
}
|
||||
break;
|
||||
case 0x0430000C:
|
||||
{
|
||||
uint32_t ModValue;
|
||||
ModValue = 0;
|
||||
if ((Value & MI_INTR_MASK_CLR_SP) != 0)
|
||||
{
|
||||
uint32_t ModValue;
|
||||
ModValue = 0;
|
||||
if ((Value & MI_INTR_MASK_CLR_SP) != 0)
|
||||
{
|
||||
ModValue |= MI_INTR_MASK_SP;
|
||||
}
|
||||
if ((Value & MI_INTR_MASK_CLR_SI) != 0)
|
||||
{
|
||||
ModValue |= MI_INTR_MASK_SI;
|
||||
}
|
||||
if ((Value & MI_INTR_MASK_CLR_AI) != 0)
|
||||
{
|
||||
ModValue |= MI_INTR_MASK_AI;
|
||||
}
|
||||
if ((Value & MI_INTR_MASK_CLR_VI) != 0)
|
||||
{
|
||||
ModValue |= MI_INTR_MASK_VI;
|
||||
}
|
||||
if ((Value & MI_INTR_MASK_CLR_PI) != 0)
|
||||
{
|
||||
ModValue |= MI_INTR_MASK_PI;
|
||||
}
|
||||
if ((Value & MI_INTR_MASK_CLR_DP) != 0)
|
||||
{
|
||||
ModValue |= MI_INTR_MASK_DP;
|
||||
}
|
||||
if (ModValue != 0)
|
||||
{
|
||||
AndConstToVariable(~ModValue, &g_Reg->MI_INTR_MASK_REG, "MI_INTR_MASK_REG");
|
||||
}
|
||||
|
||||
ModValue = 0;
|
||||
if ((Value & MI_INTR_MASK_SET_SP) != 0)
|
||||
{
|
||||
ModValue |= MI_INTR_MASK_SP;
|
||||
}
|
||||
if ((Value & MI_INTR_MASK_SET_SI) != 0)
|
||||
{
|
||||
ModValue |= MI_INTR_MASK_SI;
|
||||
}
|
||||
if ((Value & MI_INTR_MASK_SET_AI) != 0)
|
||||
{
|
||||
ModValue |= MI_INTR_MASK_AI;
|
||||
}
|
||||
if ((Value & MI_INTR_MASK_SET_VI) != 0)
|
||||
{
|
||||
ModValue |= MI_INTR_MASK_VI;
|
||||
}
|
||||
if ((Value & MI_INTR_MASK_SET_PI) != 0)
|
||||
{
|
||||
ModValue |= MI_INTR_MASK_PI;
|
||||
}
|
||||
if ((Value & MI_INTR_MASK_SET_DP) != 0)
|
||||
{
|
||||
ModValue |= MI_INTR_MASK_DP;
|
||||
}
|
||||
if (ModValue != 0)
|
||||
{
|
||||
OrConstToVariable(ModValue, &g_Reg->MI_INTR_MASK_REG, "MI_INTR_MASK_REG");
|
||||
}
|
||||
ModValue |= MI_INTR_MASK_SP;
|
||||
}
|
||||
break;
|
||||
if ((Value & MI_INTR_MASK_CLR_SI) != 0)
|
||||
{
|
||||
ModValue |= MI_INTR_MASK_SI;
|
||||
}
|
||||
if ((Value & MI_INTR_MASK_CLR_AI) != 0)
|
||||
{
|
||||
ModValue |= MI_INTR_MASK_AI;
|
||||
}
|
||||
if ((Value & MI_INTR_MASK_CLR_VI) != 0)
|
||||
{
|
||||
ModValue |= MI_INTR_MASK_VI;
|
||||
}
|
||||
if ((Value & MI_INTR_MASK_CLR_PI) != 0)
|
||||
{
|
||||
ModValue |= MI_INTR_MASK_PI;
|
||||
}
|
||||
if ((Value & MI_INTR_MASK_CLR_DP) != 0)
|
||||
{
|
||||
ModValue |= MI_INTR_MASK_DP;
|
||||
}
|
||||
if (ModValue != 0)
|
||||
{
|
||||
AndConstToVariable(~ModValue, &g_Reg->MI_INTR_MASK_REG, "MI_INTR_MASK_REG");
|
||||
}
|
||||
|
||||
ModValue = 0;
|
||||
if ((Value & MI_INTR_MASK_SET_SP) != 0)
|
||||
{
|
||||
ModValue |= MI_INTR_MASK_SP;
|
||||
}
|
||||
if ((Value & MI_INTR_MASK_SET_SI) != 0)
|
||||
{
|
||||
ModValue |= MI_INTR_MASK_SI;
|
||||
}
|
||||
if ((Value & MI_INTR_MASK_SET_AI) != 0)
|
||||
{
|
||||
ModValue |= MI_INTR_MASK_AI;
|
||||
}
|
||||
if ((Value & MI_INTR_MASK_SET_VI) != 0)
|
||||
{
|
||||
ModValue |= MI_INTR_MASK_VI;
|
||||
}
|
||||
if ((Value & MI_INTR_MASK_SET_PI) != 0)
|
||||
{
|
||||
ModValue |= MI_INTR_MASK_PI;
|
||||
}
|
||||
if ((Value & MI_INTR_MASK_SET_DP) != 0)
|
||||
{
|
||||
ModValue |= MI_INTR_MASK_DP;
|
||||
}
|
||||
if (ModValue != 0)
|
||||
{
|
||||
OrConstToVariable(ModValue, &g_Reg->MI_INTR_MASK_REG, "MI_INTR_MASK_REG");
|
||||
}
|
||||
}
|
||||
break;
|
||||
default:
|
||||
if (g_Settings->LoadBool(Debugger_ShowUnhandledMemory))
|
||||
{
|
||||
|
|
@ -1580,19 +1580,19 @@ void CMipsMemoryVM::Compile_SW_Const(uint32_t Value, uint32_t VAddr)
|
|||
}
|
||||
break;
|
||||
case 0x1fc00000:
|
||||
{
|
||||
m_RegWorkingSet.SetBlockCycleCount(m_RegWorkingSet.GetBlockCycleCount() - g_System->CountPerOp());
|
||||
UpdateCounters(m_RegWorkingSet, false, true);
|
||||
m_RegWorkingSet.SetBlockCycleCount(m_RegWorkingSet.GetBlockCycleCount() + g_System->CountPerOp());
|
||||
{
|
||||
m_RegWorkingSet.SetBlockCycleCount(m_RegWorkingSet.GetBlockCycleCount() - g_System->CountPerOp());
|
||||
UpdateCounters(m_RegWorkingSet, false, true);
|
||||
m_RegWorkingSet.SetBlockCycleCount(m_RegWorkingSet.GetBlockCycleCount() + g_System->CountPerOp());
|
||||
|
||||
BeforeCallDirect(m_RegWorkingSet);
|
||||
PushImm32(Value);
|
||||
PushImm32(PAddr);
|
||||
MoveConstToX86reg((ULONG)((CMipsMemoryVM *)this), x86_ECX);
|
||||
Call_Direct(AddressOf(&CMipsMemoryVM::SW_NonMemory), "CMipsMemoryVM::SW_NonMemory");
|
||||
AfterCallDirect(m_RegWorkingSet);
|
||||
}
|
||||
break;
|
||||
BeforeCallDirect(m_RegWorkingSet);
|
||||
PushImm32(Value);
|
||||
PushImm32(PAddr);
|
||||
MoveConstToX86reg((ULONG)((CMipsMemoryVM *)this), x86_ECX);
|
||||
Call_Direct(AddressOf(&CMipsMemoryVM::SW_NonMemory), "CMipsMemoryVM::SW_NonMemory");
|
||||
AfterCallDirect(m_RegWorkingSet);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
if (g_Settings->LoadBool(Debugger_ShowUnhandledMemory))
|
||||
{
|
||||
|
|
|
|||
|
|
@ -66,34 +66,34 @@ public:
|
|||
static void ReserveMemory();
|
||||
static void FreeReservedMemory();
|
||||
|
||||
bool Initialize ();
|
||||
void Reset ( bool EraseMemory );
|
||||
bool Initialize();
|
||||
void Reset(bool EraseMemory);
|
||||
|
||||
uint8_t * Rdram ();
|
||||
uint32_t RdramSize ();
|
||||
uint8_t * Dmem ();
|
||||
uint8_t * Imem ();
|
||||
uint8_t * PifRam ();
|
||||
uint8_t * Rdram();
|
||||
uint32_t RdramSize();
|
||||
uint8_t * Dmem();
|
||||
uint8_t * Imem();
|
||||
uint8_t * PifRam();
|
||||
|
||||
bool LB_VAddr ( uint32_t VAddr, uint8_t & Value );
|
||||
bool LH_VAddr ( uint32_t VAddr, uint16_t & Value );
|
||||
bool LW_VAddr ( uint32_t VAddr, uint32_t & Value );
|
||||
bool LD_VAddr ( uint32_t VAddr, uint64_t & Value );
|
||||
bool LB_VAddr(uint32_t VAddr, uint8_t & Value);
|
||||
bool LH_VAddr(uint32_t VAddr, uint16_t & Value);
|
||||
bool LW_VAddr(uint32_t VAddr, uint32_t & Value);
|
||||
bool LD_VAddr(uint32_t VAddr, uint64_t & Value);
|
||||
|
||||
bool LB_PAddr ( uint32_t PAddr, uint8_t & Value );
|
||||
bool LH_PAddr ( uint32_t PAddr, uint16_t & Value );
|
||||
bool LW_PAddr ( uint32_t PAddr, uint32_t & Value );
|
||||
bool LD_PAddr ( uint32_t PAddr, uint64_t & Value );
|
||||
bool LB_PAddr(uint32_t PAddr, uint8_t & Value);
|
||||
bool LH_PAddr(uint32_t PAddr, uint16_t & Value);
|
||||
bool LW_PAddr(uint32_t PAddr, uint32_t & Value);
|
||||
bool LD_PAddr(uint32_t PAddr, uint64_t & Value);
|
||||
|
||||
bool SB_VAddr ( uint32_t VAddr, uint8_t Value );
|
||||
bool SH_VAddr ( uint32_t VAddr, uint16_t Value );
|
||||
bool SW_VAddr ( uint32_t VAddr, uint32_t Value );
|
||||
bool SD_VAddr ( uint32_t VAddr, uint64_t Value );
|
||||
bool SB_VAddr(uint32_t VAddr, uint8_t Value);
|
||||
bool SH_VAddr(uint32_t VAddr, uint16_t Value);
|
||||
bool SW_VAddr(uint32_t VAddr, uint32_t Value);
|
||||
bool SD_VAddr(uint32_t VAddr, uint64_t Value);
|
||||
|
||||
bool SB_PAddr ( uint32_t PAddr, uint8_t Value );
|
||||
bool SH_PAddr ( uint32_t PAddr, uint16_t Value );
|
||||
bool SW_PAddr ( uint32_t PAddr, uint32_t Value );
|
||||
bool SD_PAddr ( uint32_t PAddr, uint64_t Value );
|
||||
bool SB_PAddr(uint32_t PAddr, uint8_t Value);
|
||||
bool SH_PAddr(uint32_t PAddr, uint16_t Value);
|
||||
bool SW_PAddr(uint32_t PAddr, uint32_t Value);
|
||||
bool SD_PAddr(uint32_t PAddr, uint64_t Value);
|
||||
|
||||
int32_t MemoryFilter(uint32_t dwExptCode, void * lpExceptionPointer);
|
||||
void UpdateFieldSerration(uint32_t interlaced);
|
||||
|
|
@ -131,17 +131,17 @@ public:
|
|||
void Compile_SWC1();
|
||||
void Compile_SDC1();
|
||||
|
||||
void ResetMemoryStack ( CRegInfo& RegInfo );
|
||||
void Compile_LB ( CX86Ops::x86Reg Reg, uint32_t Addr, bool SignExtend );
|
||||
void Compile_LH ( CX86Ops::x86Reg Reg, uint32_t Addr, bool SignExtend );
|
||||
void Compile_LW ( CX86Ops::x86Reg Reg, uint32_t Addr );
|
||||
void Compile_SB_Const ( uint8_t Value, uint32_t Addr );
|
||||
void Compile_SB_Register ( CX86Ops::x86Reg Reg, uint32_t Addr );
|
||||
void Compile_SH_Const ( uint16_t Value, uint32_t Addr );
|
||||
void Compile_SH_Register ( CX86Ops::x86Reg Reg, uint32_t Addr );
|
||||
void Compile_SW_Const ( uint32_t Value, uint32_t Addr );
|
||||
void ResetMemoryStack(CRegInfo& RegInfo);
|
||||
void Compile_LB(CX86Ops::x86Reg Reg, uint32_t Addr, bool SignExtend);
|
||||
void Compile_LH(CX86Ops::x86Reg Reg, uint32_t Addr, bool SignExtend);
|
||||
void Compile_LW(CX86Ops::x86Reg Reg, uint32_t Addr);
|
||||
void Compile_SB_Const(uint8_t Value, uint32_t Addr);
|
||||
void Compile_SB_Register(CX86Ops::x86Reg Reg, uint32_t Addr);
|
||||
void Compile_SH_Const(uint16_t Value, uint32_t Addr);
|
||||
void Compile_SH_Register(CX86Ops::x86Reg Reg, uint32_t Addr);
|
||||
void Compile_SW_Const(uint32_t Value, uint32_t Addr);
|
||||
|
||||
void Compile_SW_Register ( CX86Ops::x86Reg Reg, uint32_t Addr );
|
||||
void Compile_SW_Register(CX86Ops::x86Reg Reg, uint32_t Addr);
|
||||
|
||||
//Functions for TLB notification
|
||||
void TLB_Mapped(uint32_t VAddr, uint32_t Len, uint32_t PAddr, bool bReadOnly);
|
||||
|
|
@ -160,28 +160,28 @@ private:
|
|||
CMipsMemoryVM(const CMipsMemoryVM&); // Disable copy constructor
|
||||
CMipsMemoryVM& operator=(const CMipsMemoryVM&); // Disable assignment
|
||||
|
||||
void Compile_LW ( bool ResultSigned, bool bRecordLLbit );
|
||||
void Compile_SW ( bool bCheckLLbit );
|
||||
void Compile_LW(bool ResultSigned, bool bRecordLLbit);
|
||||
void Compile_SW(bool bCheckLLbit);
|
||||
|
||||
static void RdramChanged ( CMipsMemoryVM * _this );
|
||||
static void ChangeSpStatus ();
|
||||
static void RdramChanged(CMipsMemoryVM * _this);
|
||||
static void ChangeSpStatus();
|
||||
static void ChangeMiIntrMask();
|
||||
|
||||
bool LB_NonMemory ( uint32_t PAddr, uint32_t * Value, bool SignExtend );
|
||||
bool LH_NonMemory ( uint32_t PAddr, uint32_t * Value, bool SignExtend );
|
||||
bool LW_NonMemory ( uint32_t PAddr, uint32_t * Value );
|
||||
bool LB_NonMemory(uint32_t PAddr, uint32_t * Value, bool SignExtend);
|
||||
bool LH_NonMemory(uint32_t PAddr, uint32_t * Value, bool SignExtend);
|
||||
bool LW_NonMemory(uint32_t PAddr, uint32_t * Value);
|
||||
|
||||
bool SB_NonMemory ( uint32_t PAddr, uint8_t Value );
|
||||
bool SH_NonMemory ( uint32_t PAddr, uint16_t Value );
|
||||
bool SW_NonMemory ( uint32_t PAddr, uint32_t Value );
|
||||
bool SB_NonMemory(uint32_t PAddr, uint8_t Value);
|
||||
bool SH_NonMemory(uint32_t PAddr, uint16_t Value);
|
||||
bool SW_NonMemory(uint32_t PAddr, uint32_t Value);
|
||||
|
||||
void Compile_StoreInstructClean (x86Reg AddressReg, int32_t Length );
|
||||
void Compile_StoreInstructClean(x86Reg AddressReg, int32_t Length);
|
||||
|
||||
CMipsMemory_CallBack * const m_CBClass;
|
||||
|
||||
//Memory Locations
|
||||
static uint8_t * m_Reserve1, * m_Reserve2;
|
||||
uint8_t * m_RDRAM, * m_DMEM, * m_IMEM;
|
||||
static uint8_t * m_Reserve1, *m_Reserve2;
|
||||
uint8_t * m_RDRAM, *m_DMEM, *m_IMEM;
|
||||
uint32_t m_AllocatedRdramSize;
|
||||
|
||||
//Rom Information
|
||||
|
|
|
|||
Loading…
Reference in New Issue