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Merge pull request #2025 from vgturtle127/beautification-10 

Beautification 10 - Source\RSP directory
This commit is contained in:
zilmar 2021-03-23 12:52:08 +10:30 committed by GitHub
parent f2afda0e5e 3f630eaab0
commit d8503d659a
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
27 changed files with 760 additions and 768 deletions
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72
Source/RSP/Cpu.c
View File

@ -78,22 +78,22 @@ void Build_RSP ( void )
EleSpec[13].DW = 0;
EleSpec[14].DW = 0;
EleSpec[15].DW = 0;
EleSpec[16].DW = 0x0001020304050607; /* None */
EleSpec[17].DW = 0x0001020304050607; /* None */
EleSpec[18].DW = 0x0000020204040606; /* 0q */
EleSpec[19].DW = 0x0101030305050707; /* 1q */
EleSpec[20].DW = 0x0000000004040404; /* 0h */
EleSpec[21].DW = 0x0101010105050505; /* 1h */
EleSpec[22].DW = 0x0202020206060606; /* 2h */
EleSpec[23].DW = 0x0303030307070707; /* 3h */
EleSpec[24].DW = 0x0000000000000000; /* 0 */
EleSpec[25].DW = 0x0101010101010101; /* 1 */
EleSpec[26].DW = 0x0202020202020202; /* 2 */
EleSpec[27].DW = 0x0303030303030303; /* 3 */
EleSpec[28].DW = 0x0404040404040404; /* 4 */
EleSpec[29].DW = 0x0505050505050505; /* 5 */
EleSpec[30].DW = 0x0606060606060606; /* 6 */
EleSpec[31].DW = 0x0707070707070707; /* 7 */
EleSpec[16].DW = 0x0001020304050607; // None
EleSpec[17].DW = 0x0001020304050607; // None
EleSpec[18].DW = 0x0000020204040606; // 0q
EleSpec[19].DW = 0x0101030305050707; // 1q
EleSpec[20].DW = 0x0000000004040404; // 0h
EleSpec[21].DW = 0x0101010105050505; // 1h
EleSpec[22].DW = 0x0202020206060606; // 2h
EleSpec[23].DW = 0x0303030307070707; // 3h
EleSpec[24].DW = 0x0000000000000000; // 0
EleSpec[25].DW = 0x0101010101010101; // 1
EleSpec[26].DW = 0x0202020202020202; // 2
EleSpec[27].DW = 0x0303030303030303; // 3
EleSpec[28].DW = 0x0404040404040404; // 4
EleSpec[29].DW = 0x0505050505050505; // 5
EleSpec[30].DW = 0x0606060606060606; // 6
EleSpec[31].DW = 0x0707070707070707; // 7
Indx[ 0].DW = 0;
Indx[ 1].DW = 0;
@ -112,22 +112,22 @@ void Build_RSP ( void )
Indx[14].DW = 0;
Indx[15].DW = 0;
Indx[16].DW = 0x0001020304050607; /* None */
Indx[17].DW = 0x0001020304050607; /* None */
Indx[18].DW = 0x0103050700020406; /* 0q */
Indx[19].DW = 0x0002040601030507; /* 1q */
Indx[20].DW = 0x0102030506070004; /* 0h */
Indx[21].DW = 0x0002030406070105; /* 1h */
Indx[22].DW = 0x0001030405070206; /* 2h */
Indx[23].DW = 0x0001020405060307; /* 3h */
Indx[24].DW = 0x0102030405060700; /* 0 */
Indx[25].DW = 0x0002030405060701; /* 1 */
Indx[26].DW = 0x0001030405060702; /* 2 */
Indx[27].DW = 0x0001020405060703; /* 3 */
Indx[28].DW = 0x0001020305060704; /* 4 */
Indx[29].DW = 0x0001020304060705; /* 5 */
Indx[30].DW = 0x0001020304050706; /* 6 */
Indx[31].DW = 0x0001020304050607; /* 7 */
Indx[16].DW = 0x0001020304050607; // None
Indx[17].DW = 0x0001020304050607; // None
Indx[18].DW = 0x0103050700020406; // 0q
Indx[19].DW = 0x0002040601030507; // 1q
Indx[20].DW = 0x0102030506070004; // 0h
Indx[21].DW = 0x0002030406070105; // 1h
Indx[22].DW = 0x0001030405070206; // 2h
Indx[23].DW = 0x0001020405060307; // 3h
Indx[24].DW = 0x0102030405060700; // 0
Indx[25].DW = 0x0002030405060701; // 1
Indx[26].DW = 0x0001030405060702; // 2
Indx[27].DW = 0x0001020405060703; // 3
Indx[28].DW = 0x0001020305060704; // 4
Indx[29].DW = 0x0001020304060705; // 5
Indx[30].DW = 0x0001020304050706; // 6
Indx[31].DW = 0x0001020304050607; // 7
for (i = 16; i < 32; i ++)
{
@ -153,14 +153,14 @@ void Build_RSP ( void )
/******************************************************************
Function: DoRspCycles
Purpose: This function is to allow the RSP to run in parrel with
the r4300 switching control back to the r4300 once the
Purpose: This function is to allow the RSP to run in parallel with
the r4300i switching control back to the r4300i once the
function ends.
input: The number of cylces that is meant to be executed
input: The number of cycles that is meant to be executed
output: The number of cycles that was executed. This value can
be greater than the number of cycles that the RSP
should have performed.
(this value is ignored if the RSP is stoped)
(this value is ignored if the RSP has been stopped)
*******************************************************************/
DWORD RunInterpreterCPU(DWORD Cycles);

9
Source/RSP/Interpreter CPU.c
View File

@ -388,14 +388,14 @@ DWORD RunInterpreterCPU(DWORD Cycles) {
if (InRSPCommandsWindow) {
Enter_RSP_Commands_Window();
if (Stepping_Commands) {
DisplayError ( "Encounted a R4300i Breakpoint" );
DisplayError ( "Encountered an R4300i breakpoint" );
} else {
DisplayError ( "Encounted a R4300i Breakpoint\n\nNow Stepping" );
DisplayError ( "Encountered an R4300i breakpoint\n\nNow stepping" );
SetRSPCommandViewto( *PrgCount );
SetRSPCommandToStepping();
}
} else {
DisplayError ( "Encounted a RSP Breakpoint\n\nEntering Command Window" );
DisplayError ( "Encountered an RSP breakpoint\n\nEntering command window" );
Enter_RSP_Commands_Window();
}
}
@ -413,12 +413,11 @@ DWORD RunInterpreterCPU(DWORD Cycles) {
}
}
RDP_LogLoc(*PrgCount);
RSP_LW_IMEM(*PrgCount, &RSPOpC.Hex);
RSP_Opcode[ RSPOpC.op ]();
RSP_GPR[0].W = 0x00000000; /* MIPS $zero hard-wired to 0 */
RSP_GPR[0].W = 0x00000000; // MIPS $zero hard-wired to 0
switch (RSP_NextInstruction) {
case NORMAL:

7
Source/RSP/Interpreter CPU.h
View File

@ -12,10 +12,9 @@
extern DWORD RSP_NextInstruction, RSP_JumpTo, RSP_MfStatusCount;
/*
* standard MIPS PC-relative branch
* returns the new PC, based on whether the condition passes
*/
// Standard MIPS PC-relative branch
// Returns the new PC, based on whether the condition passes
unsigned int RSP_branch_if(int condition);
void BuildInterpreterCPU(void);

37
Source/RSP/Interpreter Ops.c
View File

@ -13,6 +13,8 @@
#include "Types.h"
#include <float.h>
// TODO: Is this still an issue? If so, investigate, and if not, remove this!
/*
* Unfortunately, GCC 4.8.2 stable still has a bug with their <float.h> that
* includes a different copy of <float.h> from a different directory.
@ -22,6 +24,7 @@
* It also is possible to emulate the RSP divide op-codes using a hardware-
* accurate LUT instead of any floating-point functions, so that works, too.
*/
#ifndef _MCW_RC
#define _MCW_RC 0x00000300
#endif
@ -32,7 +35,8 @@
extern UWORD32 Recp, RecpResult, SQroot, SQrootResult;
extern Boolean AudioHle, GraphicsHle;
/************************* OpCode functions *************************/
// Opcode functions
void RSP_Opcode_SPECIAL ( void ) {
RSP_Special[ RSPOpC.funct ]();
}
@ -164,7 +168,8 @@ void RSP_Opcode_SC2 (void) {
RSP_Sc2 [ RSPOpC.rd ]();
}
/********************** R4300i OpCodes: Special **********************/
// R4300i Opcodes: Special
void RSP_Special_SLL ( void ) {
RSP_GPR[RSPOpC.rd].W = RSP_GPR[RSPOpC.rt].W << RSPOpC.sa;
}
@ -249,7 +254,8 @@ void RSP_Special_SLTU (void) {
RSP_GPR[RSPOpC.rd].UW = (RSP_GPR[RSPOpC.rs].UW < RSP_GPR[RSPOpC.rt].UW) ? 1 : 0;
}
/********************** R4300i OpCodes: RegImm **********************/
// R4300i Opcodes: RegImm
void RSP_Opcode_BLTZ ( void ) {
RSP_NextInstruction = DELAY_SLOT;
RSP_JumpTo = RSP_branch_if(RSP_GPR[RSPOpC.rs].W < 0);
@ -272,7 +278,8 @@ void RSP_Opcode_BGEZAL ( void ) {
RSP_JumpTo = RSP_branch_if(RSP_GPR[RSPOpC.rs].W >= 0);
}
/************************** Cop0 functions *************************/
// COP0 functions
void RSP_Cop0_MF (void) {
if (LogRDP && CPUCore == InterpreterCPU)
{
@ -307,7 +314,7 @@ void RSP_Cop0_MF (void) {
case 11: RSP_GPR[RSPOpC.rt].W = *RSPInfo.DPC_STATUS_REG; break;
case 12: RSP_GPR[RSPOpC.rt].W = *RSPInfo.DPC_CLOCK_REG; break;
default:
DisplayError("have not implemented RSP MF CP0 reg %s (%d)",COP0_Name(RSPOpC.rd),RSPOpC.rd);
DisplayError("We have not implemented RSP MF CP0 reg %s (%d)",COP0_Name(RSPOpC.rd),RSPOpC.rd);
}
}
@ -390,11 +397,12 @@ void RSP_Cop0_MT (void) {
if ( ( RSP_GPR[RSPOpC.rt].W & DPC_CLR_CLOCK_CTR ) != 0) { /* DisplayError("RSP: DPC_STATUS_REG: DPC_CLR_CLOCK_CTR"); */ }
break;
default:
DisplayError("have not implemented RSP MT CP0 reg %s (%d)",COP0_Name(RSPOpC.rd),RSPOpC.rd);
DisplayError("We have not implemented RSP MT CP0 reg %s (%d)",COP0_Name(RSPOpC.rd),RSPOpC.rd);
}
}
/************************** Cop2 functions *************************/
// COP2 functions
void RSP_Cop2_MF (void) {
int element = (RSPOpC.sa >> 1);
RSP_GPR[RSPOpC.rt].B[1] = RSP_Vect[RSPOpC.rd].B[15 - element];
@ -432,7 +440,8 @@ void RSP_COP2_VECTOR (void) {
RSP_Vector[ RSPOpC.funct ]();
}
/************************** Vect functions **************************/
// Vector functions
void RSP_Vector_VMULF (void) {
int el, del;
UWORD32 temp;
@ -1264,7 +1273,7 @@ void RSP_Vector_VMRG (void) {
} else {
result.HW[el] = RSP_Vect[RSPOpC.rt].HW[del];
}
RSP_ACCUM[el].HW[1] = result.HW[el]; //suggested by angrylion
RSP_ACCUM[el].HW[1] = result.HW[el]; // Suggested by Angrylion
}
RSP_Vect[RSPOpC.sa] = result;
}
@ -1548,7 +1557,8 @@ void RSP_Vector_VRSQH (void) {
void RSP_Vector_VNOOP (void) {}
/************************** lc2 functions **************************/
// LC2 functions
void RSP_Opcode_LBV ( void ) {
uint32_t Address = (uint32_t)(RSP_GPR[RSPOpC.base].W + (RSPOpC.voffset << 0)) & 0xFFF;
RSP_LBV_DMEM( Address, RSPOpC.rt, RSPOpC.del);
@ -1604,7 +1614,8 @@ void RSP_Opcode_LTV ( void ) {
RSP_LTV_DMEM( Address, RSPOpC.rt, RSPOpC.del);
}
/************************** sc2 functions **************************/
// SC2 functions
void RSP_Opcode_SBV ( void ) {
uint32_t Address = (uint32_t)(RSP_GPR[RSPOpC.base].W + (RSPOpC.voffset << 0)) & 0xFFF;
RSP_SBV_DMEM( Address, RSPOpC.rt, RSPOpC.del);
@ -1673,9 +1684,9 @@ void rsp_UnknownOpcode (void) {
if (InRSPCommandsWindow) {
SetRSPCommandViewto( *PrgCount );
DisplayError("Unhandled Opcode\n%s\n\nStoping Emulation!", RSPOpcodeName(RSPOpC.Hex,*PrgCount));
DisplayError("Unhandled Opcode\n%s\n\nStopping emulation", RSPOpcodeName(RSPOpC.Hex,*PrgCount));
} else {
sprintf(Message,"Unhandled Opcode\n%s\n\nStoping Emulation!\n\nDo you wish to enter the debugger ?",
sprintf(Message,"Unhandled Opcode\n%s\n\nStopping emulation.\n\nWOuld you like to open the debugger?",
RSPOpcodeName(RSPOpC.Hex,*PrgCount));
response = MessageBox(NULL,Message,"Error", MB_YESNO | MB_ICONERROR);
if (response == IDYES) {

35
Source/RSP/Interpreter Ops.h
View File

@ -1,4 +1,5 @@
/************************* OpCode functions *************************/
// Opcode functions
void RSP_Opcode_SPECIAL ( void );
void RSP_Opcode_REGIMM ( void );
void RSP_Opcode_J ( void );
@ -27,7 +28,9 @@ void RSP_Opcode_SH ( void );
void RSP_Opcode_SW ( void );
void RSP_Opcode_LC2 ( void );
void RSP_Opcode_SC2 ( void );
/********************** R4300i OpCodes: Special **********************/
// R4300i Opcodes: Special
void RSP_Special_SLL ( void );
void RSP_Special_SRL ( void );
void RSP_Special_SRA ( void );
@ -47,21 +50,29 @@ void RSP_Special_XOR ( void );
void RSP_Special_NOR ( void );
void RSP_Special_SLT ( void );
void RSP_Special_SLTU ( void );
/********************** R4300i OpCodes: RegImm **********************/
// R4300i Opcodes: RegImm
void RSP_Opcode_BLTZ ( void );
void RSP_Opcode_BGEZ ( void );
void RSP_Opcode_BLTZAL ( void );
void RSP_Opcode_BGEZAL ( void );
/************************** Cop0 functions *************************/
// COP0 functions
void RSP_Cop0_MF ( void );
void RSP_Cop0_MT ( void );
/************************** Cop2 functions *************************/
// COP2 functions
void RSP_Cop2_MF ( void );
void RSP_Cop2_CF ( void );
void RSP_Cop2_MT ( void );
void RSP_Cop2_CT ( void );
void RSP_COP2_VECTOR ( void );
/************************** Vect functions **************************/
// Vector functions
void RSP_Vector_VMULF ( void );
void RSP_Vector_VMULU ( void );
void RSP_Vector_VMUDL ( void );
@ -103,7 +114,9 @@ void RSP_Vector_VRSQ ( void );
void RSP_Vector_VRSQL ( void );
void RSP_Vector_VRSQH ( void );
void RSP_Vector_VNOOP ( void );
/************************** lc2 functions **************************/
// LC2 functions
void RSP_Opcode_LBV ( void );
void RSP_Opcode_LSV ( void );
void RSP_Opcode_LLV ( void );
@ -115,7 +128,9 @@ void RSP_Opcode_LUV ( void );
void RSP_Opcode_LHV ( void );
void RSP_Opcode_LFV ( void );
void RSP_Opcode_LTV ( void );
/************************** lc2 functions **************************/
// LC2 functions
void RSP_Opcode_SBV ( void );
void RSP_Opcode_SSV ( void );
void RSP_Opcode_SLV ( void );
@ -128,5 +143,7 @@ void RSP_Opcode_SHV ( void );
void RSP_Opcode_SFV ( void );
void RSP_Opcode_STV ( void );
void RSP_Opcode_SWV ( void );
/************************** Other functions **************************/
// Other functions
void rsp_UnknownOpcode ( void );

69
Source/RSP/Main.cpp
View File

@ -58,17 +58,17 @@ enum {
Set_BreakOnStart, Set_CPUCore, Set_LogRDP, Set_LogX86Code, Set_Profiling, Set_IndvidualBlock,
Set_ShowErrors,
//Compiler settings
// Compiler settings
Set_CheckDest, Set_Accum, Set_Mmx, Set_Mmx2, Set_Sse, Set_Sections,
Set_ReOrdering, Set_GPRConstants, Set_Flags, Set_AlignVector,
//Game Settings
// Game settings
Set_JumpTableSize, Set_Mfc0Count, Set_SemaphoreExit
};
short Set_AudioHle = 0, Set_GraphicsHle = 0;
/************ DLL info **************/
// DLL info
const char * AppName ( void )
{
static stdstr_f Name("RSP %s", VER_FILE_VERSION_STR);
@ -76,11 +76,12 @@ const char * AppName ( void )
}
const char * AboutMsg ( void )
{
static stdstr_f Msg("RSP emulation Plugin\nMade for Project64 (c)\nVersion %s\n\nby Jabo & Zilmar", VER_FILE_VERSION_STR);
static stdstr_f Msg("RSP emulation plugin\nMade for Project64 (c)\nVersion %s\n\nby Jabo & Zilmar", VER_FILE_VERSION_STR);
return Msg.c_str();
}
/************ Functions ***********/
// Functions
uint32_t AsciiToHex(char * HexValue)
{
size_t Finish, Count;
@ -142,10 +143,11 @@ void DisplayError(char* Message, ...)
/******************************************************************
Function: CloseDLL
Purpose: This function is called when the emulator is closing
down allowing the dll to de-initialise.
down allowing the DLL to de-initialize.
input: none
output: none
*******************************************************************/
*******************************************************************/
EXPORT void CloseDLL(void)
{
FreeMemory();
@ -157,7 +159,8 @@ EXPORT void CloseDLL(void)
to give further information about the DLL.
input: a handle to the window that calls this function
output: none
*******************************************************************/
*******************************************************************/
EXPORT void DllAbout(void * hParent)
{
#ifdef _WIN32
@ -198,11 +201,12 @@ void FixMenuState(void)
/******************************************************************
Function: GetDllInfo
Purpose: This function allows the emulator to gather information
about the dll by filling in the PluginInfo structure.
input: a pointer to a PLUGIN_INFO stucture that needs to be
about the DLL by filling in the PluginInfo structure.
input: a pointer to a PLUGIN_INFO structure that needs to be
filled by the function. (see def above)
output: none
*******************************************************************/
*******************************************************************/
EXPORT void GetDllInfo(PLUGIN_INFO * PluginInfo)
{
PluginInfo->Version = 0x0103;
@ -219,9 +223,9 @@ EXPORT void GetDllInfo(PLUGIN_INFO * PluginInfo)
/******************************************************************
Function: GetRspDebugInfo
Purpose: This function allows the emulator to gather information
about the debug capabilities of the dll by filling in
about the debug capabilities of the DLL by filling in
the DebugInfo structure.
input: a pointer to a RSPDEBUG_INFO stucture that needs to be
input: a pointer to a RSPDEBUG_INFO structure that needs to be
filled by the function. (see def above)
output: none
*******************************************************************/
@ -260,7 +264,7 @@ EXPORT void GetRspDebugInfo(RSPDEBUG_INFO * DebugInfo)
input: Rsp_Info is passed to this function which is defined
above.
CycleCount is the number of cycles between switching
control between teh RSP and r4300i core.
control between the RSP and r4300i core.
output: none
*******************************************************************/
@ -275,12 +279,12 @@ void DetectCpuSpecs(void)
__try {
#ifdef _M_IX86
_asm {
/* Intel features */
// Intel features
mov eax, 1
cpuid
mov [Intel_Features], edx
/* AMD features */
// AMD features
mov eax, 80000001h
cpuid
or [AMD_Features], edx
@ -297,10 +301,12 @@ void DetectCpuSpecs(void)
AMD_Features = Intel_Features = 0;
}
#else
/*
* To do: With GCC, there is <cpuid.h>, but __cpuid() there is a macro and
* needs five arguments, not two. Also, GCC lacks SEH.
*/
TODO: With GCC, there is <cpuid.h>, but __cpuid() there is a macro and
needs five arguments, not two. Also, GCC lacks SEH.
*/
AMD_Features = Intel_Features = 0;
#endif
@ -345,13 +351,14 @@ EXPORT void InitiateRSP(RSP_INFO Rsp_Info, uint32_t * CycleCount)
/******************************************************************
Function: InitiateRSPDebugger
Purpose: This function is called when the DLL is started to give
information from the emulator that the n64 RSP
interface needs to intergrate the debugger with the
information from the emulator that the N64 RSP
interface needs to integrate the debugger with the
rest of the emulator.
input: DebugInfo is passed to this function which is defined
above.
output: none
*******************************************************************/
*******************************************************************/
EXPORT void InitiateRSPDebugger(DEBUG_INFO Debug_Info)
{
DebugInfo = Debug_Info;
@ -522,10 +529,11 @@ void ProcessMenuItem(int ID)
/******************************************************************
Function: RomOpen
Purpose: This function is called when a rom is opened.
Purpose: This function is called when a ROM is opened.
input: none
output: none
*******************************************************************/
*******************************************************************/
EXPORT void RomOpen(void)
{
ClearAllx86Code();
@ -540,10 +548,11 @@ EXPORT void RomOpen(void)
/******************************************************************
Function: RomClosed
Purpose: This function is called when a rom is closed.
Purpose: This function is called when a ROM is closed.
input: none
output: none
*******************************************************************/
*******************************************************************/
EXPORT void RomClosed(void)
{
if (Profiling)
@ -772,12 +781,12 @@ EXPORT void PluginLoaded(void)
RegisterSetting(Set_LogRDP, Data_DWORD_General,"Log RDP", NULL,LogRDP,NULL);
RegisterSetting(Set_LogX86Code, Data_DWORD_General,"Log X86 Code", NULL,LogX86Code,NULL);
RegisterSetting(Set_Profiling, Data_DWORD_General,"Profiling", NULL,Profiling,NULL);
RegisterSetting(Set_IndvidualBlock, Data_DWORD_General,"Indvidual Block",NULL,IndvidualBlock,NULL);
RegisterSetting(Set_IndvidualBlock, Data_DWORD_General,"Individual Block",NULL,IndvidualBlock,NULL);
RegisterSetting(Set_ShowErrors, Data_DWORD_General,"Show Errors", NULL,ShowErrors,NULL);
//Compiler settings
RegisterSetting(Set_CheckDest, Data_DWORD_General,"Check Dest Vector", NULL,Compiler.bDest,NULL);
RegisterSetting(Set_Accum, Data_DWORD_General,"Check Dest Accum", NULL,Compiler.bAccum,NULL);
// Compiler settings
RegisterSetting(Set_CheckDest, Data_DWORD_General,"Check Destination Vector", NULL,Compiler.bDest,NULL);
RegisterSetting(Set_Accum, Data_DWORD_General,"Check Destination Accumulator", NULL,Compiler.bAccum,NULL);
RegisterSetting(Set_Mmx, Data_DWORD_General,"Use MMX", NULL,Compiler.mmx,NULL);
RegisterSetting(Set_Mmx2, Data_DWORD_General,"Use MMX2", NULL,Compiler.mmx2,NULL);
RegisterSetting(Set_Sse, Data_DWORD_General,"Use SSE", NULL,Compiler.sse,NULL);

23
Source/RSP/OpCode.h
View File

@ -2,7 +2,7 @@
#include "Types.h"
#pragma warning(push)
#pragma warning(disable : 4201) // nonstandard extension used : nameless struct/union
#pragma warning(disable : 4201) // Non-standard extension used: nameless struct/union
typedef union tagOPCODE {
uint32_t Hex;
@ -48,7 +48,8 @@ typedef union tagOPCODE {
#pragma warning(pop)
//RSP OpCodes
//RSP opcodes
#define RSP_SPECIAL 0
#define RSP_REGIMM 1
#define RSP_J 2
@ -78,7 +79,8 @@ typedef union tagOPCODE {
#define RSP_LC2 50
#define RSP_SC2 58
/* RSP Special opcodes */
// RSP special opcodes
#define RSP_SPECIAL_SLL 0
#define RSP_SPECIAL_SRL 2
#define RSP_SPECIAL_SRA 3
@ -99,23 +101,27 @@ typedef union tagOPCODE {
#define RSP_SPECIAL_SLT 42
#define RSP_SPECIAL_SLTU 43
/* RSP RegImm opcodes */
// RSP RegImm opcodes
#define RSP_REGIMM_BLTZ 0
#define RSP_REGIMM_BGEZ 1
#define RSP_REGIMM_BLTZAL 16
#define RSP_REGIMM_BGEZAL 17
/* RSP COP0 opcodes */
// RSP COP0 opcodes
#define RSP_COP0_MF 0
#define RSP_COP0_MT 4
/* RSP COP2 opcodes */
// RSP COP2 opcodes
#define RSP_COP2_MF 0
#define RSP_COP2_CF 2
#define RSP_COP2_MT 4
#define RSP_COP2_CT 6
/* RSP Vector opcodes */
// RSP vector opcodes
#define RSP_VECTOR_VMULF 0
#define RSP_VECTOR_VMULU 1
#define RSP_VECTOR_VRNDP 2
@ -161,7 +167,8 @@ typedef union tagOPCODE {
#define RSP_VECTOR_VRSQH 54
#define RSP_VECTOR_VNOOP 55
/* RSP LSC2 opcodes */
// RSP LSC2 opcodes
#define RSP_LSC2_BV 0
#define RSP_LSC2_SV 1
#define RSP_LSC2_LV 2

16
Source/RSP/Profiling.cpp
View File

@ -19,7 +19,7 @@ typedef PROFILE_ENRTIES::value_type PROFILE_VALUE;
typedef struct { SPECIAL_TIMERS Timer; char * Name; } TIMER_NAME;
DWORD m_CurrentTimerAddr, CurrentDisplayCount;
DWORD m_StartTimeHi, m_StartTimeLo; //The Current Timer start time
DWORD m_StartTimeHi, m_StartTimeLo; // The current timer start time
PROFILE_ENRTIES m_Entries;
public:
@ -28,7 +28,7 @@ public:
m_CurrentTimerAddr = Timer_None;
}
//recording timing against current timer, returns the address of the timer stoped
// Recording timing against current timer, returns the address of the timer stopped
DWORD StartTimer ( DWORD Address )
{
DWORD OldTimerAddr = StopTimer();
@ -86,13 +86,13 @@ public:
return OldTimerAddr;
}
//Reset all the counters back to 0
// Reset all the counters back to 0
void ResetCounters ( void )
{
m_Entries.clear();
}
//Generate a log file with the current results, this will also reset the counters
// Generate a log file with the current results, this will also reset the counters
void GenerateLog ( void )
{
stdstr LogFileName;
@ -101,21 +101,21 @@ public:
Log.Open("RSP Profiling.txt");
LogFileName = Log.FileName();
//Get the total time
// Get the total time
__int64 TotalTime = 0;
for (PROFILE_ENRTY itemTime = m_Entries.begin(); itemTime != m_Entries.end(); itemTime++ )
{
TotalTime += itemTime->second;
}
//Create a sortable list of items
// Create a sortable list of items
std::vector<PROFILE_VALUE *> ItemList;
for (PROFILE_ENRTY Entry = m_Entries.begin(); Entry != m_Entries.end(); Entry++ )
{
ItemList.push_back(&(*Entry));
}
//sort the list with a basic bubble sort
// Sort the list with a basic bubble sort
if (ItemList.size() > 0)
{
for (size_t OuterPass = 0; OuterPass < (ItemList.size() - 1); OuterPass++ )
@ -135,7 +135,7 @@ public:
TIMER_NAME TimerNames[] = {
{Timer_Compiling, "RSP: Compiling"},
{Timer_RSP_Running, "RSP: Running"},
{Timer_R4300_Running, "R4300: Running"},
{Timer_R4300_Running, "R4300i: Running"},
{Timer_RDP_Running, "RDP: Running"},
};

17
Source/RSP/RSP Command.c
View File

@ -897,7 +897,7 @@ char * RSPSpecialName ( DWORD OpCode, DWORD PC )
OPCODE command;
command.Hex = OpCode;
PC = PC; // unused
PC = PC; // Unused
if (strcmp(mnemonics_special[command.funct], unused_op) == 0)
{
@ -978,7 +978,7 @@ char * RSPRegimmName ( DWORD OpCode, DWORD PC )
);
}
else if (command.rt == RSP_REGIMM_BGEZAL && command.rs == 0)
{ /* MIPS pseudo-instruction: BAL (Branch and Link) */
{ // MIPS pseudo-instruction: BAL (branch and link)
sprintf(
CommandName,
"BAL\t0x%04X",
@ -1003,7 +1003,7 @@ char * RSPCop0Name ( DWORD OpCode, DWORD PC )
OPCODE command;
command.Hex = OpCode;
PC = PC; // unused
PC = PC; // Unused
if (strcmp(mnemonics_cop0[command.rs], unused_op) == 0)
{
@ -1034,7 +1034,7 @@ char * RSPCop2Name ( DWORD OpCode, DWORD PC )
OPCODE command;
command.Hex = OpCode;
PC = PC; // unused
PC = PC; // Unused
if ( ( command.rs & 0x10 ) == 0 )
{
@ -1047,7 +1047,7 @@ char * RSPCop2Name ( DWORD OpCode, DWORD PC )
command.Ascii[0]
);
}
else if (command.rs & 002) /* CFC2 or CTC2 */
else if (command.rs & 002) // CFC2 or CTC2
{
sprintf(CommandName, "%s\t%s, %d",
mnemonics_cop2[command.rs],
@ -1077,7 +1077,7 @@ char * RSPCop2Name ( DWORD OpCode, DWORD PC )
);
}
else if (command.funct >= RSP_VECTOR_VRCP && command.funct < RSP_VECTOR_VNOOP)
{ /* RSP division -- VRCP[L,H], VRSQ[L,H], and VMOV */
{ // RSP division -- VRCP[L,H], VRSQ[L,H], and VMOV
sprintf(CommandName, "%s\t$v%d[%d], $v%d%s",
mnemonics_vector[command.funct],
command.sa,
@ -1109,7 +1109,7 @@ char * RSPLc2Name ( DWORD OpCode, DWORD PC )
OPCODE command;
command.Hex = OpCode;
PC = PC; // unused
PC = PC; // Unused
if (strcmp(mnemonics_lwc2[command.rd], unused_op) == 0)
{
@ -1143,7 +1143,7 @@ char * RSPSc2Name ( DWORD OpCode, DWORD PC )
OPCODE command;
command.Hex = OpCode;
PC = PC; // unused
PC = PC; // Unused
if (strcmp(mnemonics_swc2[command.rd], unused_op) == 0)
{
@ -1210,6 +1210,7 @@ char * RSPOpcodeName ( DWORD OpCode, DWORD PC )
);
break;
}
// TODO: add example code?
/* else { fall through to show the full BEQ } */
case RSP_BNE:
sprintf(CommandName, "%s\t%s, %s, 0x%04X",

2
Source/RSP/RSP Register.c
View File

@ -36,7 +36,7 @@ HWND RSP_Registers_hDlg, hTab, hStatic, hGPR[32], hCP0[16], hHIDDEN[12],
int InRSPRegisterWindow = FALSE;
WNDPROC RefreshProc;
/*** RSP Registers ***/
// RSP registers
UWORD32 RSP_GPR[32], RSP_Flags[4];
UDWORD RSP_ACCUM[8];
VECTOR RSP_Vect[32];

124
Source/RSP/RSP Registers.h
View File

@ -1,69 +1,69 @@
#include "Types.h"
#define SP_STATUS_HALT 0x001 /* Bit 0: halt */
#define SP_STATUS_BROKE 0x002 /* Bit 1: broke */
#define SP_STATUS_DMA_BUSY 0x004 /* Bit 2: dma busy */
#define SP_STATUS_DMA_FULL 0x008 /* Bit 3: dma full */
#define SP_STATUS_IO_FULL 0x010 /* Bit 4: io full */
#define SP_STATUS_SSTEP 0x020 /* Bit 5: single step */
#define SP_STATUS_INTR_BREAK 0x040 /* Bit 6: interrupt on break */
#define SP_STATUS_SIG0 0x080 /* Bit 7: signal 0 set */
#define SP_STATUS_SIG1 0x100 /* Bit 8: signal 1 set */
#define SP_STATUS_SIG2 0x200 /* Bit 9: signal 2 set */
#define SP_STATUS_SIG3 0x400 /* Bit 10: signal 3 set */
#define SP_STATUS_SIG4 0x800 /* Bit 11: signal 4 set */
#define SP_STATUS_SIG5 0x1000 /* Bit 12: signal 5 set */
#define SP_STATUS_SIG6 0x2000 /* Bit 13: signal 6 set */
#define SP_STATUS_SIG7 0x4000 /* Bit 14: signal 7 set */
#define SP_STATUS_HALT 0x001 // Bit 0: halt
#define SP_STATUS_BROKE 0x002 // Bit 1: broke
#define SP_STATUS_DMA_BUSY 0x004 // Bit 2: DMA busy
#define SP_STATUS_DMA_FULL 0x008 // Bit 3: DMA full
#define SP_STATUS_IO_FULL 0x010 // Bit 4: IO full
#define SP_STATUS_SSTEP 0x020 // Bit 5: single step
#define SP_STATUS_INTR_BREAK 0x040 // Bit 6: interrupt on break
#define SP_STATUS_SIG0 0x080 // Bit 7: signal 0 set
#define SP_STATUS_SIG1 0x100 // Bit 8: signal 1 set
#define SP_STATUS_SIG2 0x200 // Bit 9: signal 2 set
#define SP_STATUS_SIG3 0x400 // Bit 10: signal 3 set
#define SP_STATUS_SIG4 0x800 // Bit 11: signal 4 set
#define SP_STATUS_SIG5 0x1000 // Bit 12: signal 5 set
#define SP_STATUS_SIG6 0x2000 // Bit 13: signal 6 set
#define SP_STATUS_SIG7 0x4000 // Bit 14: signal 7 set
#define SP_CLR_HALT 0x00001 /* Bit 0: clear halt */
#define SP_SET_HALT 0x00002 /* Bit 1: set halt */
#define SP_CLR_BROKE 0x00004 /* Bit 2: clear broke */
#define SP_CLR_INTR 0x00008 /* Bit 3: clear intr */
#define SP_SET_INTR 0x00010 /* Bit 4: set intr */
#define SP_CLR_SSTEP 0x00020 /* Bit 5: clear sstep */
#define SP_SET_SSTEP 0x00040 /* Bit 6: set sstep */
#define SP_CLR_INTR_BREAK 0x00080 /* Bit 7: clear intr on break */
#define SP_SET_INTR_BREAK 0x00100 /* Bit 8: set intr on break */
#define SP_CLR_SIG0 0x00200 /* Bit 9: clear signal 0 */
#define SP_SET_SIG0 0x00400 /* Bit 10: set signal 0 */
#define SP_CLR_SIG1 0x00800 /* Bit 11: clear signal 1 */
#define SP_SET_SIG1 0x01000 /* Bit 12: set signal 1 */
#define SP_CLR_SIG2 0x02000 /* Bit 13: clear signal 2 */
#define SP_SET_SIG2 0x04000 /* Bit 14: set signal 2 */
#define SP_CLR_SIG3 0x08000 /* Bit 15: clear signal 3 */
#define SP_SET_SIG3 0x10000 /* Bit 16: set signal 3 */
#define SP_CLR_SIG4 0x20000 /* Bit 17: clear signal 4 */
#define SP_SET_SIG4 0x40000 /* Bit 18: set signal 4 */
#define SP_CLR_SIG5 0x80000 /* Bit 19: clear signal 5 */
#define SP_SET_SIG5 0x100000 /* Bit 20: set signal 5 */
#define SP_CLR_SIG6 0x200000 /* Bit 21: clear signal 6 */
#define SP_SET_SIG6 0x400000 /* Bit 22: set signal 6 */
#define SP_CLR_SIG7 0x800000 /* Bit 23: clear signal 7 */
#define SP_SET_SIG7 0x1000000 /* Bit 24: set signal 7 */
#define SP_CLR_HALT 0x00001 // Bit 0: clear halt
#define SP_SET_HALT 0x00002 // Bit 1: set halt
#define SP_CLR_BROKE 0x00004 // Bit 2: clear broke
#define SP_CLR_INTR 0x00008 // Bit 3: clear INTR
#define SP_SET_INTR 0x00010 // Bit 4: set INTR
#define SP_CLR_SSTEP 0x00020 // Bit 5: clear SSTEP
#define SP_SET_SSTEP 0x00040 // Bit 6: set SSTEP
#define SP_CLR_INTR_BREAK 0x00080 // Bit 7: clear INTR on break
#define SP_SET_INTR_BREAK 0x00100 // Bit 8: set INTR on break
#define SP_CLR_SIG0 0x00200 // Bit 9: clear signal 0
#define SP_SET_SIG0 0x00400 // Bit 10: set signal 0
#define SP_CLR_SIG1 0x00800 // Bit 11: clear signal 1
#define SP_SET_SIG1 0x01000 // Bit 12: set signal 1
#define SP_CLR_SIG2 0x02000 // Bit 13: clear signal 2
#define SP_SET_SIG2 0x04000 // Bit 14: set signal 2
#define SP_CLR_SIG3 0x08000 // Bit 15: clear signal 3
#define SP_SET_SIG3 0x10000 // Bit 16: set signal 3
#define SP_CLR_SIG4 0x20000 // Bit 17: clear signal 4
#define SP_SET_SIG4 0x40000 // Bit 18: set signal 4
#define SP_CLR_SIG5 0x80000 // Bit 19: clear signal 5
#define SP_SET_SIG5 0x100000 // Bit 20: set signal 5
#define SP_CLR_SIG6 0x200000 // Bit 21: clear signal 6
#define SP_SET_SIG6 0x400000 // Bit 22: set signal 6
#define SP_CLR_SIG7 0x800000 // Bit 23: clear signal 7
#define SP_SET_SIG7 0x1000000 // Bit 24: set signal 7
#define DPC_CLR_XBUS_DMEM_DMA 0x0001 /* Bit 0: clear xbus_dmem_dma */
#define DPC_SET_XBUS_DMEM_DMA 0x0002 /* Bit 1: set xbus_dmem_dma */
#define DPC_CLR_FREEZE 0x0004 /* Bit 2: clear freeze */
#define DPC_SET_FREEZE 0x0008 /* Bit 3: set freeze */
#define DPC_CLR_FLUSH 0x0010 /* Bit 4: clear flush */
#define DPC_SET_FLUSH 0x0020 /* Bit 5: set flush */
#define DPC_CLR_TMEM_CTR 0x0040 /* Bit 6: clear tmem ctr */
#define DPC_CLR_PIPE_CTR 0x0080 /* Bit 7: clear pipe ctr */
#define DPC_CLR_CMD_CTR 0x0100 /* Bit 8: clear cmd ctr */
#define DPC_CLR_CLOCK_CTR 0x0200 /* Bit 9: clear clock ctr */
#define DPC_CLR_XBUS_DMEM_DMA 0x0001 // Bit 0: clear xbus_dmem_dma
#define DPC_SET_XBUS_DMEM_DMA 0x0002 // Bit 1: set xbus_dmem_dma
#define DPC_CLR_FREEZE 0x0004 // Bit 2: clear freeze
#define DPC_SET_FREEZE 0x0008 // Bit 3: set freeze
#define DPC_CLR_FLUSH 0x0010 // Bit 4: clear flush
#define DPC_SET_FLUSH 0x0020 // Bit 5: set flush
#define DPC_CLR_TMEM_CTR 0x0040 // Bit 6: clear TMEM CTR
#define DPC_CLR_PIPE_CTR 0x0080 // Bit 7: clear pipe CTR
#define DPC_CLR_CMD_CTR 0x0100 // Bit 8: clear CMD CTR
#define DPC_CLR_CLOCK_CTR 0x0200 // Bit 9: clear clock CTR
#define DPC_STATUS_XBUS_DMEM_DMA 0x001 /* Bit 0: xbus_dmem_dma */
#define DPC_STATUS_FREEZE 0x002 /* Bit 1: freeze */
#define DPC_STATUS_FLUSH 0x004 /* Bit 2: flush */
#define DPC_STATUS_START_GCLK 0x008 /* Bit 3: start gclk */
#define DPC_STATUS_TMEM_BUSY 0x010 /* Bit 4: tmem busy */
#define DPC_STATUS_PIPE_BUSY 0x020 /* Bit 5: pipe busy */
#define DPC_STATUS_CMD_BUSY 0x040 /* Bit 6: cmd busy */
#define DPC_STATUS_CBUF_READY 0x080 /* Bit 7: cbuf ready */
#define DPC_STATUS_DMA_BUSY 0x100 /* Bit 8: dma busy */
#define DPC_STATUS_END_VALID 0x200 /* Bit 9: end valid */
#define DPC_STATUS_START_VALID 0x400 /* Bit 10: start valid */
#define DPC_STATUS_XBUS_DMEM_DMA 0x001 // Bit 0: xbus_dmem_dma
#define DPC_STATUS_FREEZE 0x002 // Bit 1: freeze
#define DPC_STATUS_FLUSH 0x004 // Bit 2: flush
#define DPC_STATUS_START_GCLK 0x008 // Bit 3: start GCLK
#define DPC_STATUS_TMEM_BUSY 0x010 // Bit 4: TMEM busy
#define DPC_STATUS_PIPE_BUSY 0x020 // Bit 5: pipe busy
#define DPC_STATUS_CMD_BUSY 0x040 // Bit 6: CMD busy
#define DPC_STATUS_CBUF_READY 0x080 // Bit 7: CBUF ready
#define DPC_STATUS_DMA_BUSY 0x100 // Bit 8: DMA busy
#define DPC_STATUS_END_VALID 0x200 // Bit 9: end valid
#define DPC_STATUS_START_VALID 0x400 // Bit 10: start valid
#define R4300i_SP_Intr 0x1
@ -117,7 +117,7 @@ void Enter_RSP_Register_Window ( void );
void InitilizeRSPRegisters (void);
void UpdateRSPRegistersScreen ( void );
/*** RSP Registers ***/
// RSP registers
extern UWORD32 RSP_GPR[32], RSP_Flags[4];
extern UDWORD RSP_ACCUM[8];
extern VECTOR RSP_Vect[32];

288
Source/RSP/Recompiler Analysis.c
View File

@ -54,7 +54,7 @@ Boolean IsNextInstructionMmx(DWORD PC)
if ((RspOp.rs & 0x10) != 0) {
switch (RspOp.funct) {
case RSP_VECTOR_VMULF:
case RSP_VECTOR_VMUDL: /* Warning: Not all handled? */
case RSP_VECTOR_VMUDL: // Warning: Not all handled?
case RSP_VECTOR_VMUDM:
case RSP_VECTOR_VMUDN:
case RSP_VECTOR_VMUDH:
@ -81,7 +81,7 @@ Boolean IsNextInstructionMmx(DWORD PC)
case RSP_VECTOR_VADD:
case RSP_VECTOR_VSUB:
/* Requires no accumulator write! & No flags! */
// Requires no accumulator write, and no flags!
if (WriteToAccum(Low16BitAccum, PC) == TRUE) {
return FALSE;
} else if (UseRspFlags(PC) == TRUE) {
@ -105,7 +105,7 @@ Boolean IsNextInstructionMmx(DWORD PC)
** TRUE: Accumulation series
** FALSE: Accumulator is reset after this op
**
** Input: PC, Location in accumulator
** Input: PC, location in accumulator
*************************************************************/
#define HIT_BRANCH 0x2
@ -138,7 +138,7 @@ DWORD WriteToAccum2(int Location, int PC, Boolean RecursiveCall)
Instruction_State = DO_DELAY_SLOT;
break;
default:
CompilerWarning("Unkown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
CompilerWarning("Unknown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
return TRUE;
}
break;
@ -171,24 +171,24 @@ DWORD WriteToAccum2(int Location, int PC, Boolean RecursiveCall)
break;
default:
CompilerWarning("Unkown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
CompilerWarning("Unknown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
return TRUE;
}
break;
case RSP_J:
/* there is no way a loopback is going to use accumulator */
// There is no way a loopback is going to use accumulator
if (Compiler.bAudioUcode && (((int)(RspOp.target << 2) & 0xFFC) < PC)) {
return FALSE;
}
/* rarely occurs let them have their way */
// Rarely occurs let them have their way
else {
Instruction_State = DO_DELAY_SLOT;
break;
}
case RSP_JAL:
/* there is no way calling a subroutine is going to use accum */
/* or come back and continue an existing calculation */
// There is no way calling a subroutine is going to use an accumulator
// or come back and continue an existing calculation
if(Compiler.bAudioUcode) {
break;
} else {
@ -204,11 +204,11 @@ DWORD WriteToAccum2(int Location, int PC, Boolean RecursiveCall)
if (Compiler.bAudioUcode) {
OPCODE NextOp;
/* ignore backward branches and pretend its a nop */
// Ignore backward branches and pretend it's a NOP
if (BranchImmed <= 0) {
break;
}
/* if the opcode 8 bytes before the dest is a J backward than ignore this */
// If the opcode (which is 8 bytes before the destination and also a J backward) then ignore this
BranchImmed = (PC + ((short)RspOp.offset << 2) + 4) & 0xFFC;
RSP_LW_IMEM(BranchImmed - 8, &NextOp.Hex);
if (RspOp.op == RSP_J && (int)(RspOp.target << 2) < PC) {
@ -260,8 +260,8 @@ DWORD WriteToAccum2(int Location, int PC, Boolean RecursiveCall)
case RSP_VECTOR_VNOR:
case RSP_VECTOR_VXOR:
case RSP_VECTOR_VNXOR:
/* since these modify the accumulator lower-16 bits we can */
/* safely assume these 'reset' the accumulator no matter what */
// Since these modify the accumulator lower-16 bits we can
// safely assume these 'reset' the accumulator no matter what
// return FALSE;
case RSP_VECTOR_VCR:
case RSP_VECTOR_VCH:
@ -283,7 +283,7 @@ DWORD WriteToAccum2(int Location, int PC, Boolean RecursiveCall)
case RSP_VECTOR_VSAW:
return TRUE;
default:
CompilerWarning("Unkown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
CompilerWarning("Unknown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
return TRUE;
}
} else {
@ -294,7 +294,7 @@ DWORD WriteToAccum2(int Location, int PC, Boolean RecursiveCall)
case RSP_COP2_MF:
break;
default:
CompilerWarning("Unkown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
CompilerWarning("Unknown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
return TRUE;
}
}
@ -322,7 +322,7 @@ DWORD WriteToAccum2(int Location, int PC, Boolean RecursiveCall)
case RSP_LSC2_HV:
break;
default:
CompilerWarning("Unkown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
CompilerWarning("Unknown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
return TRUE;
}
break;
@ -342,12 +342,12 @@ DWORD WriteToAccum2(int Location, int PC, Boolean RecursiveCall)
case RSP_LSC2_TV:
break;
default:
CompilerWarning("Unkown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
CompilerWarning("Unknown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
return TRUE;
}
break;
default:
CompilerWarning("Unkown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
CompilerWarning("Unknown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
return TRUE;
}
switch (Instruction_State) {
@ -362,42 +362,42 @@ DWORD WriteToAccum2(int Location, int PC, Boolean RecursiveCall)
} while (Instruction_State != FINISH_BLOCK);
/*
* This is a tricky situation because most of the
* microcode does loops, so looping back and checking
* can prove effective, but it's still a branch..
*/
This is a tricky situation because most of the
microcode does loops, so looping back and checking
can prove effective, but it's still a branch...
*/
if (BranchTarget != 0 && RecursiveCall == FALSE) {
DWORD BranchTaken, BranchFall;
/* analysis of branch taken */
// Analysis of branch taken
BranchTaken = WriteToAccum2(Location, BranchTarget - 4, TRUE);
/* analysis of branch as nop */
// Analysis of branch as NOP
BranchFall = WriteToAccum2(Location, PC, TRUE);
if (BranchImmed < 0) {
if (BranchTaken != FALSE) {
/*
* took this back branch and found a place
* that needs this vector as a source
*/
// took this back branch and found a place
// that needs this vector as a source
return TRUE;
} else if (BranchFall == HIT_BRANCH) {
return TRUE;
}
/* otherwise this is completely valid */
// Otherwise this is completely valid
return BranchFall;
} else {
if (BranchFall != FALSE) {
/*
* took this forward branch and found a place
* that needs this vector as a source
*/
// Took this forward branch and found a place
// that needs this vector as a source
return TRUE;
} else if (BranchTaken == HIT_BRANCH) {
return TRUE;
}
/* otherwise this is completely valid */
// Otherwise this is completely valid
return BranchTaken;
}
}
@ -420,7 +420,6 @@ Boolean WriteToAccum(int Location, int PC)
** Output:
** TRUE: Destination is used as a source later
** FALSE: Destination is over-written later
**
** Input: PC, Register
*************************************************************/
@ -454,7 +453,7 @@ Boolean WriteToVectorDest2(DWORD DestReg, int PC, Boolean RecursiveCall)
Instruction_State = DO_DELAY_SLOT;
break;
default:
CompilerWarning("Unkown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
CompilerWarning("Unknown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
return TRUE;
}
break;
@ -487,20 +486,20 @@ Boolean WriteToVectorDest2(DWORD DestReg, int PC, Boolean RecursiveCall)
break;
default:
CompilerWarning("Unkown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
CompilerWarning("Unknown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
return TRUE;
}
break;
case RSP_J:
/* there is no way a loopback is going to use accumulator */
// There is no way a loopback is going to use accumulator
if (Compiler.bAudioUcode && (int)(RspOp.target << 2) < PC) {
return FALSE;
}
/* rarely occurs let them have their way */
// Rarely occurs let them have their way
return TRUE;
case RSP_JAL:
/* Assume reg is being passed to function or used after the function call */
// Assume register is being passed to function or used after the function call
return TRUE;
case RSP_BEQ:
@ -511,11 +510,11 @@ Boolean WriteToVectorDest2(DWORD DestReg, int PC, Boolean RecursiveCall)
if (Compiler.bAudioUcode) {
OPCODE NextOp;
/* ignore backward branches and pretend its a nop */
// Ignore backward branches and pretend it's a NOP
if (BranchImmed <= 0) {
break;
}
/* if the opcode 8 bytes before the dest is a J backward than ignore this */
// If the opcode (which is 8 bytes before the destination and also a J backward) then ignore this
BranchImmed = (PC + ((short)RspOp.offset << 2) + 4) & 0xFFC;
RSP_LW_IMEM(BranchImmed - 8, &NextOp.Hex);
if (RspOp.op == RSP_J && (int)(RspOp.target << 2) < PC) {
@ -592,7 +591,7 @@ Boolean WriteToVectorDest2(DWORD DestReg, int PC, Boolean RecursiveCall)
if (DestReg == RspOp.sa) { return FALSE; }
break;
default:
CompilerWarning("Unkown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
CompilerWarning("Unknown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
return TRUE;
}
} else {
@ -607,7 +606,7 @@ Boolean WriteToVectorDest2(DWORD DestReg, int PC, Boolean RecursiveCall)
if (DestReg == RspOp.rd) { return TRUE; }
break;
default:
CompilerWarning("Unkown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
CompilerWarning("Unknown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
return TRUE;
}
}
@ -641,7 +640,7 @@ Boolean WriteToVectorDest2(DWORD DestReg, int PC, Boolean RecursiveCall)
break;
default:
CompilerWarning("Unkown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
CompilerWarning("Unknown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
return TRUE;
}
break;
@ -678,12 +677,12 @@ Boolean WriteToVectorDest2(DWORD DestReg, int PC, Boolean RecursiveCall)
break;
default:
CompilerWarning("Unkown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
CompilerWarning("Unknown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
return TRUE;
}
break;
default:
CompilerWarning("Unkown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
CompilerWarning("Unknown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
return TRUE;
}
switch (Instruction_State) {
@ -698,42 +697,42 @@ Boolean WriteToVectorDest2(DWORD DestReg, int PC, Boolean RecursiveCall)
} while (Instruction_State != FINISH_BLOCK);
/*
* This is a tricky situation because most of the
* microcode does loops, so looping back and checking
* can prove effective, but it's still a branch..
*/
This is a tricky situation because most of the
microcode does loops, so looping back and checking
can prove effective, but it's still a branch...
*/
if (BranchTarget != 0 && RecursiveCall == FALSE) {
DWORD BranchTaken, BranchFall;
/* analysis of branch taken */
// Analysis of branch taken
BranchTaken = WriteToVectorDest2(DestReg, BranchTarget - 4, TRUE);
/* analysis of branch as nop */
// Analysis of branch as NOP
BranchFall = WriteToVectorDest2(DestReg, PC, TRUE);
if (BranchImmed < 0) {
if (BranchTaken != FALSE) {
/*
* took this back branch and found a place
* Took this back branch and found a place
* that needs this vector as a source
*/
return TRUE;
} else if (BranchFall == HIT_BRANCH) {
return TRUE;
}
/* otherwise this is completely valid */
// Otherwise this is completely valid
return BranchFall;
} else {
if (BranchFall != FALSE) {
/*
* took this forward branch and found a place
* Took this forward branch and found a place
* that needs this vector as a source
*/
return TRUE;
} else if (BranchTaken == HIT_BRANCH) {
return TRUE;
}
/* otherwise this is completely valid */
// Otherwise this is completely valid
return BranchTaken;
}
}
@ -747,7 +746,7 @@ Boolean WriteToVectorDest(DWORD DestReg, int PC)
value = WriteToVectorDest2(DestReg, PC, FALSE);
if (value == HIT_BRANCH) {
return TRUE; /* ??? */
return TRUE; // TODO: ???
} else
return value;
}
@ -758,11 +757,10 @@ Boolean WriteToVectorDest(DWORD DestReg, int PC)
** Output:
** TRUE: Flags are determined not in use
** FALSE: Either unable to determine or are in use
**
** Input: PC
*************************************************************/
/* TODO: consider delay slots and such in a branch? */
// TODO: consider delay slots and such in a branch?
Boolean UseRspFlags(int PC)
{
OPCODE RspOp;
@ -790,7 +788,7 @@ Boolean UseRspFlags(int PC)
Instruction_State = DO_DELAY_SLOT;
break;
default:
CompilerWarning("Unkown opcode in UseRspFlags\n%s",RSPOpcodeName(RspOp.Hex,PC));
CompilerWarning("Unknown opcode in UseRspFlags\n%s",RSPOpcodeName(RspOp.Hex,PC));
return TRUE;
}
break;
@ -820,7 +818,7 @@ Boolean UseRspFlags(int PC)
break;
default:
CompilerWarning("Unkown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
CompilerWarning("Unknown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
return TRUE;
}
break;
@ -897,7 +895,7 @@ Boolean UseRspFlags(int PC)
break;
default:
CompilerWarning("Unkown opcode in UseRspFlags\n%s",RSPOpcodeName(RspOp.Hex,PC));
CompilerWarning("Unknown opcode in UseRspFlags\n%s",RSPOpcodeName(RspOp.Hex,PC));
return TRUE;
}
} else {
@ -910,7 +908,7 @@ Boolean UseRspFlags(int PC)
case RSP_COP2_MF:
break;
default:
CompilerWarning("Unkown opcode in UseRspFlags\n%s",RSPOpcodeName(RspOp.Hex,PC));
CompilerWarning("Unknown opcode in UseRspFlags\n%s",RSPOpcodeName(RspOp.Hex,PC));
return TRUE;
}
}
@ -938,7 +936,7 @@ Boolean UseRspFlags(int PC)
case RSP_LSC2_HV:
break;
default:
CompilerWarning("Unkown opcode in UseRspFlags\n%s",RSPOpcodeName(RspOp.Hex,PC));
CompilerWarning("Unknown opcode in UseRspFlags\n%s",RSPOpcodeName(RspOp.Hex,PC));
return TRUE;
}
break;
@ -958,12 +956,12 @@ Boolean UseRspFlags(int PC)
case RSP_LSC2_TV:
break;
default:
CompilerWarning("Unkown opcode in UseRspFlags\n%s",RSPOpcodeName(RspOp.Hex,PC));
CompilerWarning("Unknown opcode in UseRspFlags\n%s",RSPOpcodeName(RspOp.Hex,PC));
return TRUE;
}
break;
default:
CompilerWarning("Unkown opcode in UseRspFlags\n%s",RSPOpcodeName(RspOp.Hex,PC));
CompilerWarning("Unknown opcode in UseRspFlags\n%s",RSPOpcodeName(RspOp.Hex,PC));
return TRUE;
}
switch (Instruction_State) {
@ -985,7 +983,6 @@ Boolean UseRspFlags(int PC)
** Output:
** TRUE: Register is constant throughout
** FALSE: Register is not constant at all
**
** Input: PC, Pointer to constant to fill
*************************************************************/
@ -1003,7 +1000,7 @@ Boolean IsRegisterConstant(DWORD Reg, DWORD * Constant)
RSP_LW_IMEM(PC, &RspOp.Hex);
/* resample command in microcode likes S7 */
// Resample command in microcode likes S7
/* if (PC == 0xFBC) {
PC += 4;
continue;
@ -1041,7 +1038,7 @@ Boolean IsRegisterConstant(DWORD Reg, DWORD * Constant)
break;
default:
// CompilerWarning("Unkown opcode in IsRegisterConstant\n%s",RSPOpcodeName(RspOp.Hex,PC));
// CompilerWarning("Unknown opcode in IsRegisterConstant\n%s",RSPOpcodeName(RspOp.Hex,PC));
// return FALSE;
break;
}
@ -1117,7 +1114,7 @@ Boolean IsRegisterConstant(DWORD Reg, DWORD * Constant)
break;
default:
// CompilerWarning("Unkown opcode in IsRegisterConstant\n%s",RSPOpcodeName(RspOp.Hex,PC));
// CompilerWarning("Unknown opcode in IsRegisterConstant\n%s",RSPOpcodeName(RspOp.Hex,PC));
// return FALSE;
break;
}
@ -1141,7 +1138,7 @@ Boolean IsRegisterConstant(DWORD Reg, DWORD * Constant)
case RSP_SC2:
break;
default:
// CompilerWarning("Unkown opcode in IsRegisterConstant\n%s",RSPOpcodeName(RspOp.Hex,PC));
// CompilerWarning("Unknown opcode in IsRegisterConstant\n%s",RSPOpcodeName(RspOp.Hex,PC));
// return FALSE;
break;
}
@ -1162,13 +1159,12 @@ Boolean IsRegisterConstant(DWORD Reg, DWORD * Constant)
** Output:
** TRUE: opcode is a branch
** FALSE: opcode is not a branch
**
** Input: PC
*************************************************************/
Boolean IsOpcodeBranch(DWORD PC, OPCODE RspOp)
{
PC = PC; // unused
PC = PC; // Unused
switch (RspOp.op) {
case RSP_REGIMM:
@ -1266,31 +1262,31 @@ Boolean IsOpcodeBranch(DWORD PC, OPCODE RspOp)
** with valid opcode data
*************************************************************/
/* 3 possible values, GPR, VEC, VEC & GPR, NOOP is zero */
// 3 possible values, GPR, VEC, VEC & GPR, NOOP is zero
#define GPR_Instruction 0x0001 /* GPR Instruction flag */
#define VEC_Instruction 0x0002 /* Vec Instruction flag */
#define COPO_MF_Instruction 0x0080 /* MF Cop 0 Instruction */
#define Flag_Instruction 0x0100 /* Access Flags */
#define Instruction_Mask (GPR_Instruction | VEC_Instruction)
/* 3 possible values, one flag must be set only */
// 3 possible values, one flag must be set only
#define Load_Operation 0x0004 /* Load Instruction flag */
#define Store_Operation 0x0008 /* Store Instruction flag */
#define Accum_Operation 0x0010 /* Vector op uses accum - loads & stores dont */
#define MemOperation_Mask (Load_Operation | Store_Operation)
#define Operation_Mask (MemOperation_Mask | Accum_Operation)
/* Per situation basis flags */
// Per situation basis flags
#define VEC_ResetAccum 0x0000 /* Vector op resets acc */
#define VEC_Accumulate 0x0020 /* Vector op accumulates */
/* N/A in instruction assembler syntax, possibly an unused register specifier */
// N/A in instruction assembler syntax, possibly an unused register specifier
#define UNUSED_OPERAND ~0u
#define InvalidOpcode 0x0040
#pragma warning(push)
#pragma warning(disable : 4201) // nonstandard extension used : nameless struct/union
#pragma warning(disable : 4201) // Non-standard extension used: nameless struct/union
typedef struct {
union {
@ -1321,7 +1317,7 @@ void GetInstructionInfo(DWORD PC, OPCODE * RspOp, OPCODE_INFO * info) {
break;
default:
CompilerWarning("Unkown opcode in GetInstructionInfo\n%s",RSPOpcodeName(RspOp->Hex,PC));
CompilerWarning("Unknown opcode in GetInstructionInfo\n%s",RSPOpcodeName(RspOp->Hex,PC));
info->flags = InvalidOpcode;
break;
}
@ -1369,7 +1365,7 @@ void GetInstructionInfo(DWORD PC, OPCODE * RspOp, OPCODE_INFO * info) {
break;
default:
CompilerWarning("Unkown opcode in GetInstructionInfo\n%s",RSPOpcodeName(RspOp->Hex,PC));
CompilerWarning("Unknown opcode in GetInstructionInfo\n%s",RSPOpcodeName(RspOp->Hex,PC));
info->flags = InvalidOpcode;
break;
}
@ -1500,14 +1496,14 @@ void GetInstructionInfo(DWORD PC, OPCODE * RspOp, OPCODE_INFO * info) {
info->DestReg = RspOp->sa;
info->SourceReg0 = RspOp->rt;
info->SourceReg1 = UNUSED_OPERAND;
info->flags = VEC_Instruction | VEC_ResetAccum | Accum_Operation; /* Assume reset? */
info->flags = VEC_Instruction | VEC_ResetAccum | Accum_Operation; // Assume reset?
break;
case RSP_VECTOR_VMRG:
info->DestReg = RspOp->sa;
info->SourceReg0 = RspOp->rt;
info->SourceReg1 = RspOp->rd;
info->flags = VEC_Instruction | VEC_ResetAccum | Accum_Operation | Flag_Instruction; /* Assum reset? */
info->flags = VEC_Instruction | VEC_ResetAccum | Accum_Operation | Flag_Instruction; // Assume reset?
break;
case RSP_VECTOR_VSAW:
@ -1519,7 +1515,7 @@ void GetInstructionInfo(DWORD PC, OPCODE * RspOp, OPCODE_INFO * info) {
break;
default:
CompilerWarning("Unkown opcode in GetInstructionInfo\n%s",RSPOpcodeName(RspOp->Hex,PC));
CompilerWarning("Unknown opcode in GetInstructionInfo\n%s",RSPOpcodeName(RspOp->Hex,PC));
info->flags = InvalidOpcode;
break;
}
@ -1538,7 +1534,7 @@ void GetInstructionInfo(DWORD PC, OPCODE * RspOp, OPCODE_INFO * info) {
info->flags = GPR_Instruction | Load_Operation | Flag_Instruction;
break;
/* RD is always the vector register, RT is always GPR */
// RD is always the vector register, RT is always GPR
case RSP_COP2_MT:
info->DestReg = RspOp->rd;
info->SourceReg0 = RspOp->rt;
@ -1552,7 +1548,7 @@ void GetInstructionInfo(DWORD PC, OPCODE * RspOp, OPCODE_INFO * info) {
info->flags = VEC_Instruction | GPR_Instruction | Store_Operation;
break;
default:
CompilerWarning("Unkown opcode in GetInstructionInfo\n%s",RSPOpcodeName(RspOp->Hex,PC));
CompilerWarning("Unknown opcode in GetInstructionInfo\n%s",RSPOpcodeName(RspOp->Hex,PC));
info->flags = InvalidOpcode;
break;
}
@ -1596,7 +1592,7 @@ void GetInstructionInfo(DWORD PC, OPCODE * RspOp, OPCODE_INFO * info) {
info->flags = InvalidOpcode;
break;
default:
CompilerWarning("Unkown opcode in GetInstructionInfo\n%s",RSPOpcodeName(RspOp->Hex,PC));
CompilerWarning("Unknown opcode in GetInstructionInfo\n%s",RSPOpcodeName(RspOp->Hex,PC));
info->flags = InvalidOpcode;
break;
}
@ -1623,13 +1619,13 @@ void GetInstructionInfo(DWORD PC, OPCODE * RspOp, OPCODE_INFO * info) {
info->flags = InvalidOpcode;
break;
default:
CompilerWarning("Unkown opcode in GetInstructionInfo\n%s",RSPOpcodeName(RspOp->Hex,PC));
CompilerWarning("Unknown opcode in GetInstructionInfo\n%s",RSPOpcodeName(RspOp->Hex,PC));
info->flags = InvalidOpcode;
break;
}
break;
default:
/* CompilerWarning("Unkown opcode in GetInstructionInfo\n%s",RSPOpcodeName(RspOp->Hex,PC));
/* CompilerWarning("Unknown opcode in GetInstructionInfo\n%s",RSPOpcodeName(RspOp->Hex,PC));
*/ info->flags = InvalidOpcode;
break;
}
@ -1702,7 +1698,7 @@ Boolean CompareInstructions(DWORD PC, OPCODE * Top, OPCODE * Bottom)
CPU_Message("to %s (%X)", RSPOpcodeName ( Bottom->Hex, PC), PC);
#endif
/* usually branches and such */
// Usually branches and such
if ((info0.flags & InvalidOpcode) != 0) return FALSE;
if ((info1.flags & InvalidOpcode) != 0) return FALSE;
@ -1710,156 +1706,162 @@ Boolean CompareInstructions(DWORD PC, OPCODE * Top, OPCODE * Bottom)
InstructionType = (info0.flags & Instruction_Mask) << 2;
InstructionType |= info1.flags & Instruction_Mask;
InstructionType &= 0x0F; /* Paranoia */
InstructionType &= 0x0F; // Paranoia
/* 4 bit range, 16 possible combinations */
// 4-bit range, 16 possible combinations
switch (InstructionType) {
/*
** Detect noop instruction, 7 cases, (see flags) */
case 0x01: case 0x02: case 0x03: /* First is a noop */
// Detect NOOP instruction, 7 cases, (see flags)
case 0x01: case 0x02: case 0x03: // First is a NOOP
return TRUE;
case 0x00: /* Both ??? */
case 0x10: case 0x20: case 0x30: /* Second is a noop */
case 0x00: // Both?
case 0x10: case 0x20: case 0x30: // Second is a NOOP
return FALSE;
case 0x06: /* GPR than Vector - 01,10 */
case 0x06: // GPR then Vector - 01,10
if ((info0.flags & MemOperation_Mask) != 0 && (info1.flags & MemOperation_Mask) != 0) {
/* TODO: We have a vector & GPR memory operation */
// TODO: We have a vector and GPR memory operation
return FALSE;
} else if ((info1.flags & MemOperation_Mask) != 0) {
/* We have a vector memory operation */
// We have a vector memory operation
return (info1.IndexReg == info0.DestReg) ? FALSE : TRUE;
}
/* We could have memory or normal gpr instruction here
** paired with some kind of vector operation
*/
// We could have memory or normal GPR instruction here
// paired with some kind of vector operation
return TRUE;
case 0x0A: /* Vector than Vector - 10,10 */
case 0x0A: // Vector then Vector - 10,10
/*
** Check for Vector Store than Vector multiply (VMULF)
** Check for vector store then vector multiply (VMULF)
**
** This basically gives preferences to putting stores
** as close to the finish of an operation as possible
*/
if ((info0.flags & Store_Operation) != 0 && (info1.flags & Accum_Operation) != 0
&& !(info1.flags & VEC_Accumulate)) { return FALSE; }
/*
** Look for loads and than some kind of vector operation
** that does no accumulating, there is no reason to reorder
*/
// Look for loads and than some kind of vector operation
// that does no accumulating, there is no reason to reorder
if ((info0.flags & Load_Operation) != 0 && (info1.flags & Accum_Operation) != 0
&& !(info1.flags & VEC_Accumulate)) { return FALSE; }
if ((info0.flags & MemOperation_Mask) != 0 && (info1.flags & MemOperation_Mask) != 0) {
/*
** TODO: This is a bitch, its best to leave it alone
**/
// TODO: This is a pain, it's best to leave it alone
return FALSE;
} else if ((info1.flags & MemOperation_Mask) != 0) {
/* Remember stored reg & loaded reg are the same */
// Remember stored REG & loaded REG are the same
if (info0.DestReg == info1.DestReg) { return FALSE; }
if (info1.flags & Load_Operation) {
if (info0.SourceReg0 == info1.DestReg) { return FALSE; }
if (info0.SourceReg1 == info1.DestReg) { return FALSE; }
} else if (info1.flags & Store_Operation) {
/* It can store source regs */
// It can store source REGS
return TRUE;
}
return TRUE;
} else if ((info0.flags & MemOperation_Mask) != 0) {
/* Remember stored reg & loaded reg are the same */
// Remember stored REG & loaded REG are the same
if (info0.DestReg == info1.DestReg) { return FALSE; }
if (info0.flags & Load_Operation) {
if (info1.SourceReg0 == info0.DestReg) { return FALSE; }
if (info1.SourceReg1 == info0.DestReg) { return FALSE; }
} else if (info0.flags & Store_Operation) {
/* It can store source regs */
// It can store source REGS
return TRUE;
}
return TRUE;
} else if ((info0.flags & VEC_Accumulate) != 0) {
/*
** Example:
** VMACF
** VMUDH or VMADH or VADD
** VMACF
** VMUDH or VMADH or VADD
*/
return FALSE;
} else if ((info1.flags & VEC_Accumulate) != 0) {
/*
** Example:
** VMULF
** VMADH
** VMULF
** VMADH
*/
return FALSE;
} else {
/*
** Example:
** VMULF or VADDC
** VADD or VMUDH
** VMULF or VADDC
** VADD or VMUDH
*/
return FALSE;
}
break;
case 0x09: /* Vector than GPR - 10,01 */
/**********
** this is where the bias comes into play, otherwise
** we can sit here all day swapping these 2 types
***********/
case 0x09: // Vector then GPR - 10,01
/*
This is where the bias comes into play, otherwise
we can sit here all day swapping these 2 types
*/
return FALSE;
case 0x05: /* GPR than GPR - 01,01 */
case 0x07: /* GPR than Cop2 - 01, 11 */
case 0x0D: /* Cop2 than GPR - 11, 01 */
case 0x0F: /* Cop2 than Cop2 - 11, 11 */
case 0x05: // GPR then GPR - 01,01
case 0x07: // GPR then COP2 - 01, 11
case 0x0D: // COP2 then GPR - 11, 01
case 0x0F: // COP2 then COP2 - 11, 11
return FALSE;
case 0x0B: /* Vector than Cop2 - 10, 11 */
case 0x0B: // Vector then COP2 - 10, 11
if (info1.flags & Load_Operation) {
/* Move To Cop2 (dest) from GPR (source) */
// Move To COP2 (destination) from GPR (source)
if (info1.DestReg == info0.DestReg) { return FALSE; }
if (info1.DestReg == info0.SourceReg0) { return FALSE; }
if (info1.DestReg == info0.SourceReg1) { return FALSE; }
} else if (info1.flags & Store_Operation) {
/* Move From Cop2 (source) to GPR (dest) */
// Move From COP2 (source) to GPR (destination)
if (info1.SourceReg0 == info0.DestReg) { return FALSE; }
if (info1.SourceReg0 == info0.SourceReg0) { return FALSE; }
if (info1.SourceReg0 == info0.SourceReg1) { return FALSE; }
} else {
CompilerWarning("ReOrder: Unhandled Vector than Cop2");
CompilerWarning("Reorder: Unhandled Vector than COP2");
}
// we want vectors on top
// We want vectors on top
return FALSE;
case 0x0E: /* Cop2 than Vector - 11, 10 */
case 0x0E: // COP2 then Vector - 11, 10
if (info0.flags & Load_Operation) {
/* Move To Cop2 (dest) from GPR (source) */
// Move To COP2 (destination) from GPR (source)
if (info0.DestReg == info1.DestReg) { return FALSE; }
if (info0.DestReg == info1.SourceReg0) { return FALSE; }
if (info0.DestReg == info1.SourceReg1) { return FALSE; }
} else if (info0.flags & Store_Operation) {
/* Move From Cop2 (source) to GPR (dest) */
// Move From COP2 (source) to GPR (destination)
if (info0.SourceReg0 == info1.DestReg) { return FALSE; }
if (info0.SourceReg0 == info1.SourceReg0) { return FALSE; }
if (info0.SourceReg0 == info1.SourceReg1) { return FALSE; }
if (info0.DestReg == info1.SourceReg0) { return FALSE; }
} else {
CompilerWarning("ReOrder: Unhandled Cop2 than Vector");
CompilerWarning("Reorder: Unhandled COP2 than Vector");
}
// we want this at the top
// We want this at the top
return TRUE;
default:
CompilerWarning("ReOrder: Unhandled instruction type: %i", InstructionType);
CompilerWarning("Reorder: Unhandled instruction type: %i", InstructionType);
}
return FALSE;

89
Source/RSP/Recompiler CPU.c
View File

@ -17,10 +17,10 @@
#include "x86.h"
#include "Types.h"
#pragma warning(disable : 4152) // nonstandard extension, function/data pointer conversion in expression
#pragma warning(disable : 4152) // Non-standard extension, function/data pointer conversion in expression
/* #define REORDER_BLOCK_VERBOSE */
#define LINK_BRANCHES_VERBOSE /* no choice really */
// #define REORDER_BLOCK_VERBOSE
#define LINK_BRANCHES_VERBOSE // No choice really
#define X86_RECOMP_VERBOSE
#define BUILD_BRANCHLABELS_VERBOSE
@ -404,11 +404,10 @@ void BuildRecompilerCPU ( void ) {
/******************************************************
** ReOrderSubBlock
**
** Desc:
** this can be done, but will be interesting to put
** Description:
** This can be done, but will be interesting to put
** between branches labels, and actual branches, whichever
** occurs first in code
**
********************************************************/
void ReOrderInstructions(DWORD StartPC, DWORD EndPC) {
@ -419,12 +418,12 @@ void ReOrderInstructions(DWORD StartPC, DWORD EndPC) {
PreviousOp.Hex = *(DWORD*)(RSPInfo.IMEM + StartPC);
if (TRUE == IsOpcodeBranch(StartPC, PreviousOp)) {
/* the sub block ends here anyway */
// The sub block ends here anyway
return;
}
if (IsOpcodeNop(StartPC) && IsOpcodeNop(StartPC + 4) && IsOpcodeNop(StartPC + 8)) {
/* Dont even bother */
// Don't even bother
return;
}
@ -450,7 +449,7 @@ void ReOrderInstructions(DWORD StartPC, DWORD EndPC) {
CurrentOp.Hex = *(DWORD*)(RSPInfo.IMEM + CurrentPC);
if (TRUE == CompareInstructions(CurrentPC, &PreviousOp, &CurrentOp)) {
/* Move current opcode up */
// Move current opcode up
*(DWORD*)(RSPInfo.IMEM + CurrentPC - 4) = CurrentOp.Hex;
*(DWORD*)(RSPInfo.IMEM + CurrentPC) = PreviousOp.Hex;
@ -491,7 +490,7 @@ void ReOrderSubBlock(RSP_BLOCK * Block) {
return;
}
/* find the label or jump closest to us */
// Find the label or jump closest to us
if (RspCode.LabelCount) {
for (count = 0; count < RspCode.LabelCount; count++) {
if (RspCode.BranchLabels[count] < end && RspCode.BranchLabels[count] > Block->CurrPC) {
@ -506,17 +505,16 @@ void ReOrderSubBlock(RSP_BLOCK * Block) {
}
}
}
/* it wont actually re-order the op at the end */
// It wont actually re-order the op at the end
ReOrderInstructions(Block->CurrPC, end);
}
/******************************************************
** DetectGPRConstants
**
** Desc:
** Description:
** this needs to be called on a sub-block basis, like
** after every time we hit a branch and delay slot
**
********************************************************/
void DetectGPRConstants(RSP_CODE * code) {
@ -530,11 +528,11 @@ void DetectGPRConstants(RSP_CODE * code) {
}
CPU_Message("***** Detecting constants *****");
/* R0 is constant zero, R31 or RA is not constant */
// R0 is constant zero, R31 or RA is not constant
code->bIsRegConst[0] = TRUE;
code->MipsRegConst[0] = 0;
/* Do your global search for them */
// Do your global search for them
for (Count = 1; Count < 31; Count++) {
if (IsRegisterConstant(Count, &Constant) == TRUE) {
CPU_Message("Global: %s is a constant of: %08X", GPR_Name(Count), Constant);
@ -548,12 +546,11 @@ void DetectGPRConstants(RSP_CODE * code) {
/******************************************************
** CompilerToggleBuffer and ClearX86Code
**
** Desc:
** Description:
** 1> toggles the compiler buffer, useful for poorly
** taken branches like alignment
**
** 2> clears all the x86 code, jump tables etc
**
** 2> clears all the x86 code, jump tables etc.
********************************************************/
void CompilerToggleBuffer(void) {
@ -596,10 +593,8 @@ void ClearAllx86Code (void) {
/******************************************************
** Link Branches
**
** Desc:
** Description:
** resolves all the collected branches, x86 style
**
********************************************************/
void LinkBranches(RSP_BLOCK * Block) {
@ -624,7 +619,7 @@ void LinkBranches(RSP_BLOCK * Block) {
CPU_Message("===== (Generate Code: %04X) =====", Target);
Save = *Block;
/* compile this block and link */
// Compile this block and link
CompilerRSPBlock();
LinkBranches(Block);
@ -648,11 +643,10 @@ void LinkBranches(RSP_BLOCK * Block) {
/******************************************************
** BuildBranchLabels
**
** Desc:
** Description:
** Branch labels are used to start and stop re-ordering
** sections as well as set the jump table to points
** within a block that are safe
**
********************************************************/
void BuildBranchLabels(void) {
@ -678,9 +672,9 @@ void BuildBranchLabels(void) {
}
RspCode.BranchLocations[RspCode.BranchCount++] = i;
if (RspOp.op == RSP_SPECIAL) {
/* register jump not predictable */
// Register jump not predictable
} else if (RspOp.op == RSP_J || RspOp.op == RSP_JAL) {
/* for JAL its a sub-block for returns */
// For JAL its a sub-block for returns
Dest = (RspOp.target << 2) & 0xFFC;
RspCode.BranchLabels[RspCode.LabelCount] = Dest;
RspCode.LabelCount += 1;
@ -726,7 +720,7 @@ void CompilerLinkBlocks(void) {
CPU_Message("***** Linking block to X86: %08X *****", KnownCode);
NextInstruction = FINISH_BLOCK;
/* block linking scenario */
// Block linking scenario
JmpLabel32("Linked block", 0);
x86_SetBranch32b(RecompPos - 4, KnownCode);
}
@ -743,7 +737,7 @@ void CompilerRSPBlock(void)
CurrentBlock.StartPC = CompilePC;
CurrentBlock.CurrPC = CompilePC;
/* Align the block to a boundary */
// Align the block to a boundary
if (X86BaseAddress & 7)
{
register size_t Count;
@ -757,7 +751,7 @@ void CompilerRSPBlock(void)
CPU_Message("====== block %d ======", BlockID++);
CPU_Message("x86 code at: %X",RecompPos);
CPU_Message("Jumpt Table: %X",Table );
CPU_Message("Jump Table: %X",Table );
CPU_Message("Start of Block: %X",CurrentBlock.StartPC );
CPU_Message("====== recompiled code ======");
@ -766,29 +760,28 @@ void CompilerRSPBlock(void)
ReOrderSubBlock(&CurrentBlock);
}
/* this is for the block about to be compiled */
// This is for the block about to be compiled
*(JumpTable + (CompilePC >> 2)) = RecompPos;
do {
/*
* Re-Ordering is setup to allow us to have loop labels
* so here we see if this is one and put it in the jump table
*/
// Reordering is setup to allow us to have loop labels
// so here we see if this is one and put it in the jump table
if (NextInstruction == NORMAL && IsJumpLabel(CompilePC)) {
/* jumps come around twice */
// Jumps come around twice
if (NULL == *(JumpTable + (CompilePC >> 2))) {
CPU_Message("***** Adding Jump Table Entry for PC: %04X at X86: %08X *****", CompilePC, RecompPos);
CPU_Message("");
*(JumpTable + (CompilePC >> 2)) = RecompPos;
/* reorder from here to next label or branch */
// Reorder from here to next label or branch
CurrentBlock.CurrPC = CompilePC;
ReOrderSubBlock(&CurrentBlock);
} else if (NextInstruction != DELAY_SLOT_DONE) {
/*
* we could link the blocks here, but performance
* wise it might be better to just let it run
*/
// We could link the blocks here, but performance-wise it might be better to just let it run
}
}
@ -815,7 +808,7 @@ void CompilerRSPBlock(void)
}
if (RSPOpC.Hex == 0xFFFFFFFF) {
/* i think this pops up an unknown op dialog */
// I think this pops up an unknown OP dialog
/* NextInstruction = FINISH_BLOCK; */
} else {
RSP_Opcode[ RSPOpC.op ]();
@ -843,12 +836,12 @@ void CompilerRSPBlock(void)
if (CompilePC >= 0x1000) {
NextInstruction = FINISH_BLOCK;
} else if (NULL == *(JumpTable + (CompilePC >> 2))) {
/* this is for the new block being compiled now */
// This is for the new block being compiled now
CPU_Message("**** Continuing static SubBlock (jump table entry added for PC: %04X at X86: %08X) *****", CompilePC, RecompPos);
*(JumpTable + (CompilePC >> 2)) = RecompPos;
CurrentBlock.CurrPC = CompilePC;
/* reorder from after delay to next label or branch */
// Reorder from after delay to next label or branch
ReOrderSubBlock(&CurrentBlock);
} else {
CompilerLinkBlocks();
@ -862,7 +855,7 @@ void CompilerRSPBlock(void)
break;
}
} while (NextInstruction != FINISH_BLOCK && (CompilePC < 0x1000 || NextInstruction == DELAY_SLOT));
CPU_Message("==== end of recompiled code ====");
CPU_Message("==== End of recompiled code ====");
if (Compiler.bReOrdering == TRUE) {
memcpy(RSPInfo.IMEM, IMEM_SAVE, 0x1000);
@ -904,11 +897,9 @@ DWORD RunRecompilerCPU ( DWORD Cycles ) {
Block = *(JumpTable + (*PrgCount >> 2));
/*
** we are done compiling, but we may have references
** to fill in still either from this block, or jumps
** that go out of it, let's rock
**/
// We are done compiling, but we may have references
// to fill in still either from this block, or jumps
// that go out of it, let's rock
LinkBranches(&CurrentBlock);
if (Profiling && !IndvidualBlock) {

32
Source/RSP/Recompiler CPU.h
View File

@ -37,21 +37,21 @@ void CompilerToggleBuffer (void);
Boolean RSP_DoSections(void);
typedef struct {
DWORD StartPC, CurrPC; /* block start */
DWORD StartPC, CurrPC; // Block start
struct {
DWORD TargetPC; /* Target for this unknown branch */
DWORD * X86JumpLoc; /* Our x86 dword to fill */
} BranchesToResolve[200]; /* Branches inside or outside block */
DWORD TargetPC; // Target for this unknown branch
DWORD * X86JumpLoc; // Our x86 DWORD to fill
} BranchesToResolve[200]; // Branches inside or outside block
DWORD ResolveCount; /* Branches with NULL jump table */
DWORD ResolveCount; // Branches with NULL jump table
} RSP_BLOCK;
extern RSP_BLOCK CurrentBlock;
typedef struct {
Boolean bIsRegConst[32]; /* Boolean toggle for constant */
DWORD MipsRegConst[32]; /* Value of register 32-bit */
Boolean bIsRegConst[32]; // Boolean toggle for constant
DWORD MipsRegConst[32]; // Value of register 32-bit
DWORD BranchLabels[250];
DWORD LabelCount;
DWORD BranchLocations[250];
@ -64,15 +64,15 @@ extern RSP_CODE RspCode;
#define MipsRegConst(i) (RspCode.MipsRegConst[i])
typedef struct {
Boolean mmx, mmx2, sse; /* CPU specs and compiling */
Boolean bFlags; /* RSP Flag Analysis */
Boolean bReOrdering; /* Instruction reordering */
Boolean bSections; /* Microcode sections */
Boolean bDest; /* Vector destionation toggle */
Boolean bAccum; /* Accumulator toggle */
Boolean bGPRConstants; /* Analyze GPR constants */
Boolean bAlignVector; /* Align known vector loads */
Boolean bAudioUcode; /* Audio ucode analysis */
Boolean mmx, mmx2, sse; // CPU specs and compiling
Boolean bFlags; // RSP flag analysis
Boolean bReOrdering; // Instruction reordering
Boolean bSections; // Microcode sections
Boolean bDest; // Vector destination toggle
Boolean bAccum; // Accumulator toggle
Boolean bGPRConstants; // Analyze GPR constants
Boolean bAlignVector; // Align known vector loads
Boolean bAudioUcode; // Audio microcode analysis
} RSP_COMPILER;
extern RSP_COMPILER Compiler;

369
Source/RSP/Recompiler Ops.c
View File

@ -14,21 +14,21 @@
#include "Profiling.h"
#include "Types.h"
#pragma warning(disable : 4152) // nonstandard extension, function/data pointer conversion in expression
#pragma warning(disable : 4152) // Non-standard extension, function/data pointer conversion in expression
extern Boolean AudioHle, GraphicsHle;
UWORD32 Recp, RecpResult, SQroot, SQrootResult;
DWORD ESP_RegSave = 0, EBP_RegSave = 0;
DWORD BranchCompare = 0;
/* align option affects: sw, lh, sh */
/* align option affects: lrv, ssv, lsv */
// Align option affects: SW, LH, SH
// Align option affects: LRV, SSV, LSV
#define Compile_Immediates /* ADDI, ADDIU, ANDI, ORI, XORI, LUI */
#define Compile_GPRLoads /* LB, LH, LW, LBU, LHU */
#define Compile_GPRStores /* SB, SH, SW */
#define Compile_Special /* SLL, SRL, SRA, SRLV */
/* XOR, OR, AND, SUB, SUBU, ADDU, ADD, SLT */
#define Compile_Immediates // ADDI, ADDIU, ANDI, ORI, XORI, LUI
#define Compile_GPRLoads // LB, LH, LW, LBU, LHU
#define Compile_GPRStores // SB, SH, SW
#define Compile_Special // SLL, SRL, SRA, SRLV
// XOR, OR, AND, SUB, SUBU, ADDU, ADD, SLT
#define Compile_Cop0
#define Compile_Cop2
@ -37,16 +37,16 @@ DWORD BranchCompare = 0;
#define RSP_VectorMisc
#ifdef RSP_VectorMuls
# define CompileVmulf /* Verified 12/17/2000 - Jabo */
# define CompileVmacf /* Rewritten & Verified 12/15/2000 - Jabo */
# define CompileVmudm /* Verified 12/17/2000 - Jabo */
# define CompileVmudh /* Verified 12/17/2000 - Jabo */
# define CompileVmudn /* Verified 12/17/2000 - Jabo */
# define CompileVmudl /* Verified 12/17/2000 - Jabo */
# define CompileVmulf // Verified 12/17/2000 - Jabo
# define CompileVmacf // Rewritten and Verified 12/15/2000 - Jabo
# define CompileVmudm // Verified 12/17/2000 - Jabo
# define CompileVmudh // Verified 12/17/2000 - Jabo
# define CompileVmudn // Verified 12/17/2000 - Jabo
# define CompileVmudl // Verified 12/17/2000 - Jabo
# define CompileVmadl
# define CompileVmadm /* Verified 12/17/2000 - Jabo */
# define CompileVmadh /* Verified 12/15/2000 - Jabo */
# define CompileVmadn /* Verified 12/17/2000 - Jabo */
# define CompileVmadm // Verified 12/17/2000 - Jabo
# define CompileVmadh // Verified 12/15/2000 - Jabo
# define CompileVmadn // Verified 12/17/2000 - Jabo
#endif
#ifdef RSP_VectorMisc
# define CompileVne
@ -57,14 +57,14 @@ DWORD BranchCompare = 0;
# define CompileVrcpl
# define CompileVrsqh
# define CompileVrcph
# define CompileVsaw /* Verified 12/17/2000 - Jabo */
# define CompileVabs /* Verified 12/15/2000 - Jabo */
# define CompileVmov /* Verified 12/17/2000 - Jabo */
# define CompileVxor /* Verified 12/17/2000 - Jabo */
# define CompileVor /* Verified 12/17/2000 - Jabo */
# define CompileVand /* Verified 12/17/2000 - Jabo */
# define CompileVsub /* Verified 12/17/2000 - Jabo (watch flags) */
# define CompileVadd /* Verified 12/17/2000 - Jabo (watch flags) */
# define CompileVsaw // Verified 12/17/2000 - Jabo
# define CompileVabs // Verified 12/15/2000 - Jabo
# define CompileVmov // Verified 12/17/2000 - Jabo
# define CompileVxor // Verified 12/17/2000 - Jabo
# define CompileVor // Verified 12/17/2000 - Jabo
# define CompileVand // Verified 12/17/2000 - Jabo
# define CompileVsub // Verified 12/17/2000 - Jabo (watch flags)
# define CompileVadd // Verified 12/17/2000 - Jabo (watch flags)
# define CompileVaddc
# define CompileVsubc
# define CompileVmrg
@ -77,14 +77,14 @@ DWORD BranchCompare = 0;
# define CompileLpv
# define CompileLuv
# define CompileLhv
# define CompileSqv /* Verified 12/17/2000 - Jabo */
# define CompileSdv /* Verified 12/17/2000 - Jabo */
# define CompileSsv /* Verified 12/17/2000 - Jabo */
# define CompileLrv /* Rewritten & Verified 12/17/2000 - Jabo */
# define CompileLqv /* Verified 12/17/2000 - Jabo */
# define CompileLdv /* Verified 12/17/2000 - Jabo */
# define CompileLsv /* Verified 12/17/2000 - Jabo */
# define CompileLlv /* Verified 12/17/2000 - Jabo */
# define CompileSqv // Verified 12/17/2000 - Jabo
# define CompileSdv // Verified 12/17/2000 - Jabo
# define CompileSsv // Verified 12/17/2000 - Jabo
# define CompileLrv // Rewritten & Verified 12/17/2000 - Jabo
# define CompileLqv // Verified 12/17/2000 - Jabo
# define CompileLdv // Verified 12/17/2000 - Jabo
# define CompileLsv // Verified 12/17/2000 - Jabo
# define CompileLlv // Verified 12/17/2000 - Jabo
# define CompileSlv
#endif
@ -118,11 +118,11 @@ void Cheat_r4300iOpcodeNoMessage(p_func FunctAddress, char * FunctName) {
}
void x86_SetBranch8b(void * JumpByte, void * Destination) {
/* calculate 32-bit relative offset */
// Calculate 32-bit relative offset
size_t n = (BYTE*)Destination - ((BYTE*)JumpByte + 1);
SSIZE_T signed_n = (SSIZE_T)n;
/* check limits, no pun intended */
// Check limits, no pun intended
if (signed_n > +128 || signed_n < -127) {
CompilerWarning(
"FATAL: Jump out of 8b range %i (PC = %04X)", n, CompilePC
@ -158,7 +158,8 @@ void CompileBranchExit(DWORD TargetPC, DWORD ContinuePC)
Ret();
}
/************************* OpCode functions *************************/
// OpCode functions
void Compile_SPECIAL ( void ) {
RSP_Special[ RSPOpC.funct ]();
}
@ -191,7 +192,7 @@ void Compile_JAL ( void ) {
MoveConstToVariable(CompilePC + 8, &RSP_GPR[31].UW, "RA.W");
NextInstruction = DO_DELAY_SLOT;
} else if ( NextInstruction == DELAY_SLOT_DONE ) {
// before we branch quickly update our stats
// Before we branch quickly update our stats
if (Profiling && IndvidualBlock)
{
char Str[40];
@ -260,7 +261,7 @@ void Compile_BEQ(void)
}
JeLabel32("BranchEqual", 0);
} else {
/* take a look at the branch compare variable */
// Take a look at the branch compare variable
CompConstToVariable(TRUE, &BranchCompare, "BranchCompare");
JeLabel32("BranchEqual", 0);
}
@ -320,7 +321,7 @@ void Compile_BNE(void)
}
JneLabel32("BranchNotEqual", 0);
} else {
/* take a look at the branch compare variable */
// Take a look at the branch compare variable
CompConstToVariable(TRUE, &BranchCompare, "BranchCompare");
JeLabel32("BranchNotEqual", 0);
}
@ -366,7 +367,7 @@ void Compile_BLEZ(void)
CompConstToVariable(0,&RSP_GPR[RSPOpC.rs].W,GPR_Name(RSPOpC.rs));
JleLabel32("BranchLessEqual", 0);
} else {
/* take a look at the branch compare variable */
// Take a look at the branch compare variable
CompConstToVariable(TRUE, &BranchCompare, "BranchCompare");
JeLabel32("BranchLessEqual", 0);
}
@ -411,7 +412,7 @@ void Compile_BGTZ(void)
CompConstToVariable(0,&RSP_GPR[RSPOpC.rs].W,GPR_Name(RSPOpC.rs));
JgLabel32("BranchGreater", 0);
} else {
/* take a look at the branch compare variable */
// Take a look at the branch compare variable
CompConstToVariable(TRUE, &BranchCompare, "BranchCompare");
JeLabel32("BranchGreater", 0);
}
@ -858,9 +859,8 @@ void Compile_LHU ( void ) {
}
}
/*
* should really just do it by bytes but whatever for now
*/
// TODO: Should really just do it by bytes but whatever for now
MoveVariableToX86reg(&RSP_GPR[RSPOpC.base].UW, GPR_Name(RSPOpC.base), x86_EBX);
if (Offset != 0) {
AddConstToX86Reg(x86_EBX, Offset);
@ -1010,7 +1010,7 @@ void Compile_SW ( void ) {
if ((Addr & 3) != 0) {
if (Addr > 0xFFC) {
DisplayError("hmmmm.... Problem with:\nRSP_SW_DMEM");
DisplayError("There is a problem with:\nRSP_SW_DMEM");
return;
}
if (IsRegConst(RSPOpC.rt) == TRUE) {
@ -1101,7 +1101,8 @@ void Compile_LC2 (void) {
void Compile_SC2 (void) {
RSP_Sc2 [ RSPOpC.rd ]();
}
/********************** R4300i OpCodes: Special **********************/
// R4300i OpCodes: Special
void Compile_Special_SLL ( void ) {
#ifndef Compile_Special
@ -1188,7 +1189,7 @@ void Compile_Special_JR (void) {
if ( NextInstruction == NORMAL ) {
CPU_Message(" %X %s",CompilePC,RSPOpcodeName(RSPOpC.Hex,CompilePC));
/* transfer destination to location pointed to by PrgCount */
// Transfer destination to location pointed to by PrgCount
MoveVariableToX86reg(&RSP_GPR[RSPOpC.rs].W,GPR_Name(RSPOpC.rs),x86_EAX);
AndConstToX86Reg(x86_EAX,0xFFC);
MoveX86regToVariable(x86_EAX,PrgCount,"RSP PC");
@ -1211,7 +1212,7 @@ void Compile_Special_JR (void) {
JeLabel8("Null", 0);
Jump = RecompPos - 1;
// before we branch quickly update our stats
// Before we branch quickly update our stats
/*if (CompilePC == 0x080) {
Pushad();
Call_Direct(UpdateAudioTimer, "UpdateAudioTimer");
@ -1499,7 +1500,8 @@ void Compile_Special_SLTU ( void ) {
Cheat_r4300iOpcode(RSP_Special_SLTU,"RSP_Special_SLTU");
}
/********************** R4300i OpCodes: RegImm **********************/
// R4300i OpCodes: RegImm
void Compile_RegImm_BLTZ(void)
{
static Boolean bDelayAffect;
@ -1529,7 +1531,7 @@ void Compile_RegImm_BLTZ(void)
CompConstToVariable(0,&RSP_GPR[RSPOpC.rs].W,GPR_Name(RSPOpC.rs));
JlLabel32("BranchLess", 0);
} else {
/* take a look at the branch compare variable */
// Take a look at the branch compare variable
CompConstToVariable(TRUE, &BranchCompare, "BranchCompare");
JeLabel32("BranchLess", 0);
}
@ -1575,7 +1577,7 @@ void Compile_RegImm_BGEZ(void)
CompConstToVariable(0,&RSP_GPR[RSPOpC.rs].W,GPR_Name(RSPOpC.rs));
JgeLabel32("BranchGreaterEqual", 0);
} else {
/* take a look at the branch compare variable */
// Take a look at the branch compare variable
CompConstToVariable(TRUE, &BranchCompare, "BranchCompare");
JeLabel32("BranchGreaterEqual", 0);
}
@ -1609,7 +1611,7 @@ void Compile_RegImm_BLTZAL ( void ) {
return;
}
/* take a look at the branch compare variable */
// Take a look at the branch compare variable
CompConstToVariable(TRUE, &BranchCompare, "BranchCompare");
JeLabel32("BranchLessEqual", 0);
Branch_AddRef(Target, (DWORD*)(RecompPos - 4));
@ -1655,7 +1657,7 @@ void Compile_RegImm_BGEZAL(void)
CompConstToVariable(0,&RSP_GPR[RSPOpC.rs].W,GPR_Name(RSPOpC.rs));
JgeLabel32("BranchGreaterEqual", 0);
} else {
/* take a look at the branch compare variable */
// Take a look at the branch compare variable
CompConstToVariable(TRUE, &BranchCompare, "BranchCompare");
JeLabel32("BranchGreaterEqual", 0);
}
@ -1670,7 +1672,7 @@ void Compile_RegImm_BGEZAL(void)
}
}
/************************** Cop0 functions *************************/
// COP0 functions
void Compile_Cop0_MF ( void ) {
CPU_Message(" %X %s",CompilePC,RSPOpcodeName(RSPOpC.Hex,CompilePC));
@ -1904,7 +1906,8 @@ void Compile_Cop0_MT ( void )
x86_SetBranch8b(Jump, RecompPos);
}
}
/************************** Cop2 functions *************************/
// COP2 functions
void Compile_Cop2_MF ( void ) {
char Reg[256];
@ -2034,7 +2037,7 @@ void Compile_COP2_VECTOR (void) {
RSP_Vector[ RSPOpC.funct ]();
}
/************************** Vect functions **************************/
// Vector functions
UDWORD MMX_Scratch;
@ -2087,17 +2090,16 @@ void RSP_MultiElement2Mmx(int MmxReg1, int MmxReg2) {
DWORD Rs = RSPOpC.rs & 0x0f;
/*
* Ok, this is tricky, hopefully this clears it up:
* OK, this is tricky, hopefully this clears it up:
*
* $vd[0] = $vd[0] + $vt[2]
* because of swapped registers becomes:
* $vd[7] = $vd[7] + $vt[5]
*
* we must perform this swap correctly, this involves the 3-bit
* xclusive or, 2-bits of which are done within a dword boundary,
* We must perform this swap correctly, this involves the 3-bit
* exclusive or, 2-bits of which are done within a DWORD boundary,
* the last bit, is ignored because we are loading the source linearly,
* so the xclusive or has transparently happened on that side
*
* so the exclusive or has transparently happened on that side
*/
switch (Rs) {
@ -2163,13 +2165,13 @@ Boolean Compile_Vector_VMULF_MMX(void)
{
char Reg[256];
/* Do our MMX checks here */
// Do our MMX checks here
if (IsMmxEnabled == FALSE)
return FALSE;
if ((RSPOpC.rs & 0x0f) >= 2 && !(RSPOpC.rs & 8) && IsMmx2Enabled == FALSE)
return FALSE;
/* NOTE: Problem here is the lack of +/- 0x8000 rounding */
// NOTE: Problem here is the lack of +/- 0x8000 rounding
sprintf(Reg, "RSP_Vect[%i].UHW[0]", RSPOpC.rd);
MmxMoveQwordVariableToReg(x86_MM0, &RSP_Vect[RSPOpC.rd].UHW[0], Reg);
sprintf(Reg, "RSP_Vect[%i].UHW[4]", RSPOpC.rd);
@ -2264,7 +2266,7 @@ void Compile_Vector_VMULF ( void ) {
if (bWriteToAccum == TRUE) {
MoveX86regToVariable(x86_EAX, &RSP_ACCUM[el].HW[1], "RSP_ACCUM[el].HW[1]");
/* calculate sign extension into edx */
// Calculate sign extension into EDX
MoveX86RegToX86Reg(x86_EAX, x86_EDX);
ShiftRightSignImmed(x86_EDX, 31);
}
@ -2291,7 +2293,7 @@ Boolean Compile_Vector_VMUDL_MMX(void)
{
char Reg[256];
/* Do our MMX checks here */
// Do our MMX checks here
if (IsMmxEnabled == FALSE)
return FALSE;
if (IsMmx2Enabled == FALSE)
@ -2398,7 +2400,7 @@ Boolean Compile_Vector_VMUDM_MMX(void)
{
char Reg[256];
/* Do our MMX checks here */
// Do our MMX checks here
if (IsMmxEnabled == FALSE)
return FALSE;
if (IsMmx2Enabled == FALSE)
@ -2415,7 +2417,7 @@ Boolean Compile_Vector_VMUDM_MMX(void)
sprintf(Reg, "RSP_Vect[%i].UHW[4]", RSPOpC.rt);
MmxMoveQwordVariableToReg(x86_MM5, &RSP_Vect[RSPOpC.rt].UHW[4], Reg);
/* Copy the signed portion */
// Copy the signed portion
MmxMoveRegToReg(x86_MM2, x86_MM0);
MmxMoveRegToReg(x86_MM3, x86_MM1);
@ -2431,7 +2433,7 @@ Boolean Compile_Vector_VMUDM_MMX(void)
} else if (RSPOpC.rs & 8) {
RSP_Element2Mmx(x86_MM4);
/* Copy the signed portion */
// Copy the signed portion
MmxMoveRegToReg(x86_MM2, x86_MM0);
MmxMoveRegToReg(x86_MM3, x86_MM1);
@ -2447,7 +2449,7 @@ Boolean Compile_Vector_VMUDM_MMX(void)
} else {
RSP_MultiElement2Mmx(x86_MM4, x86_MM5);
/* Copy the signed portion */
// Copy the signed portion
MmxMoveRegToReg(x86_MM2, x86_MM0);
MmxMoveRegToReg(x86_MM3, x86_MM1);
@ -2462,7 +2464,7 @@ Boolean Compile_Vector_VMUDM_MMX(void)
MmxPmullwRegToReg(x86_MM3, x86_MM5);
}
/* Add them up */
// Add them up
MmxPaddwRegToReg(x86_MM0, x86_MM2);
MmxPaddwRegToReg(x86_MM1, x86_MM3);
@ -2565,7 +2567,7 @@ Boolean Compile_Vector_VMUDN_MMX(void)
{
char Reg[256];
/* Do our MMX checks here */
// Do our MMX checks here
if (IsMmxEnabled == FALSE)
return FALSE;
if ((RSPOpC.rs & 0x0f) >= 2 && !(RSPOpC.rs & 8) && IsMmx2Enabled == FALSE)
@ -2669,7 +2671,7 @@ Boolean Compile_Vector_VMUDH_MMX(void)
{
char Reg[256];
/* Do our MMX checks here */
// Do our MMX checks here
if (IsMmxEnabled == FALSE)
return FALSE;
if ((RSPOpC.rs & 0x0f) >= 2 && !(RSPOpC.rs & 8) && IsMmx2Enabled == FALSE)
@ -2680,7 +2682,7 @@ Boolean Compile_Vector_VMUDH_MMX(void)
sprintf(Reg, "RSP_Vect[%i].HW[4]", RSPOpC.rd);
MmxMoveQwordVariableToReg(x86_MM1, &RSP_Vect[RSPOpC.rd].HW[4], Reg);
/* Registers 4 & 5 are high */
// Registers 4 and 5 are high
MmxMoveRegToReg(x86_MM4, x86_MM0);
MmxMoveRegToReg(x86_MM5, x86_MM1);
@ -2717,7 +2719,7 @@ Boolean Compile_Vector_VMUDH_MMX(void)
MmxPmulhwRegToReg(x86_MM5, x86_MM3);
}
/* 0 & 1 are low, 4 & 5 are high */
// 0 and 1 are low, 4 and 5 are high
MmxMoveRegToReg(x86_MM6, x86_MM0);
MmxMoveRegToReg(x86_MM7, x86_MM1);
@ -2726,7 +2728,7 @@ Boolean Compile_Vector_VMUDH_MMX(void)
MmxUnpackLowWord(x86_MM1, x86_MM5);
MmxUnpackHighWord(x86_MM7, x86_MM5);
/* Integrate copies */
// Integrate copies
MmxPackSignedDwords(x86_MM0, x86_MM6);
MmxPackSignedDwords(x86_MM1, x86_MM7);
@ -2764,14 +2766,14 @@ void Compile_Vector_VMUDH ( void ) {
Push(x86_EBP);
sprintf(Reg, "RSP_Vect[%i].HW[0]", RSPOpC.rd);
/* Load source */
// Load source
del = (RSPOpC.rs & 0x07) ^ 7;
sprintf(Reg, "RSP_Vect[%i].HW[%i]", RSPOpC.rt, del);
MoveSxVariableToX86regHalf(&RSP_Vect[RSPOpC.rt].HW[del], Reg, x86_EBX);
/*
* Pipe lined segment 0
*/
// Pipe lined segment 0
sprintf(Reg, "RSP_Vect[%i].HW[0]", RSPOpC.rd);
MoveOffsetToX86reg((size_t)&RSP_Vect[RSPOpC.rd].HW[0], Reg, x86_EBP);
@ -2798,9 +2800,9 @@ void Compile_Vector_VMUDH ( void ) {
MoveX86RegToX86regPointerDisp(x86_EDX, x86_EBP, 24);
MoveX86RegToX86regPointerDisp(x86_ESI, x86_EBP, 28);
/*
* Pipe lined segment 1
*/
// Pipe lined segment 1
sprintf(Reg, "RSP_Vect[%i].HW[0]", RSPOpC.rd);
MoveOffsetToX86reg((size_t)&RSP_Vect[RSPOpC.rd].HW[0], Reg, x86_EBP);
@ -2835,9 +2837,9 @@ void Compile_Vector_VMUDH ( void ) {
MoveSxVariableToX86regHalf(&RSP_Vect[RSPOpC.rt].HW[del], Reg, x86_EBX);
}
if (bWriteToDest == TRUE) {
/*
* Prepare for conditional moves
*/
// Prepare for conditional moves
MoveConstToX86reg(0x00007fff, x86_ESI);
MoveConstToX86reg(0xFFFF8000, x86_EDI);
}
@ -2888,9 +2890,9 @@ void Compile_Vector_VMACF ( void ) {
CPU_Message(" %X %s",CompilePC,RSPOpcodeName(RSPOpC.Hex,CompilePC));
if (bWriteToDest == TRUE) {
/*
* Prepare for conditional moves
*/
// Prepare for conditional moves
MoveConstToX86reg(0x00007fff, x86_ESI);
MoveConstToX86reg(0xFFFF8000, x86_EDI);
}
@ -2965,9 +2967,9 @@ void Compile_Vector_VMADL ( void ) {
}
if (bWriteToDest == TRUE) {
/*
* Prepare for conditional moves
*/
// Prepare for conditional moves
MoveConstToX86reg(0x00007FFF, x86_ESI);
MoveConstToX86reg(0xFFFF8000, x86_EDI);
@ -3033,9 +3035,9 @@ void Compile_Vector_VMADM ( void ) {
MoveZxVariableToX86regHalf(&RSP_Vect[RSPOpC.rt].HW[del], Reg, x86_EBX);
}
if (bWriteToDest == TRUE) {
/*
* Prepare for conditional moves
*/
// Prepare for conditional moves
MoveConstToX86reg(0x00007fff, x86_ESI);
MoveConstToX86reg(0xFFFF8000, x86_EDI);
}
@ -3079,7 +3081,7 @@ void Compile_Vector_VMADM ( void ) {
AdcX86regToVariable(x86_EDX, &RSP_ACCUM[el].W[1], "RSP_ACCUM[el].W[1]");
if (bWriteToDest == TRUE) {
/* For compare */
// For compare
sprintf(Reg, "RSP_ACCUM[%i].W[1]", el);
MoveVariableToX86reg(&RSP_ACCUM[el].W[1], "RSP_ACCUM[el].W[1]", x86_EAX);
@ -3116,9 +3118,9 @@ void Compile_Vector_VMADN ( void ) {
MoveSxVariableToX86regHalf(&RSP_Vect[RSPOpC.rt].HW[del], Reg, x86_EBX);
}
if (bWriteToDest == TRUE) {
/*
* Prepare for conditional moves
*/
// Prepare for conditional moves
MoveConstToX86reg(0x0000ffff, x86_ESI);
MoveConstToX86reg(0x00000000, x86_EDI);
}
@ -3150,15 +3152,15 @@ void Compile_Vector_VMADN ( void ) {
AdcX86regToVariable(x86_EDX, &RSP_ACCUM[el].W[1], "RSP_ACCUM[el].W[1]");
if (bWriteToDest == TRUE) {
/* For compare */
// For compare
sprintf(Reg, "RSP_ACCUM[%i].W[1]", el);
MoveVariableToX86reg(&RSP_ACCUM[el].W[1], Reg, x86_EAX);
/* For vector */
// For vector
sprintf(Reg, "RSP_ACCUM[%i].HW[1]", el);
MoveVariableToX86regHalf(&RSP_ACCUM[el].HW[1], Reg, x86_ECX);
/* Weird eh */
// TODO: Weird eh?
CompConstToX86reg(x86_EAX, 0x7fff);
CondMoveGreater(x86_ECX, x86_ESI);
CompConstToX86reg(x86_EAX, (DWORD)(-0x8000));
@ -3191,9 +3193,9 @@ void Compile_Vector_VMADH ( void ) {
}
if (bWriteToDest == TRUE) {
/*
* Prepare for conditional moves
*/
// Prepare for conditional moves
MoveConstToX86reg(0x00007fff, x86_ESI);
MoveConstToX86reg(0xFFFF8000, x86_EDI);
}
@ -3203,9 +3205,9 @@ void Compile_Vector_VMADH ( void ) {
sprintf(Reg, "RSP_Vect[%i].HW[0]", RSPOpC.rd);
MoveOffsetToX86reg((size_t)&RSP_Vect[RSPOpC.rd].HW[0], Reg, x86_EBP);
/*
* Pipe lined segment 0
*/
// Pipe lined segment 0
MoveSxX86RegPtrDispToX86RegHalf(x86_EBP, 0, x86_EAX);
MoveSxX86RegPtrDispToX86RegHalf(x86_EBP, 2, x86_ECX);
MoveSxX86RegPtrDispToX86RegHalf(x86_EBP, 4, x86_EDI);
@ -3225,9 +3227,8 @@ void Compile_Vector_VMADH ( void ) {
sprintf(Reg, "RSP_ACCUM[%i].W[1]", 3);
AddX86regToVariable(x86_ESI, &RSP_ACCUM[3].W[1], Reg);
/*
* Pipe lined segment 1
*/
// Pipe lined segment 1
MoveSxX86RegPtrDispToX86RegHalf(x86_EBP, 8, x86_EAX);
MoveSxX86RegPtrDispToX86RegHalf(x86_EBP, 10, x86_ECX);
MoveSxX86RegPtrDispToX86RegHalf(x86_EBP, 12, x86_EDI);
@ -3304,7 +3305,7 @@ Boolean Compile_Vector_VADD_MMX(void)
{
char Reg[256];
/* Do our MMX checks here */
// Do our MMX checks here
if (IsMmxEnabled == FALSE)
return FALSE;
if ((RSPOpC.rs & 0x0f) >= 2 && !(RSPOpC.rs & 8) && IsMmx2Enabled == FALSE)
@ -3373,14 +3374,14 @@ void Compile_Vector_VADD ( void ) {
MoveSxVariableToX86regHalf(&RSP_Vect[RSPOpC.rt].HW[del], Reg, x86_EBX);
}
if (bWriteToDest == TRUE) {
/*
* Prepare for conditional moves
*/
// Prepare for conditional moves
MoveConstToX86reg(0x00007fff, x86_ESI);
MoveConstToX86reg(0xffff8000, x86_EDI);
}
/* Used for involking x86 carry flag */
// Used for invoking x86 carry flag
XorX86RegToX86Reg(x86_ECX, x86_ECX);
Push(x86_EBP);
MoveVariableToX86reg(&RSP_Flags[0].UW, "RSP_Flags[0].UW", x86_EBP);
@ -3426,7 +3427,7 @@ Boolean Compile_Vector_VSUB_MMX(void)
{
char Reg[256];
/* Do our MMX checks here */
// Do our MMX checks here
if (IsMmxEnabled == FALSE)
return FALSE;
if ((RSPOpC.rs & 0x0f) >= 2 && !(RSPOpC.rs & 8) && IsMmx2Enabled == FALSE)
@ -3490,7 +3491,7 @@ void Compile_Vector_VSUB ( void ) {
Push(x86_EBP);
/* Used for involking the x86 carry flag */
// Used for invoking the x86 carry flag
XorX86RegToX86Reg(x86_ECX, x86_ECX);
MoveVariableToX86reg(&RSP_Flags[0].UW, "RSP_Flags[0].UW", x86_EBP);
@ -3501,9 +3502,9 @@ void Compile_Vector_VSUB ( void ) {
}
if (bWriteToDest == TRUE) {
/*
* Prepare for conditional moves
*/
// Prepare for conditional moves
MoveConstToX86reg(0x00007fff, x86_ESI);
MoveConstToX86reg(0xffff8000, x86_EDI);
}
@ -3549,7 +3550,7 @@ Boolean Compile_Vector_VABS_MMX(void)
{
char Reg[256];
/* Do our MMX checks here */
// Do our MMX checks here
if (IsMmxEnabled == FALSE)
return FALSE;
if ((RSPOpC.rs & 0x0f) >= 2 && !(RSPOpC.rs & 8) && IsMmx2Enabled == FALSE)
@ -3646,21 +3647,18 @@ void Compile_Vector_VABS ( void ) {
del = EleSpec[RSPOpC.rs].B[el];
if (RSPOpC.rd == RSPOpC.rt && (RSPOpC.rs & 0xF) < 2) {
/**
** Optimize: EDI/ESI unused, and ECX is const etc
***/
// Optimize: EDI/ESI unused, and ECX is CONST etc.
sprintf(Reg, "RSP_Vect[%i].HW[%i]", RSPOpC.rd, el);
MoveSxVariableToX86regHalf(&RSP_Vect[RSPOpC.rd].HW[el], Reg, x86_EAX);
/*** Obtain the negative of the source ****/
// Obtain the negative of the source
MoveX86RegToX86Reg(x86_EAX, x86_EBX);
NegateX86reg(x86_EBX);
/**
** determine negative value,
** note: negate(FFFF8000h) == 00008000h
***/
// Determine negative value,
// Note: negate(FFFF8000h) == 00008000h
MoveConstToX86reg(0x7fff, x86_ECX);
CompConstToX86reg(x86_EBX, 0x00008000);
@ -3679,23 +3677,20 @@ void Compile_Vector_VABS ( void ) {
MoveX86regHalfToVariable(x86_EAX, &RSP_ACCUM[el].HW[1], Reg);
}
} else {
/**
** Optimize: ESI unused, and EDX is const etc
***/
// Optimize: ESI unused, and EDX is CONST etc.
sprintf(Reg, "RSP_Vect[%i].HW[%i]", RSPOpC.rd, el);
MoveSxVariableToX86regHalf(&RSP_Vect[RSPOpC.rd].HW[el], Reg, x86_EAX);
sprintf(Reg, "RSP_Vect[%i].HW[%i]", RSPOpC.rt, del);
MoveSxVariableToX86regHalf(&RSP_Vect[RSPOpC.rt].HW[del], Reg, x86_EBX);
/*** Obtain the negative of the source ****/
// Obtain the negative of the source
MoveX86RegToX86Reg(x86_EBX, x86_ECX);
NegateX86reg(x86_EBX);
/**
** determine negative value,
** note: negate(FFFF8000h) == 00008000h
***/
// Determine negative value,
// Note: negate(FFFF8000h) == 00008000h
MoveConstToX86reg(0x7fff, x86_EDX);
CompConstToX86reg(x86_EBX, 0x00008000);
@ -3738,7 +3733,7 @@ void Compile_Vector_VADDC ( void ) {
MoveZxVariableToX86regHalf(&RSP_Vect[RSPOpC.rt].HW[del], Reg, x86_EBX);
}
/* Initialize flag register */
// Initialize flag register
XorX86RegToX86Reg(x86_ECX, x86_ECX);
Push(x86_EBP);
@ -3803,7 +3798,7 @@ void Compile_Vector_VSUBC ( void ) {
MoveZxVariableToX86regHalf(&RSP_Vect[RSPOpC.rt].HW[del], Reg, x86_EBX);
}
/* Initialize flag register */
// Initialize flag register
XorX86RegToX86Reg(x86_ECX, x86_ECX);
for (count = 0; count < 8; count++) {
@ -4164,7 +4159,7 @@ void Compile_Vector_VGE(void)
{ /*
Boolean bWriteToAccum = WriteToAccum(Low16BitAccum, CompilePC);
/* FIXME: works ok, but needs careful flag analysis */
/* TODO: works ok, but needs careful flag analysis */
/* #if defined (DLIST)
if (bWriteToAccum == FALSE && TRUE == Compile_Vector_VGE_MMX()) {
return;
@ -4315,7 +4310,7 @@ Boolean Compile_Vector_VAND_MMX(void)
{
char Reg[256];
/* Do our MMX checks here */
// Do our MMX checks here
if (IsMmxEnabled == FALSE)
return FALSE;
if ((RSPOpC.rs & 0x0f) >= 2 && !(RSPOpC.rs & 8) && IsMmx2Enabled == FALSE)
@ -4409,7 +4404,7 @@ Boolean Compile_Vector_VNAND_MMX(void)
{
char Reg[256];
/* Do our MMX checks here */
// Do our MMX checks here
if (IsMmxEnabled == FALSE)
return FALSE;
if ((RSPOpC.rs & 0x0f) >= 2 && !(RSPOpC.rs & 8) && IsMmx2Enabled == FALSE)
@ -4507,7 +4502,7 @@ Boolean Compile_Vector_VOR_MMX(void)
{
char Reg[256];
/* Do our MMX checks here */
// Do our MMX checks here
if (IsMmxEnabled == FALSE)
return FALSE;
if ((RSPOpC.rs & 0x0f) >= 2 && !(RSPOpC.rs & 8) && IsMmx2Enabled == FALSE)
@ -4598,7 +4593,7 @@ Boolean Compile_Vector_VNOR_MMX(void)
{
char Reg[256];
/* Do our MMX checks here */
// Do our MMX checks here
if (IsMmxEnabled == FALSE)
return FALSE;
if ((RSPOpC.rs & 0x0f) >= 2 && !(RSPOpC.rs & 8) && IsMmx2Enabled == FALSE)
@ -4692,7 +4687,7 @@ Boolean Compile_Vector_VXOR_MMX(void)
{
char Reg[256];
/* Do our MMX checks here */
// Do our MMX checks here
if (IsMmxEnabled == FALSE)
return FALSE;
if ((RSPOpC.rs & 0x0f) >= 2 && !(RSPOpC.rs & 8) && IsMmx2Enabled == FALSE)
@ -4773,7 +4768,7 @@ Boolean Compile_Vector_VNXOR_MMX(void)
{
char Reg[256];
/* Do our MMX checks here */
// Do our MMX checks here
if (IsMmxEnabled == FALSE)
return FALSE;
if ((RSPOpC.rs & 0x0f) >= 2 && !(RSPOpC.rs & 8) && IsMmx2Enabled == FALSE)
@ -5114,7 +5109,7 @@ void Compile_Vector_VNOOP ( void ) {
}
/************************** lc2 functions **************************/
// LC2 functions
void Compile_Opcode_LBV ( void ) {
char Reg[256];
@ -5238,9 +5233,9 @@ void Compile_Opcode_LLV ( void ) {
JneLabel32("Unaligned", 0);
Jump[0] = RecompPos - 4;
/*
* Unaligned
*/
// Unaligned
CompilerToggleBuffer();
CPU_Message(" Unaligned:");
@ -5250,13 +5245,12 @@ void Compile_Opcode_LLV ( void ) {
Jump[1] = RecompPos - 4;
CompilerToggleBuffer();
/*
* Aligned
*/
// Aligned
AndConstToX86Reg(x86_EBX, 0x0fff);
MoveN64MemToX86reg(x86_EAX, x86_EBX);
/* Because of byte swapping this swizzle works nicely */
// Because of byte swapping this swizzle works nicely
sprintf(Reg, "RSP_Vect[%i].B[%i]", RSPOpC.rt, 16 - RSPOpC.del - 4);
MoveX86regToVariable(x86_EAX, &RSP_Vect[RSPOpC.rt].B[16 - RSPOpC.del - 4], Reg);
@ -5275,7 +5269,7 @@ void Compile_Opcode_LDV ( void ) {
CPU_Message(" %X %s",CompilePC,RSPOpcodeName(RSPOpC.Hex,CompilePC));
/* FIXME: Conker's hits this */
// TODO: Conker's hits this
//if ((RSPOpC.del & 0x7) != 0) {
// rsp_UnknownOpcode();
// return;
@ -5344,9 +5338,9 @@ void Compile_Opcode_LDV ( void ) {
XorConstToX86Reg(x86_EAX, 3);
MoveN64MemToX86regByte(x86_EDX, x86_EAX);
MoveX86regByteToX86regPointer(x86_EDX, x86_EDI);
IncX86reg(x86_EBX); /* address constant */
DecX86reg(x86_EDI); /* vector pointer */
DecX86reg(x86_ECX); /* counter */
IncX86reg(x86_EBX); // Address constant
DecX86reg(x86_EDI); // Vector pointer
DecX86reg(x86_ECX); // Counter
JneLabel8("Loop", 0);
x86_SetBranch8b(RecompPos - 1, LoopEntry);
@ -5357,7 +5351,7 @@ void Compile_Opcode_LDV ( void ) {
MoveN64MemToX86reg(x86_EAX, x86_EBX);
MoveN64MemDispToX86reg(x86_ECX, x86_EBX, 4);
/* Because of byte swapping this swizzle works nicely */
// Because of byte swapping this swizzle works nicely
sprintf(Reg, "RSP_Vect[%i].B[%i]", RSPOpC.rt, 16 - RSPOpC.del - 4);
MoveX86regToVariable(x86_EAX, &RSP_Vect[RSPOpC.rt].B[16 - RSPOpC.del - 4], Reg);
if (RSPOpC.del != 12){
@ -5392,11 +5386,9 @@ void Compile_Opcode_LQV ( void ) {
Cheat_r4300iOpcodeNoMessage(RSP_Opcode_LQV,"RSP_Opcode_LQV");
return;
}
/*
* Aligned store
*/
// Aligned store
if (IsSseEnabled == FALSE) {
sprintf(Reg, "Dmem+%Xh+0", Addr);
MoveVariableToX86reg(RSPInfo.DMEM + Addr + 0, Reg, x86_EAX);
@ -5490,7 +5482,7 @@ void Compile_Opcode_LRV ( void ) {
JneLabel32("Unaligned", 0);
Jump[0] = RecompPos - 4;
/* Unaligned */
// Unaligned
CompilerToggleBuffer();
CPU_Message(" Unaligned:");
@ -5503,7 +5495,7 @@ void Compile_Opcode_LRV ( void ) {
CompilerToggleBuffer();
}
/* Aligned */
// Aligned
MoveX86RegToX86Reg(x86_EBX, x86_EAX);
AndConstToX86Reg(x86_EAX, 0x0F);
AndConstToX86Reg(x86_EBX, 0x0ff0);
@ -5528,9 +5520,9 @@ void Compile_Opcode_LRV ( void ) {
MoveN64MemToX86regHalf(x86_EDX, x86_ESI);
MoveX86regHalfToX86regPointer(x86_EDX, x86_EAX);
AddConstToX86Reg(x86_EBX, 2); /* Dmem pointer */
SubConstFromX86Reg(x86_EAX, 2); /* Vector pointer */
DecX86reg(x86_ECX); /* Loop counter */
AddConstToX86Reg(x86_EBX, 2); // DMEM pointer
SubConstFromX86Reg(x86_EAX, 2); // Vector pointer
DecX86reg(x86_ECX); // Loop counter
JneLabel8("Loop", 0);
x86_SetBranch8b(RecompPos - 1, Loop);
@ -5879,7 +5871,7 @@ void Compile_Opcode_LTV ( void ) {
Cheat_r4300iOpcode(RSP_Opcode_LTV,"RSP_Opcode_LTV");
}
/************************** sc2 functions **************************/
// SC2 functions
void Compile_Opcode_SBV ( void ) {
Cheat_r4300iOpcode(RSP_Opcode_SBV,"RSP_Opcode_SBV");
@ -5985,9 +5977,8 @@ void Compile_Opcode_SLV ( void ) {
JneLabel32("Unaligned", 0);
Jump[0] = RecompPos - 4;
/*
* Unaligned
*/
// Unaligned
CompilerToggleBuffer();
CPU_Message(" Unaligned:");
@ -5997,12 +5988,10 @@ void Compile_Opcode_SLV ( void ) {
Jump[1] = RecompPos - 4;
CompilerToggleBuffer();
/*
* Aligned
*/
/* Because of byte swapping this swizzle works nicely */
// Aligned
// Because of byte swapping this swizzle works nicely
sprintf(Reg, "RSP_Vect[%i].B[%i]", RSPOpC.rt, 16 - RSPOpC.del - 4);
MoveVariableToX86reg(&RSP_Vect[RSPOpC.rt].B[16 - RSPOpC.del - 4], Reg, x86_EAX);
@ -6073,9 +6062,9 @@ void Compile_Opcode_SDV ( void ) {
XorConstToX86Reg(x86_EAX, 3);
MoveX86regPointerToX86regByte(x86_EDX, x86_EDI);
MoveX86regByteToN64Mem(x86_EDX, x86_EAX);
IncX86reg(x86_EBX); /* address constant */
DecX86reg(x86_EDI); /* vector pointer */
DecX86reg(x86_ECX); /* counter */
IncX86reg(x86_EBX); // Address constant
DecX86reg(x86_EDI); // Vector pointer
DecX86reg(x86_ECX); // Counter
JneLabel8("Loop", 0);
x86_SetBranch8b(RecompPos - 1, LoopEntry);
@ -6118,11 +6107,9 @@ void Compile_Opcode_SQV ( void ) {
Cheat_r4300iOpcodeNoMessage(RSP_Opcode_SQV,"RSP_Opcode_SQV");
return;
}
/*
* Aligned store
*/
// Aligned store
if (IsSseEnabled == FALSE) {
if (RSPOpC.del == 12) {
sprintf(Reg, "RSP_Vect[%i].B[0]", RSPOpC.rt);
@ -6250,7 +6237,7 @@ void Compile_Opcode_SWV ( void ) {
Cheat_r4300iOpcode(RSP_Opcode_SWV,"RSP_Opcode_SWV");
}
/************************** Other functions **************************/
// Other functions
void Compile_UnknownOpcode (void) {
CPU_Message(" %X Unhandled Opcode: %s",CompilePC, RSPOpcodeName(RSPOpC.Hex,CompilePC) );

35
Source/RSP/Recompiler Ops.h
View File

@ -1,4 +1,5 @@
/************************* OpCode functions *************************/
// OpCode functions
void Compile_SPECIAL ( void );
void Compile_REGIMM ( void );
void Compile_J ( void );
@ -27,7 +28,9 @@ void Compile_SH ( void );
void Compile_SW ( void );
void Compile_LC2 ( void );
void Compile_SC2 ( void );
/********************** R4300i OpCodes: Special **********************/
// R4300i OpCodes: Special
void Compile_Special_SLL ( void );
void Compile_Special_SRL ( void );
void Compile_Special_SRA ( void );
@ -47,21 +50,29 @@ void Compile_Special_XOR ( void );
void Compile_Special_NOR ( void );
void Compile_Special_SLT ( void );
void Compile_Special_SLTU ( void );
/********************** R4300i OpCodes: RegImm **********************/
// R4300i OpCodes: RegImm
void Compile_RegImm_BLTZ ( void );
void Compile_RegImm_BGEZ ( void );
void Compile_RegImm_BLTZAL ( void );
void Compile_RegImm_BGEZAL ( void );
/************************** Cop0 functions *************************/
// COP0 functions
void Compile_Cop0_MF ( void );
void Compile_Cop0_MT ( void );
/************************** Cop2 functions *************************/
// COP2 functions
void Compile_Cop2_MF ( void );
void Compile_Cop2_CF ( void );
void Compile_Cop2_MT ( void );
void Compile_Cop2_CT ( void );
void Compile_COP2_VECTOR ( void );
/************************** Vect functions **************************/
// Vector functions
void Compile_Vector_VMULF ( void );
void Compile_Vector_VMULU ( void );
void Compile_Vector_VMUDL ( void );
@ -103,7 +114,9 @@ void Compile_Vector_VRSQ ( void );
void Compile_Vector_VRSQL ( void );
void Compile_Vector_VRSQH ( void );
void Compile_Vector_VNOOP ( void );
/************************** lc2 functions **************************/
// LC2 functions
void Compile_Opcode_LBV ( void );
void Compile_Opcode_LSV ( void );
void Compile_Opcode_LLV ( void );
@ -115,7 +128,9 @@ void Compile_Opcode_LUV ( void );
void Compile_Opcode_LHV ( void );
void Compile_Opcode_LFV ( void );
void Compile_Opcode_LTV ( void );
/************************** sc2 functions **************************/
// SC2 functions
void Compile_Opcode_SBV ( void );
void Compile_Opcode_SSV ( void );
void Compile_Opcode_SLV ( void );
@ -128,5 +143,7 @@ void Compile_Opcode_SHV ( void );
void Compile_Opcode_SFV ( void );
void Compile_Opcode_SWV ( void );
void Compile_Opcode_STV ( void );
/************************** Other functions **************************/
// Other functions
void Compile_UnknownOpcode (void);

199
Source/RSP/Recompiler Sections.c
View File

@ -12,15 +12,12 @@
#include "x86.h"
#include "Types.h"
#pragma warning(disable : 4152) // nonstandard extension, function/data pointer conversion in expression
#pragma warning(disable : 4152) // Non-standard extension, function/data pointer conversion in expression
void RSP_Sections_VMUDH ( OPCODE RspOp, DWORD AccumStyle ) {
char Reg[256];
/*****************************************
** VMUDH
** - affects the upper 32-bits
******************************************/
// VMUDH - affects the upper 32-bits
if (AccumStyle == Low16BitAccum) {
MmxXorRegToReg(x86_MM0, x86_MM0);
@ -30,13 +27,13 @@ void RSP_Sections_VMUDH ( OPCODE RspOp, DWORD AccumStyle ) {
RSPOpC = RspOp;
/**** Load source registers ****/
// Load source registers
sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rd);
MmxMoveQwordVariableToReg(x86_MM0, &RSP_Vect[RspOp.rd].HW[0], Reg);
sprintf(Reg, "RSP_Vect[%i].HW[4]", RspOp.rd);
MmxMoveQwordVariableToReg(x86_MM1, &RSP_Vect[RspOp.rd].HW[4], Reg);
/******* VMUDH *******/
// VMUDH
if ((RspOp.rs & 0x0f) < 2) {
sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rt);
MmxMoveQwordVariableToReg(x86_MM2, &RSP_Vect[RspOp.rt].HW[0], Reg);
@ -74,10 +71,7 @@ void RSP_Sections_VMUDH ( OPCODE RspOp, DWORD AccumStyle ) {
void RSP_Sections_VMADH ( OPCODE RspOp, DWORD AccumStyle ) {
char Reg[256];
/*****************************************
** VMADH
** - affects the upper 32-bits
******************************************/
// VMADH - affects the upper 32-bits
if (AccumStyle == Low16BitAccum) {
return;
@ -85,13 +79,13 @@ void RSP_Sections_VMADH ( OPCODE RspOp, DWORD AccumStyle ) {
RSPOpC = RspOp;
/**** Load source registers ****/
// Load source registers
sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rd);
MmxMoveQwordVariableToReg(x86_MM0 + 2, &RSP_Vect[RspOp.rd].HW[0], Reg);
sprintf(Reg, "RSP_Vect[%i].HW[4]", RspOp.rd);
MmxMoveQwordVariableToReg(x86_MM1 + 2, &RSP_Vect[RspOp.rd].HW[4], Reg);
/******* VMUDH *******/
// VMUDH
if ((RspOp.rs & 0x0f) < 2) {
sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rt);
MmxMoveQwordVariableToReg(x86_MM2 + 2, &RSP_Vect[RspOp.rt].HW[0], Reg);
@ -132,10 +126,7 @@ void RSP_Sections_VMADH ( OPCODE RspOp, DWORD AccumStyle ) {
void RSP_Sections_VMUDL ( OPCODE RspOp, DWORD AccumStyle ) {
char Reg[256];
/*****************************************
** VMUDL
** - affects the lower 16-bits
******************************************/
// VMUDL - affects the lower 16-bits
if (AccumStyle != Low16BitAccum) {
MmxXorRegToReg(x86_MM0, x86_MM0);
@ -145,13 +136,13 @@ void RSP_Sections_VMUDL ( OPCODE RspOp, DWORD AccumStyle ) {
RSPOpC = RspOp;
/**** Load source registers ****/
// Load source registers
sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rd);
MmxMoveQwordVariableToReg(x86_MM0, &RSP_Vect[RspOp.rd].HW[0], Reg);
sprintf(Reg, "RSP_Vect[%i].HW[4]", RspOp.rd);
MmxMoveQwordVariableToReg(x86_MM1, &RSP_Vect[RspOp.rd].HW[4], Reg);
/******* VMUDL *******/
// VMUDL
if ((RspOp.rs & 0x0f) < 2) {
sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rt);
MmxMoveQwordVariableToReg(x86_MM2, &RSP_Vect[RspOp.rt].HW[0], Reg);
@ -174,10 +165,7 @@ void RSP_Sections_VMUDL ( OPCODE RspOp, DWORD AccumStyle ) {
void RSP_Sections_VMADL ( OPCODE RspOp, DWORD AccumStyle ) {
char Reg[256];
/*****************************************
** VMADL
** - affects the lower 16-bits
******************************************/
// VMADL - affects the lower 16-bits
if (AccumStyle != Low16BitAccum) {
return;
@ -185,13 +173,13 @@ void RSP_Sections_VMADL ( OPCODE RspOp, DWORD AccumStyle ) {
RSPOpC = RspOp;
/**** Load source registers ****/
// Load source registers
sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rd);
MmxMoveQwordVariableToReg(x86_MM0 + 2, &RSP_Vect[RspOp.rd].HW[0], Reg);
sprintf(Reg, "RSP_Vect[%i].HW[4]", RspOp.rd);
MmxMoveQwordVariableToReg(x86_MM1 + 2, &RSP_Vect[RspOp.rd].HW[4], Reg);
/******* VMADL *******/
// VMADL
if ((RspOp.rs & 0x0f) < 2) {
sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rt);
MmxMoveQwordVariableToReg(x86_MM2 + 2, &RSP_Vect[RspOp.rt].HW[0], Reg);
@ -217,10 +205,7 @@ void RSP_Sections_VMADL ( OPCODE RspOp, DWORD AccumStyle ) {
void RSP_Sections_VMUDM ( OPCODE RspOp, DWORD AccumStyle ) {
char Reg[256];
/*****************************************
** VMUDM
** - affects the middle 32-bits, s16*u16
******************************************/
// VMUDM - affects the middle 32-bits, s16*u16
if (AccumStyle == High16BitAccum) {
MmxXorRegToReg(x86_MM0, x86_MM0);
@ -230,13 +215,13 @@ void RSP_Sections_VMUDM ( OPCODE RspOp, DWORD AccumStyle ) {
RSPOpC = RspOp;
/**** Load source registers ****/
// Load source registers
sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rd);
MmxMoveQwordVariableToReg(x86_MM0, &RSP_Vect[RspOp.rd].HW[0], Reg);
sprintf(Reg, "RSP_Vect[%i].HW[4]", RspOp.rd);
MmxMoveQwordVariableToReg(x86_MM1, &RSP_Vect[RspOp.rd].HW[4], Reg);
/******* VMUDM *******/
// VMUDM
if (AccumStyle != Middle16BitAccum) {
if ((RspOp.rs & 0x0f) < 2) {
sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rt);
@ -262,7 +247,7 @@ void RSP_Sections_VMUDM ( OPCODE RspOp, DWORD AccumStyle ) {
sprintf(Reg, "RSP_Vect[%i].UHW[4]", RSPOpC.rt);
MmxMoveQwordVariableToReg(x86_MM5, &RSP_Vect[RSPOpC.rt].UHW[4], Reg);
/* Copy the signed portion */
// Copy the signed portion
MmxMoveRegToReg(x86_MM2, x86_MM0);
MmxMoveRegToReg(x86_MM3, x86_MM1);
@ -278,7 +263,7 @@ void RSP_Sections_VMUDM ( OPCODE RspOp, DWORD AccumStyle ) {
} else if ((RSPOpC.rs & 0xF) >= 8) {
RSP_Element2Mmx(x86_MM4);
/* Copy the signed portion */
// Copy the signed portion
MmxMoveRegToReg(x86_MM2, x86_MM0);
MmxMoveRegToReg(x86_MM3, x86_MM1);
@ -294,7 +279,7 @@ void RSP_Sections_VMUDM ( OPCODE RspOp, DWORD AccumStyle ) {
} else {
RSP_MultiElement2Mmx(x86_MM4, x86_MM5);
/* Copy the signed portion */
// Copy the signed portion
MmxMoveRegToReg(x86_MM2, x86_MM0);
MmxMoveRegToReg(x86_MM3, x86_MM1);
@ -309,7 +294,7 @@ void RSP_Sections_VMUDM ( OPCODE RspOp, DWORD AccumStyle ) {
MmxPmullwRegToReg(x86_MM3, x86_MM5);
}
/* Add them up */
// Add them up
MmxPaddwRegToReg(x86_MM0, x86_MM2);
MmxPaddwRegToReg(x86_MM1, x86_MM3);
}
@ -318,10 +303,7 @@ void RSP_Sections_VMUDM ( OPCODE RspOp, DWORD AccumStyle ) {
void RSP_Sections_VMADM ( OPCODE RspOp, DWORD AccumStyle ) {
char Reg[256];
/*****************************************
** VMADM
** - affects the middle 32-bits, s16*u16
******************************************/
// VMADM - affects the middle 32-bits, s16*u16
if (AccumStyle == High16BitAccum) {
MmxXorRegToReg(x86_MM0, x86_MM0);
@ -331,13 +313,13 @@ void RSP_Sections_VMADM ( OPCODE RspOp, DWORD AccumStyle ) {
RSPOpC = RspOp;
/**** Load source registers ****/
// Load source registers
sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rd);
MmxMoveQwordVariableToReg(x86_MM0 + 2, &RSP_Vect[RspOp.rd].HW[0], Reg);
sprintf(Reg, "RSP_Vect[%i].HW[4]", RspOp.rd);
MmxMoveQwordVariableToReg(x86_MM1 + 2, &RSP_Vect[RspOp.rd].HW[4], Reg);
/******* VMADM *******/
// VMADM
if (AccumStyle != Middle16BitAccum) {
if ((RspOp.rs & 0x0f) < 2) {
sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rt);
@ -363,7 +345,7 @@ void RSP_Sections_VMADM ( OPCODE RspOp, DWORD AccumStyle ) {
sprintf(Reg, "RSP_Vect[%i].UHW[4]", RSPOpC.rt);
MmxMoveQwordVariableToReg(x86_MM5 + 2, &RSP_Vect[RSPOpC.rt].UHW[4], Reg);
/* Copy the signed portion */
// Copy the signed portion
MmxMoveRegToReg(x86_MM2 + 2, x86_MM0 + 2);
MmxMoveRegToReg(x86_MM3 + 2, x86_MM1 + 2);
@ -379,7 +361,7 @@ void RSP_Sections_VMADM ( OPCODE RspOp, DWORD AccumStyle ) {
} else if ((RSPOpC.rs & 0xF) >= 8) {
RSP_Element2Mmx(x86_MM4 + 2);
/* Copy the signed portion */
// Copy the signed portion
MmxMoveRegToReg(x86_MM2 + 2, x86_MM0 + 2);
MmxMoveRegToReg(x86_MM3 + 2, x86_MM1 + 2);
@ -395,7 +377,7 @@ void RSP_Sections_VMADM ( OPCODE RspOp, DWORD AccumStyle ) {
} else {
RSP_MultiElement2Mmx(x86_MM4 + 2, x86_MM5 + 2);
/* Copy the signed portion */
// Copy the signed portion
MmxMoveRegToReg(x86_MM2 + 2, x86_MM0 + 2);
MmxMoveRegToReg(x86_MM3 + 2, x86_MM1 + 2);
@ -410,7 +392,7 @@ void RSP_Sections_VMADM ( OPCODE RspOp, DWORD AccumStyle ) {
MmxPmullwRegToReg(x86_MM3 + 2, x86_MM5 + 2);
}
/* Add them up */
// Add them up
MmxPaddwRegToReg(x86_MM0 + 2, x86_MM2 + 2);
MmxPaddwRegToReg(x86_MM1 + 2, x86_MM3 + 2);
}
@ -422,10 +404,7 @@ void RSP_Sections_VMADM ( OPCODE RspOp, DWORD AccumStyle ) {
void RSP_Sections_VMUDN ( OPCODE RspOp, DWORD AccumStyle ) {
char Reg[256];
/*****************************************
** VMUDN
** - affects the middle 32-bits, u16*s16
******************************************/
// VMUDN - affects the middle 32-bits, u16*s16
if (AccumStyle == High16BitAccum) {
MmxXorRegToReg(x86_MM0, x86_MM0);
@ -435,10 +414,10 @@ void RSP_Sections_VMUDN ( OPCODE RspOp, DWORD AccumStyle ) {
RSPOpC = RspOp;
/******* VMUDN *******/
// VMUDN
if (AccumStyle != Middle16BitAccum) {
/**** Load source registers ****/
// Load source registers
sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rd);
MmxMoveQwordVariableToReg(x86_MM0, &RSP_Vect[RspOp.rd].HW[0], Reg);
sprintf(Reg, "RSP_Vect[%i].HW[4]", RspOp.rd);
@ -465,12 +444,10 @@ void RSP_Sections_VMUDN ( OPCODE RspOp, DWORD AccumStyle ) {
}
} else {
/***
** NOTE: for code clarity, this is the same as VMUDM,
** just the mmx registers are swapped, this is easier
****/
// NOTE: for code clarity, this is the same as VMUDM,
// just the MMX registers are swapped, this is easier
/**** Load source registers ****/
// Load source registers
sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rd);
MmxMoveQwordVariableToReg(x86_MM4, &RSP_Vect[RspOp.rd].HW[0], Reg);
sprintf(Reg, "RSP_Vect[%i].HW[4]", RspOp.rd);
@ -488,7 +465,7 @@ void RSP_Sections_VMUDN ( OPCODE RspOp, DWORD AccumStyle ) {
RSP_MultiElement2Mmx(x86_MM0, x86_MM1);
}
/* Copy the signed portion */
// Copy the signed portion
MmxMoveRegToReg(x86_MM2, x86_MM0);
MmxMoveRegToReg(x86_MM3, x86_MM1);
@ -502,7 +479,7 @@ void RSP_Sections_VMUDN ( OPCODE RspOp, DWORD AccumStyle ) {
MmxPmullwRegToReg(x86_MM2, x86_MM4);
MmxPmullwRegToReg(x86_MM3, x86_MM5);
/* Add them up */
// Add them up
MmxPaddwRegToReg(x86_MM0, x86_MM2);
MmxPaddwRegToReg(x86_MM1, x86_MM3);
}
@ -511,10 +488,7 @@ void RSP_Sections_VMUDN ( OPCODE RspOp, DWORD AccumStyle ) {
void RSP_Sections_VMADN ( OPCODE RspOp, DWORD AccumStyle ) {
char Reg[256];
/*****************************************
** VMADN
** - affects the middle 32-bits, u16*s16
******************************************/
// VMADN - affects the middle 32-bits, u16*s16
if (AccumStyle == High16BitAccum) {
return;
@ -522,9 +496,9 @@ void RSP_Sections_VMADN ( OPCODE RspOp, DWORD AccumStyle ) {
RSPOpC = RspOp;
/******* VMADN *******/
// VMADN
if (AccumStyle != Middle16BitAccum) {
/**** Load source registers ****/
// Load source registers
sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rd);
MmxMoveQwordVariableToReg(x86_MM0 + 2, &RSP_Vect[RspOp.rd].HW[0], Reg);
sprintf(Reg, "RSP_Vect[%i].HW[4]", RspOp.rd);
@ -551,12 +525,10 @@ void RSP_Sections_VMADN ( OPCODE RspOp, DWORD AccumStyle ) {
}
} else {
/*
** NOTE: for code clarity, this is the same as VMADM,
** just the mmx registers are swapped, this is easier
*/
// NOTE: for code clarity, this is the same as VMADM,
// just the MMX registers are swapped, this is easier
/**** Load source registers ****/
// Load source registers
sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rd);
MmxMoveQwordVariableToReg(x86_MM4 + 2, &RSP_Vect[RspOp.rd].HW[0], Reg);
sprintf(Reg, "RSP_Vect[%i].HW[4]", RspOp.rd);
@ -574,7 +546,7 @@ void RSP_Sections_VMADN ( OPCODE RspOp, DWORD AccumStyle ) {
RSP_MultiElement2Mmx(x86_MM0 + 2, x86_MM1 + 2);
}
/* Copy the signed portion */
// Copy the signed portion
MmxMoveRegToReg(x86_MM2 + 2, x86_MM0 + 2);
MmxMoveRegToReg(x86_MM3 + 2, x86_MM1 + 2);
@ -588,15 +560,14 @@ void RSP_Sections_VMADN ( OPCODE RspOp, DWORD AccumStyle ) {
MmxPmullwRegToReg(x86_MM2 + 2, x86_MM4 + 2);
MmxPmullwRegToReg(x86_MM3 + 2, x86_MM5 + 2);
/* Add them up */
// Add them up
MmxPaddwRegToReg(x86_MM0 + 2, x86_MM2 + 2);
MmxPaddwRegToReg(x86_MM1 + 2, x86_MM3 + 2);
}
/*
** only thing is when we are responsible for clamping
** so we adopt unsigned here?
*/
// Only thing is when we are responsible for clamping
// So we adopt unsigned here?
MmxPaddswRegToReg(x86_MM0, x86_MM0 + 2);
MmxPaddswRegToReg(x86_MM1, x86_MM1 + 2);
@ -605,10 +576,7 @@ void RSP_Sections_VMADN ( OPCODE RspOp, DWORD AccumStyle ) {
void RSP_Sections_VMULF ( OPCODE RspOp, DWORD AccumStyle ) {
char Reg[256];
/*****************************************
** VMULF
** - affects the middle 32-bits, s16*s16*2
******************************************/
// VMULF - affects the middle 32-bits, s16*s16*2
if (AccumStyle == High16BitAccum) {
MmxXorRegToReg(x86_MM0, x86_MM0);
@ -618,13 +586,13 @@ void RSP_Sections_VMULF ( OPCODE RspOp, DWORD AccumStyle ) {
RSPOpC = RspOp;
/**** Load source registers ****/
// Load source registers
sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rd);
MmxMoveQwordVariableToReg(x86_MM0, &RSP_Vect[RspOp.rd].HW[0], Reg);
sprintf(Reg, "RSP_Vect[%i].HW[4]", RspOp.rd);
MmxMoveQwordVariableToReg(x86_MM1, &RSP_Vect[RspOp.rd].HW[4], Reg);
/******* VMULF *******/
// VMULF
if ((RspOp.rs & 0x0f) < 2) {
sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rt);
MmxMoveQwordVariableToReg(x86_MM2, &RSP_Vect[RspOp.rt].HW[0], Reg);
@ -665,10 +633,7 @@ void RSP_Sections_VMULF ( OPCODE RspOp, DWORD AccumStyle ) {
void RSP_Sections_VMACF ( OPCODE RspOp, DWORD AccumStyle ) {
char Reg[256];
/*****************************************
** VMACF
** - affects the upper 32-bits, s16*s16*2
******************************************/
// VMACF - affects the upper 32-bits, s16*s16*2
if (AccumStyle == High16BitAccum) {
return;
@ -676,13 +641,13 @@ void RSP_Sections_VMACF ( OPCODE RspOp, DWORD AccumStyle ) {
RSPOpC = RspOp;
/**** Load source registers ****/
// Load source registers
sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rd);
MmxMoveQwordVariableToReg(x86_MM0 + 2, &RSP_Vect[RspOp.rd].HW[0], Reg);
sprintf(Reg, "RSP_Vect[%i].HW[4]", RspOp.rd);
MmxMoveQwordVariableToReg(x86_MM1 + 2, &RSP_Vect[RspOp.rd].HW[4], Reg);
/******* VMACF *******/
// VMACF
if ((RspOp.rs & 0x0f) < 2) {
sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rt);
MmxMoveQwordVariableToReg(x86_MM2 + 2, &RSP_Vect[RspOp.rt].HW[0], Reg);
@ -722,9 +687,9 @@ void RSP_Sections_VMACF ( OPCODE RspOp, DWORD AccumStyle ) {
MmxPaddswRegToReg(x86_MM1, x86_MM1 + 2);
}
/******************** Microcode Sections *********************/
// Microcode sections
static DWORD Section_000_VMADN; /* Yah i know, but leave it */
static DWORD Section_000_VMADN; // Yeah I know, but leave it
Boolean Check_Section_000(void)
{
@ -733,13 +698,9 @@ Boolean Check_Section_000(void)
RSP_LW_IMEM(CompilePC + 0x00, &op0.Hex);
/************************************
** Example: (mario audio microcode)
**
** 0x574 VMUDN $v30, $v3, $v23
** 0x578 VMADN $v30, $v4, $v23
**
*************************************/
// Example: (Mario audio microcode)
// 0x574 VMUDN $v30, $v3, $v23
// 0x578 VMADN $v30, $v4, $v23
if (!(op0.op == RSP_CP2 && (op0.rs & 0x10) != 0 && op0.funct == RSP_VECTOR_VMUDN)) {
return FALSE;
@ -760,12 +721,12 @@ Boolean Check_Section_000(void)
}
}
/* We need at least 1 VMADN */
// We need at least 1 VMADN
if (Section_000_VMADN == 0) {
return FALSE;
}
/* FIXME: check dest & flushes */
// TODO: check destination and flushes
if (TRUE == WriteToAccum(7, CompilePC + 0x4 + (Section_000_VMADN * 4) - 0x4)) {
return FALSE;
}
@ -838,12 +799,9 @@ Boolean Check_Section_001(void)
RSP_LW_IMEM(CompilePC + 0x00, &op0.Hex);
/************************************
** Example: (mario audio microcode)
**
** 0xCC0 VMULF $v28, $v28, $v10 [6]
** 0xCC4 VMACF $v28, $v17, $v16
*************************************/
// Example: (Mario audio microcode)
// 0xCC0 VMULF $v28, $v28, $v10 [6]
// 0xCC4 VMACF $v28, $v17, $v16
if (!(op0.op == RSP_CP2 && (op0.rs & 0x10) != 0 && op0.funct == RSP_VECTOR_VMULF)) {
return FALSE;
@ -864,7 +822,7 @@ Boolean Check_Section_001(void)
}
}
/* We need at least 1 VMACF */
// We need at least 1 VMACF
if (Section_001_VMACF == 0) {
return FALSE;
}
@ -873,7 +831,7 @@ Boolean Check_Section_001(void)
return FALSE;
}
/* dests are checked elsewhere, this is fine */
// Destinations are checked elsewhere, this is fine
if (TRUE == WriteToAccum(7, CompilePC + 0x4 + (Section_001_VMACF * 4) - 0x4)) {
return FALSE;
}
@ -931,9 +889,8 @@ Boolean Check_Section_002(void)
RSP_LW_IMEM(CompilePC + (Count * 0x04), &op[Count].Hex);
}
/************************************
** Example: (mario audio microcode)
**
/*
** Example: (Mario audio microcode)
** 5F4 VMUDH $v2, $v21, $v27 [6]
** 5F8 VMADH $v2, $v20, $v27 [7]
** 5FC VMADH $v2, $v19, $v30 [0]
@ -944,9 +901,9 @@ Boolean Check_Section_002(void)
** 610 VMADH $v2, $v14, $v30 [5]
** 614 VMADH $v2, $v13, $v30 [6]
** 618 VMADH $v2, $v30, $v31 [5]
** 61C VSAW $v26 [9], $v7, $v28
** 620 VSAW $v28 [8], $v7, $v28
************************************/
** 61C VSAW $v26 [9], $v7, $v28
** 620 VSAW $v28 [8], $v7, $v28
*/
if (IsMmxEnabled == FALSE) {
return FALSE;
@ -1004,12 +961,12 @@ void Compile_Section_002 ( void ) {
vmudh = op[0];
RSP_Sections_VMUDH(vmudh, High16BitAccum);
/******* VMADHs *******/
// VMADHs
for (Count = 1; Count < 10; Count++) {
RSP_Sections_VMADH(op[Count], High16BitAccum);
}
/***** VSAWs *****/
// VSAWs
vsaw = op[10];
MmxXorRegToReg(x86_MM4, x86_MM4);
sprintf(Reg, "RSP_Vect[%i].HW[0]", RSPOpC.sa);
@ -1037,14 +994,12 @@ Boolean Check_Section_003(void)
RSP_LW_IMEM(CompilePC + (Count * 0x04), &op[Count].Hex);
}
/************************************
** Example: (zelda audio microcode)
**
** VMUDM $v23, $v31, $v23 [7]
** VMADH $v23, $v31, $v22 [7]
** VMADM $v22, $v25, $v18 [4]
** VMADN $v23, $v31, $v30 [0]
************************************/
// Example: (Zelda audio microcode)
// VMUDM $v23, $v31, $v23 [7]
// VMADH $v23, $v31, $v22 [7]
// VMADM $v22, $v25, $v18 [4]
// VMADN $v23, $v31, $v30 [0]
if (op[0].Hex == 0x4BF7FDC5 && op[1].Hex == 0x4BF6FDCF && op[2].Hex == 0x4B92CD8D && op[3].Hex == 0x4B1EFDCE) {
if (TRUE == WriteToAccum(7, CompilePC + 0xc))

31
Source/RSP/Rsp.h
View File

@ -15,7 +15,7 @@ extern "C" {
#define CALL
#endif
/************ Profiling **************/
// Profiling
#define Default_ProfilingOn FALSE
#define Default_IndvidualBlock FALSE
#define Default_ShowErrors FALSE
@ -27,21 +27,18 @@ extern "C" {
#define PLUGIN_TYPE_CONTROLLER 4
typedef struct {
uint16_t Version; /* Should be set to 0x0101 */
uint16_t Type; /* Set to PLUGIN_TYPE_RSP */
char Name[100]; /* Name of the DLL */
uint16_t Version; // Should be set to 0x0101
uint16_t Type; // Set to PLUGIN_TYPE_RSP
char Name[100]; // Name of the DLL
/* If DLL supports memory these memory options then set them to TRUE or FALSE
if it does not support it */
int NormalMemory; /* a normal BYTE array */
int MemoryBswaped; /* a normal BYTE array where the memory has been pre
bswap on a dword (32 bits) boundry */
// If DLL supports memory these memory options then set them to TRUE or FALSE if it does not support it
int NormalMemory; // A normal BYTE array
int MemoryBswaped; // A normal BYTE array where the memory has been pre-bswap'd on a DWORD (32-bit) boundary
} PLUGIN_INFO;
typedef struct {
void * hInst;
int MemoryBswaped; /* If this is set to TRUE, then the memory has been pre
bswap on a dword (32 bits) boundry */
int MemoryBswaped; // If this is set to TRUE, then the memory has been pre-bswap'd on a DWORD (32-bit) boundary
uint8_t * HEADER;
uint8_t * RDRAM;
uint8_t * DMEM;
@ -77,7 +74,7 @@ typedef struct {
typedef struct {
long left, top, right, bottom;
} rectangle; /* <windows.h> equivalent: RECT */
} rectangle; // <windows.h> equivalent: RECT
typedef struct {
void * hdc;
Boolean fErase;
@ -85,15 +82,15 @@ typedef struct {
Boolean fRestore;
Boolean fIncUpdate;
uint8_t rgbReserved[32];
} window_paint; /* <windows.h> equivalent: PAINTSTRUCT */
} window_paint; // <windows.h> equivalent: PAINTSTRUCT
typedef struct {
/* Menu */
/* Items should have an ID between 5001 and 5100 */
// Menu
// Items should have an ID between 5001 and 5100
void * hRSPMenu;
void (*ProcessMenuItem) ( int ID );
/* Break Points */
// Breakpoints
int UseBPoints;
char BPPanelName[20];
void (*Add_BPoint) ( void );
@ -105,7 +102,7 @@ typedef struct {
void (*RemoveBpoint) (void * hList, int index);
void (*RemoveAllBpoint) ( void );
/* RSP command Window */
// RSP command window
void (*Enter_RSP_Commands_Window) ( void );
} RSPDEBUG_INFO;

25
Source/RSP/Types.h
View File

@ -3,21 +3,22 @@
#include <Common/stdtypes.h>
/*
* pointer to RSP operation code functions or "func"
* This is the type of all RSP interpreter and recompiler functions.
*/
// Pointer to RSP operation code functions or "func"
// This is the type of all RSP interpreter and recompiler functions
typedef void(*p_func)(void);
// TODO: Rewrite/remove/address?
/*
* `BOOL` is Windows-specific so is going to tend to be avoided.
* `int` is the exact replacement.
*
* However, saying "int" all the time for true/false is a little ambiguous.
*
* Maybe in the future, with C++ (or C99) rewrites, we can switch to `bool`.
* Until then, a simple type definition will help emphasize true/false logic.
*/
`BOOL` is Windows-specific so is going to tend to be avoided.
`int` is the exact replacement.
However, saying "int" all the time for true/false is a little ambiguous.
Maybe in the future, with C++ (or C99) rewrites, we can switch to `bool`.
Until then, a simple type definition will help emphasize true/false logic.
*/
typedef int Boolean;
#if !defined(FALSE) && !defined(TRUE)
#define FALSE 0

2
Source/RSP/Version.h.in
View File

@ -7,7 +7,7 @@
#define VERSION_BUILD 9999
#define GIT_VERSION ""
#define VER_FILE_DESCRIPTION_STR "RSP emulation Plugin"
#define VER_FILE_DESCRIPTION_STR "RSP emulation plugin"
#define VER_FILE_VERSION VERSION_MAJOR, VERSION_MINOR, VERSION_REVISION, VERSION_BUILD
#define VER_FILE_VERSION_STR STRINGIZE(VERSION_MAJOR) \
"." STRINGIZE(VERSION_MINOR) \

14
Source/RSP/X86.c
View File

@ -8,7 +8,7 @@
#include "log.h"
#include "Types.h"
#pragma warning(disable : 4152) // nonstandard extension, function/data pointer conversion in expression
#pragma warning(disable : 4152) // Non-standard extension, function/data pointer conversion in expression
#define PUTDST8(dest,value) (*((BYTE *)(dest))=(BYTE)(value)); dest += 1;
#define PUTDST16(dest,value) (*((WORD *)(dest))=(WORD)(value)); dest += 2;
@ -136,7 +136,7 @@ void AddConstToX86Reg(int x86Reg, size_t Const)
const size_t sign_extension_mask = ~(zero_extension_mask);
const size_t extension_from_8bit = Const & sign_extension_mask;
/* To do: if 64-bit x86, then what if `Const' upper DWORD set? */
// TODO: If 64-bit x86, then what if `Const' upper DWORD set?
CPU_Message(" add %s, %Xh",x86_Name(x86Reg),Const);
if (extension_from_8bit != 0 && extension_from_8bit != sign_extension_mask) {
switch (x86Reg) {
@ -1084,10 +1084,10 @@ void JsLabel32(char *Label, DWORD Value) {
PUTDST32(RecompPos,Value);
}
/*
** NOTE: this op can get really complex with muls
** if we need this rewrite it into 1 function
**/
// TODO: Rewrite this?
// NOTE: This op can get really complex with muls
// If we need this, rewrite it into 1 function
void LeaSourceAndOffset(int x86DestReg, int x86SourceReg, size_t offset) {
WORD x86Command = 0;
@ -1118,7 +1118,7 @@ void LeaSourceAndOffset(int x86DestReg, int x86SourceReg, size_t offset) {
DisplayError("LeaSourceAndOffset\nUnknown x86 Register");
}
// To do: Check high DWORD of offset for 64-bit x86.
// TODO: Check high DWORD of offset for 64-bit x86
if ((offset & 0x00000000FFFFFF80) != 0 && (offset & ~0x7F) != ~0x7F) {
PUTDST16(RecompPos,x86Command);
PUTDST32(RecompPos,offset);

2
Source/RSP/X86.h
View File

@ -224,7 +224,7 @@ void SseMoveRegToReg ( int Dest, int Source );
void SseXorRegToReg ( int Dest, int Source );
#pragma warning(push)
#pragma warning(disable : 4201) // nonstandard extension used : nameless struct/union
#pragma warning(disable : 4201) // Non-standard extension used: nameless struct/union
typedef union {
struct {

8
Source/RSP/breakpoint.c
View File

@ -24,7 +24,7 @@ int AddRSP_BPoint( DWORD Location, int Confirm )
if (NoOfBpoints == MaxBPoints)
{
DisplayError("Max amount of Break Points set");
DisplayError("Max amount of break points set");
return FALSE;
}
@ -32,7 +32,7 @@ int AddRSP_BPoint( DWORD Location, int Confirm )
{
if (BPoint[count].Location == Location)
{
DisplayError("You already have this Break Point");
DisplayError("You already have this break point");
return FALSE;
}
}
@ -77,7 +77,7 @@ void CreateBPPanel ( void * hDlg, rectangle rcBox )
{
if (hRSPLocation != NULL) { return; }
rcBox = rcBox; // remove warning of unused
rcBox = rcBox; // Remove warning of unused
BPoint_Win_hDlg = hDlg;
@ -100,7 +100,7 @@ void HideBPPanel ( void )
void PaintBPPanel ( window_paint ps )
{
TextOut( ps.hdc, 29,60,"Break when the Program Counter equals",37);
TextOut( ps.hdc, 29,60,"Break when the program counter equals",37);
TextOut( ps.hdc, 59,85,"0x",2);
}

1
Source/RSP/breakpoint.h
View File

@ -21,4 +21,3 @@ void RemoveAllBpoint ( void );
int AddRSP_BPoint ( DWORD Location, int Confirm );
int CheckForRSPBPoint ( DWORD Location );
void RemoveRSPBreakPoint (DWORD Location);

12
Source/RSP/dma.c
View File

@ -6,7 +6,7 @@
#include "RSP Registers.h"
#include "memory.h"
// #define RSP_SAFE_DMA /* unoptimized dma transfers */
// #define RSP_SAFE_DMA // Unoptimized DMA transfers
void SP_DMA_READ (void)
{
@ -17,13 +17,13 @@ void SP_DMA_READ (void)
if (addr > 0x7FFFFF)
{
DisplayError("SP DMA READ\nSP_DRAM_ADDR_REG not in RDRam space");
DisplayError("SP DMA READ\nSP_DRAM_ADDR_REG not in RDRAM space");
return;
}
if ((*RSPInfo.SP_RD_LEN_REG & 0xFFF) + 1 + (*RSPInfo.SP_MEM_ADDR_REG & 0xFFF) > 0x1000)
{
DisplayError("SP DMA READ\ncould not fit copy in memory segment");
DisplayError("SP DMA READ\nCould not fit copy in memory segment");
return;
}
@ -74,7 +74,7 @@ void SP_DMA_READ (void)
}
#endif
/* FIXME: could this be a problem DMEM to IMEM (?) */
// TODO: Could this be a problem DMEM to IMEM?
if (CPUCore == RecompilerCPU && (*RSPInfo.SP_MEM_ADDR_REG & 0x1000) != 0)
{
SetJumpTable(End);
@ -93,13 +93,13 @@ void SP_DMA_WRITE (void)
if (addr > 0x7FFFFF)
{
DisplayError("SP DMA WRITE\nSP_DRAM_ADDR_REG not in RDRam space");
DisplayError("SP DMA WRITE\nSP_DRAM_ADDR_REG not in RDRAM space");
return;
}
if ((*RSPInfo.SP_WR_LEN_REG & 0xFFF) + 1 + (*RSPInfo.SP_MEM_ADDR_REG & 0xFFF) > 0x1000)
{
DisplayError("SP DMA WRITE\ncould not fit copy in memory segment");
DisplayError("SP DMA WRITE\nCould not fit copy in memory segment");
return;
}

2
Source/RSP/log.cpp
View File

@ -272,7 +272,7 @@ void Log_MT_CP0 ( unsigned int PC, int CP0Reg, int Value ) {
case 14: Log_Message("%03X: Stored 0x%08X in DPC_PIPEBUSY_REG",PC,Value); break;
case 15: Log_Message("%03X: Stored 0x%08X in DPC_TMEM_REG",PC,Value); break;
default:
Log_Message("%03X: Unkown RSP CP0 register %d",PC,CP0Reg);
Log_Message("%03X: Unknown RSP CP0 register %d",PC,CP0Reg);
break;*/
}
}

8
Source/RSP/memory.c
View File

@ -30,7 +30,7 @@ int AllocateMemory (void) {
if (JumpTables == NULL){
JumpTables = (BYTE *)VirtualAlloc( NULL, 0x1000 * MaxMaps, MEM_COMMIT, PAGE_READWRITE );
if( JumpTables == NULL ) {
DisplayError("Not enough memory for Jump Table!");
DisplayError("Not enough memory for jump table!");
return FALSE;
}
}
@ -141,7 +141,7 @@ void RSP_LFV_DMEM ( uint32_t Addr, int vect, int element ) {
void RSP_LH_DMEM ( uint32_t Addr, uint16_t * Value ) {
if ((Addr & 0x1) != 0) {
if (Addr > 0xFFE) {
DisplayError("hmmmm.... Problem with:\nRSP_LH_DMEM");
DisplayError("There is a problem with:\nRSP_LH_DMEM");
return;
}
Addr &= 0xFFF;
@ -260,7 +260,7 @@ void RSP_LW_DMEM ( uint32_t Addr, uint32_t * Value ) {
if ((Addr & 0x3) != 0) {
Addr &= 0xFFF;
if (Addr > 0xFFC) {
DisplayError("hmmmm.... Problem with:\nRSP_LW_DMEM");
DisplayError("There is a problem with:\nRSP_LW_DMEM");
return;
}
*Value = *(uint8_t *)(RSPInfo.DMEM + ((Addr + 0) ^ 3)) << 24;
@ -516,7 +516,7 @@ void RSP_SW_DMEM ( uint32_t Addr, uint32_t Value ) {
Addr &= 0xFFF;
if ((Addr & 0x3) != 0) {
if (Addr > 0xFFC) {
DisplayError("hmmmm.... Problem with:\nRSP_SW_DMEM");
DisplayError("There is a problem with:\nRSP_SW_DMEM");
return;
}
*(uint8_t *)(RSPInfo.DMEM + ((Addr + 0) ^ 3)) = (Value >> 24) & 0xFF;