Core: Remove SystemRegisters
This commit is contained in:
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d58168bcb9
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d6a2ae80c1
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@ -218,20 +218,6 @@ const char * CRegName::FPR_Ctrl[32] = {
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"FCSR",
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};
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uint32_t * CSystemRegisters::_PROGRAM_COUNTER = nullptr;
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MIPS_DWORD * CSystemRegisters::_GPR = nullptr;
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MIPS_DWORD * CSystemRegisters::_FPR = nullptr;
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uint64_t * CSystemRegisters::_CP0 = nullptr;
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MIPS_DWORD * CSystemRegisters::_RegHI = nullptr;
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MIPS_DWORD * CSystemRegisters::_RegLO = nullptr;
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uint32_t ** CSystemRegisters::_FPR_UW = nullptr;
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uint64_t ** CSystemRegisters::_FPR_UDW = nullptr;
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float ** CSystemRegisters::_FPR_S;
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float ** CSystemRegisters::_FPR_S_L;
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double ** CSystemRegisters::_FPR_D;
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uint32_t * CSystemRegisters::_FPCR = nullptr;
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uint32_t * CSystemRegisters::_LLBit = nullptr;
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CP0registers::CP0registers(uint64_t * _CP0) :
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INDEX_REGISTER(_CP0[0]),
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RANDOM_REGISTER(_CP0[1]),
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@ -532,28 +518,11 @@ void CRegisters::Reset(bool bPostPif, CMipsMemoryVM & MMU)
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m_System.m_TLB.COP0StatusChanged();
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}
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void CRegisters::SetAsCurrentSystem()
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{
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_PROGRAM_COUNTER = &m_PROGRAM_COUNTER;
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_GPR = m_GPR;
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_FPR = m_FPR;
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_CP0 = m_CP0;
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_RegHI = &m_HI;
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_RegLO = &m_LO;
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_FPR_UW = m_FPR_UW;
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_FPR_UDW = m_FPR_UDW;
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_FPR_S = m_FPR_S;
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_FPR_S_L = m_FPR_S_L;
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_FPR_D = m_FPR_D;
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_FPCR = m_FPCR;
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_LLBit = &m_LLBit;
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}
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uint64_t CRegisters::Cop0_MF(COP0Reg Reg)
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{
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if (LogCP0reads() && Reg <= COP0Reg_31)
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{
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LogMessage("%08X: R4300i read from %s (0x%08X)", (*_PROGRAM_COUNTER), CRegName::Cop0[Reg], m_CP0[Reg]);
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LogMessage("%08X: R4300i read from %s (0x%08X)", m_PROGRAM_COUNTER, CRegName::Cop0[Reg], m_CP0[Reg]);
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}
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if (Reg == COP0Reg_Count || Reg == COP0Reg_Wired || Reg == COP0Reg_Random)
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@ -572,10 +541,10 @@ void CRegisters::Cop0_MT(COP0Reg Reg, uint64_t Value)
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{
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if (LogCP0changes() && Reg <= COP0Reg_31)
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{
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LogMessage("%08X: Writing 0x%I64U to %s register (originally: 0x%I64U)", (*_PROGRAM_COUNTER), Value, CRegName::Cop0[Reg], m_CP0[Reg]);
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LogMessage("%08X: Writing 0x%I64U to %s register (originally: 0x%I64U)", m_PROGRAM_COUNTER, Value, CRegName::Cop0[Reg], m_CP0[Reg]);
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if (Reg == 11) // Compare
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{
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LogMessage("%08X: Cause register changed from %08X to %08X", (*_PROGRAM_COUNTER), (uint32_t)CAUSE_REGISTER.Value, (uint32_t)(g_Reg->CAUSE_REGISTER.Value & ~CAUSE_IP7));
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LogMessage("%08X: Cause register changed from %08X to %08X", m_PROGRAM_COUNTER, (uint32_t)CAUSE_REGISTER.Value, (uint32_t)(g_Reg->CAUSE_REGISTER.Value & ~CAUSE_IP7));
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}
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}
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m_CP0Latch = Value;
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@ -684,7 +653,7 @@ void CRegisters::Cop1_CT(uint32_t Reg, uint32_t Value)
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{
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if (Reg == 31)
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{
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FPStatusReg & StatusReg = (FPStatusReg &)_FPCR[31];
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FPStatusReg & StatusReg = (FPStatusReg &)m_FPCR[31];
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StatusReg.Value = (Value & 0x183FFFF);
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if (((StatusReg.Cause.Inexact & StatusReg.Enable.Inexact) != 0) ||
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@ -418,24 +418,6 @@ public:
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static const char * FPR_Ctrl[32];
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};
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class CSystemRegisters
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{
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protected:
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static uint32_t * _PROGRAM_COUNTER;
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static MIPS_DWORD * _GPR;
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static MIPS_DWORD * _FPR;
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static uint64_t * _CP0;
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static MIPS_DWORD * _RegHI;
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static MIPS_DWORD * _RegLO;
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static uint32_t ** _FPR_UW;
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static uint64_t ** _FPR_UDW;
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static float ** _FPR_S;
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static float ** _FPR_S_L;
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static double ** _FPR_D;
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static uint32_t * _FPCR;
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static uint32_t * _LLBit;
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};
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class CN64System;
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class CSystemEvents;
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class CTLB;
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@ -444,7 +426,6 @@ class CRegisters :
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public CLogging,
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private CDebugSettings,
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private CGameSettings,
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protected CSystemRegisters,
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public CP0registers,
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public RDRAMRegistersReg,
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public MIPSInterfaceReg,
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@ -501,7 +482,6 @@ public:
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bool DoIntrException();
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void FixFpuLocations();
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void Reset(bool bPostPif, CMipsMemoryVM & MMU);
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void SetAsCurrentSystem();
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void TriggerAddressException(uint64_t Address, uint32_t ExceptionCode);
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void TriggerException(uint32_t ExceptionCode, uint32_t Coprocessor = 0);
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@ -131,18 +131,18 @@ void CTLB::WriteEntry(uint32_t Index, bool Random)
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if (m_tlb[Index].EntryDefined)
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{
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uint32_t FastIndx = Index << 1;
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if (*_PROGRAM_COUNTER >= m_FastTlb[FastIndx].VSTART &&
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*_PROGRAM_COUNTER < m_FastTlb[FastIndx].VEND &&
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if (m_Reg.m_PROGRAM_COUNTER >= m_FastTlb[FastIndx].VSTART &&
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m_Reg.m_PROGRAM_COUNTER < m_FastTlb[FastIndx].VEND &&
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m_FastTlb[FastIndx].ValidEntry && m_FastTlb[FastIndx].VALID)
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{
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WriteTrace(TraceTLB, TraceDebug, "Ignored PC: %X VAddr Start: %I64X VEND: %I64X", *_PROGRAM_COUNTER, m_FastTlb[FastIndx].VSTART, m_FastTlb[FastIndx].VEND);
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WriteTrace(TraceTLB, TraceDebug, "Ignored PC: %X VAddr Start: %I64X VEND: %I64X", m_Reg.m_PROGRAM_COUNTER, m_FastTlb[FastIndx].VSTART, m_FastTlb[FastIndx].VEND);
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return;
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}
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if (*_PROGRAM_COUNTER >= m_FastTlb[FastIndx + 1].VSTART &&
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*_PROGRAM_COUNTER < m_FastTlb[FastIndx + 1].VEND &&
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if (m_Reg.m_PROGRAM_COUNTER >= m_FastTlb[FastIndx + 1].VSTART &&
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m_Reg.m_PROGRAM_COUNTER < m_FastTlb[FastIndx + 1].VEND &&
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m_FastTlb[FastIndx + 1].ValidEntry && m_FastTlb[FastIndx + 1].VALID)
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{
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WriteTrace(TraceTLB, TraceDebug, "Ignored PC: %X VAddr Start: %X VEND: %X", *_PROGRAM_COUNTER, m_FastTlb[FastIndx + 1].VSTART, m_FastTlb[FastIndx + 1].VEND);
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WriteTrace(TraceTLB, TraceDebug, "Ignored PC: %X VAddr Start: %X VEND: %X", m_Reg.m_PROGRAM_COUNTER, m_FastTlb[FastIndx + 1].VSTART, m_FastTlb[FastIndx + 1].VEND);
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return;
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}
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}
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@ -29,7 +29,6 @@ struct TLB_ENTRY
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};
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class CTLB :
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protected CSystemRegisters,
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private CGameSettings
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{
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friend class CDebugTlb;
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@ -963,8 +963,6 @@ bool CN64System::SetActiveSystem(bool bActive)
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if (bActive)
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{
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m_Reg.SetAsCurrentSystem();
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g_System = this;
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if (g_BaseSystem == this)
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{
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@ -15,6 +15,7 @@ extern "C" void __clear_cache_android(uint8_t * begin, uint8_t * end);
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CCodeBlock::CCodeBlock(CMipsMemoryVM & MMU, CRegisters & Reg, uint32_t VAddrEnter) :
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m_MMU(MMU),
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m_Reg(Reg),
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m_VAddrEnter(VAddrEnter),
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m_VAddrFirst(VAddrEnter),
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m_VAddrLast(VAddrEnter),
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@ -55,6 +55,10 @@ public:
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{
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return m_RecompilerOps;
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}
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CRegisters & Registers()
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{
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return m_Reg;
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}
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const std::string & CodeLog() const
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{
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return m_CodeLog;
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@ -116,6 +120,7 @@ private:
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typedef std::list<CCodeSection *> SectionList;
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CMipsMemoryVM & m_MMU;
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CRegisters & m_Reg;
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SectionMap m_SectionMap;
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SectionList m_Sections;
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CCodeSection * m_EnterSection;
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@ -14,8 +14,7 @@ class CRecompiler :
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protected CDebugSettings,
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public CRecompilerSettings,
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public CFunctionMap,
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public CRecompMemory,
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private CSystemRegisters
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public CRecompMemory
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{
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public:
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enum REMOVE_REASON
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@ -9578,7 +9578,6 @@ void CX86RecompilerOps::OverflowDelaySlot(bool TestTimer)
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m_Assembler.PushImm32("g_System->CountPerOp()", g_System->CountPerOp());
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m_Assembler.CallThis((uint32_t)&g_System->m_OpCodes, AddressOf(&R4300iOp::ExecuteOps), "R4300iOp::ExecuteOps", 8);
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m_Assembler.AddConstToX86Reg(asmjit::x86::esp, 4);
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if (g_System->bFastSP() && g_Recompiler)
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{
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@ -125,6 +125,7 @@ asmjit::x86::St GetX86FpuRegFromIndex(x86RegFpuIndex Index)
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}
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CX86RegInfo::CX86RegInfo(CCodeBlock & CodeBlock, CX86Ops & Assembler) :
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m_Reg(CodeBlock.Registers()),
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m_CodeBlock(CodeBlock),
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m_Assembler(Assembler),
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m_Stack_TopPos(0),
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@ -151,6 +152,7 @@ CX86RegInfo::CX86RegInfo(CCodeBlock & CodeBlock, CX86Ops & Assembler) :
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}
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CX86RegInfo::CX86RegInfo(const CX86RegInfo & rhs) :
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m_Reg(rhs.m_Reg),
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m_CodeBlock(rhs.m_CodeBlock),
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m_Assembler(rhs.m_CodeBlock.RecompilerOps()->Assembler())
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{
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@ -897,7 +899,7 @@ void CX86RegInfo::Map_GPR_32bit(int32_t MipsReg, bool SignValue, int32_t MipsReg
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{
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if (IsUnknown(MipsRegToLoad))
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{
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m_Assembler.MoveVariableToX86reg(Reg, &_GPR[MipsRegToLoad].UW[0], CRegName::GPR_Lo[MipsRegToLoad]);
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m_Assembler.MoveVariableToX86reg(Reg, &m_Reg.m_GPR[MipsRegToLoad].UW[0], CRegName::GPR_Lo[MipsRegToLoad]);
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}
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else if (IsMapped(MipsRegToLoad))
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{
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@ -995,8 +997,8 @@ void CX86RegInfo::Map_GPR_64bit(int32_t MipsReg, int32_t MipsRegToLoad)
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{
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if (IsUnknown(MipsRegToLoad))
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{
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m_Assembler.MoveVariableToX86reg(x86Hi, &_GPR[MipsRegToLoad].UW[1], CRegName::GPR_Hi[MipsRegToLoad]);
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m_Assembler.MoveVariableToX86reg(x86lo, &_GPR[MipsRegToLoad].UW[0], CRegName::GPR_Lo[MipsRegToLoad]);
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m_Assembler.MoveVariableToX86reg(x86Hi, &m_Reg.m_GPR[MipsRegToLoad].UW[1], CRegName::GPR_Hi[MipsRegToLoad]);
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m_Assembler.MoveVariableToX86reg(x86lo, &m_Reg.m_GPR[MipsRegToLoad].UW[0], CRegName::GPR_Lo[MipsRegToLoad]);
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}
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else if (IsMapped(MipsRegToLoad))
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{
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@ -1203,7 +1205,7 @@ asmjit::x86::Gp CX86RegInfo::Map_TempReg(asmjit::x86::Gp Reg, int32_t MipsReg, b
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{
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if (IsUnknown(MipsReg))
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{
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m_Assembler.MoveVariableToX86reg(Reg, &_GPR[MipsReg].UW[1], CRegName::GPR_Hi[MipsReg]);
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m_Assembler.MoveVariableToX86reg(Reg, &m_Reg.m_GPR[MipsReg].UW[1], CRegName::GPR_Hi[MipsReg]);
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}
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else if (IsMapped(MipsReg))
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{
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@ -1237,7 +1239,7 @@ asmjit::x86::Gp CX86RegInfo::Map_TempReg(asmjit::x86::Gp Reg, int32_t MipsReg, b
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{
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if (IsUnknown(MipsReg))
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{
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m_Assembler.MoveVariableToX86reg(Reg, &_GPR[MipsReg].UW[0], CRegName::GPR_Lo[MipsReg]);
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m_Assembler.MoveVariableToX86reg(Reg, &m_Reg.m_GPR[MipsReg].UW[0], CRegName::GPR_Lo[MipsReg]);
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}
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else if (IsMapped(MipsReg))
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{
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@ -1531,19 +1533,19 @@ void CX86RegInfo::UnMap_FPR(int32_t Reg, bool WriteBackValue)
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switch (m_x86fpu_State[StackTopPos()])
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{
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case FPU_Dword:
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m_Assembler.MoveVariableToX86reg(TempReg, &_FPR_S[m_x86fpu_MappedTo[StackTopPos()]], stdstr_f("_FPR_S[%d]", m_x86fpu_MappedTo[StackTopPos()]).c_str());
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m_Assembler.MoveVariableToX86reg(TempReg, &m_Reg.m_FPR_S[m_x86fpu_MappedTo[StackTopPos()]], stdstr_f("_FPR_S[%d]", m_x86fpu_MappedTo[StackTopPos()]).c_str());
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m_Assembler.fpuStoreIntegerDwordFromX86Reg(StackTopPos(), TempReg, true);
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break;
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case FPU_Qword:
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m_Assembler.MoveVariableToX86reg(TempReg, &_FPR_D[m_x86fpu_MappedTo[StackTopPos()]], stdstr_f("_FPR_D[%d]", m_x86fpu_MappedTo[StackTopPos()]).c_str());
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m_Assembler.MoveVariableToX86reg(TempReg, &m_Reg.m_FPR_D[m_x86fpu_MappedTo[StackTopPos()]], stdstr_f("_FPR_D[%d]", m_x86fpu_MappedTo[StackTopPos()]).c_str());
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m_Assembler.fpuStoreIntegerQwordFromX86Reg(StackTopPos(), TempReg, true);
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break;
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case FPU_Float:
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m_Assembler.MoveVariableToX86reg(TempReg, &_FPR_S[m_x86fpu_MappedTo[StackTopPos()]], stdstr_f("_FPR_S[%d]", m_x86fpu_MappedTo[StackTopPos()]).c_str());
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m_Assembler.MoveVariableToX86reg(TempReg, &m_Reg.m_FPR_S[m_x86fpu_MappedTo[StackTopPos()]], stdstr_f("_FPR_S[%d]", m_x86fpu_MappedTo[StackTopPos()]).c_str());
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m_Assembler.fpuStoreDwordFromX86Reg(StackTopPos(), TempReg, true);
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break;
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case FPU_Double:
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m_Assembler.MoveVariableToX86reg(TempReg, &_FPR_D[m_x86fpu_MappedTo[StackTopPos()]], stdstr_f("_FPR_D[%d]", m_x86fpu_MappedTo[StackTopPos()]).c_str());
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m_Assembler.MoveVariableToX86reg(TempReg, &m_Reg.m_FPR_D[m_x86fpu_MappedTo[StackTopPos()]], stdstr_f("_FPR_D[%d]", m_x86fpu_MappedTo[StackTopPos()]).c_str());
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m_Assembler.fpuStoreQwordFromX86Reg(StackTopPos(), TempReg, true);
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break;
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default:
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@ -1608,20 +1610,20 @@ void CX86RegInfo::UnMap_GPR(uint32_t Reg, bool WriteBackValue)
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}
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if (Is64Bit(Reg))
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{
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m_Assembler.MoveConstToVariable(&_GPR[Reg].UW[1], CRegName::GPR_Hi[Reg], GetMipsRegHi(Reg));
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m_Assembler.MoveConstToVariable(&_GPR[Reg].UW[0], CRegName::GPR_Lo[Reg], GetMipsRegLo(Reg));
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m_Assembler.MoveConstToVariable(&m_Reg.m_GPR[Reg].UW[1], CRegName::GPR_Hi[Reg], GetMipsRegHi(Reg));
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m_Assembler.MoveConstToVariable(&m_Reg.m_GPR[Reg].UW[0], CRegName::GPR_Lo[Reg], GetMipsRegLo(Reg));
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SetMipsRegState(Reg, STATE_UNKNOWN);
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return;
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}
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if ((GetMipsRegLo(Reg) & 0x80000000) != 0)
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{
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m_Assembler.MoveConstToVariable(&_GPR[Reg].UW[1], CRegName::GPR_Hi[Reg], 0xFFFFFFFF);
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m_Assembler.MoveConstToVariable(&m_Reg.m_GPR[Reg].UW[1], CRegName::GPR_Hi[Reg], 0xFFFFFFFF);
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}
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else
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{
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m_Assembler.MoveConstToVariable(&_GPR[Reg].UW[1], CRegName::GPR_Hi[Reg], 0);
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m_Assembler.MoveConstToVariable(&m_Reg.m_GPR[Reg].UW[1], CRegName::GPR_Hi[Reg], 0);
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}
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m_Assembler.MoveConstToVariable(&_GPR[Reg].UW[0], CRegName::GPR_Lo[Reg], GetMipsRegLo(Reg));
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m_Assembler.MoveConstToVariable(&m_Reg.m_GPR[Reg].UW[0], CRegName::GPR_Lo[Reg], GetMipsRegLo(Reg));
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SetMipsRegState(Reg, STATE_UNKNOWN);
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return;
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}
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@ -1640,11 +1642,11 @@ void CX86RegInfo::UnMap_GPR(uint32_t Reg, bool WriteBackValue)
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SetMipsRegState(Reg, STATE_UNKNOWN);
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return;
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}
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m_Assembler.MoveX86regToVariable(&_GPR[Reg].UW[0], CRegName::GPR_Lo[Reg], GetMipsRegMapLo(Reg));
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m_Assembler.MoveX86regToVariable(&m_Reg.m_GPR[Reg].UW[0], CRegName::GPR_Lo[Reg], GetMipsRegMapLo(Reg));
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if (Is64Bit(Reg))
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{
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SetMipsRegMapLo(Reg, x86Reg_Unknown);
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m_Assembler.MoveX86regToVariable(&_GPR[Reg].UW[1], CRegName::GPR_Hi[Reg], GetMipsRegMapHi(Reg));
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m_Assembler.MoveX86regToVariable(&m_Reg.m_GPR[Reg].UW[1], CRegName::GPR_Hi[Reg], GetMipsRegMapHi(Reg));
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SetMipsRegMapHi(Reg, x86Reg_Unknown);
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}
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else
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@ -1654,11 +1656,11 @@ void CX86RegInfo::UnMap_GPR(uint32_t Reg, bool WriteBackValue)
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if (IsSigned(Reg))
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{
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m_Assembler.sar(GetMipsRegMapLo(Reg), 31);
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m_Assembler.MoveX86regToVariable(&_GPR[Reg].UW[1], CRegName::GPR_Hi[Reg], GetMipsRegMapLo(Reg));
|
||||
m_Assembler.MoveX86regToVariable(&m_Reg.m_GPR[Reg].UW[1], CRegName::GPR_Hi[Reg], GetMipsRegMapLo(Reg));
|
||||
}
|
||||
else
|
||||
{
|
||||
m_Assembler.MoveConstToVariable(&_GPR[Reg].UW[1], CRegName::GPR_Hi[Reg], 0);
|
||||
m_Assembler.MoveConstToVariable(&m_Reg.m_GPR[Reg].UW[1], CRegName::GPR_Hi[Reg], 0);
|
||||
}
|
||||
}
|
||||
SetMipsRegMapLo(Reg, x86Reg_Unknown);
|
||||
|
@ -1820,11 +1822,11 @@ void CX86RegInfo::WriteBackRegisters()
|
|||
}
|
||||
if ((GetMipsRegLo(count) & 0x80000000) != 0)
|
||||
{
|
||||
m_Assembler.MoveX86regToVariable(&_GPR[count].UW[1], CRegName::GPR_Hi[count], asmjit::x86::esi);
|
||||
m_Assembler.MoveX86regToVariable(&m_Reg.m_GPR[count].UW[1], CRegName::GPR_Hi[count], asmjit::x86::esi);
|
||||
}
|
||||
else
|
||||
{
|
||||
m_Assembler.MoveX86regToVariable(&_GPR[count].UW[1], CRegName::GPR_Hi[count], asmjit::x86::edi);
|
||||
m_Assembler.MoveX86regToVariable(&m_Reg.m_GPR[count].UW[1], CRegName::GPR_Hi[count], asmjit::x86::edi);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -1838,7 +1840,7 @@ void CX86RegInfo::WriteBackRegisters()
|
|||
bEdiZero = true;
|
||||
}
|
||||
}
|
||||
m_Assembler.MoveX86regToVariable(&_GPR[count].UW[0], CRegName::GPR_Lo[count], asmjit::x86::edi);
|
||||
m_Assembler.MoveX86regToVariable(&m_Reg.m_GPR[count].UW[0], CRegName::GPR_Lo[count], asmjit::x86::edi);
|
||||
}
|
||||
else if (GetMipsRegLo(count) == 0xFFFFFFFF)
|
||||
{
|
||||
|
@ -1850,11 +1852,11 @@ void CX86RegInfo::WriteBackRegisters()
|
|||
bEsiSign = true;
|
||||
}
|
||||
}
|
||||
m_Assembler.MoveX86regToVariable(&_GPR[count].UW[0], CRegName::GPR_Lo[count], asmjit::x86::esi);
|
||||
m_Assembler.MoveX86regToVariable(&m_Reg.m_GPR[count].UW[0], CRegName::GPR_Lo[count], asmjit::x86::esi);
|
||||
}
|
||||
else
|
||||
{
|
||||
m_Assembler.MoveConstToVariable(&_GPR[count].UW[0], CRegName::GPR_Lo[count], GetMipsRegLo(count));
|
||||
m_Assembler.MoveConstToVariable(&m_Reg.m_GPR[count].UW[0], CRegName::GPR_Lo[count], GetMipsRegLo(count));
|
||||
}
|
||||
|
||||
SetMipsRegState(count, CX86RegInfo::STATE_UNKNOWN);
|
||||
|
@ -1867,7 +1869,7 @@ void CX86RegInfo::WriteBackRegisters()
|
|||
m_Assembler.xor_(asmjit::x86::edi, asmjit::x86::edi);
|
||||
bEdiZero = true;
|
||||
}
|
||||
m_Assembler.MoveX86regToVariable(&_GPR[count].UW[1], CRegName::GPR_Hi[count], asmjit::x86::edi);
|
||||
m_Assembler.MoveX86regToVariable(&m_Reg.m_GPR[count].UW[1], CRegName::GPR_Hi[count], asmjit::x86::edi);
|
||||
}
|
||||
|
||||
if (GetMipsRegLo(count) == 0)
|
||||
|
@ -1880,11 +1882,11 @@ void CX86RegInfo::WriteBackRegisters()
|
|||
bEdiZero = true;
|
||||
}
|
||||
}
|
||||
m_Assembler.MoveX86regToVariable(&_GPR[count].UW[0], CRegName::GPR_Lo[count], asmjit::x86::edi);
|
||||
m_Assembler.MoveX86regToVariable(&m_Reg.m_GPR[count].UW[0], CRegName::GPR_Lo[count], asmjit::x86::edi);
|
||||
}
|
||||
else
|
||||
{
|
||||
m_Assembler.MoveConstToVariable(&_GPR[count].UW[0], CRegName::GPR_Lo[count], GetMipsRegLo(count));
|
||||
m_Assembler.MoveConstToVariable(&m_Reg.m_GPR[count].UW[0], CRegName::GPR_Lo[count], GetMipsRegLo(count));
|
||||
}
|
||||
SetMipsRegState(count, CX86RegInfo::STATE_UNKNOWN);
|
||||
break;
|
||||
|
@ -1902,28 +1904,28 @@ void CX86RegInfo::WriteBackRegisters()
|
|||
|
||||
if (GetMipsRegHi(count) == 0)
|
||||
{
|
||||
m_Assembler.MoveX86regToVariable(&_GPR[count].UW[1], CRegName::GPR_Hi[count], asmjit::x86::edi);
|
||||
m_Assembler.MoveX86regToVariable(&m_Reg.m_GPR[count].UW[1], CRegName::GPR_Hi[count], asmjit::x86::edi);
|
||||
}
|
||||
else if (GetMipsRegLo(count) == 0xFFFFFFFF)
|
||||
{
|
||||
m_Assembler.MoveX86regToVariable(&_GPR[count].UW[1], CRegName::GPR_Hi[count], asmjit::x86::esi);
|
||||
m_Assembler.MoveX86regToVariable(&m_Reg.m_GPR[count].UW[1], CRegName::GPR_Hi[count], asmjit::x86::esi);
|
||||
}
|
||||
else
|
||||
{
|
||||
m_Assembler.MoveConstToVariable(&_GPR[count].UW[1], CRegName::GPR_Hi[count], GetMipsRegHi(count));
|
||||
m_Assembler.MoveConstToVariable(&m_Reg.m_GPR[count].UW[1], CRegName::GPR_Hi[count], GetMipsRegHi(count));
|
||||
}
|
||||
|
||||
if (GetMipsRegLo(count) == 0)
|
||||
{
|
||||
m_Assembler.MoveX86regToVariable(&_GPR[count].UW[0], CRegName::GPR_Lo[count], asmjit::x86::edi);
|
||||
m_Assembler.MoveX86regToVariable(&m_Reg.m_GPR[count].UW[0], CRegName::GPR_Lo[count], asmjit::x86::edi);
|
||||
}
|
||||
else if (GetMipsRegLo(count) == 0xFFFFFFFF)
|
||||
{
|
||||
m_Assembler.MoveX86regToVariable(&_GPR[count].UW[0], CRegName::GPR_Lo[count], asmjit::x86::esi);
|
||||
m_Assembler.MoveX86regToVariable(&m_Reg.m_GPR[count].UW[0], CRegName::GPR_Lo[count], asmjit::x86::esi);
|
||||
}
|
||||
else
|
||||
{
|
||||
m_Assembler.MoveConstToVariable(&_GPR[count].UW[0], CRegName::GPR_Lo[count], GetMipsRegLo(count));
|
||||
m_Assembler.MoveConstToVariable(&m_Reg.m_GPR[count].UW[0], CRegName::GPR_Lo[count], GetMipsRegLo(count));
|
||||
}
|
||||
SetMipsRegState(count, CX86RegInfo::STATE_UNKNOWN);
|
||||
break;
|
||||
|
|
|
@ -41,8 +41,7 @@ asmjit::x86::St GetX86FpuRegFromIndex(x86RegFpuIndex Index);
|
|||
|
||||
class CX86RegInfo :
|
||||
public CRegBase,
|
||||
private CDebugSettings,
|
||||
private CSystemRegisters
|
||||
private CDebugSettings
|
||||
{
|
||||
public:
|
||||
// Enums
|
||||
|
@ -175,6 +174,7 @@ public:
|
|||
private:
|
||||
CX86RegInfo();
|
||||
|
||||
CRegisters & m_Reg;
|
||||
CCodeBlock & m_CodeBlock;
|
||||
CX86Ops & m_Assembler;
|
||||
asmjit::x86::Gp UnMap_8BitTempReg();
|
||||
|
|
Loading…
Reference in New Issue