From bac3517c86628a29f64584e85d8c00b1b629fe75 Mon Sep 17 00:00:00 2001 From: zilmar Date: Mon, 2 May 2022 19:10:35 +0930 Subject: [PATCH] [Core] Change tlb empty to be -1 and remove rdram from tlb value --- .../N64System/Mips/MemoryVirtualMem.cpp | 77 ++++++++----------- .../N64System/Mips/MemoryVirtualMem.h | 4 +- .../Recompiler/x86/x86RecompilerOps.cpp | 40 +++++++++- 3 files changed, 72 insertions(+), 49 deletions(-) diff --git a/Source/Project64-core/N64System/Mips/MemoryVirtualMem.cpp b/Source/Project64-core/N64System/Mips/MemoryVirtualMem.cpp index c068e5269..a634bffcd 100755 --- a/Source/Project64-core/N64System/Mips/MemoryVirtualMem.cpp +++ b/Source/Project64-core/N64System/Mips/MemoryVirtualMem.cpp @@ -82,12 +82,12 @@ void CMipsMemoryVM::Reset(bool /*EraseMemory*/) } if (m_TLB_ReadMap) { - memset(m_TLB_ReadMap, 0, 0xFFFFF * sizeof(size_t)); - memset(m_TLB_WriteMap, 0, 0xFFFFF * sizeof(size_t)); + memset(m_TLB_ReadMap, -1, 0xFFFFF * sizeof(size_t)); + memset(m_TLB_WriteMap, -1, 0xFFFFF * sizeof(size_t)); for (size_t Address = 0x80000000; Address < 0xC0000000; Address += 0x1000) { - m_TLB_ReadMap[Address >> 12] = ((size_t)m_RDRAM + (Address & 0x1FFFFFFF)) - Address; - m_TLB_WriteMap[Address >> 12] = ((size_t)m_RDRAM + (Address & 0x1FFFFFFF)) - Address; + m_TLB_ReadMap[Address >> 12] = (Address & 0x1FFFFFFF) - Address; + m_TLB_WriteMap[Address >> 12] = (Address & 0x1FFFFFFF) - Address; } if (g_Settings->LoadDword(Rdb_TLB_VAddrStart) != 0) @@ -108,8 +108,8 @@ void CMipsMemoryVM::Reset(bool /*EraseMemory*/) { m_MemoryReadMap[Address >> 12] = ((size_t)g_Rom->GetRomAddress() + (TargetAddress - 0x10000000)) - Address; } - m_TLB_ReadMap[Address >> 12] = ((size_t)m_RDRAM + TargetAddress) - Address; - m_TLB_WriteMap[Address >> 12] = ((size_t)m_RDRAM + TargetAddress) - Address; + m_TLB_ReadMap[Address >> 12] = TargetAddress - Address; + m_TLB_WriteMap[Address >> 12] = TargetAddress - Address; } } } @@ -197,7 +197,7 @@ bool CMipsMemoryVM::Initialize(bool SyncSystem) return false; } - m_TLB_ReadMap = new size_t[0x100000]; + m_TLB_ReadMap = new uint32_t[0x100000]; if (m_TLB_ReadMap == nullptr) { WriteTrace(TraceN64System, TraceError, "Failed to allocate m_TLB_ReadMap (Size: 0x%X)", 0x100000 * sizeof(size_t)); @@ -205,7 +205,7 @@ bool CMipsMemoryVM::Initialize(bool SyncSystem) return false; } - m_TLB_WriteMap = new size_t[0x100000]; + m_TLB_WriteMap = new uint32_t[0x100000]; if (m_TLB_WriteMap == nullptr) { WriteTrace(TraceN64System, TraceError, "Failed to allocate m_TLB_WriteMap (Size: 0x%X)", 0xFFFFF * sizeof(size_t)); @@ -274,12 +274,12 @@ bool CMipsMemoryVM::LB_VAddr(uint32_t VAddr, uint8_t& Value) Value = *(uint8_t*)(MemoryPtr + (VAddr ^ 3)); return true; } - if (m_TLB_ReadMap[VAddr >> 12] == 0) + if (m_TLB_ReadMap[VAddr >> 12] == -1) { return false; } - Value = *(uint8_t*)(m_TLB_ReadMap[VAddr >> 12] + (VAddr ^ 3)); + Value = *(uint8_t*)((m_TLB_ReadMap[VAddr >> 12] + (VAddr ^ 3)) + m_RDRAM); return true; } @@ -291,12 +291,12 @@ bool CMipsMemoryVM::LH_VAddr(uint32_t VAddr, uint16_t& Value) Value = *(uint16_t*)(MemoryPtr + (VAddr ^ 2)); return true; } - if (m_TLB_ReadMap[VAddr >> 12] == 0) + if (m_TLB_ReadMap[VAddr >> 12] == -1) { return false; } - Value = *(uint16_t*)(m_TLB_ReadMap[VAddr >> 12] + (VAddr ^ 2)); + Value = *(uint16_t*)((m_TLB_ReadMap[VAddr >> 12] + (VAddr ^ 2)) + m_RDRAM); return true; } @@ -318,22 +318,13 @@ bool CMipsMemoryVM::LW_VAddr(uint32_t VAddr, uint32_t & Value) } } - uint8_t* BaseAddress = (uint8_t*)m_TLB_ReadMap[VAddr >> 12]; - if (BaseAddress == nullptr) + uint32_t BaseAddress = m_TLB_ReadMap[VAddr >> 12]; + if (BaseAddress == -1) { return false; } - Value = *(uint32_t*)(BaseAddress + VAddr); - - // if (LookUpMode == FuncFind_ChangeMemory) - // { - // g_Notify->BreakPoint(__FILE__, __LINE__); - // if ( (Command.Hex >> 16) == 0x7C7C) - // { - // Command.Hex = OrigMem[(Command.Hex & 0xFFFF)].OriginalValue; - // } - // } + Value = *(uint32_t*)(BaseAddress + VAddr + m_RDRAM); return true; } @@ -346,13 +337,13 @@ bool CMipsMemoryVM::LD_VAddr(uint32_t VAddr, uint64_t& Value) *((uint32_t*)(&Value) + 0) = *(uint32_t*)(MemoryPtr + VAddr + 4); return true; } - if (m_TLB_ReadMap[VAddr >> 12] == 0) + if (m_TLB_ReadMap[VAddr >> 12] == -1) { return false; } - *((uint32_t*)(&Value) + 1) = *(uint32_t*)(m_TLB_ReadMap[VAddr >> 12] + VAddr); - *((uint32_t*)(&Value) + 0) = *(uint32_t*)(m_TLB_ReadMap[VAddr >> 12] + VAddr + 4); + *((uint32_t*)(&Value) + 1) = *(uint32_t*)(m_TLB_ReadMap[VAddr >> 12] + VAddr + m_RDRAM); + *((uint32_t*)(&Value) + 0) = *(uint32_t*)(m_TLB_ReadMap[VAddr >> 12] + VAddr + 4 + m_RDRAM); return true; } @@ -364,12 +355,12 @@ bool CMipsMemoryVM::SB_VAddr(uint32_t VAddr, uint8_t Value) *(uint8_t*)(MemoryPtr + (VAddr ^ 3)) = Value; return true; } - if (m_TLB_WriteMap[VAddr >> 12] == 0) + if (m_TLB_WriteMap[VAddr >> 12] == -1) { return false; } - *(uint8_t*)(m_TLB_WriteMap[VAddr >> 12] + (VAddr ^ 3)) = Value; + *(uint8_t*)(m_TLB_WriteMap[VAddr >> 12] + (VAddr ^ 3) + m_RDRAM) = Value; return true; } @@ -381,12 +372,12 @@ bool CMipsMemoryVM::SH_VAddr(uint32_t VAddr, uint16_t Value) *(uint16_t*)(MemoryPtr + (VAddr ^ 2)) = Value; return true; } - if (m_TLB_WriteMap[VAddr >> 12] == 0) + if (m_TLB_WriteMap[VAddr >> 12] == -1) { return false; } - *(uint16_t*)(m_TLB_WriteMap[VAddr >> 12] + (VAddr ^ 2)) = Value; + *(uint16_t*)(m_TLB_WriteMap[VAddr >> 12] + (VAddr ^ 2) + m_RDRAM) = Value; return true; } @@ -408,12 +399,12 @@ bool CMipsMemoryVM::SW_VAddr(uint32_t VAddr, uint32_t Value) } } - if (m_TLB_WriteMap[VAddr >> 12] == 0) + if (m_TLB_WriteMap[VAddr >> 12] == -1) { return false; } - *(uint32_t*)(m_TLB_WriteMap[VAddr >> 12] + VAddr) = Value; + *(uint32_t*)(m_TLB_WriteMap[VAddr >> 12] + VAddr + m_RDRAM) = Value; return true; } @@ -426,28 +417,28 @@ bool CMipsMemoryVM::SD_VAddr(uint32_t VAddr, uint64_t Value) *(uint32_t*)(MemoryPtr + VAddr + 4) = *((uint32_t*)(&Value)); return true; } - if (m_TLB_WriteMap[VAddr >> 12] == 0) + if (m_TLB_WriteMap[VAddr >> 12] == -1) { return false; } - *(uint32_t*)(m_TLB_WriteMap[VAddr >> 12] + VAddr + 0) = *((uint32_t*)(&Value) + 1); - *(uint32_t*)(m_TLB_WriteMap[VAddr >> 12] + VAddr + 4) = *((uint32_t*)(&Value)); + *(uint32_t*)(m_TLB_WriteMap[VAddr >> 12] + VAddr + m_RDRAM + 0) = *((uint32_t*)(&Value) + 1); + *(uint32_t*)(m_TLB_WriteMap[VAddr >> 12] + VAddr + m_RDRAM + 4) = *((uint32_t*)(&Value)); return true; } bool CMipsMemoryVM::ValidVaddr(uint32_t VAddr) const { - return m_TLB_ReadMap[VAddr >> 12] != 0; + return m_TLB_ReadMap[VAddr >> 12] != -1; } bool CMipsMemoryVM::VAddrToPAddr(uint32_t VAddr, uint32_t &PAddr) const { - if (m_TLB_ReadMap[VAddr >> 12] == 0) + if (m_TLB_ReadMap[VAddr >> 12] == -1) { return false; } - PAddr = (uint32_t)((uint8_t *)(m_TLB_ReadMap[VAddr >> 12] + VAddr) - m_RDRAM); + PAddr = (uint32_t)(uint8_t *)(m_TLB_ReadMap[VAddr >> 12] + VAddr); return true; } @@ -705,11 +696,11 @@ void CMipsMemoryVM::TLB_Mapped(uint32_t VAddr, uint32_t Len, uint32_t PAddr, boo { size_t Index = Address >> 12; m_MemoryReadMap[Index] = (size_t)((m_RDRAM + (Address - VAddr + PAddr)) - Address); - m_TLB_ReadMap[Index] = ((size_t)m_RDRAM + (Address - VAddr + PAddr)) - Address; + m_TLB_ReadMap[Index] = ((size_t)(Address - VAddr + PAddr)) - Address; if (!bReadOnly) { m_MemoryWriteMap[Index] = (size_t)((m_RDRAM + (Address - VAddr + PAddr)) - Address); - m_TLB_WriteMap[Index] = ((size_t)m_RDRAM + (Address - VAddr + PAddr)) - Address; + m_TLB_WriteMap[Index] = ((size_t)(Address - VAddr + PAddr)) - Address; } } } @@ -722,8 +713,8 @@ void CMipsMemoryVM::TLB_Unmaped(uint32_t Vaddr, uint32_t Len) size_t Index = Address >> 12; m_MemoryReadMap[Index] = (size_t)-1; m_MemoryWriteMap[Index] = (size_t)-1; - m_TLB_ReadMap[Index] = 0; - m_TLB_WriteMap[Index] = 0; + m_TLB_ReadMap[Index] = -1; + m_TLB_WriteMap[Index] = -1; } } diff --git a/Source/Project64-core/N64System/Mips/MemoryVirtualMem.h b/Source/Project64-core/N64System/Mips/MemoryVirtualMem.h index 1cc3734fc..d3524d1ef 100644 --- a/Source/Project64-core/N64System/Mips/MemoryVirtualMem.h +++ b/Source/Project64-core/N64System/Mips/MemoryVirtualMem.h @@ -176,8 +176,8 @@ private: uint32_t m_AllocatedRdramSize; mutable char m_strLabelName[100]; - size_t * m_TLB_ReadMap; - size_t * m_TLB_WriteMap; + uint32_t * m_TLB_ReadMap; + uint32_t * m_TLB_WriteMap; size_t * m_MemoryReadMap; size_t * m_MemoryWriteMap; diff --git a/Source/Project64-core/N64System/Recompiler/x86/x86RecompilerOps.cpp b/Source/Project64-core/N64System/Recompiler/x86/x86RecompilerOps.cpp index a4af4a759..2732bb2c9 100644 --- a/Source/Project64-core/N64System/Recompiler/x86/x86RecompilerOps.cpp +++ b/Source/Project64-core/N64System/Recompiler/x86/x86RecompilerOps.cpp @@ -341,21 +341,21 @@ void CX86RecompilerOps::PostCompileOpcode(void) void CX86RecompilerOps::CompileReadTLBMiss(uint32_t VirtualAddress, x86Reg LookUpReg) { MoveConstToVariable(VirtualAddress, g_TLBLoadAddress, "TLBLoadAddress"); - TestX86RegToX86Reg(LookUpReg, LookUpReg); + CompConstToX86reg(LookUpReg, (uint32_t)-1); CompileExit(m_CompilePC, m_CompilePC, m_RegWorkingSet, CExitInfo::TLBReadMiss, false, JeLabel32); } void CX86RecompilerOps::CompileReadTLBMiss(x86Reg AddressReg, x86Reg LookUpReg) { MoveX86regToVariable(AddressReg, g_TLBLoadAddress, "TLBLoadAddress"); - TestX86RegToX86Reg(LookUpReg, LookUpReg); + CompConstToX86reg(LookUpReg, (uint32_t)-1); CompileExit(m_CompilePC, m_CompilePC, m_RegWorkingSet, CExitInfo::TLBReadMiss, false, JeLabel32); } void CX86RecompilerOps::CompileWriteTLBMiss(x86Reg AddressReg, x86Reg LookUpReg) { MoveX86regToVariable(AddressReg, &g_TLBStoreAddress, "g_TLBStoreAddress"); - TestX86RegToX86Reg(LookUpReg, LookUpReg); + CompConstToX86reg(LookUpReg, (uint32_t)-1); CompileExit(m_CompilePC, m_CompilePC, m_RegWorkingSet, CExitInfo::TLBWriteMiss, false, JeLabel32); } @@ -2761,6 +2761,7 @@ void CX86RecompilerOps::LB_KnownAddress(x86Reg Reg, uint32_t VAddr, bool SignExt MoveConstToX86reg(VAddr >> 12, TlbMappReg); MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TlbMappReg, TlbMappReg, 4); CompileReadTLBMiss(AddrReg, TlbMappReg); + AddConstToX86Reg(TlbMappReg, (uint32_t)m_MMU.Rdram()); CPU_Message(""); CPU_Message(stdstr_f(" MemoryReadMap_%X_Found:", m_CompilePC).c_str()); SetJump8(JumpFound, *g_RecompPos); @@ -2834,6 +2835,7 @@ void CX86RecompilerOps::LH_KnownAddress(x86Reg Reg, uint32_t VAddr, bool SignExt MoveConstToX86reg(VAddr >> 12, TlbMappReg); MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TlbMappReg, TlbMappReg, 4); CompileReadTLBMiss(AddrReg, TlbMappReg); + AddConstToX86Reg(TlbMappReg, (uint32_t)m_MMU.Rdram()); CPU_Message(""); CPU_Message(stdstr_f(" MemoryReadMap_%X_Found:", m_CompilePC).c_str()); SetJump8(JumpFound, *g_RecompPos); @@ -2944,6 +2946,7 @@ void CX86RecompilerOps::LB() ShiftRightUnsignImmed(TempReg2, 12); MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4); CompileReadTLBMiss(TempReg1, TempReg2); + AddConstToX86Reg(TempReg2, (uint32_t)m_MMU.Rdram()); CPU_Message(""); CPU_Message(stdstr_f(" MemoryReadMap_%X_Found:", m_CompilePC).c_str()); SetJump8(JumpFound, *g_RecompPos); @@ -3006,6 +3009,7 @@ void CX86RecompilerOps::LH() ShiftRightUnsignImmed(TempReg2, 12); MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4); CompileReadTLBMiss(TempReg1, TempReg2); + AddConstToX86Reg(TempReg2, (uint32_t)m_MMU.Rdram()); CPU_Message(""); CPU_Message(stdstr_f(" MemoryReadMap_%X_Found:", m_CompilePC).c_str()); SetJump8(JumpFound, *g_RecompPos); @@ -3075,6 +3079,7 @@ void CX86RecompilerOps::LWL() MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4); CompileReadTLBMiss(TempReg1, TempReg2); + AddConstToX86Reg(TempReg2, (uint32_t)m_MMU.Rdram()); CPU_Message(""); CPU_Message(stdstr_f(" MemoryReadMap_%X_Found:", m_CompilePC).c_str()); SetJump8(JumpFound, *g_RecompPos); @@ -3129,6 +3134,10 @@ void CX86RecompilerOps::LW(bool ResultSigned, bool bRecordLLBit) } else { + m_RegWorkingSet.SetBlockCycleCount(m_RegWorkingSet.GetBlockCycleCount() - g_System->CountPerOp()); + UpdateCounters(m_RegWorkingSet, false, true); + m_RegWorkingSet.SetBlockCycleCount(m_RegWorkingSet.GetBlockCycleCount() + g_System->CountPerOp()); + PreReadInstruction(); if (IsMapped(m_Opcode.rt)) { @@ -3171,6 +3180,7 @@ void CX86RecompilerOps::LW(bool ResultSigned, bool bRecordLLBit) ShiftRightUnsignImmed(TempReg2, 12); MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4); CompileReadTLBMiss(TempReg1, TempReg2); + AddConstToX86Reg(TempReg2, (uint32_t)m_MMU.Rdram()); CPU_Message(""); CPU_Message(stdstr_f(" MemoryReadMap_%X_Found:", m_CompilePC).c_str()); SetJump8(JumpFound, *g_RecompPos); @@ -3206,6 +3216,7 @@ void CX86RecompilerOps::LW_KnownAddress(x86Reg Reg, uint32_t VAddr) MoveConstToX86reg(VAddr >> 12, TlbMappReg); MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TlbMappReg, TlbMappReg, 4); CompileReadTLBMiss(VAddr, TlbMappReg); + AddConstToX86Reg(TlbMappReg, (uint32_t)m_MMU.Rdram()); CPU_Message(""); CPU_Message(stdstr_f(" MemoryWriteMap_%X_Found:", m_CompilePC).c_str()); SetJump8(JumpFound, *g_RecompPos); @@ -3507,6 +3518,7 @@ void CX86RecompilerOps::LBU() ShiftRightUnsignImmed(TempReg2, 12); MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4); CompileReadTLBMiss(TempReg1, TempReg2); + AddConstToX86Reg(TempReg2, (uint32_t)m_MMU.Rdram()); CPU_Message(""); CPU_Message(stdstr_f(" MemoryReadMap_%X_Found:", m_CompilePC).c_str()); SetJump8(JumpFound, *g_RecompPos); @@ -3571,6 +3583,7 @@ void CX86RecompilerOps::LHU() ShiftRightUnsignImmed(TempReg2, 12); MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4); CompileReadTLBMiss(TempReg1, TempReg2); + AddConstToX86Reg(TempReg2, (uint32_t)m_MMU.Rdram()); CPU_Message(""); CPU_Message(stdstr_f(" MemoryReadMap_%X_Found:", m_CompilePC).c_str()); SetJump8(JumpFound, *g_RecompPos); @@ -3645,6 +3658,7 @@ void CX86RecompilerOps::LWR() ShiftRightUnsignImmed(TempReg2, 12); MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4); CompileReadTLBMiss(TempReg1, TempReg2); + AddConstToX86Reg(TempReg2, (uint32_t)m_MMU.Rdram()); CPU_Message(""); CPU_Message(stdstr_f(" MemoryReadMap_%X_Found:", m_CompilePC).c_str()); SetJump8(JumpFound, *g_RecompPos); @@ -3741,6 +3755,7 @@ void CX86RecompilerOps::SB() ShiftRightUnsignImmed(TempReg2, 12); MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4); CompileWriteTLBMiss(TempReg1, TempReg2); + AddConstToX86Reg(TempReg2, (uint32_t)m_MMU.Rdram()); CPU_Message(""); CPU_Message(stdstr_f(" MemoryWriteMap_%X_Found:", m_CompilePC).c_str()); SetJump8(JumpFound, *g_RecompPos); @@ -3830,6 +3845,7 @@ void CX86RecompilerOps::SH() ShiftRightUnsignImmed(TempReg2, 12); MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4); CompileWriteTLBMiss(TempReg1, TempReg2); + AddConstToX86Reg(TempReg2, (uint32_t)m_MMU.Rdram()); CPU_Message(""); CPU_Message(stdstr_f(" MemoryWriteMap_%X_Found:", m_CompilePC).c_str()); SetJump8(JumpFound, *g_RecompPos); @@ -3907,6 +3923,7 @@ void CX86RecompilerOps::SWL() ShiftRightUnsignImmed(TempReg2, 12); MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4); CompileReadTLBMiss(TempReg1, TempReg2); + AddConstToX86Reg(TempReg2, (uint32_t)m_MMU.Rdram()); CPU_Message(""); CPU_Message(stdstr_f(" MemoryReadMap_%X_Found:", m_CompilePC).c_str()); SetJump8(JumpFound, *g_RecompPos); @@ -3945,6 +3962,7 @@ void CX86RecompilerOps::SWL() MoveX86RegToX86Reg(TempReg1, TempReg2); ShiftRightUnsignImmed(TempReg2, 12); MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4); + AddConstToX86Reg(TempReg2, (uint32_t)m_MMU.Rdram()); CPU_Message(""); CPU_Message(stdstr_f(" MemoryReadMap_%X_Found:", m_CompilePC).c_str()); SetJump8(JumpFound2, *g_RecompPos); @@ -4057,6 +4075,7 @@ void CX86RecompilerOps::SW(bool bCheckLLbit) ShiftRightUnsignImmed(TempReg2, 12); MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4); CompileWriteTLBMiss(TempReg1, TempReg2); + AddConstToX86Reg(TempReg2, (uint32_t)m_MMU.Rdram()); CPU_Message(""); CPU_Message(stdstr_f(" MemoryWriteMap_%X_Found:", m_CompilePC).c_str()); SetJump8(JumpFound, *g_RecompPos); @@ -4149,6 +4168,7 @@ void CX86RecompilerOps::SWR() ShiftRightUnsignImmed(TempReg2, 12); MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4); CompileReadTLBMiss(TempReg1, TempReg2); + AddConstToX86Reg(TempReg2, (uint32_t)m_MMU.Rdram()); CPU_Message(""); CPU_Message(stdstr_f(" MemoryReadMap_%X_Found:", m_CompilePC).c_str()); SetJump8(JumpFound, *g_RecompPos); @@ -4188,10 +4208,10 @@ void CX86RecompilerOps::SWR() MoveX86RegToX86Reg(TempReg1, TempReg2); ShiftRightUnsignImmed(TempReg2, 12); MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4); + AddConstToX86Reg(TempReg2, (uint32_t)m_MMU.Rdram()); CPU_Message(""); CPU_Message(stdstr_f(" MemoryReadMap_%X_Found2:", m_CompilePC).c_str()); SetJump8(JumpFound2, *g_RecompPos); - MoveX86regToX86regPointer(Value, TempReg1, TempReg2); } @@ -4315,6 +4335,7 @@ void CX86RecompilerOps::LWC1() ShiftRightUnsignImmed(TempReg2, 12); MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4); CompileReadTLBMiss(TempReg1, TempReg2); + AddConstToX86Reg(TempReg2, (uint32_t)m_MMU.Rdram()); CPU_Message(""); CPU_Message(stdstr_f(" MemoryReadMap_%X_Found:", m_CompilePC).c_str()); SetJump8(JumpFound, *g_RecompPos); @@ -4410,6 +4431,7 @@ void CX86RecompilerOps::LDC1() ShiftRightUnsignImmed(TempReg2, 12); MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4); CompileReadTLBMiss(TempReg1, TempReg2); + AddConstToX86Reg(TempReg2, (uint32_t)m_MMU.Rdram()); CPU_Message(""); CPU_Message(stdstr_f(" MemoryReadMap_%X_Found:", m_CompilePC).c_str()); SetJump8(JumpFound, *g_RecompPos); @@ -4495,6 +4517,7 @@ void CX86RecompilerOps::LD() ShiftRightUnsignImmed(TempReg2, 12); MoveVariableDispToX86Reg(g_MMU->m_TLB_ReadMap, "MMU->TLB_ReadMap", TempReg2, TempReg2, 4); CompileReadTLBMiss(TempReg1, TempReg2); + AddConstToX86Reg(TempReg2, (uint32_t)m_MMU.Rdram()); CPU_Message(""); CPU_Message(stdstr_f(" MemoryReadMap_%X_Found:", m_CompilePC).c_str()); SetJump8(JumpFound, *g_RecompPos); @@ -4572,6 +4595,7 @@ void CX86RecompilerOps::SWC1() ShiftRightUnsignImmed(TempReg2, 12); MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4); CompileWriteTLBMiss(TempReg1, TempReg2); + AddConstToX86Reg(TempReg2, (uint32_t)m_MMU.Rdram()); CPU_Message(""); CPU_Message(stdstr_f(" MemoryWriteMap_%X_Found:", m_CompilePC).c_str()); SetJump8(JumpFound, *g_RecompPos); @@ -4644,6 +4668,7 @@ void CX86RecompilerOps::SDC1() ShiftRightUnsignImmed(TempReg2, 12); MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4); CompileWriteTLBMiss(TempReg1, TempReg2); + AddConstToX86Reg(TempReg2, (uint32_t)m_MMU.Rdram()); CPU_Message(""); CPU_Message(stdstr_f(" MemoryWriteMap_%X_Found:", m_CompilePC).c_str()); SetJump8(JumpFound, *g_RecompPos); @@ -4733,6 +4758,7 @@ void CX86RecompilerOps::SD() ShiftRightUnsignImmed(TempReg2, 12); MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4); CompileWriteTLBMiss(TempReg1, TempReg2); + AddConstToX86Reg(TempReg2, (uint32_t)m_MMU.Rdram()); CPU_Message(""); CPU_Message(stdstr_f(" MemoryWriteMap_%X_Found:", m_CompilePC).c_str()); SetJump8(JumpFound, *g_RecompPos); @@ -10389,6 +10415,7 @@ void CX86RecompilerOps::SB_Const(uint8_t Value, uint32_t VAddr) ShiftRightUnsignImmed(TempReg2, 12); MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4); CompileWriteTLBMiss(TempReg1, TempReg2); + AddConstToX86Reg(TempReg2, (uint32_t)m_MMU.Rdram()); CPU_Message(""); CPU_Message(stdstr_f(" MemoryWriteMap_%X_Found:", m_CompilePC).c_str()); SetJump8(JumpFound, *g_RecompPos); @@ -10446,6 +10473,7 @@ void CX86RecompilerOps::SB_Register(x86Reg Reg, uint32_t VAddr) ShiftRightUnsignImmed(TempReg2, 12); MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4); CompileWriteTLBMiss(TempReg1, TempReg2); + AddConstToX86Reg(TempReg2, (uint32_t)m_MMU.Rdram()); CPU_Message(""); CPU_Message(stdstr_f(" MemoryWriteMap_%X_Found:", m_CompilePC).c_str()); SetJump8(JumpFound, *g_RecompPos); @@ -10504,6 +10532,7 @@ void CX86RecompilerOps::SH_Const(uint16_t Value, uint32_t VAddr) ShiftRightUnsignImmed(TempReg2, 12); MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4); CompileWriteTLBMiss(TempReg1, TempReg2); + AddConstToX86Reg(TempReg2, (uint32_t)m_MMU.Rdram()); CPU_Message(""); CPU_Message(stdstr_f(" MemoryWriteMap_%X_Found:", m_CompilePC).c_str()); SetJump8(JumpFound, *g_RecompPos); @@ -10564,6 +10593,7 @@ void CX86RecompilerOps::SH_Register(x86Reg Reg, uint32_t VAddr) ShiftRightUnsignImmed(TempReg2, 12); MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4); CompileWriteTLBMiss(TempReg1, TempReg2); + AddConstToX86Reg(TempReg2, (uint32_t)m_MMU.Rdram()); CPU_Message(""); CPU_Message(stdstr_f(" MemoryWriteMap_%X_Found:", m_CompilePC).c_str()); SetJump8(JumpFound, *g_RecompPos); @@ -10623,6 +10653,7 @@ void CX86RecompilerOps::SW_Const(uint32_t Value, uint32_t VAddr) ShiftRightUnsignImmed(TempReg2, 12); MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4); CompileWriteTLBMiss(TempReg1, TempReg2); + AddConstToX86Reg(TempReg2, (uint32_t)m_MMU.Rdram()); CPU_Message(""); CPU_Message(stdstr_f(" MemoryWriteMap_%X_Found:", m_CompilePC).c_str()); SetJump8(JumpFound, *g_RecompPos); @@ -11200,6 +11231,7 @@ void CX86RecompilerOps::SW_Register(x86Reg Reg, uint32_t VAddr) ShiftRightUnsignImmed(TempReg2, 12); MoveVariableDispToX86Reg(g_MMU->m_TLB_WriteMap, "MMU->TLB_WriteMap", TempReg2, TempReg2, 4); CompileWriteTLBMiss(TempReg1, TempReg2); + AddConstToX86Reg(TempReg2, (uint32_t)m_MMU.Rdram()); CPU_Message(""); CPU_Message(stdstr_f(" MemoryWriteMap_%X_Found:", m_CompilePC).c_str()); SetJump8(JumpFound, *g_RecompPos);