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Merge pull request #1002 from cxd4/rsp-compiled-o_OOO 

[RSP] Optimize compiling scalar whole selections.
This commit is contained in:
zilmar 2016-06-05 17:12:26 +10:00
parent 077780d0f3 30aedd45ba
commit b8507e6b4b
1 changed files with 46 additions and 46 deletions
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92
Source/RSP/Recompiler Ops.c
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@ -2126,7 +2126,7 @@ Boolean Compile_Vector_VMULF_MMX(void)
/* Do our MMX checks here */
if (IsMmxEnabled == FALSE)
return FALSE;
if ((RSPOpC.rs & 0x0f) >= 2 && (RSPOpC.rs & 0x0f) <= 7 && IsMmx2Enabled == FALSE)
if ((RSPOpC.rs & 0x0f) >= 2 && !(RSPOpC.rs & 8) && IsMmx2Enabled == FALSE)
return FALSE;
/* NOTE: Problem here is the lack of +/- 0x8000 rounding */
@ -2145,7 +2145,7 @@ Boolean Compile_Vector_VMULF_MMX(void)
sprintf(Reg, "RSP_Vect[%i].UHW[4]", RSPOpC.rt);
MmxPmulhwRegToVariable(x86_MM1, &RSP_Vect[RSPOpC.rt].UHW[4], Reg);
}
} else if ((RSPOpC.rs & 0xF) >= 8) {
} else if (RSPOpC.rs & 8) {
RSP_Element2Mmx(x86_MM2);
MmxPmulhwRegToReg(x86_MM0, x86_MM2);
MmxPmulhwRegToReg(x86_MM1, x86_MM2);
@ -2172,7 +2172,7 @@ void Compile_Vector_VMULF ( void ) {
char Reg[256];
int count, el, del;
Boolean bOptimize = ((RSPOpC.rs & 0xF) >= 8) ? TRUE : FALSE;
Boolean bOptimize = (RSPOpC.rs & 8) ? TRUE : FALSE;
Boolean bWriteToAccum = WriteToAccum(EntireAccum, CompilePC);
Boolean bWriteToDest = WriteToVectorDest(RSPOpC.sa, CompilePC);
@ -2275,7 +2275,7 @@ Boolean Compile_Vector_VMUDL_MMX(void)
MmxPmulhuwRegToReg(x86_MM0, x86_MM2);
MmxPmulhuwRegToReg(x86_MM1, x86_MM3);
}
} else if ((RSPOpC.rs & 0xF) >= 8) {
} else if (RSPOpC.rs & 8) {
RSP_Element2Mmx(x86_MM2);
MmxPmulhuwRegToReg(x86_MM0, x86_MM2);
MmxPmulhuwRegToReg(x86_MM1, x86_MM2);
@ -2300,7 +2300,7 @@ void Compile_Vector_VMUDL ( void ) {
char Reg[256];
int count, el, del;
Boolean bOptimize = ((RSPOpC.rs & 0xF) >= 8) ? TRUE : FALSE;
Boolean bOptimize = (RSPOpC.rs & 8) ? TRUE : FALSE;
Boolean bWriteToDest = WriteToVectorDest(RSPOpC.sa, CompilePC);
Boolean bWriteToAccum = WriteToAccum(EntireAccum, CompilePC);
@ -2388,7 +2388,7 @@ Boolean Compile_Vector_VMUDM_MMX(void)
MmxPsrawImmed(x86_MM3, 15);
MmxPmullwRegToReg(x86_MM2, x86_MM4);
MmxPmullwRegToReg(x86_MM3, x86_MM5);
} else if ((RSPOpC.rs & 0xF) >= 8) {
} else if (RSPOpC.rs & 8) {
RSP_Element2Mmx(x86_MM4);
/* Copy the signed portion */
@ -2441,7 +2441,7 @@ void Compile_Vector_VMUDM ( void ) {
char Reg[256];
int count, el, del;
Boolean bOptimize = ((RSPOpC.rs & 0xF) >= 8) ? TRUE : FALSE;
Boolean bOptimize = (RSPOpC.rs & 8) ? TRUE : FALSE;
Boolean bWriteToDest = WriteToVectorDest(RSPOpC.sa, CompilePC);
Boolean bWriteToAccum = WriteToAccum(EntireAccum, CompilePC);
@ -2528,7 +2528,7 @@ Boolean Compile_Vector_VMUDN_MMX(void)
/* Do our MMX checks here */
if (IsMmxEnabled == FALSE)
return FALSE;
if ((RSPOpC.rs & 0x0f) >= 2 && (RSPOpC.rs & 0x0f) <= 7 && IsMmx2Enabled == FALSE)
if ((RSPOpC.rs & 0x0f) >= 2 && !(RSPOpC.rs & 8) && IsMmx2Enabled == FALSE)
return FALSE;
sprintf(Reg, "RSP_Vect[%i].UHW[0]", RSPOpC.rd);
@ -2541,7 +2541,7 @@ Boolean Compile_Vector_VMUDN_MMX(void)
MmxPmullwVariableToReg(x86_MM0, &RSP_Vect[RSPOpC.rt].UHW[0], Reg);
sprintf(Reg, "RSP_Vect[%i].UHW[4]", RSPOpC.rt);
MmxPmullwVariableToReg(x86_MM1, &RSP_Vect[RSPOpC.rt].UHW[4], Reg);
} else if ((RSPOpC.rs & 0xF) >= 8) {
} else if (RSPOpC.rs & 8) {
RSP_Element2Mmx(x86_MM2);
MmxPmullwRegToReg(x86_MM0, x86_MM2);
MmxPmullwRegToReg(x86_MM1, x86_MM2);
@ -2566,7 +2566,7 @@ void Compile_Vector_VMUDN ( void ) {
char Reg[256];
int count, el, del;
Boolean bOptimize = ((RSPOpC.rs & 0xF) >= 8) ? TRUE : FALSE;
Boolean bOptimize = (RSPOpC.rs & 8) ? TRUE : FALSE;
Boolean bWriteToDest = WriteToVectorDest(RSPOpC.sa, CompilePC);
Boolean bWriteToAccum = WriteToAccum(EntireAccum, CompilePC);
@ -2632,7 +2632,7 @@ Boolean Compile_Vector_VMUDH_MMX(void)
/* Do our MMX checks here */
if (IsMmxEnabled == FALSE)
return FALSE;
if ((RSPOpC.rs & 0x0f) >= 2 && (RSPOpC.rs & 0x0f) <= 7 && IsMmx2Enabled == FALSE)
if ((RSPOpC.rs & 0x0f) >= 2 && !(RSPOpC.rs & 8) && IsMmx2Enabled == FALSE)
return FALSE;
sprintf(Reg, "RSP_Vect[%i].HW[0]", RSPOpC.rd);
@ -2661,7 +2661,7 @@ Boolean Compile_Vector_VMUDH_MMX(void)
MmxPmullwRegToReg(x86_MM1, x86_MM3);
MmxPmulhwRegToReg(x86_MM5, x86_MM3);
}
} else if ((RSPOpC.rs & 0x0f) >= 8) {
} else if (RSPOpC.rs & 8) {
RSP_Element2Mmx(x86_MM2);
MmxPmullwRegToReg(x86_MM0, x86_MM2);
@ -2705,7 +2705,7 @@ void Compile_Vector_VMUDH ( void ) {
char Reg[256];
int count, el, del;
Boolean bOptimize = ((RSPOpC.rs & 0xF) >= 8) ? TRUE : FALSE;
Boolean bOptimize = (RSPOpC.rs & 8) ? TRUE : FALSE;
Boolean bWriteToDest = WriteToVectorDest(RSPOpC.sa, CompilePC);
Boolean bWriteToAccum = WriteToAccum(EntireAccum, CompilePC);
@ -2838,7 +2838,7 @@ void Compile_Vector_VMACF ( void ) {
char Reg[256];
int count, el, del;
Boolean bOptimize = ((RSPOpC.rs & 0xF) >= 8) ? TRUE : FALSE;
Boolean bOptimize = (RSPOpC.rs & 8) ? TRUE : FALSE;
Boolean bWriteToDest = WriteToVectorDest(RSPOpC.sa, CompilePC);
#ifndef CompileVmacf
@ -2909,7 +2909,7 @@ void Compile_Vector_VMADL ( void ) {
char Reg[256];
int count, el, del;
Boolean bOptimize = ((RSPOpC.rs & 0xF) >= 8) ? TRUE : FALSE;
Boolean bOptimize = (RSPOpC.rs & 8) ? TRUE : FALSE;
Boolean bWriteToDest = WriteToVectorDest(RSPOpC.sa, CompilePC);
#ifndef CompileVmadl
@ -2978,7 +2978,7 @@ void Compile_Vector_VMADM ( void ) {
char Reg[256];
int count, el, del;
Boolean bOptimize = ((RSPOpC.rs & 0xF) >= 8) ? TRUE : FALSE;
Boolean bOptimize = (RSPOpC.rs & 8) ? TRUE : FALSE;
Boolean bWriteToDest = WriteToVectorDest(RSPOpC.sa, CompilePC);
#ifndef CompileVmadm
@ -3061,7 +3061,7 @@ void Compile_Vector_VMADN ( void ) {
char Reg[256];
int count, el, del;
Boolean bOptimize = ((RSPOpC.rs & 0xF) >= 8) ? TRUE : FALSE;
Boolean bOptimize = (RSPOpC.rs & 8) ? TRUE : FALSE;
Boolean bWriteToDest = WriteToVectorDest(RSPOpC.sa, CompilePC);
#ifndef CompileVmadn
@ -3135,7 +3135,7 @@ void Compile_Vector_VMADH ( void ) {
char Reg[256];
int count, el, del;
Boolean bOptimize = ((RSPOpC.rs & 0xF) >= 8) ? TRUE : FALSE;
Boolean bOptimize = (RSPOpC.rs & 8) ? TRUE : FALSE;
Boolean bWriteToDest = WriteToVectorDest(RSPOpC.sa, CompilePC);
#ifndef CompileVmadh
@ -3267,7 +3267,7 @@ Boolean Compile_Vector_VADD_MMX(void)
/* Do our MMX checks here */
if (IsMmxEnabled == FALSE)
return FALSE;
if ((RSPOpC.rs & 0x0f) >= 2 && (RSPOpC.rs & 0x0f) <= 7 && IsMmx2Enabled == FALSE)
if ((RSPOpC.rs & 0x0f) >= 2 && !(RSPOpC.rs & 8) && IsMmx2Enabled == FALSE)
return FALSE;
sprintf(Reg, "RSP_Vect[%i].UHW[0]", RSPOpC.rd);
@ -3275,7 +3275,7 @@ Boolean Compile_Vector_VADD_MMX(void)
sprintf(Reg, "RSP_Vect[%i].UHW[4]", RSPOpC.rd);
MmxMoveQwordVariableToReg(x86_MM1, &RSP_Vect[RSPOpC.rd].UHW[4], Reg);
if ((RSPOpC.rs & 15) >= 8) {
if (RSPOpC.rs & 8) {
RSP_Element2Mmx(x86_MM2);
MmxPaddswRegToReg(x86_MM0, x86_MM2);
MmxPaddswRegToReg(x86_MM1, x86_MM2);
@ -3312,7 +3312,7 @@ void Compile_Vector_VADD ( void ) {
int count, el, del;
Boolean bWriteToDest = WriteToVectorDest(RSPOpC.sa, CompilePC);
Boolean bElement = ((RSPOpC.rs & 0xF) >= 8) ? TRUE : FALSE;
Boolean bElement = (RSPOpC.rs & 8) ? TRUE : FALSE;
Boolean bWriteToAccum = WriteToAccum(Low16BitAccum, CompilePC);
Boolean bFlagUseage = UseRspFlags(CompilePC);
@ -3389,7 +3389,7 @@ Boolean Compile_Vector_VSUB_MMX(void)
/* Do our MMX checks here */
if (IsMmxEnabled == FALSE)
return FALSE;
if ((RSPOpC.rs & 0x0f) >= 2 && (RSPOpC.rs & 0x0f) <= 7 && IsMmx2Enabled == FALSE)
if ((RSPOpC.rs & 0x0f) >= 2 && !(RSPOpC.rs & 8) && IsMmx2Enabled == FALSE)
return FALSE;
sprintf(Reg, "RSP_Vect[%i].UHW[0]", RSPOpC.rd);
@ -3433,7 +3433,7 @@ void Compile_Vector_VSUB ( void ) {
int count, el, del;
Boolean bWriteToDest = WriteToVectorDest(RSPOpC.sa, CompilePC);
Boolean bOptimize = ((RSPOpC.rs & 0xF) >= 8) ? TRUE : FALSE;
Boolean bOptimize = (RSPOpC.rs & 8) ? TRUE : FALSE;
Boolean bWriteToAccum = WriteToAccum(Low16BitAccum, CompilePC);
Boolean bFlagUseage = UseRspFlags(CompilePC);
@ -3512,7 +3512,7 @@ Boolean Compile_Vector_VABS_MMX(void)
/* Do our MMX checks here */
if (IsMmxEnabled == FALSE)
return FALSE;
if ((RSPOpC.rs & 0x0f) >= 2 && (RSPOpC.rs & 0x0f) <= 7 && IsMmx2Enabled == FALSE)
if ((RSPOpC.rs & 0x0f) >= 2 && !(RSPOpC.rs & 8) && IsMmx2Enabled == FALSE)
return FALSE;
sprintf(Reg, "RSP_Vect[%i].UHW[0]", RSPOpC.rd);
@ -3684,7 +3684,7 @@ void Compile_Vector_VADDC ( void ) {
Boolean bWriteToDest = WriteToVectorDest(RSPOpC.sa, CompilePC);
Boolean bWriteToAccum = WriteToAccum(Low16BitAccum, CompilePC);
Boolean bElement = ((RSPOpC.rs & 0xF) >= 8) ? TRUE : FALSE;
Boolean bElement = (RSPOpC.rs & 8) ? TRUE : FALSE;
#ifndef CompileVaddc
Cheat_r4300iOpcode(RSP_Vector_VADDC,"RSP_Vector_VADDC"); return;
@ -3749,7 +3749,7 @@ void Compile_Vector_VSUBC ( void ) {
Boolean bWriteToDest = WriteToVectorDest(RSPOpC.sa, CompilePC);
Boolean bWriteToAccum = WriteToAccum(Low16BitAccum, CompilePC);
Boolean bElement = ((RSPOpC.rs & 0xF) >= 8) ? TRUE : FALSE;
Boolean bElement = (RSPOpC.rs & 8) ? TRUE : FALSE;
#ifndef CompileVsubc
Cheat_r4300iOpcode(RSP_Vector_VSUBC,"RSP_Vector_VSUBC"); return;
@ -4082,7 +4082,7 @@ Boolean Compile_Vector_VGE_MMX(void)
{
char Reg[256];
if ((RSPOpC.rs & 0xF) >= 2 && (RSPOpC.rs & 0xF) <= 7 && IsMmx2Enabled == FALSE)
if ((RSPOpC.rs & 0xF) >= 2 && !(RSPOpC.rs & 8) && IsMmx2Enabled == FALSE)
return FALSE;
CPU_Message(" %X %s",CompilePC,RSPOpcodeName(RSPOpC.Hex,CompilePC));
@ -4100,19 +4100,19 @@ Boolean Compile_Vector_VGE_MMX(void)
MmxMoveQwordVariableToReg(x86_MM4, &RSP_Vect[RSPOpC.rt].HW[0], Reg);
sprintf(Reg, "RSP_Vect[%i].HW[4]", RSPOpC.rt);
MmxMoveQwordVariableToReg(x86_MM5, &RSP_Vect[RSPOpC.rt].HW[4], Reg);
} else if ((RSPOpC.rs & 0x0f) >= 8) {
} else if (RSPOpC.rs & 8) {
RSP_Element2Mmx(x86_MM4);
} else {
RSP_MultiElement2Mmx(x86_MM4, x86_MM5);
}
MmxCompareGreaterWordRegToReg(x86_MM2, x86_MM4);
MmxCompareGreaterWordRegToReg(x86_MM3, ((RSPOpC.rs & 0x0f) >= 8) ? x86_MM4 : x86_MM5);
MmxCompareGreaterWordRegToReg(x86_MM3, (RSPOpC.rs & 8) ? x86_MM4 : x86_MM5);
MmxPandRegToReg(x86_MM0, x86_MM2);
MmxPandRegToReg(x86_MM1, x86_MM3);
MmxPandnRegToReg(x86_MM2, x86_MM4);
MmxPandnRegToReg(x86_MM3, ((RSPOpC.rs & 0x0f) >= 8) ? x86_MM4 : x86_MM5);
MmxPandnRegToReg(x86_MM3, (RSPOpC.rs & 8) ? x86_MM4 : x86_MM5);
MmxPorRegToReg(x86_MM0, x86_MM2);
MmxPorRegToReg(x86_MM1, x86_MM3);
@ -4278,7 +4278,7 @@ Boolean Compile_Vector_VAND_MMX(void)
/* Do our MMX checks here */
if (IsMmxEnabled == FALSE)
return FALSE;
if ((RSPOpC.rs & 0x0f) >= 2 && (RSPOpC.rs & 0x0f) <= 7 && IsMmx2Enabled == FALSE)
if ((RSPOpC.rs & 0x0f) >= 2 && !(RSPOpC.rs & 8) && IsMmx2Enabled == FALSE)
return FALSE;
sprintf(Reg, "RSP_Vect[%i].UHW[0]", RSPOpC.rd);
@ -4286,7 +4286,7 @@ Boolean Compile_Vector_VAND_MMX(void)
sprintf(Reg, "RSP_Vect[%i].UHW[4]", RSPOpC.rd);
MmxMoveQwordVariableToReg(x86_MM1, &RSP_Vect[RSPOpC.rd].UHW[4], Reg);
if ((RSPOpC.rs & 0xF) >= 8) {
if (RSPOpC.rs & 8) {
RSP_Element2Mmx(x86_MM2);
MmxPandRegToReg(x86_MM0, x86_MM2);
MmxPandRegToReg(x86_MM1, x86_MM2);
@ -4317,7 +4317,7 @@ void Compile_Vector_VAND(void)
char Reg[256];
int el, del, count;
Boolean bWriteToDest = WriteToVectorDest(RSPOpC.sa, CompilePC);
Boolean bElement = ((RSPOpC.rs & 0xF) >= 8) ? TRUE : FALSE;
Boolean bElement = (RSPOpC.rs & 8) ? TRUE : FALSE;
Boolean bWriteToAccum = WriteToAccum(Low16BitAccum, CompilePC);
#ifndef CompileVand
@ -4372,7 +4372,7 @@ Boolean Compile_Vector_VNAND_MMX(void)
/* Do our MMX checks here */
if (IsMmxEnabled == FALSE)
return FALSE;
if ((RSPOpC.rs & 0x0f) >= 2 && (RSPOpC.rs & 0x0f) <= 7 && IsMmx2Enabled == FALSE)
if ((RSPOpC.rs & 0x0f) >= 2 && !(RSPOpC.rs & 8) && IsMmx2Enabled == FALSE)
return FALSE;
sprintf(Reg, "RSP_Vect[%i].UHW[0]", RSPOpC.rd);
@ -4381,7 +4381,7 @@ Boolean Compile_Vector_VNAND_MMX(void)
MmxMoveQwordVariableToReg(x86_MM1, &RSP_Vect[RSPOpC.rd].UHW[4], Reg);
MmxPcmpeqwRegToReg(x86_MM7, x86_MM7);
if ((RSPOpC.rs & 0xF) >= 8) {
if (RSPOpC.rs & 8) {
RSP_Element2Mmx(x86_MM2);
MmxPandRegToReg(x86_MM0, x86_MM2);
MmxPandRegToReg(x86_MM1, x86_MM2);
@ -4413,7 +4413,7 @@ void Compile_Vector_VNAND ( void ) {
char Reg[256];
int el, del, count;
Boolean bWriteToDest = WriteToVectorDest(RSPOpC.sa, CompilePC);
Boolean bElement = ((RSPOpC.rs & 0xF) >= 8) ? TRUE : FALSE;
Boolean bElement = (RSPOpC.rs & 8) ? TRUE : FALSE;
Boolean bWriteToAccum = WriteToAccum(Low16BitAccum, CompilePC);
#ifndef CompileVnand
@ -4470,7 +4470,7 @@ Boolean Compile_Vector_VOR_MMX(void)
/* Do our MMX checks here */
if (IsMmxEnabled == FALSE)
return FALSE;
if ((RSPOpC.rs & 0x0f) >= 2 && (RSPOpC.rs & 0x0f) <= 7 && IsMmx2Enabled == FALSE)
if ((RSPOpC.rs & 0x0f) >= 2 && !(RSPOpC.rs & 8) && IsMmx2Enabled == FALSE)
return FALSE;
sprintf(Reg, "RSP_Vect[%i].UHW[0]", RSPOpC.rd);
@ -4480,7 +4480,7 @@ Boolean Compile_Vector_VOR_MMX(void)
if ((RSPOpC.rs & 0xF) < 2 && (RSPOpC.rd == RSPOpC.rt)) {
} else if ((RSPOpC.rs & 0xF) >= 8) {
} else if (RSPOpC.rs & 8) {
RSP_Element2Mmx(x86_MM2);
MmxPorRegToReg(x86_MM0, x86_MM2);
MmxPorRegToReg(x86_MM1, x86_MM2);
@ -4509,7 +4509,7 @@ Boolean Compile_Vector_VOR_MMX(void)
void Compile_Vector_VOR ( void ) {
char Reg[256];
int el, del, count;
Boolean bElement = ((RSPOpC.rs & 0xF) >= 8) ? TRUE : FALSE;
Boolean bElement = (RSPOpC.rs & 8) ? TRUE : FALSE;
Boolean bWriteToAccum = WriteToAccum(Low16BitAccum, CompilePC);
#ifndef CompileVor
@ -4561,7 +4561,7 @@ Boolean Compile_Vector_VNOR_MMX(void)
/* Do our MMX checks here */
if (IsMmxEnabled == FALSE)
return FALSE;
if ((RSPOpC.rs & 0x0f) >= 2 && (RSPOpC.rs & 0x0f) <= 7 && IsMmx2Enabled == FALSE)
if ((RSPOpC.rs & 0x0f) >= 2 && !(RSPOpC.rs & 8) && IsMmx2Enabled == FALSE)
return FALSE;
sprintf(Reg, "RSP_Vect[%i].UHW[0]", RSPOpC.rd);
@ -4570,7 +4570,7 @@ Boolean Compile_Vector_VNOR_MMX(void)
MmxMoveQwordVariableToReg(x86_MM1, &RSP_Vect[RSPOpC.rd].UHW[4], Reg);
MmxPcmpeqwRegToReg(x86_MM7, x86_MM7);
if ((RSPOpC.rs & 0xF) >= 8) {
if (RSPOpC.rs & 8) {
RSP_Element2Mmx(x86_MM2);
MmxPorRegToReg(x86_MM0, x86_MM2);
MmxPorRegToReg(x86_MM1, x86_MM2);
@ -4601,7 +4601,7 @@ Boolean Compile_Vector_VNOR_MMX(void)
void Compile_Vector_VNOR ( void ) {
char Reg[256];
int el, del, count;
Boolean bElement = ((RSPOpC.rs & 0xF) >= 8) ? TRUE : FALSE;
Boolean bElement = (RSPOpC.rs & 8) ? TRUE : FALSE;
Boolean bWriteToAccum = WriteToAccum(Low16BitAccum, CompilePC);
#ifndef CompileVnor
@ -4655,7 +4655,7 @@ Boolean Compile_Vector_VXOR_MMX(void)
/* Do our MMX checks here */
if (IsMmxEnabled == FALSE)
return FALSE;
if ((RSPOpC.rs & 0x0f) >= 2 && (RSPOpC.rs & 0x0f) <= 7 && IsMmx2Enabled == FALSE)
if ((RSPOpC.rs & 0x0f) >= 2 && !(RSPOpC.rs & 8) && IsMmx2Enabled == FALSE)
return FALSE;
if ((RSPOpC.rs & 0xF) < 2 && (RSPOpC.rd == RSPOpC.rt)) {
@ -4673,7 +4673,7 @@ Boolean Compile_Vector_VXOR_MMX(void)
sprintf(Reg, "RSP_Vect[%i].UHW[4]", RSPOpC.rd);
MmxMoveQwordVariableToReg(x86_MM1, &RSP_Vect[RSPOpC.rd].UHW[4], Reg);
if ((RSPOpC.rs & 0xF) >= 8) {
if (RSPOpC.rs & 8) {
RSP_Element2Mmx(x86_MM2);
MmxXorRegToReg(x86_MM0, x86_MM2);
MmxXorRegToReg(x86_MM1, x86_MM2);
@ -4736,7 +4736,7 @@ Boolean Compile_Vector_VNXOR_MMX(void)
/* Do our MMX checks here */
if (IsMmxEnabled == FALSE)
return FALSE;
if ((RSPOpC.rs & 0x0f) >= 2 && (RSPOpC.rs & 0x0f) <= 7 && IsMmx2Enabled == FALSE)
if ((RSPOpC.rs & 0x0f) >= 2 && !(RSPOpC.rs & 8) && IsMmx2Enabled == FALSE)
return FALSE;
if ((RSPOpC.rs & 0xF) < 2 && (RSPOpC.rd == RSPOpC.rt)) {
@ -4755,7 +4755,7 @@ Boolean Compile_Vector_VNXOR_MMX(void)
MmxMoveQwordVariableToReg(x86_MM1, &RSP_Vect[RSPOpC.rd].UHW[4], Reg);
MmxPcmpeqwRegToReg(x86_MM7, x86_MM7);
if ((RSPOpC.rs & 0xF) >= 8) {
if (RSPOpC.rs & 8) {
RSP_Element2Mmx(x86_MM2);
MmxXorRegToReg(x86_MM0, x86_MM2);
MmxXorRegToReg(x86_MM1, x86_MM2);