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[Android] Get PushArmReg to handle the rest of the registers

This commit is contained in:
zilmar 2016-10-01 11:37:50 +10:00
parent f41484339d
commit b0f9a7773d
1 changed files with 32 additions and 15 deletions
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47
Source/Project64-core/N64System/Recompiler/Arm/ArmOps.cpp
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@ -550,15 +550,11 @@ void CArmOps::PushArmReg(uint16_t Registers)
{
return;
}
if ((Registers & ArmPushPop_R8) != 0) { g_Notify->BreakPoint(__FILE__,__LINE__); }
if ((Registers & ArmPushPop_R9) != 0) { g_Notify->BreakPoint(__FILE__,__LINE__); }
if ((Registers & ArmPushPop_R10) != 0) { g_Notify->BreakPoint(__FILE__,__LINE__); }
if ((Registers & ArmPushPop_R11) != 0) { g_Notify->BreakPoint(__FILE__,__LINE__); }
if ((Registers & ArmPushPop_R12) != 0) { g_Notify->BreakPoint(__FILE__,__LINE__); }
if ((Registers & ArmPushPop_R13) != 0) { g_Notify->BreakPoint(__FILE__,__LINE__); }
if ((Registers & ArmPushPop_R15) != 0) { g_Notify->BreakPoint(__FILE__,__LINE__); }
if ((Registers & ArmPushPop_SP) != 0) { g_Notify->BreakPoint(__FILE__,__LINE__); }
if ((Registers & ArmPushPop_PC) != 0) { g_Notify->BreakPoint(__FILE__,__LINE__); }
std::string pushed;
if ((Registers & ArmPushPop_R0) != 0) { pushed += pushed.length() > 0 ? ", r0" : "r0"; }
if ((Registers & ArmPushPop_R1) != 0) { pushed += pushed.length() > 0 ? ", r1" : "r1"; }
if ((Registers & ArmPushPop_R2) != 0) { pushed += pushed.length() > 0 ? ", r2" : "r2"; }
if ((Registers & ArmPushPop_R3) != 0) { pushed += pushed.length() > 0 ? ", r3" : "r3"; }
@ -566,17 +562,38 @@ void CArmOps::PushArmReg(uint16_t Registers)
if ((Registers & ArmPushPop_R5) != 0) { pushed += pushed.length() > 0 ? ", r5" : "r5"; }
if ((Registers & ArmPushPop_R6) != 0) { pushed += pushed.length() > 0 ? ", r6" : "r6"; }
if ((Registers & ArmPushPop_R7) != 0) { pushed += pushed.length() > 0 ? ", r7" : "r7"; }
if ((Registers & ArmPushPop_R8) != 0) { pushed += pushed.length() > 0 ? ", r8" : "r8"; }
if ((Registers & ArmPushPop_R9) != 0) { pushed += pushed.length() > 0 ? ", r9" : "r9"; }
if ((Registers & ArmPushPop_R10) != 0) { pushed += pushed.length() > 0 ? ", r10" : "r10"; }
if ((Registers & ArmPushPop_R11) != 0) { pushed += pushed.length() > 0 ? ", fp" : "fp"; }
if ((Registers & ArmPushPop_R12) != 0) { pushed += pushed.length() > 0 ? ", ip" : "ip"; }
if ((Registers & ArmPushPop_LR) != 0) { pushed += pushed.length() > 0 ? ", lr" : "lr"; }
CPU_Message(" push\t%s", pushed.c_str());
bool lr = (Registers & ArmPushPop_LR) != 0;
Registers &= Registers & ~ArmPushPop_LR;
if ((Registers & ArmPushPop_R8) != 0 ||
(Registers & ArmPushPop_R9) != 0 ||
(Registers & ArmPushPop_R10) != 0 ||
(Registers & ArmPushPop_R11) != 0 ||
(Registers & ArmPushPop_R12) != 0)
{
CPU_Message("%X: push\t{%s}", (int32_t)*g_RecompPos, pushed.c_str());
ArmThumbOpcode op = {0};
op.Push.register_list = (uint8_t)Registers;
op.Push.m = lr ? 1 : 0;
op.Push.opcode = ArmPUSH;
AddCode16(op.Hex);
Arm32Opcode op = {0};
op.PushPop.register_list = Registers;
op.PushPop.opcode = 0xE92D;
AddCode32(op.Hex);
}
else
{
CPU_Message(" push\t%s", pushed.c_str());
bool lr = (Registers & ArmPushPop_LR) != 0;
Registers &= Registers & ~ArmPushPop_LR;
ArmThumbOpcode op = {0};
op.Push.register_list = (uint8_t)Registers;
op.Push.m = lr ? 1 : 0;
op.Push.opcode = ArmPUSH;
AddCode16(op.Hex);
}
}
void CArmOps::PopArmReg(uint16_t Registers)