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[Project64] Add Write32MIPSInterface

This commit is contained in:
zilmar 2015-12-22 16:31:13 +11:00
parent 31159ed039
commit adc422fca7
2 changed files with 112 additions and 105 deletions
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188
Source/Project64-core/N64System/Mips/MemoryVirtualMem.cpp
View File

@ -2662,97 +2662,7 @@ bool CMipsMemoryVM::SW_NonMemory(uint32_t PAddr, uint32_t Value)
}
break;
case 0x04100000: Write32DPCommandRegisters(); break;
case 0x04300000:
switch (PAddr)
{
case 0x04300000:
g_Reg->MI_MODE_REG &= ~0x7F;
g_Reg->MI_MODE_REG |= (Value & 0x7F);
if ((Value & MI_CLR_INIT) != 0)
{
g_Reg->MI_MODE_REG &= ~MI_MODE_INIT;
}
if ((Value & MI_SET_INIT) != 0)
{
g_Reg->MI_MODE_REG |= MI_MODE_INIT;
}
if ((Value & MI_CLR_EBUS) != 0)
{
g_Reg->MI_MODE_REG &= ~MI_MODE_EBUS;
}
if ((Value & MI_SET_EBUS) != 0)
{
g_Reg->MI_MODE_REG |= MI_MODE_EBUS;
}
if ((Value & MI_CLR_DP_INTR) != 0)
{
g_Reg->MI_INTR_REG &= ~MI_INTR_DP;
g_Reg->m_GfxIntrReg &= ~MI_INTR_DP;
g_Reg->CheckInterrupts();
}
if ((Value & MI_CLR_RDRAM) != 0)
{
g_Reg->MI_MODE_REG &= ~MI_MODE_RDRAM;
}
if ((Value & MI_SET_RDRAM) != 0)
{
g_Reg->MI_MODE_REG |= MI_MODE_RDRAM;
}
break;
case 0x0430000C:
if ((Value & MI_INTR_MASK_CLR_SP) != 0)
{
g_Reg->MI_INTR_MASK_REG &= ~MI_INTR_MASK_SP;
}
if ((Value & MI_INTR_MASK_SET_SP) != 0)
{
g_Reg->MI_INTR_MASK_REG |= MI_INTR_MASK_SP;
}
if ((Value & MI_INTR_MASK_CLR_SI) != 0)
{
g_Reg->MI_INTR_MASK_REG &= ~MI_INTR_MASK_SI;
}
if ((Value & MI_INTR_MASK_SET_SI) != 0)
{
g_Reg->MI_INTR_MASK_REG |= MI_INTR_MASK_SI;
}
if ((Value & MI_INTR_MASK_CLR_AI) != 0)
{
g_Reg->MI_INTR_MASK_REG &= ~MI_INTR_MASK_AI;
}
if ((Value & MI_INTR_MASK_SET_AI) != 0)
{
g_Reg->MI_INTR_MASK_REG |= MI_INTR_MASK_AI;
}
if ((Value & MI_INTR_MASK_CLR_VI) != 0)
{
g_Reg->MI_INTR_MASK_REG &= ~MI_INTR_MASK_VI;
}
if ((Value & MI_INTR_MASK_SET_VI) != 0)
{
g_Reg->MI_INTR_MASK_REG |= MI_INTR_MASK_VI;
}
if ((Value & MI_INTR_MASK_CLR_PI) != 0)
{
g_Reg->MI_INTR_MASK_REG &= ~MI_INTR_MASK_PI;
}
if ((Value & MI_INTR_MASK_SET_PI) != 0)
{
g_Reg->MI_INTR_MASK_REG |= MI_INTR_MASK_PI;
}
if ((Value & MI_INTR_MASK_CLR_DP) != 0)
{
g_Reg->MI_INTR_MASK_REG &= ~MI_INTR_MASK_DP;
}
if ((Value & MI_INTR_MASK_SET_DP) != 0)
{
g_Reg->MI_INTR_MASK_REG |= MI_INTR_MASK_DP;
}
break;
default:
return false;
}
break;
case 0x04300000: Write32MIPSInterface(); break;
case 0x04400000:
switch (PAddr)
{
@ -5738,3 +5648,99 @@ void CMipsMemoryVM::Write32DPCommandRegisters(void)
}
}
}
void CMipsMemoryVM::Write32MIPSInterface(void)
{
switch ((m_MemLookupAddress & 0xFFFFFFF))
{
case 0x04300000:
g_Reg->MI_MODE_REG &= ~0x7F;
g_Reg->MI_MODE_REG |= (m_MemLookupValue.UW[0] & 0x7F);
if ((m_MemLookupValue.UW[0] & MI_CLR_INIT) != 0)
{
g_Reg->MI_MODE_REG &= ~MI_MODE_INIT;
}
if ((m_MemLookupValue.UW[0] & MI_SET_INIT) != 0)
{
g_Reg->MI_MODE_REG |= MI_MODE_INIT;
}
if ((m_MemLookupValue.UW[0] & MI_CLR_EBUS) != 0)
{
g_Reg->MI_MODE_REG &= ~MI_MODE_EBUS;
}
if ((m_MemLookupValue.UW[0] & MI_SET_EBUS) != 0)
{
g_Reg->MI_MODE_REG |= MI_MODE_EBUS;
}
if ((m_MemLookupValue.UW[0] & MI_CLR_DP_INTR) != 0)
{
g_Reg->MI_INTR_REG &= ~MI_INTR_DP;
g_Reg->m_GfxIntrReg &= ~MI_INTR_DP;
g_Reg->CheckInterrupts();
}
if ((m_MemLookupValue.UW[0] & MI_CLR_RDRAM) != 0)
{
g_Reg->MI_MODE_REG &= ~MI_MODE_RDRAM;
}
if ((m_MemLookupValue.UW[0] & MI_SET_RDRAM) != 0)
{
g_Reg->MI_MODE_REG |= MI_MODE_RDRAM;
}
break;
case 0x0430000C:
if ((m_MemLookupValue.UW[0] & MI_INTR_MASK_CLR_SP) != 0)
{
g_Reg->MI_INTR_MASK_REG &= ~MI_INTR_MASK_SP;
}
if ((m_MemLookupValue.UW[0] & MI_INTR_MASK_SET_SP) != 0)
{
g_Reg->MI_INTR_MASK_REG |= MI_INTR_MASK_SP;
}
if ((m_MemLookupValue.UW[0] & MI_INTR_MASK_CLR_SI) != 0)
{
g_Reg->MI_INTR_MASK_REG &= ~MI_INTR_MASK_SI;
}
if ((m_MemLookupValue.UW[0] & MI_INTR_MASK_SET_SI) != 0)
{
g_Reg->MI_INTR_MASK_REG |= MI_INTR_MASK_SI;
}
if ((m_MemLookupValue.UW[0] & MI_INTR_MASK_CLR_AI) != 0)
{
g_Reg->MI_INTR_MASK_REG &= ~MI_INTR_MASK_AI;
}
if ((m_MemLookupValue.UW[0] & MI_INTR_MASK_SET_AI) != 0)
{
g_Reg->MI_INTR_MASK_REG |= MI_INTR_MASK_AI;
}
if ((m_MemLookupValue.UW[0] & MI_INTR_MASK_CLR_VI) != 0)
{
g_Reg->MI_INTR_MASK_REG &= ~MI_INTR_MASK_VI;
}
if ((m_MemLookupValue.UW[0] & MI_INTR_MASK_SET_VI) != 0)
{
g_Reg->MI_INTR_MASK_REG |= MI_INTR_MASK_VI;
}
if ((m_MemLookupValue.UW[0] & MI_INTR_MASK_CLR_PI) != 0)
{
g_Reg->MI_INTR_MASK_REG &= ~MI_INTR_MASK_PI;
}
if ((m_MemLookupValue.UW[0] & MI_INTR_MASK_SET_PI) != 0)
{
g_Reg->MI_INTR_MASK_REG |= MI_INTR_MASK_PI;
}
if ((m_MemLookupValue.UW[0] & MI_INTR_MASK_CLR_DP) != 0)
{
g_Reg->MI_INTR_MASK_REG &= ~MI_INTR_MASK_DP;
}
if ((m_MemLookupValue.UW[0] & MI_INTR_MASK_SET_DP) != 0)
{
g_Reg->MI_INTR_MASK_REG |= MI_INTR_MASK_DP;
}
break;
default:
if (bHaveDebugger())
{
g_Notify->BreakPoint(__FILE__, __LINE__);
}
}
}

1
Source/Project64-core/N64System/Mips/MemoryVirtualMem.h
View File

@ -199,6 +199,7 @@ private:
static void Write32RDRAMRegisters(void);
static void Write32SPRegisters(void);
static void Write32DPCommandRegisters(void);
static void Write32MIPSInterface(void);
CMipsMemory_CallBack * const m_CBClass;