RSP: Add Compile_Vector_VRNDP, Compile_Vector_VMULQ, Compile_Opcode_LWV
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@ -264,8 +264,8 @@ void BuildRecompilerCPU(void)
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RSP_Vector[0] = Compile_Vector_VMULF;
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RSP_Vector[1] = Compile_Vector_VMULU;
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RSP_Vector[2] = Compile_UnknownOpcode;
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RSP_Vector[3] = Compile_UnknownOpcode;
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RSP_Vector[2] = Compile_Vector_VRNDP;
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RSP_Vector[3] = Compile_Vector_VMULQ;
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RSP_Vector[4] = Compile_Vector_VMUDL;
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RSP_Vector[5] = Compile_Vector_VMUDM;
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RSP_Vector[6] = Compile_Vector_VMUDN;
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@ -337,7 +337,7 @@ void BuildRecompilerCPU(void)
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RSP_Lc2[7] = Compile_Opcode_LUV;
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RSP_Lc2[8] = Compile_Opcode_LHV;
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RSP_Lc2[9] = Compile_Opcode_LFV;
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RSP_Lc2[10] = Compile_UnknownOpcode;
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RSP_Lc2[10] = Compile_Opcode_LWV;
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RSP_Lc2[11] = Compile_Opcode_LTV;
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RSP_Lc2[12] = Compile_UnknownOpcode;
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RSP_Lc2[13] = Compile_UnknownOpcode;
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@ -583,7 +583,6 @@ void Compile_ADDIU(void)
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#else
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CPU_Message(" %X %s", CompilePC, RSPInstruction(CompilePC, RSPOpC.Value).NameAndParam().c_str());
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int Immediate = (short)RSPOpC.immediate;
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if (RSPOpC.rt == RSPOpC.rs)
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@ -651,7 +650,6 @@ void Compile_SLTIU(void)
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CPU_Message(" %X %s", CompilePC, RSPInstruction(CompilePC, RSPOpC.Value).NameAndParam().c_str());
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Immediate = (short)RSPOpC.immediate;
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XorX86RegToX86Reg(x86_ECX, x86_ECX);
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CompConstToVariable(Immediate, &RSP_GPR[RSPOpC.rs].UW, GPR_Name(RSPOpC.rs));
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@ -672,7 +670,6 @@ void Compile_ANDI(void)
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#else
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CPU_Message(" %X %s", CompilePC, RSPInstruction(CompilePC, RSPOpC.Value).NameAndParam().c_str());
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int Immediate = (unsigned short)RSPOpC.immediate;
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if (RSPOpC.rt == RSPOpC.rs)
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{
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@ -2209,6 +2206,18 @@ void Compile_Cop0_MF(void)
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Call_Direct(AddressOf(&RSPRegisterHandlerPlugin::ReadReg), "RSPRegisterHandlerPlugin::ReadReg");
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MoveX86regToVariable(x86_EAX, &RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt));
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break;
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case 2:
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MoveConstToX86reg((uint32_t)(g_RSPRegisterHandler.get()), x86_ECX);
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PushImm32("RSPRegister_RD_LEN", RSPRegister_RD_LEN);
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Call_Direct(AddressOf(&RSPRegisterHandlerPlugin::ReadReg), "RSPRegisterHandlerPlugin::ReadReg");
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MoveX86regToVariable(x86_EAX, &RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt));
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break;
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case 3:
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MoveConstToX86reg((uint32_t)(g_RSPRegisterHandler.get()), x86_ECX);
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PushImm32("RSPRegister_WR_LEN", RSPRegister_WR_LEN);
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Call_Direct(AddressOf(&RSPRegisterHandlerPlugin::ReadReg), "RSPRegisterHandlerPlugin::ReadReg");
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MoveX86regToVariable(x86_EAX, &RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt));
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break;
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case 4:
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MoveConstToX86reg((uint32_t)(g_RSPRegisterHandler.get()), x86_ECX);
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PushImm32("RSPRegister_STATUS", RSPRegister_STATUS);
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@ -2863,6 +2872,16 @@ void Compile_Vector_VMULU(void)
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Cheat_r4300iOpcode(RSP_Vector_VMULU, "RSP_Vector_VMULU");
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}
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void Compile_Vector_VRNDP(void)
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{
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Cheat_r4300iOpcode(RSP_Vector_VRNDP, "RSP_Vector_VRNDP");
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}
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void Compile_Vector_VMULQ(void)
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{
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Cheat_r4300iOpcode(RSP_Vector_VMULQ, "RSP_Vector_VMULQ");
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}
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bool Compile_Vector_VMUDL_MMX(void)
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{
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char Reg[256];
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@ -6070,12 +6089,6 @@ void Compile_Opcode_LSV(void)
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char Reg[256];
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int offset = (RSPOpC.voffset << 1);
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if (RSPOpC.del > 14)
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{
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rsp_UnknownOpcode();
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return;
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}
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#ifndef CompileLsv
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Cheat_r4300iOpcode(RSP_Opcode_LSV, "RSP_Opcode_LSV");
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return;
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@ -6442,7 +6455,7 @@ void Compile_Opcode_LRV(void)
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if (RSPOpC.del != 0)
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{
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rsp_UnknownOpcode();
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Cheat_r4300iOpcode(RSP_Opcode_LRV, "RSP_Opcode_LRV");
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return;
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}
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@ -6840,6 +6853,11 @@ void Compile_Opcode_LFV(void)
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Cheat_r4300iOpcode(RSP_Opcode_LFV, "RSP_Opcode_LFV");
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}
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void Compile_Opcode_LWV(void)
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{
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Cheat_r4300iOpcode(RSP_Opcode_LWV, "RSP_Opcode_LWV");
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}
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void Compile_Opcode_LTV(void)
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{
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Cheat_r4300iOpcode(RSP_Opcode_LTV, "RSP_Opcode_LTV");
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@ -76,6 +76,8 @@ void Compile_COP2_VECTOR(void);
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void Compile_Vector_VMULF(void);
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void Compile_Vector_VMULU(void);
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void Compile_Vector_VRNDP(void);
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void Compile_Vector_VMULQ(void);
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void Compile_Vector_VMUDL(void);
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void Compile_Vector_VMUDM(void);
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void Compile_Vector_VMUDN(void);
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@ -128,6 +130,7 @@ void Compile_Opcode_LPV(void);
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void Compile_Opcode_LUV(void);
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void Compile_Opcode_LHV(void);
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void Compile_Opcode_LFV(void);
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void Compile_Opcode_LWV(void);
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void Compile_Opcode_LTV(void);
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// SC2 functions
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