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Core: have tlb read/write map use -1 for an empty value

This commit is contained in:
zilmar 2025-05-08 15:08:53 +09:30
parent 400f110fc5
commit abbd18d6b4
3 changed files with 31 additions and 33 deletions
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52
Source/Project64-core/N64System/Mips/MemoryVirtualMem.cpp
View File

@ -73,26 +73,24 @@ void CMipsMemoryVM::Reset(bool /*EraseMemory*/)
{
if (m_TLB_ReadMap)
{
size_t address;
memset(m_TLB_ReadMap, 0, 0xFFFFF * sizeof(size_t));
memset(m_TLB_WriteMap, 0, 0xFFFFF * sizeof(size_t));
for (address = 0x80000000; address < 0xC0000000; address += 0x1000)
memset(m_TLB_ReadMap, -1, 0xFFFFF * sizeof(m_TLB_ReadMap[0]));
memset(m_TLB_WriteMap, -1, 0xFFFFF * sizeof(m_TLB_WriteMap[0]));
for (uint32_t Address = 0x80000000; Address < 0xC0000000; Address += 0x1000)
{
m_TLB_ReadMap[address >> 12] = ((size_t)m_RDRAM + (address & 0x1FFFFFFF)) - address;
m_TLB_WriteMap[address >> 12] = ((size_t)m_RDRAM + (address & 0x1FFFFFFF)) - address;
m_TLB_ReadMap[Address >> 12] = ((size_t)m_RDRAM + (Address & 0x1FFFFFFF)) - Address;
m_TLB_WriteMap[Address >> 12] = ((size_t)m_RDRAM + (Address & 0x1FFFFFFF)) - Address;
}
if (g_Settings->LoadDword(Rdb_TLB_VAddrStart) != 0)
{
size_t Start = g_Settings->LoadDword(Rdb_TLB_VAddrStart); //0x7F000000;
size_t Len = g_Settings->LoadDword(Rdb_TLB_VAddrLen); //0x01000000;
size_t PAddr = g_Settings->LoadDword(Rdb_TLB_PAddrStart); //0x10034b30;
size_t End = Start + Len;
for (address = Start; address < End; address += 0x1000)
uint32_t Start = g_Settings->LoadDword(Rdb_TLB_VAddrStart); //0x7F000000;
uint32_t Len = g_Settings->LoadDword(Rdb_TLB_VAddrLen); //0x01000000;
uint32_t PAddr = g_Settings->LoadDword(Rdb_TLB_PAddrStart); //0x10034b30;
uint32_t End = Start + Len;
for (uint32_t Address = Start; Address < End; Address += 0x1000)
{
m_TLB_ReadMap[address >> 12] = ((size_t)m_RDRAM + (address - Start + PAddr)) - address;
m_TLB_WriteMap[address >> 12] = ((size_t)m_RDRAM + (address - Start + PAddr)) - address;
m_TLB_ReadMap[Address >> 12] = ((size_t)m_RDRAM + (Address - Start + PAddr)) - Address;
m_TLB_WriteMap[Address >> 12] = ((size_t)m_RDRAM + (Address - Start + PAddr)) - Address;
}
}
}
@ -310,7 +308,7 @@ CFlashram* CMipsMemoryVM::GetFlashram()
bool CMipsMemoryVM::LB_VAddr(uint32_t VAddr, uint8_t& Value)
{
if (m_TLB_ReadMap[VAddr >> 12] == 0)
if (m_TLB_ReadMap[VAddr >> 12] == -1)
{
return false;
}
@ -321,7 +319,7 @@ bool CMipsMemoryVM::LB_VAddr(uint32_t VAddr, uint8_t& Value)
bool CMipsMemoryVM::LH_VAddr(uint32_t VAddr, uint16_t& Value)
{
if (m_TLB_ReadMap[VAddr >> 12] == 0)
if (m_TLB_ReadMap[VAddr >> 12] == -1)
{
return false;
}
@ -343,7 +341,7 @@ bool CMipsMemoryVM::LW_VAddr(uint32_t VAddr, uint32_t& Value)
}
uint8_t* BaseAddress = (uint8_t*)m_TLB_ReadMap[VAddr >> 12];
if (BaseAddress == nullptr)
if (BaseAddress == (uint8_t*)-1)
{
return false;
}
@ -363,7 +361,7 @@ bool CMipsMemoryVM::LW_VAddr(uint32_t VAddr, uint32_t& Value)
bool CMipsMemoryVM::LD_VAddr(uint32_t VAddr, uint64_t& Value)
{
if (m_TLB_ReadMap[VAddr >> 12] == 0)
if (m_TLB_ReadMap[VAddr >> 12] == -1)
{
return false;
}
@ -444,7 +442,7 @@ bool CMipsMemoryVM::LD_PAddr(uint32_t PAddr, uint64_t& Value)
bool CMipsMemoryVM::SB_VAddr(uint32_t VAddr, uint8_t Value)
{
if (m_TLB_WriteMap[VAddr >> 12] == 0)
if (m_TLB_WriteMap[VAddr >> 12] == -1)
{
return false;
}
@ -455,7 +453,7 @@ bool CMipsMemoryVM::SB_VAddr(uint32_t VAddr, uint8_t Value)
bool CMipsMemoryVM::SH_VAddr(uint32_t VAddr, uint16_t Value)
{
if (m_TLB_WriteMap[VAddr >> 12] == 0)
if (m_TLB_WriteMap[VAddr >> 12] == -1)
{
return false;
}
@ -476,7 +474,7 @@ bool CMipsMemoryVM::SW_VAddr(uint32_t VAddr, uint32_t Value)
}
}
if (m_TLB_WriteMap[VAddr >> 12] == 0)
if (m_TLB_WriteMap[VAddr >> 12] == -1)
{
return false;
}
@ -487,7 +485,7 @@ bool CMipsMemoryVM::SW_VAddr(uint32_t VAddr, uint32_t Value)
bool CMipsMemoryVM::SD_VAddr(uint32_t VAddr, uint64_t Value)
{
if (m_TLB_WriteMap[VAddr >> 12] == 0)
if (m_TLB_WriteMap[VAddr >> 12] == -1)
{
return false;
}
@ -568,12 +566,12 @@ bool CMipsMemoryVM::SD_PAddr(uint32_t PAddr, uint64_t Value)
bool CMipsMemoryVM::ValidVaddr(uint32_t VAddr) const
{
return m_TLB_ReadMap[VAddr >> 12] != 0;
return m_TLB_ReadMap[VAddr >> 12] != -1;
}
bool CMipsMemoryVM::VAddrToRealAddr(uint32_t VAddr, void * &RealAddress) const
{
if (m_TLB_ReadMap[VAddr >> 12] == 0)
if (m_TLB_ReadMap[VAddr >> 12] == -1)
{
return false;
}
@ -584,7 +582,7 @@ bool CMipsMemoryVM::VAddrToRealAddr(uint32_t VAddr, void * &RealAddress) const
bool CMipsMemoryVM::TranslateVaddr(uint32_t VAddr, uint32_t &PAddr) const
{
// Change the virtual address to a physical address
if (m_TLB_ReadMap[VAddr >> 12] == 0)
if (m_TLB_ReadMap[VAddr >> 12] == -1)
{
return false;
}
@ -1005,8 +1003,8 @@ void CMipsMemoryVM::TLB_Unmaped(uint32_t Vaddr, uint32_t Len)
for (count = Vaddr; count < End; count += 0x1000)
{
size_t Index = count >> 12;
m_TLB_ReadMap[Index] = 0;
m_TLB_WriteMap[Index] = 0;
m_TLB_ReadMap[Index] = -1;
m_TLB_WriteMap[Index] = -1;
}
}

8
Source/Project64-core/N64System/Mips/MemoryVirtualMem.h
View File

@ -106,8 +106,8 @@ public:
private:
CMipsMemoryVM();
CMipsMemoryVM(const CMipsMemoryVM&);
CMipsMemoryVM& operator=(const CMipsMemoryVM&);
CMipsMemoryVM(const CMipsMemoryVM &);
CMipsMemoryVM & operator=(const CMipsMemoryVM &);
#if defined(__i386__) || defined(_M_IX86)
friend class CX86RecompilerOps;
@ -208,8 +208,8 @@ private:
mutable char m_strLabelName[100];
// Big look up table to quickly translate the TLB to real memory addresses
size_t * m_TLB_ReadMap;
size_t * m_TLB_WriteMap;
uint32_t * m_TLB_ReadMap;
uint32_t * m_TLB_WriteMap;
static uint32_t m_MemLookupAddress;
static MIPS_DWORD m_MemLookupValue;

4
Source/Project64-core/N64System/Recompiler/x86/x86RecompilerOps.cpp
View File

@ -332,14 +332,14 @@ void CX86RecompilerOps::PostCompileOpcode(void)
void CX86RecompilerOps::CompileReadTLBMiss(uint32_t VirtualAddress, x86Reg LookUpReg)
{
MoveConstToVariable(VirtualAddress, g_TLBLoadAddress, "TLBLoadAddress");
TestX86RegToX86Reg(LookUpReg, LookUpReg);
CompConstToX86reg(LookUpReg, -1);
CompileExit(m_CompilePC, m_CompilePC, m_RegWorkingSet, CExitInfo::TLBReadMiss, false, JeLabel32);
}
void CX86RecompilerOps::CompileReadTLBMiss(x86Reg AddressReg, x86Reg LookUpReg)
{
MoveX86regToVariable(AddressReg, g_TLBLoadAddress, "TLBLoadAddress");
TestX86RegToX86Reg(LookUpReg, LookUpReg);
CompConstToX86reg(LookUpReg, -1);
CompileExit(m_CompilePC, m_CompilePC, m_RegWorkingSet, CExitInfo::TLBReadMiss, false, JeLabel32);
}