Merge pull request #656 from LegendOfDragoon/master
Improve VLT, VGE, VEQ, and VNE in RSP Recompiler
This commit is contained in:
zilmar
commit
a903ae5647
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@ -74,6 +74,10 @@ DWORD BranchCompare = 0;
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# define CompileVmadn /* Verified 12/17/2000 - Jabo */
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#endif
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#ifdef RSP_VectorMisc
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# define CompileVne
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# define CompileVeq
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# define CompileVge
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# define CompileVlt
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# define CompileVrcp
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# define CompileVrcpl
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# define CompileVrsqh
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@ -3834,15 +3838,220 @@ void Compile_Vector_VSAW ( void ) {
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}
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void Compile_Vector_VLT ( void ) {
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BOOL bWriteToDest = WriteToVectorDest(RSPOpC.sa, CompilePC);
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BOOL bWriteToAccum = WriteToAccum(Low16BitAccum, CompilePC);
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BYTE *jump[3];
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DWORD flag;
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char Reg[256];
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int el, del, last;
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#ifndef CompileVlt
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Cheat_r4300iOpcode(RSP_Vector_VLT,"RSP_Vector_VLT");
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return;
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#endif
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CPU_Message(" %X %s", CompilePC, RSPOpcodeName(RSPOpC.Hex, CompilePC));
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last = -1;
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XorX86RegToX86Reg(x86_EBX, x86_EBX);
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MoveVariableToX86reg(&RSP_Flags[0].UW, "&RSP_Flags[0].UW", x86_ESI);
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for (el = 0; el < 8; el++) {
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del = EleSpec[RSPOpC.rs].B[el];
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flag = 0x101 << (7 - el);
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if (del != el || RSPOpC.rt != RSPOpC.rd) {
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if (del != last) {
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sprintf(Reg, "RSP_Vect[%i].HW[%i]", RSPOpC.rt, del);
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MoveSxVariableToX86regHalf(&RSP_Vect[RSPOpC.rt].HW[del], Reg, x86_ECX);
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last = del;
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}
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sprintf(Reg, "RSP_Vect[%i].HW[%i]", RSPOpC.rd, el);
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MoveSxVariableToX86regHalf(&RSP_Vect[RSPOpC.rd].HW[el], Reg, x86_EDX);
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CompX86RegToX86Reg(x86_EDX, x86_ECX);
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JgeLabel8("jge", 0);
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jump[0] = (BYTE*)(RecompPos - 1);
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if (bWriteToAccum || bWriteToDest) {
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sprintf(Reg, "RSP_ACCUM[%i].HW[1]", el);
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MoveX86regHalfToVariable(x86_EDX, &RSP_ACCUM[el].HW[1], Reg);
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}
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OrConstToX86Reg((flag & 0xFF), x86_EBX);
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JmpLabel8("jmp", 0);
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jump[1] = (BYTE*)(RecompPos - 1);
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x86_SetBranch8b(jump[0], RecompPos);
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if (bWriteToAccum || bWriteToDest) {
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sprintf(Reg, "RSP_ACCUM[%i].HW[1]", el);
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MoveX86regHalfToVariable(x86_ECX, &RSP_ACCUM[el].HW[1], Reg);
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}
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JneLabel8("jne", 0);
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jump[2] = (BYTE*)(RecompPos - 1);
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MoveX86RegToX86Reg(x86_ESI, x86_EDI);
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AndConstToX86Reg(x86_EDI, flag);
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ShiftRightUnsignImmed(x86_EDI, 8);
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AndX86RegToX86Reg(x86_EDI, x86_ESI);
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OrX86RegToX86Reg(x86_EBX, x86_EDI);
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x86_SetBranch8b(jump[2], RecompPos);
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x86_SetBranch8b(jump[1], RecompPos);
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} else {
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MoveX86RegToX86Reg(x86_ESI, x86_EDI);
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if (bWriteToAccum || bWriteToDest) {
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sprintf(Reg, "RSP_ACCUM[%i].HW[1]", el);
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MoveX86regHalfToVariable(x86_ECX, &RSP_ACCUM[el].HW[1], Reg);
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}
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AndConstToX86Reg(x86_EDI, flag);
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ShiftRightUnsignImmed(x86_EDI, 8);
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AndX86RegToX86Reg(x86_EDI, x86_ESI);
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OrX86RegToX86Reg(x86_EBX, x86_EDI);
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}
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}
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MoveConstToVariable(0, &RSP_Flags[0].UW, "RSP_Flags[0].UW");
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MoveX86regToVariable(x86_EBX, &RSP_Flags[1].UW, "RSP_Flags[1].UW");
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if (bWriteToDest != FALSE) {
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for (el = 0; el < 8; el += 2) {
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sprintf(Reg, "RSP_ACCUM[%i].HW[1]", el);
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MoveVariableToX86regHalf(&RSP_ACCUM[el].HW[1], Reg, x86_EAX);
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sprintf(Reg, "RSP_ACCUM[%i].HW[1]", el + 1);
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MoveVariableToX86regHalf(&RSP_ACCUM[el + 1].HW[1], Reg, x86_ECX);
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sprintf(Reg, "RSP_Vect[%i].HW[%i]", RSPOpC.sa, el);
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MoveX86regHalfToVariable(x86_EAX, &RSP_Vect[RSPOpC.sa].HW[el], Reg);
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sprintf(Reg, "RSP_Vect[%i].HW[%i]", RSPOpC.sa, el + 1);
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MoveX86regHalfToVariable(x86_ECX, &RSP_Vect[RSPOpC.sa].HW[el + 1], Reg);
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}
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}
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}
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void Compile_Vector_VEQ ( void ) {
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BOOL bWriteToDest = WriteToVectorDest(RSPOpC.sa, CompilePC);
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BOOL bWriteToAccum = WriteToAccum(Low16BitAccum, CompilePC);
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DWORD flag;
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char Reg[256];
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int count, el, del, last = -1;
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#ifndef CompileVeq
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Cheat_r4300iOpcode(RSP_Vector_VEQ,"RSP_Vector_VEQ");
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return;
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#endif
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CPU_Message(" %X %s", CompilePC, RSPOpcodeName(RSPOpC.Hex, CompilePC));
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MoveZxVariableToX86regHalf(&RSP_Flags[0].UHW[1], "&RSP_Flags[0].UHW[1]", x86_EBX);
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XorConstToX86Reg(x86_EBX, 0xFFFF);
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for (el = 0; el < 8; el++) {
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del = EleSpec[RSPOpC.rs].B[el];
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flag = (0x101 << (7 - el)) ^ 0xFFFF;
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if (del != el || RSPOpC.rt != RSPOpC.rd) {
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if (del != last) {
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sprintf(Reg, "RSP_Vect[%i].HW[%i]", RSPOpC.rt, del);
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MoveZxVariableToX86regHalf(&RSP_Vect[RSPOpC.rt].HW[del], Reg, x86_ECX);
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last = del;
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}
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sprintf(Reg, "RSP_Vect[%i].HW[%i]", RSPOpC.rd, el);
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MoveZxVariableToX86regHalf(&RSP_Vect[RSPOpC.rd].HW[el], Reg, x86_EDX);
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if (bWriteToAccum) {
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sprintf(Reg, "RSP_ACCUM[%i].HW[1]", el);
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MoveX86regHalfToVariable(x86_ECX, &RSP_ACCUM[el].HW[1], Reg);
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}
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SubX86RegToX86Reg(x86_EDX, x86_ECX);
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CompConstToX86reg(x86_EDX, 1);
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SbbX86RegToX86Reg(x86_EDX, x86_EDX);
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OrConstToX86Reg(flag, x86_EDX);
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AndX86RegToX86Reg(x86_EBX, x86_EDX);
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} else {
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if (bWriteToAccum) {
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sprintf(Reg, "RSP_ACCUM[%i].HW[1]", el);
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MoveX86regHalfToVariable(x86_ECX, &RSP_ACCUM[el].HW[1], Reg);
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}
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}
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}
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MoveConstToVariable(0, &RSP_Flags[0].UW, "RSP_Flags[0].UW");
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MoveX86regToVariable(x86_EBX, &RSP_Flags[1].UW, "RSP_Flags[1].UW");
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if (bWriteToDest != FALSE) {
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for (count = 0; count < 8; count++) {
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el = EleSpec[RSPOpC.rs].B[count];
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if (el != last) {
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sprintf(Reg, "RSP_Vect[%i].UHW[%i]", RSPOpC.rt, el);
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MoveVariableToX86regHalf(&RSP_Vect[RSPOpC.rt].UHW[el], Reg, x86_EDX);
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last = el;
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}
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sprintf(Reg, "RSP_Vect[%i].HW[%i]", RSPOpC.sa, count);
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MoveX86regHalfToVariable(x86_EDX, &RSP_Vect[RSPOpC.sa].HW[count], Reg);
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}
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}
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}
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void Compile_Vector_VNE ( void ) {
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BOOL bWriteToDest = WriteToVectorDest(RSPOpC.sa, CompilePC);
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BOOL bWriteToAccum = WriteToAccum(Low16BitAccum, CompilePC);
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DWORD flag;
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char Reg[256];
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int el, del, last = -1;
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#ifndef CompileVne
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Cheat_r4300iOpcode(RSP_Vector_VNE,"RSP_Vector_VNE");
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return;
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#endif
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CPU_Message(" %X %s", CompilePC, RSPOpcodeName(RSPOpC.Hex, CompilePC));
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MoveZxVariableToX86regHalf(&RSP_Flags[0].UHW[1], "&RSP_Flags[0].UHW[1]", x86_EBX);
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for (el = 0; el < 8; el++) {
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del = EleSpec[RSPOpC.rs].B[el];
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flag = 0x101 << (7 - el);
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if (del != el || RSPOpC.rt != RSPOpC.rd) {
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sprintf(Reg, "RSP_Vect[%i].HW[%i]", RSPOpC.rd, el);
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MoveZxVariableToX86regHalf(&RSP_Vect[RSPOpC.rd].HW[el], Reg, x86_EDX);
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if (del != last) {
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sprintf(Reg, "RSP_Vect[%i].HW[%i]", RSPOpC.rt, del);
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MoveZxVariableToX86regHalf(&RSP_Vect[RSPOpC.rt].HW[del], Reg, x86_ECX);
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last = del;
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}
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if (bWriteToAccum) {
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sprintf(Reg, "RSP_ACCUM[%i].HW[1]", el);
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MoveX86regHalfToVariable(x86_EDX, &RSP_ACCUM[el].HW[1], Reg);
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}
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SubX86RegToX86Reg(x86_EDX, x86_ECX);
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NegateX86reg(x86_EDX);
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SbbX86RegToX86Reg(x86_EDX, x86_EDX);
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AndConstToX86Reg(x86_EDX, flag);
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OrX86RegToX86Reg(x86_EBX, x86_EDX);
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} else {
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if (bWriteToAccum) {
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sprintf(Reg, "RSP_ACCUM[%i].HW[1]", el);
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MoveX86regHalfToVariable(x86_EDX, &RSP_ACCUM[el].HW[1], Reg);
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}
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}
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}
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MoveConstToVariable(0, &RSP_Flags[0].UW, "RSP_Flags[0].UW");
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MoveX86regToVariable(x86_EBX, &RSP_Flags[1].UW, "RSP_Flags[1].UW");
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if (bWriteToDest != FALSE) {
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for (el = 0; el < 4; el++) {
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sprintf(Reg, "RSP_Vect[%i].W[%i]", RSPOpC.rd, el);
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MoveVariableToX86reg(&RSP_Vect[RSPOpC.rd].W[el], Reg, x86_EDX);
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sprintf(Reg, "RSP_Vect[%i].W[%i]", RSPOpC.sa, el);
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MoveX86regToVariable(x86_EDX, &RSP_Vect[RSPOpC.sa].W[el], Reg);
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}
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}
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}
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BOOL Compile_Vector_VGE_MMX ( void ) {
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@ -3896,7 +4105,97 @@ void Compile_Vector_VGE ( void ) {
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}
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#endif
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*/
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BOOL bWriteToDest = WriteToVectorDest(RSPOpC.sa, CompilePC);
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BOOL bWriteToAccum = WriteToAccum(Low16BitAccum, CompilePC);
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BYTE *jump[3];
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DWORD flag;
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char Reg[256];
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int el, del, last = -1;
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#ifndef CompileVge
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Cheat_r4300iOpcode(RSP_Vector_VGE,"RSP_Vector_VGE");
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return;
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#endif
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CPU_Message(" %X %s", CompilePC, RSPOpcodeName(RSPOpC.Hex, CompilePC));
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XorX86RegToX86Reg(x86_EBX, x86_EBX);
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MoveVariableToX86reg(&RSP_Flags[0].UW, "&RSP_Flags[0].UW", x86_ESI);
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for (el = 0; el < 8; el++) {
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del = EleSpec[RSPOpC.rs].B[el];
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flag = 0x101 << (7 - el);
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if (del != el || RSPOpC.rt != RSPOpC.rd) {
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if (del != last) {
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sprintf(Reg, "RSP_Vect[%i].HW[%i]", RSPOpC.rt, del);
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MoveSxVariableToX86regHalf(&RSP_Vect[RSPOpC.rt].HW[del], Reg, x86_ECX);
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last = del;
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}
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sprintf(Reg, "RSP_Vect[%i].HW[%i]", RSPOpC.rd, el);
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MoveSxVariableToX86regHalf(&RSP_Vect[RSPOpC.rd].HW[el], Reg, x86_EDX);
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CompX86RegToX86Reg(x86_EDX, x86_ECX);
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JleLabel8("jle", 0);
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jump[0] = (BYTE*)(RecompPos - 1);
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if (bWriteToAccum || bWriteToDest) {
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sprintf(Reg, "RSP_ACCUM[%i].HW[1]", el);
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MoveX86regHalfToVariable(x86_EDX, &RSP_ACCUM[el].HW[1], Reg);
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}
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OrConstToX86Reg((flag & 0xFF), x86_EBX);
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JmpLabel8("jmp", 0);
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jump[1] = (BYTE*)(RecompPos - 1);\
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x86_SetBranch8b(jump[0], RecompPos);
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if (bWriteToAccum || bWriteToDest) {
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sprintf(Reg, "RSP_ACCUM[%i].HW[1]", el);
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MoveX86regHalfToVariable(x86_ECX, &RSP_ACCUM[el].HW[1], Reg);
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}
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JneLabel8("jne", 0);
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jump[2] = (BYTE*)(RecompPos - 1);
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MoveX86RegToX86Reg(x86_ESI, x86_EDI);
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AndConstToX86Reg(x86_EDI, flag);
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SubConstFromX86Reg(x86_EDI, flag);
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ShiftRightSignImmed(x86_EDI, 31);
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AndConstToX86Reg(x86_EDI, (flag & 0xFF));
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OrX86RegToX86Reg(x86_EBX, x86_EDI);
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x86_SetBranch8b(jump[1], RecompPos);
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x86_SetBranch8b(jump[2], RecompPos);
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} else {
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MoveX86RegToX86Reg(x86_ESI, x86_EDI);
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if (bWriteToAccum || bWriteToDest) {
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sprintf(Reg, "RSP_ACCUM[%i].HW[1]", el);
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MoveX86regHalfToVariable(x86_ECX, &RSP_ACCUM[el].HW[1], Reg);
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}
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AndConstToX86Reg(x86_EDI, flag);
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SubConstFromX86Reg(x86_EDI, flag);
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ShiftRightSignImmed(x86_EDI, 31);
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AndConstToX86Reg(x86_EDI, (flag & 0xFF));
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OrX86RegToX86Reg(x86_EBX, x86_EDI);
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}
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}
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MoveConstToVariable(0, &RSP_Flags[0].UW, "RSP_Flags[0].UW");
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MoveX86regToVariable(x86_EBX, &RSP_Flags[1].UW, "RSP_Flags[1].UW");
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if (bWriteToDest != FALSE) {
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for (el = 0; el < 8; el += 2) {
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sprintf(Reg, "RSP_ACCUM[%i].HW[1]", el + 0);
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MoveVariableToX86regHalf(&RSP_ACCUM[el].HW[1], Reg, x86_EAX);
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sprintf(Reg, "RSP_ACCUM[%i].HW[1]", el + 1);
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MoveVariableToX86regHalf(&RSP_ACCUM[el + 1].HW[1], Reg, x86_ECX);
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sprintf(Reg, "RSP_Vect[%i].HW[%i]", RSPOpC.sa, el + 0);
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MoveX86regHalfToVariable(x86_EAX, &RSP_Vect[RSPOpC.sa].HW[el + 0], Reg);
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sprintf(Reg, "RSP_Vect[%i].HW[%i]", RSPOpC.sa, el + 1);
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MoveX86regHalfToVariable(x86_ECX, &RSP_Vect[RSPOpC.sa].HW[el + 1], Reg);
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}
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}
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}
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void Compile_Vector_VCL ( void ) {
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