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Merge branch 'master' of https://github.com/project64/project64

This commit is contained in:
zilmar 2015-11-29 09:59:44 +11:00
parent 5b7020453e a90bc7d8b2
commit a76ebeccd6
2 changed files with 145 additions and 1 deletions
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144
Source/nragev20/GBCart.cpp
View File

@ -28,6 +28,8 @@ bool ReadCartMBC3(LPGBCART Cart, WORD dwAddress, BYTE *Data);
bool WriteCartMBC3(LPGBCART Cart, WORD dwAddress, BYTE *Data);
bool ReadCartMBC5(LPGBCART Cart, WORD dwAddress, BYTE *Data);
bool WriteCartMBC5(LPGBCART Cart, WORD dwAddress, BYTE *Data);
bool ReadCartCamera(LPGBCART Cart, WORD dwAddress, BYTE *Data);
bool WriteCartCamera(LPGBCART Cart, WORD dwAddress, BYTE *Data);
// Tries to read RTC data from separate file (not integrated into SAV)
// success sets the useTDF flag
@ -289,6 +291,14 @@ bool LoadCart(LPGBCART Cart, LPCTSTR RomFileName, LPCTSTR RamFileName, LPCTSTR T
Cart->bHasTimer = false;
Cart->bHasRumble = true;
break;
case 0xFC:
//GAME BOY CAMERA
Cart->iCartType = GB_CAMERA;
Cart->bHasRam = true;
Cart->bHasBattery = true;
Cart->bHasTimer = false;
Cart->bHasRumble = false;
break;
default:
WarningMessage( IDS_ERR_GBROM, MB_OK | MB_ICONWARNING);
DebugWriteA("TPak: unsupported paktype\n");
@ -319,6 +329,10 @@ bool LoadCart(LPGBCART Cart, LPCTSTR RomFileName, LPCTSTR RamFileName, LPCTSTR T
Cart->ptrfnReadCart = &ReadCartMBC5;
Cart->ptrfnWriteCart = &WriteCartMBC5;
break;
case GB_CAMERA:
Cart->ptrfnReadCart = &ReadCartCamera;
Cart->ptrfnWriteCart = &WriteCartCamera;
break;
default: // Don't pretend we know how to handle carts we don't support
Cart->ptrfnReadCart = NULL;
Cart->ptrfnWriteCart = NULL;
@ -1052,6 +1066,136 @@ bool WriteCartMBC5(LPGBCART Cart, WORD dwAddress, BYTE *Data)
return true;
}
// Done
bool ReadCartCamera(LPGBCART Cart, WORD dwAddress, BYTE *Data)
{
if ((dwAddress < 0x4000)) //Rom Bank 0
{
CopyMemory(Data, &Cart->RomData[dwAddress], 32);
DebugWriteA("Nonbanked ROM read - CAMERA\n");
}
else if ((dwAddress >= 0x4000) && (dwAddress < 0x8000)) //Switchable ROM BANK
{
if (Cart->iCurrentRomBankNo >= Cart->iNumRomBanks)
{
ZeroMemory(Data, 32);
DebugWriteA("Banked ROM read: (Banking Error)");
DebugWriteByteA(Cart->iCurrentRomBankNo);
DebugWriteA("\n");
}
else {
CopyMemory(Data, &Cart->RomData[dwAddress - 0x4000 + (Cart->iCurrentRomBankNo << 14)], 32);
DebugWriteA("Banked ROM read: Bank=");
DebugWriteByteA(Cart->iCurrentRomBankNo);
DebugWriteA("\n");
}
}
else if ((dwAddress >= 0xA000) && (dwAddress <= 0xC000)) //Upper bounds of memory map
{
if (Cart->iCurrentRamBankNo & 0x10)
{
//REGISTER MODE
ZeroMemory(Data, 32);
DebugWriteA("REGISTER read (Camera): All Zero\n", Cart->iCurrentRamBankNo);
}
else
{
//RAM MODE
if (Cart->bHasRam)
{
if (Cart->iCurrentRamBankNo >= Cart->iNumRamBanks)
{
ZeroMemory(Data, 32);
DebugWriteA("Failed RAM read: (Banking Error) %02X\n", Cart->iCurrentRamBankNo);
}
else
{
CopyMemory(Data, &Cart->RamData[dwAddress - 0xA000 + (Cart->iCurrentRamBankNo << 13)], 32);
DebugWriteA("RAM read: Bank %02X\n", Cart->iCurrentRamBankNo);
}
}
else
{
ZeroMemory(Data, 32);
DebugWriteA("Failed RAM read: (RAM Not Present)\n");
}
}
}
else
{
DebugWriteA("Bad read from GBCamera cart, address %04X\n", dwAddress);
}
return true;
}
//Done
bool WriteCartCamera(LPGBCART Cart, WORD dwAddress, BYTE *Data)
{
if ((dwAddress >= 0x0000) && (dwAddress <= 0x1FFF)) // We shouldn't be able to read/write to RAM unless this is toggled on
{
Cart->bRamEnableState = (Data[0] == 0x0A);
DebugWriteA("Set RAM enable: %d\n", Cart->bRamEnableState);
}
else if ((dwAddress >= 0x2000) && (dwAddress <= 0x2FFF)) // ROM bank select, low bits
{
Cart->iCurrentRomBankNo &= 0xFF00;
Cart->iCurrentRomBankNo |= Data[0];
// Cart->iCurrentRomBankNo = ((int) Data[0]) | (Cart->iCurrentRomBankNo & 0x100);
DebugWriteA("Set ROM Bank: %02X\n", Cart->iCurrentRomBankNo);
}
else if ((dwAddress >= 0x4000) && (dwAddress <= 0x4FFF)) // Camera Register & RAM bank select
{
if (Data[0] & 0x10)
{
//REGISTER MODE
Cart->iCurrentRamBankNo = Data[0];
DebugWriteA("Set Register Bank (Camera): %02X\n", Cart->iCurrentRamBankNo);
}
else
{
//RAM MODE
if (Cart->bHasRam)
{
Cart->iCurrentRamBankNo = Data[0] & 0x0F;
DebugWriteA("Set RAM Bank: %02X\n", Cart->iCurrentRamBankNo);
}
}
}
else if ((dwAddress >= 0xA000) && (dwAddress <= 0xBFFF)) // Write to RAM
{
if (Cart->iCurrentRamBankNo & 0x10)
{
//REGISTER MODE (DO NOTHING)
DebugWriteA("REGISTER write (Camera): Do nothing\n");
}
else
{
//RAM MODE
if (Cart->bHasRam)
{
if (Cart->iCurrentRamBankNo >= Cart->iNumRamBanks)
{
DebugWriteA("RAM write: Buffer error on ");
DebugWriteByteA(Cart->iCurrentRamBankNo);
DebugWriteA("\n");
}
else
{
DebugWriteA("RAM write: Bank %02X\n", Cart->iCurrentRamBankNo);
CopyMemory(&Cart->RamData[dwAddress - 0xA000 + (Cart->iCurrentRamBankNo << 13)], Data, 32);
}
}
}
}
else
{
DebugWriteA("Bad write to GBCamera cart, address %04X\n", dwAddress);
}
return true;
}
bool SaveCart(LPGBCART Cart, LPTSTR SaveFile, LPTSTR TimeFile)
{
DWORD NumQuarterBlocks = 0;

2
Source/nragev20/GBCart.h
View File

@ -61,7 +61,7 @@ iCartType values:
7 = TAMA 5
8 = HuC 3
9 = HuC 1
Note, that 6 and up are not implemented yet.
Note, that 7 and up are not implemented yet.
*/
#define GB_NORM 0x00