Core: Have CX86RecompilerOps::SPECIAL_AND unmap the register on const write
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@ -5519,9 +5519,12 @@ void CX86RecompilerOps::SPECIAL_AND()
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{
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{
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if (m_RegWorkingSet.Is64Bit(m_Opcode.rt) || m_RegWorkingSet.Is64Bit(m_Opcode.rs))
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if (m_RegWorkingSet.Is64Bit(m_Opcode.rt) || m_RegWorkingSet.Is64Bit(m_Opcode.rs))
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{
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{
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m_RegWorkingSet.SetMipsReg(m_Opcode.rd,
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uint64_t Value = (m_RegWorkingSet.Is64Bit(m_Opcode.rt) ? m_RegWorkingSet.GetMipsReg(m_Opcode.rt) : (int64_t)m_RegWorkingSet.GetMipsRegLo_S(m_Opcode.rt)) & (m_RegWorkingSet.Is64Bit(m_Opcode.rs) ? m_RegWorkingSet.GetMipsReg(m_Opcode.rs) : (int64_t)m_RegWorkingSet.GetMipsRegLo_S(m_Opcode.rs));
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(m_RegWorkingSet.Is64Bit(m_Opcode.rt) ? m_RegWorkingSet.GetMipsReg(m_Opcode.rt) : (int64_t)m_RegWorkingSet.GetMipsRegLo_S(m_Opcode.rt)) &
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if (m_RegWorkingSet.IsMapped(m_Opcode.rd))
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(m_RegWorkingSet.Is64Bit(m_Opcode.rs) ? m_RegWorkingSet.GetMipsReg(m_Opcode.rs) : (int64_t)m_RegWorkingSet.GetMipsRegLo_S(m_Opcode.rs)));
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{
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m_RegWorkingSet.UnMap_GPR(m_Opcode.rd, false);
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}
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m_RegWorkingSet.SetMipsReg(m_Opcode.rd, Value);
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if (m_RegWorkingSet.GetMipsRegLo_S(m_Opcode.rd) < 0 && m_RegWorkingSet.GetMipsRegHi_S(m_Opcode.rd) == -1)
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if (m_RegWorkingSet.GetMipsRegLo_S(m_Opcode.rd) < 0 && m_RegWorkingSet.GetMipsRegHi_S(m_Opcode.rd) == -1)
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{
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{
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@ -5538,7 +5541,12 @@ void CX86RecompilerOps::SPECIAL_AND()
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}
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}
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else
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else
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{
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{
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m_RegWorkingSet.SetMipsReg(m_Opcode.rd, m_RegWorkingSet.GetMipsRegLo(m_Opcode.rt) & m_RegWorkingSet.GetMipsReg(m_Opcode.rs));
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uint32_t Value = m_RegWorkingSet.GetMipsRegLo(m_Opcode.rt) & m_RegWorkingSet.GetMipsReg(m_Opcode.rs);
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if (m_RegWorkingSet.IsMapped(m_Opcode.rd))
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{
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m_RegWorkingSet.UnMap_GPR(m_Opcode.rd, false);
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}
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m_RegWorkingSet.SetMipsReg(m_Opcode.rd, Value);
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m_RegWorkingSet.SetMipsRegState(m_Opcode.rd, CRegInfo::STATE_CONST_32_SIGN);
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m_RegWorkingSet.SetMipsRegState(m_Opcode.rd, CRegInfo::STATE_CONST_32_SIGN);
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}
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}
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}
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}
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