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changed some of the functions to set/get register information to be clearer setters and getters

This commit is contained in:
zilmar 2012-10-04 21:01:10 +10:00
parent 18c8a8c548
commit a3c225ecf5
6 changed files with 686 additions and 673 deletions
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154
Source/Project64/N64 System/Mips/Memory Virtual Mem.cpp
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@ -2380,7 +2380,7 @@ void CMipsMemoryVM::Compile_LB (void)
if (IsConst(Opcode.base)) {
DWORD Address = (cMipsRegLo(Opcode.base) + (short)Opcode.offset) ^ 3;
Map_GPR_32bit(Opcode.rt,TRUE,0);
Compile_LB(cMipsRegMapLo(Opcode.rt),Address,TRUE);
Compile_LB(MipsRegMapLo(Opcode.rt),Address,TRUE);
return;
}
if (IsMapped(Opcode.rt)) { ProtectGPR(Opcode.rt); }
@ -2388,7 +2388,7 @@ void CMipsMemoryVM::Compile_LB (void)
ProtectGPR(Opcode.base);
if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,cMipsRegMapLo(Opcode.base),(short)Opcode.offset);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
}
@ -2404,12 +2404,12 @@ void CMipsMemoryVM::Compile_LB (void)
CompileReadTLBMiss(TempReg1,TempReg2);
XorConstToX86Reg(TempReg1,3);
Map_GPR_32bit(Opcode.rt,TRUE,-1);
MoveSxByteX86regPointerToX86reg(TempReg1, TempReg2,cMipsRegMapLo(Opcode.rt));
MoveSxByteX86regPointerToX86reg(TempReg1, TempReg2,MipsRegMapLo(Opcode.rt));
} else {
AndConstToX86Reg(TempReg1,0x1FFFFFFF);
XorConstToX86Reg(TempReg1,3);
Map_GPR_32bit(Opcode.rt,TRUE,-1);
MoveSxN64MemToX86regByte(cMipsRegMapLo(Opcode.rt), TempReg1);
MoveSxN64MemToX86regByte(MipsRegMapLo(Opcode.rt), TempReg1);
}
}
@ -2425,7 +2425,7 @@ void CMipsMemoryVM::Compile_LBU (void)
if (IsConst(Opcode.base)) {
DWORD Address = (cMipsRegLo(Opcode.base) + (short)Opcode.offset) ^ 3;
Map_GPR_32bit(Opcode.rt,FALSE,0);
Compile_LB(cMipsRegMapLo(Opcode.rt),Address,FALSE);
Compile_LB(MipsRegMapLo(Opcode.rt),Address,FALSE);
return;
}
if (IsMapped(Opcode.rt)) { ProtectGPR(Opcode.rt); }
@ -2433,7 +2433,7 @@ void CMipsMemoryVM::Compile_LBU (void)
ProtectGPR(Opcode.base);
if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,cMipsRegMapLo(Opcode.base),(short)Opcode.offset);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
}
@ -2449,12 +2449,12 @@ void CMipsMemoryVM::Compile_LBU (void)
CompileReadTLBMiss(TempReg1,TempReg2);
XorConstToX86Reg(TempReg1,3);
Map_GPR_32bit(Opcode.rt,FALSE,-1);
MoveZxByteX86regPointerToX86reg(TempReg1, TempReg2,cMipsRegMapLo(Opcode.rt));
MoveZxByteX86regPointerToX86reg(TempReg1, TempReg2,MipsRegMapLo(Opcode.rt));
} else {
AndConstToX86Reg(TempReg1,0x1FFFFFFF);
XorConstToX86Reg(TempReg1,3);
Map_GPR_32bit(Opcode.rt,FALSE,-1);
MoveZxN64MemToX86regByte(cMipsRegMapLo(Opcode.rt), TempReg1);
MoveZxN64MemToX86regByte(MipsRegMapLo(Opcode.rt), TempReg1);
}
}
@ -2470,7 +2470,7 @@ void CMipsMemoryVM::Compile_LH (void)
if (IsConst(Opcode.base)) {
DWORD Address = (cMipsRegLo(Opcode.base) + (short)Opcode.offset) ^ 2;
Map_GPR_32bit(Opcode.rt,TRUE,0);
Compile_LH(cMipsRegMapLo(Opcode.rt),Address,TRUE);
Compile_LH(MipsRegMapLo(Opcode.rt),Address,TRUE);
return;
}
if (IsMapped(Opcode.rt)) { ProtectGPR(Opcode.rt); }
@ -2478,7 +2478,7 @@ void CMipsMemoryVM::Compile_LH (void)
ProtectGPR(Opcode.base);
if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,cMipsRegMapLo(Opcode.base),(short)Opcode.offset);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
}
@ -2494,12 +2494,12 @@ void CMipsMemoryVM::Compile_LH (void)
CompileReadTLBMiss(TempReg1,TempReg2);
XorConstToX86Reg(TempReg1,2);
Map_GPR_32bit(Opcode.rt,TRUE,-1);
MoveSxHalfX86regPointerToX86reg(TempReg1, TempReg2,cMipsRegMapLo(Opcode.rt));
MoveSxHalfX86regPointerToX86reg(TempReg1, TempReg2,MipsRegMapLo(Opcode.rt));
} else {
AndConstToX86Reg(TempReg1,0x1FFFFFFF);
XorConstToX86Reg(TempReg1,2);
Map_GPR_32bit(Opcode.rt,TRUE,-1);
MoveSxN64MemToX86regHalf(cMipsRegMapLo(Opcode.rt), TempReg1);
MoveSxN64MemToX86regHalf(MipsRegMapLo(Opcode.rt), TempReg1);
}
}
@ -2515,7 +2515,7 @@ void CMipsMemoryVM::Compile_LHU (void)
if (IsConst(Opcode.base)) {
DWORD Address = (cMipsRegLo(Opcode.base) + (short)Opcode.offset) ^ 2;
Map_GPR_32bit(Opcode.rt,FALSE,0);
Compile_LH(cMipsRegMapLo(Opcode.rt),Address,FALSE);
Compile_LH(MipsRegMapLo(Opcode.rt),Address,FALSE);
return;
}
if (IsMapped(Opcode.rt)) { ProtectGPR(Opcode.rt); }
@ -2523,7 +2523,7 @@ void CMipsMemoryVM::Compile_LHU (void)
ProtectGPR(Opcode.base);
if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,cMipsRegMapLo(Opcode.base),(short)Opcode.offset);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
}
@ -2539,12 +2539,12 @@ void CMipsMemoryVM::Compile_LHU (void)
CompileReadTLBMiss(TempReg1,TempReg2);
XorConstToX86Reg(TempReg1,2);
Map_GPR_32bit(Opcode.rt,FALSE,-1);
MoveZxHalfX86regPointerToX86reg(TempReg1, TempReg2,cMipsRegMapLo(Opcode.rt));
MoveZxHalfX86regPointerToX86reg(TempReg1, TempReg2,MipsRegMapLo(Opcode.rt));
} else {
AndConstToX86Reg(TempReg1,0x1FFFFFFF);
XorConstToX86Reg(TempReg1,2);
Map_GPR_32bit(Opcode.rt,TRUE,-1);
MoveZxN64MemToX86regHalf(cMipsRegMapLo(Opcode.rt), TempReg1);
MoveZxN64MemToX86regHalf(MipsRegMapLo(Opcode.rt), TempReg1);
}
}
@ -2562,24 +2562,24 @@ void CMipsMemoryVM::Compile_LW (void)
Map_GPR_32bit(Opcode.rt,TRUE,-1);
TempReg1 = Map_MemoryStack(x86_Any,true);
sprintf(String,"%Xh",(short)Opcode.offset);
MoveVariableDispToX86Reg((void *)((DWORD)(short)Opcode.offset),String,cMipsRegMapLo(Opcode.rt),TempReg1,1);
MoveVariableDispToX86Reg((void *)((DWORD)(short)Opcode.offset),String,MipsRegMapLo(Opcode.rt),TempReg1,1);
} else {
if (IsConst(Opcode.base)) {
DWORD Address = cMipsRegLo(Opcode.base) + (short)Opcode.offset;
Map_GPR_32bit(Opcode.rt,TRUE,-1);
Compile_LW(cMipsRegMapLo(Opcode.rt),Address);
Compile_LW(MipsRegMapLo(Opcode.rt),Address);
} else {
if (bUseTlb()) {
if (IsMapped(Opcode.rt)) { ProtectGPR(Opcode.rt); }
if (IsMapped(Opcode.base) && Opcode.offset == 0) {
ProtectGPR(Opcode.base);
TempReg1 = cMipsRegMapLo(Opcode.base);
TempReg1 = MipsRegMapLo(Opcode.base);
} else {
if (IsMapped(Opcode.base)) {
ProtectGPR(Opcode.base);
if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,cMipsRegMapLo(Opcode.base),(short)Opcode.offset);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
}
@ -2594,22 +2594,22 @@ void CMipsMemoryVM::Compile_LW (void)
MoveVariableDispToX86Reg(m_TLB_ReadMap,"m_TLB_ReadMap",TempReg2,TempReg2,4);
CompileReadTLBMiss(TempReg1,TempReg2);
Map_GPR_32bit(Opcode.rt,TRUE,-1);
MoveX86regPointerToX86reg(TempReg1, TempReg2,cMipsRegMapLo(Opcode.rt));
MoveX86regPointerToX86reg(TempReg1, TempReg2,MipsRegMapLo(Opcode.rt));
} else {
if (IsMapped(Opcode.base)) {
ProtectGPR(Opcode.base);
if (Opcode.offset != 0) {
Map_GPR_32bit(Opcode.rt,TRUE,-1);
LeaSourceAndOffset(cMipsRegMapLo(Opcode.rt),cMipsRegMapLo(Opcode.base),(short)Opcode.offset);
LeaSourceAndOffset(MipsRegMapLo(Opcode.rt),MipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else {
Map_GPR_32bit(Opcode.rt,TRUE,Opcode.base);
}
} else {
Map_GPR_32bit(Opcode.rt,TRUE,Opcode.base);
AddConstToX86Reg(cMipsRegMapLo(Opcode.rt),(short)Opcode.immediate);
AddConstToX86Reg(MipsRegMapLo(Opcode.rt),(short)Opcode.immediate);
}
AndConstToX86Reg(cMipsRegMapLo(Opcode.rt),0x1FFFFFFF);
MoveN64MemToX86reg(cMipsRegMapLo(Opcode.rt),cMipsRegMapLo(Opcode.rt));
AndConstToX86Reg(MipsRegMapLo(Opcode.rt),0x1FFFFFFF);
MoveN64MemToX86reg(MipsRegMapLo(Opcode.rt),MipsRegMapLo(Opcode.rt));
}
}
}
@ -2654,7 +2654,7 @@ void CMipsMemoryVM::Compile_LWC1 (void)
if (IsMapped(Opcode.base) && Opcode.offset == 0) {
if (bUseTlb()) {
ProtectGPR(Opcode.base);
TempReg1 = cMipsRegMapLo(Opcode.base);
TempReg1 = MipsRegMapLo(Opcode.base);
} else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
}
@ -2663,7 +2663,7 @@ void CMipsMemoryVM::Compile_LWC1 (void)
ProtectGPR(Opcode.base);
if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,cMipsRegMapLo(Opcode.base),(short)Opcode.offset);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
}
@ -2715,9 +2715,9 @@ void CMipsMemoryVM::Compile_LWL (void)
Map_GPR_32bit(Opcode.rt,TRUE,Opcode.rt);
x86Reg Value = Map_TempReg(x86_Any,-1,FALSE);
Compile_LW(Value,(Address & ~3));
AndConstToX86Reg(cMipsRegMapLo(Opcode.rt),LWL_MASK[Offset]);
AndConstToX86Reg(MipsRegMapLo(Opcode.rt),LWL_MASK[Offset]);
ShiftLeftSignImmed(Value,(BYTE)LWL_SHIFT[Offset]);
AddX86RegToX86Reg(cMipsRegMapLo(Opcode.rt),Value);
AddX86RegToX86Reg(MipsRegMapLo(Opcode.rt),Value);
return;
}
@ -2727,7 +2727,7 @@ void CMipsMemoryVM::Compile_LWL (void)
ProtectGPR(Opcode.base);
if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,cMipsRegMapLo(Opcode.base),(short)Opcode.offset);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
}
@ -2750,7 +2750,7 @@ void CMipsMemoryVM::Compile_LWL (void)
AndConstToX86Reg(TempReg1,~3);
Map_GPR_32bit(Opcode.rt,TRUE,Opcode.rt);
AndVariableDispToX86Reg((void *)LWL_MASK,"LWL_MASK",cMipsRegMapLo(Opcode.rt),OffsetReg,Multip_x4);
AndVariableDispToX86Reg((void *)LWL_MASK,"LWL_MASK",MipsRegMapLo(Opcode.rt),OffsetReg,Multip_x4);
MoveVariableDispToX86Reg((void *)LWL_SHIFT,"LWL_SHIFT",shift,OffsetReg,4);
if (bUseTlb()) {
MoveX86regPointerToX86reg(TempReg1, TempReg2,TempReg1);
@ -2759,7 +2759,7 @@ void CMipsMemoryVM::Compile_LWL (void)
MoveN64MemToX86reg(TempReg1,TempReg1);
}
ShiftLeftSign(TempReg1);
AddX86RegToX86Reg(cMipsRegMapLo(Opcode.rt),TempReg1);
AddX86RegToX86Reg(MipsRegMapLo(Opcode.rt),TempReg1);
}
void CMipsMemoryVM::Compile_LWR (void)
@ -2778,9 +2778,9 @@ void CMipsMemoryVM::Compile_LWR (void)
Map_GPR_32bit(Opcode.rt,TRUE,Opcode.rt);
x86Reg Value = Map_TempReg(x86_Any,-1,FALSE);
Compile_LW(Value,(Address & ~3));
AndConstToX86Reg(cMipsRegMapLo(Opcode.rt),LWR_MASK[Offset]);
AndConstToX86Reg(MipsRegMapLo(Opcode.rt),LWR_MASK[Offset]);
ShiftRightUnsignImmed(Value,(BYTE)LWR_SHIFT[Offset]);
AddX86RegToX86Reg(cMipsRegMapLo(Opcode.rt),Value);
AddX86RegToX86Reg(MipsRegMapLo(Opcode.rt),Value);
return;
}
@ -2790,7 +2790,7 @@ void CMipsMemoryVM::Compile_LWR (void)
ProtectGPR(Opcode.base);
if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,cMipsRegMapLo(Opcode.base),(short)Opcode.offset);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
}
@ -2814,7 +2814,7 @@ void CMipsMemoryVM::Compile_LWR (void)
AndConstToX86Reg(TempReg1,~3);
Map_GPR_32bit(Opcode.rt,TRUE,Opcode.rt);
AndVariableDispToX86Reg((void *)LWR_MASK,"LWR_MASK",cMipsRegMapLo(Opcode.rt),OffsetReg,Multip_x4);
AndVariableDispToX86Reg((void *)LWR_MASK,"LWR_MASK",MipsRegMapLo(Opcode.rt),OffsetReg,Multip_x4);
MoveVariableDispToX86Reg((void *)LWR_SHIFT,"LWR_SHIFT",shift,OffsetReg,4);
if (bUseTlb()) {
MoveX86regPointerToX86reg(TempReg1, TempReg2,TempReg1);
@ -2823,7 +2823,7 @@ void CMipsMemoryVM::Compile_LWR (void)
MoveN64MemToX86reg(TempReg1,TempReg1);
}
ShiftRightUnsign(TempReg1);
AddX86RegToX86Reg(cMipsRegMapLo(Opcode.rt),TempReg1);
AddX86RegToX86Reg(MipsRegMapLo(Opcode.rt),TempReg1);
}
void CMipsMemoryVM::Compile_LWU (void)
@ -2838,7 +2838,7 @@ void CMipsMemoryVM::Compile_LWU (void)
if (IsConst(Opcode.base)) {
DWORD Address = (cMipsRegLo(Opcode.base) + (short)Opcode.offset);
Map_GPR_32bit(Opcode.rt,FALSE,0);
Compile_LW(cMipsRegMapLo(Opcode.rt),Address);
Compile_LW(MipsRegMapLo(Opcode.rt),Address);
return;
}
if (IsMapped(Opcode.rt)) { ProtectGPR(Opcode.rt); }
@ -2846,7 +2846,7 @@ void CMipsMemoryVM::Compile_LWU (void)
ProtectGPR(Opcode.base);
if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,cMipsRegMapLo(Opcode.base),(short)Opcode.offset);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
}
@ -2861,11 +2861,11 @@ void CMipsMemoryVM::Compile_LWU (void)
MoveVariableDispToX86Reg(m_TLB_ReadMap,"m_TLB_ReadMap",TempReg2,TempReg2,4);
CompileReadTLBMiss(TempReg1,TempReg2);
Map_GPR_32bit(Opcode.rt,FALSE,-1);
MoveZxHalfX86regPointerToX86reg(TempReg1, TempReg2,cMipsRegMapLo(Opcode.rt));
MoveZxHalfX86regPointerToX86reg(TempReg1, TempReg2,MipsRegMapLo(Opcode.rt));
} else {
AndConstToX86Reg(TempReg1,0x1FFFFFFF);
Map_GPR_32bit(Opcode.rt,TRUE,-1);
MoveZxN64MemToX86regHalf(cMipsRegMapLo(Opcode.rt), TempReg1);
MoveZxN64MemToX86regHalf(MipsRegMapLo(Opcode.rt), TempReg1);
}
}
@ -2881,8 +2881,8 @@ void CMipsMemoryVM::Compile_LD (void)
if (IsConst(Opcode.base)) {
DWORD Address = cMipsRegLo(Opcode.base) + (short)Opcode.offset;
Map_GPR_64bit(Opcode.rt,-1);
Compile_LW(cMipsRegMapHi(Opcode.rt),Address);
Compile_LW(cMipsRegMapLo(Opcode.rt),Address + 4);
Compile_LW(MipsRegMapHi(Opcode.rt),Address);
Compile_LW(MipsRegMapLo(Opcode.rt),Address + 4);
if (bFastSP() && Opcode.rt == 29)
{
ResetMemoryStack();
@ -2893,7 +2893,7 @@ void CMipsMemoryVM::Compile_LD (void)
if (IsMapped(Opcode.base) && Opcode.offset == 0) {
if (bUseTlb()) {
ProtectGPR(Opcode.base);
TempReg1 = cMipsRegMapLo(Opcode.base);
TempReg1 = MipsRegMapLo(Opcode.base);
} else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
}
@ -2902,7 +2902,7 @@ void CMipsMemoryVM::Compile_LD (void)
ProtectGPR(Opcode.base);
if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,cMipsRegMapLo(Opcode.base),(short)Opcode.offset);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
}
@ -2920,13 +2920,13 @@ void CMipsMemoryVM::Compile_LD (void)
//0041C522 85 C0 test eax,eax
//0041C524 75 01 jne 0041C527
Map_GPR_64bit(Opcode.rt,-1);
MoveX86regPointerToX86reg(TempReg1, TempReg2,cMipsRegMapHi(Opcode.rt));
MoveX86regPointerToX86regDisp8(TempReg1, TempReg2,cMipsRegMapLo(Opcode.rt),4);
MoveX86regPointerToX86reg(TempReg1, TempReg2,MipsRegMapHi(Opcode.rt));
MoveX86regPointerToX86regDisp8(TempReg1, TempReg2,MipsRegMapLo(Opcode.rt),4);
} else {
AndConstToX86Reg(TempReg1,0x1FFFFFFF);
Map_GPR_64bit(Opcode.rt,-1);
MoveN64MemToX86reg(cMipsRegMapHi(Opcode.rt),TempReg1);
MoveN64MemDispToX86reg(cMipsRegMapLo(Opcode.rt),TempReg1,4);
MoveN64MemToX86reg(MipsRegMapHi(Opcode.rt),TempReg1);
MoveN64MemDispToX86reg(MipsRegMapLo(Opcode.rt),TempReg1,4);
}
if (bFastSP() && Opcode.rt == 29)
{
@ -2966,7 +2966,7 @@ void CMipsMemoryVM::Compile_LDC1 (void)
if (IsMapped(Opcode.base) && Opcode.offset == 0) {
if (bUseTlb()) {
ProtectGPR(Opcode.base);
TempReg1 = cMipsRegMapLo(Opcode.base);
TempReg1 = MipsRegMapLo(Opcode.base);
} else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
}
@ -2975,7 +2975,7 @@ void CMipsMemoryVM::Compile_LDC1 (void)
ProtectGPR(Opcode.base);
if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,cMipsRegMapLo(Opcode.base),(short)Opcode.offset);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
}
@ -3065,8 +3065,8 @@ void CMipsMemoryVM::Compile_SB (void)
if (IsConst(Opcode.rt)) {
Compile_SB_Const((BYTE)cMipsRegLo(Opcode.rt), Address);
} else if (IsMapped(Opcode.rt) && Is8BitReg(cMipsRegMapLo(Opcode.rt))) {
Compile_SB_Register(cMipsRegMapLo(Opcode.rt), Address);
} else if (IsMapped(Opcode.rt) && Is8BitReg(MipsRegMapLo(Opcode.rt))) {
Compile_SB_Register(MipsRegMapLo(Opcode.rt), Address);
} else {
Compile_SB_Register(Map_TempReg(x86_Any8Bit,Opcode.rt,FALSE), Address);
}
@ -3077,7 +3077,7 @@ void CMipsMemoryVM::Compile_SB (void)
ProtectGPR(Opcode.base);
if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,cMipsRegMapLo(Opcode.base),(short)Opcode.offset);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
}
@ -3099,8 +3099,8 @@ void CMipsMemoryVM::Compile_SB (void)
XorConstToX86Reg(TempReg1,3);
if (IsConst(Opcode.rt)) {
MoveConstByteToX86regPointer((BYTE)cMipsRegLo(Opcode.rt),TempReg1, TempReg2);
} else if (IsMapped(Opcode.rt) && Is8BitReg(cMipsRegMapLo(Opcode.rt))) {
MoveX86regByteToX86regPointer(cMipsRegMapLo(Opcode.rt),TempReg1, TempReg2);
} else if (IsMapped(Opcode.rt) && Is8BitReg(MipsRegMapLo(Opcode.rt))) {
MoveX86regByteToX86regPointer(MipsRegMapLo(Opcode.rt),TempReg1, TempReg2);
} else {
UnProtectGPR(Opcode.rt);
MoveX86regByteToX86regPointer(Map_TempReg(x86_Any8Bit,Opcode.rt,FALSE),TempReg1, TempReg2);
@ -3110,8 +3110,8 @@ void CMipsMemoryVM::Compile_SB (void)
XorConstToX86Reg(TempReg1,3);
if (IsConst(Opcode.rt)) {
MoveConstByteToN64Mem((BYTE)cMipsRegLo(Opcode.rt),TempReg1);
} else if (IsMapped(Opcode.rt) && Is8BitReg(cMipsRegMapLo(Opcode.rt))) {
MoveX86regByteToN64Mem(cMipsRegMapLo(Opcode.rt),TempReg1);
} else if (IsMapped(Opcode.rt) && Is8BitReg(MipsRegMapLo(Opcode.rt))) {
MoveX86regByteToN64Mem(MipsRegMapLo(Opcode.rt),TempReg1);
} else {
UnProtectGPR(Opcode.rt);
MoveX86regByteToN64Mem(Map_TempReg(x86_Any8Bit,Opcode.rt,FALSE),TempReg1);
@ -3132,7 +3132,7 @@ void CMipsMemoryVM::Compile_SH (void)
if (IsConst(Opcode.rt)) {
Compile_SH_Const((WORD)cMipsRegLo(Opcode.rt), Address);
} else if (IsMapped(Opcode.rt)) {
Compile_SH_Register(cMipsRegMapLo(Opcode.rt), Address);
Compile_SH_Register(MipsRegMapLo(Opcode.rt), Address);
} else {
Compile_SH_Register(Map_TempReg(x86_Any,Opcode.rt,FALSE), Address);
}
@ -3143,7 +3143,7 @@ void CMipsMemoryVM::Compile_SH (void)
ProtectGPR(Opcode.base);
if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,cMipsRegMapLo(Opcode.base),(short)Opcode.offset);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
}
@ -3165,7 +3165,7 @@ void CMipsMemoryVM::Compile_SH (void)
if (IsConst(Opcode.rt)) {
MoveConstHalfToX86regPointer((WORD)cMipsRegLo(Opcode.rt),TempReg1, TempReg2);
} else if (IsMapped(Opcode.rt)) {
MoveX86regHalfToX86regPointer(cMipsRegMapLo(Opcode.rt),TempReg1, TempReg2);
MoveX86regHalfToX86regPointer(MipsRegMapLo(Opcode.rt),TempReg1, TempReg2);
} else {
MoveX86regHalfToX86regPointer(Map_TempReg(x86_Any,Opcode.rt,FALSE),TempReg1, TempReg2);
}
@ -3175,7 +3175,7 @@ void CMipsMemoryVM::Compile_SH (void)
if (IsConst(Opcode.rt)) {
MoveConstHalfToN64Mem((WORD)cMipsRegLo(Opcode.rt),TempReg1);
} else if (IsMapped(Opcode.rt)) {
MoveX86regHalfToN64Mem(cMipsRegMapLo(Opcode.rt),TempReg1);
MoveX86regHalfToN64Mem(MipsRegMapLo(Opcode.rt),TempReg1);
} else {
MoveX86regHalfToN64Mem(Map_TempReg(x86_Any,Opcode.rt,FALSE),TempReg1);
}
@ -3195,7 +3195,7 @@ void CMipsMemoryVM::Compile_SW (void)
if (IsConst(Opcode.rt)) {
MoveConstToMemoryDisp (cMipsRegLo(Opcode.rt),TempReg1, (DWORD)((short)Opcode.offset));
} else if (IsMapped(Opcode.rt)) {
MoveX86regToMemory(cMipsRegMapLo(Opcode.rt),TempReg1,(DWORD)((short)Opcode.offset));
MoveX86regToMemory(MipsRegMapLo(Opcode.rt),TempReg1,(DWORD)((short)Opcode.offset));
} else {
TempReg2 = Map_TempReg(x86_Any,Opcode.rt,FALSE);
MoveX86regToMemory(TempReg2,TempReg1,(DWORD)((short)Opcode.offset));
@ -3207,7 +3207,7 @@ void CMipsMemoryVM::Compile_SW (void)
if (IsConst(Opcode.rt)) {
Compile_SW_Const(cMipsRegLo(Opcode.rt), Address);
} else if (IsMapped(Opcode.rt)) {
Compile_SW_Register(cMipsRegMapLo(Opcode.rt), Address);
Compile_SW_Register(MipsRegMapLo(Opcode.rt), Address);
} else {
Compile_SW_Register(Map_TempReg(x86_Any,Opcode.rt,FALSE), Address);
}
@ -3218,7 +3218,7 @@ void CMipsMemoryVM::Compile_SW (void)
ProtectGPR(Opcode.base);
if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,cMipsRegMapLo(Opcode.base),(short)Opcode.offset);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
}
@ -3240,7 +3240,7 @@ void CMipsMemoryVM::Compile_SW (void)
if (IsConst(Opcode.rt)) {
MoveConstToX86regPointer(cMipsRegLo(Opcode.rt),TempReg1, TempReg2);
} else if (IsMapped(Opcode.rt)) {
MoveX86regToX86regPointer(cMipsRegMapLo(Opcode.rt),TempReg1, TempReg2);
MoveX86regToX86regPointer(MipsRegMapLo(Opcode.rt),TempReg1, TempReg2);
} else {
MoveX86regToX86regPointer(Map_TempReg(x86_Any,Opcode.rt,FALSE),TempReg1, TempReg2);
}
@ -3249,7 +3249,7 @@ void CMipsMemoryVM::Compile_SW (void)
if (IsConst(Opcode.rt)) {
MoveConstToN64Mem(cMipsRegLo(Opcode.rt),TempReg1);
} else if (IsMapped(Opcode.rt)) {
MoveX86regToN64Mem(cMipsRegMapLo(Opcode.rt),TempReg1);
MoveX86regToN64Mem(MipsRegMapLo(Opcode.rt),TempReg1);
} else {
MoveX86regToN64Mem(Map_TempReg(x86_Any,Opcode.rt,FALSE),TempReg1);
}
@ -3283,7 +3283,7 @@ void CMipsMemoryVM::Compile_SWC1 (void)
ProtectGPR(Opcode.base);
if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,cMipsRegMapLo(Opcode.base),(short)Opcode.offset);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
}
@ -3351,7 +3351,7 @@ void CMipsMemoryVM::Compile_SWL (void)
ProtectGPR(Opcode.base);
if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,cMipsRegMapLo(Opcode.base),(short)Opcode.offset);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
}
@ -3390,7 +3390,7 @@ void CMipsMemoryVM::Compile_SWL (void)
if (IsConst(Opcode.rt)) {
MoveConstToX86reg(cMipsRegLo(Opcode.rt),OffsetReg);
} else if (IsMapped(Opcode.rt)) {
MoveX86RegToX86Reg(cMipsRegMapLo(Opcode.rt),OffsetReg);
MoveX86RegToX86Reg(MipsRegMapLo(Opcode.rt),OffsetReg);
} else {
MoveVariableToX86reg(&_GPR[Opcode.rt].UW[0],CRegName::GPR_Lo[Opcode.rt],OffsetReg);
}
@ -3434,7 +3434,7 @@ void CMipsMemoryVM::Compile_SWR (void)
ProtectGPR(Opcode.base);
if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,cMipsRegMapLo(Opcode.base),(short)Opcode.offset);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
}
@ -3473,7 +3473,7 @@ void CMipsMemoryVM::Compile_SWR (void)
if (IsConst(Opcode.rt)) {
MoveConstToX86reg(cMipsRegLo(Opcode.rt),OffsetReg);
} else if (IsMapped(Opcode.rt)) {
MoveX86RegToX86Reg(cMipsRegMapLo(Opcode.rt),OffsetReg);
MoveX86RegToX86Reg(MipsRegMapLo(Opcode.rt),OffsetReg);
} else {
MoveVariableToX86reg(&_GPR[Opcode.rt].UW[0],CRegName::GPR_Lo[Opcode.rt],OffsetReg);
}
@ -3559,7 +3559,7 @@ void CMipsMemoryVM::Compile_SD (void)
Compile_SW_Const(cMipsRegLo(Opcode.rt), Address + 4);
} else if (IsMapped(Opcode.rt)) {
Compile_SW_Register(Is64Bit(Opcode.rt) ? MipsRegMapHi(Opcode.rt) : Map_TempReg(x86_Any,Opcode.rt,TRUE), Address);
Compile_SW_Register(cMipsRegMapLo(Opcode.rt), Address + 4);
Compile_SW_Register(MipsRegMapLo(Opcode.rt), Address + 4);
} else {
TempReg1 = Map_TempReg(x86_Any,Opcode.rt,TRUE);
Compile_SW_Register(TempReg1, Address);
@ -3571,7 +3571,7 @@ void CMipsMemoryVM::Compile_SD (void)
ProtectGPR(Opcode.base);
if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,cMipsRegMapLo(Opcode.base),(short)Opcode.offset);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
}
@ -3607,7 +3607,7 @@ void CMipsMemoryVM::Compile_SD (void)
MoveX86regToX86regPointer(Map_TempReg(x86_Any,Opcode.rt,TRUE),TempReg1, TempReg2);
}
AddConstToX86Reg(TempReg1,4);
MoveX86regToX86regPointer(cMipsRegMapLo(Opcode.rt),TempReg1, TempReg2);
MoveX86regToX86regPointer(MipsRegMapLo(Opcode.rt),TempReg1, TempReg2);
} else {
x86Reg Reg = Map_TempReg(x86_Any,Opcode.rt,TRUE);
MoveX86regToX86regPointer(Reg,TempReg1, TempReg2);
@ -3633,7 +3633,7 @@ void CMipsMemoryVM::Compile_SD (void)
} else {
MoveConstToN64Mem(0,TempReg1);
}
MoveX86regToN64MemDisp(cMipsRegMapLo(Opcode.rt),TempReg1, 4);
MoveX86regToN64MemDisp(MipsRegMapLo(Opcode.rt),TempReg1, 4);
} else {
x86Reg Reg;
MoveX86regToN64Mem(Reg = Map_TempReg(x86_Any,Opcode.rt,TRUE), TempReg1);
@ -3673,7 +3673,7 @@ void CMipsMemoryVM::Compile_SDC1 (void)
ProtectGPR(Opcode.base);
if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,cMipsRegMapLo(Opcode.base),(short)Opcode.offset);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
}

363
Source/Project64/N64 System/Recompiler/Code Section.cpp
View File

@ -642,27 +642,27 @@ void CCodeSection::SyncRegState ( const CRegInfo & SyncTo )
{
x86Reg Reg, x86RegHi;
if (cMipsRegState(i) == SyncTo.cMipsRegState(i) ||
(b32BitCore() && cMipsRegState(i) == CRegInfo::STATE_MAPPED_32_ZERO && SyncTo.cMipsRegState(i) == CRegInfo::STATE_MAPPED_32_SIGN) ||
(b32BitCore() && cMipsRegState(i) == CRegInfo::STATE_MAPPED_32_SIGN && SyncTo.cMipsRegState(i) == CRegInfo::STATE_MAPPED_32_ZERO))
if (MipsRegState(i) == SyncTo.MipsRegState(i) ||
(b32BitCore() && MipsRegState(i) == CRegInfo::STATE_MAPPED_32_ZERO && SyncTo.MipsRegState(i) == CRegInfo::STATE_MAPPED_32_SIGN) ||
(b32BitCore() && MipsRegState(i) == CRegInfo::STATE_MAPPED_32_SIGN && SyncTo.MipsRegState(i) == CRegInfo::STATE_MAPPED_32_ZERO))
{
switch (cMipsRegState(i)) {
switch (MipsRegState(i)) {
case CRegInfo::STATE_UNKNOWN: continue;
case CRegInfo::STATE_MAPPED_64:
if (cMipsRegMapHi(i) == SyncTo.cMipsRegMapHi(i) &&
cMipsRegMapLo(i) == SyncTo.cMipsRegMapLo(i))
if (MipsRegMapHi(i) == SyncTo.MipsRegMapHi(i) &&
MipsRegMapLo(i) == SyncTo.MipsRegMapLo(i))
{
continue;
}
break;
case CRegInfo::STATE_MAPPED_32_ZERO:
case CRegInfo::STATE_MAPPED_32_SIGN:
if (MipsRegMapLo(i) == SyncTo.cMipsRegMapLo(i)) {
if (MipsRegMapLo(i) == SyncTo.MipsRegMapLo(i)) {
continue;
}
break;
case CRegInfo::STATE_CONST_64:
if (MipsReg(i) != SyncTo.cMipsReg(i)) {
if (MipsReg(i) != SyncTo.MipsReg(i)) {
#if (!defined(EXTERNAL_RELEASE))
_Notify->DisplayError("Umm.. how ???");
#endif
@ -683,11 +683,11 @@ void CCodeSection::SyncRegState ( const CRegInfo & SyncTo )
}
changed = true;
switch (SyncTo.cMipsRegState(i)) {
switch (SyncTo.MipsRegState(i)) {
case CRegInfo::STATE_UNKNOWN: UnMap_GPR(i,true); break;
case CRegInfo::STATE_MAPPED_64:
Reg = SyncTo.cMipsRegMapLo(i);
x86RegHi = SyncTo.cMipsRegMapHi(i);
Reg = SyncTo.MipsRegMapLo(i);
x86RegHi = SyncTo.MipsRegMapHi(i);
UnMap_X86reg(Reg);
UnMap_X86reg(x86RegHi);
switch (MipsRegState(i)) {
@ -727,16 +727,16 @@ void CCodeSection::SyncRegState ( const CRegInfo & SyncTo )
#endif
continue;
}
MipsRegMapLo(i) = Reg;
MipsRegMapHi(i) = x86RegHi;
MipsRegState(i) = CRegInfo::STATE_MAPPED_64;
m_RegWorkingSet.SetMipsRegMapLo(i,Reg);
m_RegWorkingSet.SetMipsRegMapHi(i,x86RegHi);
m_RegWorkingSet.SetMipsRegState(i,CRegInfo::STATE_MAPPED_64);
m_RegWorkingSet.SetX86Mapped(Reg,CRegInfo::GPR_Mapped);
m_RegWorkingSet.SetX86Mapped(x86RegHi,CRegInfo::GPR_Mapped);
m_RegWorkingSet.SetX86MapOrder(Reg,1);
m_RegWorkingSet.SetX86MapOrder(x86RegHi,1);
break;
case CRegInfo::STATE_MAPPED_32_SIGN:
Reg = SyncTo.cMipsRegMapLo(i);
Reg = SyncTo.MipsRegMapLo(i);
UnMap_X86reg(Reg);
switch (MipsRegState(i)) {
case CRegInfo::STATE_UNKNOWN: MoveVariableToX86reg(&_GPR[i].UW[0],CRegName::GPR_Lo[i],Reg); break;
@ -764,13 +764,13 @@ void CCodeSection::SyncRegState ( const CRegInfo & SyncTo )
_Notify->DisplayError("Do something with states in SyncRegState\nSTATE_MAPPED_32_SIGN\n%d",MipsRegState(i));
#endif
}
MipsRegMapLo(i) = Reg;
MipsRegState(i) = CRegInfo::STATE_MAPPED_32_SIGN;
m_RegWorkingSet.SetMipsRegMapLo(i,Reg);
m_RegWorkingSet.SetMipsRegState(i, CRegInfo::STATE_MAPPED_32_SIGN);
m_RegWorkingSet.SetX86Mapped(Reg,CRegInfo::GPR_Mapped);
m_RegWorkingSet.SetX86MapOrder(Reg,1);
break;
case CRegInfo::STATE_MAPPED_32_ZERO:
Reg = SyncTo.cMipsRegMapLo(i);
Reg = SyncTo.MipsRegMapLo(i);
UnMap_X86reg(Reg);
switch (MipsRegState(i)) {
case CRegInfo::STATE_MAPPED_64:
@ -807,15 +807,15 @@ void CCodeSection::SyncRegState ( const CRegInfo & SyncTo )
_Notify->DisplayError("Do something with states in SyncRegState\nSTATE_MAPPED_32_ZERO\n%d",MipsRegState(i));
#endif
}
MipsRegMapLo(i) = Reg;
MipsRegState(i) = SyncTo.cMipsRegState(i);
m_RegWorkingSet.SetMipsRegMapLo(i,Reg);
m_RegWorkingSet.SetMipsRegState(i, SyncTo.MipsRegState(i));
m_RegWorkingSet.SetX86Mapped(Reg,CRegInfo::GPR_Mapped);
m_RegWorkingSet.SetX86MapOrder(Reg,1);
break;
default:
#if (!defined(EXTERNAL_RELEASE))
CPU_Message("%d - %d reg: %s (%d)",SyncTo.cMipsRegState(i),MipsRegState(i),CRegName::GPR[i],i);
_Notify->DisplayError("%d\n%d\nreg: %s (%d)",SyncTo.cMipsRegState(i),MipsRegState(i),CRegName::GPR[i],i);
CPU_Message("%d - %d reg: %s (%d)",SyncTo.MipsRegState(i),MipsRegState(i),CRegName::GPR[i],i);
_Notify->DisplayError("%d\n%d\nreg: %s (%d)",SyncTo.MipsRegState(i),MipsRegState(i),CRegName::GPR[i],i);
_Notify->DisplayError("Do something with states in SyncRegState");
#endif
changed = false;
@ -1368,19 +1368,22 @@ void CCodeSection::AddParent(CCodeSection * Parent )
void CCodeSection::TestRegConstantStates( CRegInfo & Base, CRegInfo & Reg )
{
for (int i = 0; i < 32; i++) {
if (Reg.MipsRegState(i) != Base.MipsRegState(i)) {
Reg.MipsRegState(i) = CRegInfo::STATE_UNKNOWN;
if (Reg.MipsRegState(i) != Base.MipsRegState(i))
{
Reg.SetMipsRegState(i,CRegInfo::STATE_UNKNOWN);
}
if (Reg.IsConst(i))
{
if (Reg.Is32Bit(i))
{
if (Reg.MipsRegLo(i) != Base.MipsRegLo(i)) {
Reg.MipsRegState(i) = CRegInfo::STATE_UNKNOWN;
if (Reg.MipsRegLo(i) != Base.MipsRegLo(i))
{
Reg.SetMipsRegState(i, CRegInfo::STATE_UNKNOWN);
}
} else {
if (Reg.MipsReg(i) != Base.MipsReg(i)) {
Reg.MipsRegState(i) = CRegInfo::STATE_UNKNOWN;
if (Reg.MipsReg(i) != Base.MipsReg(i))
{
Reg.SetMipsRegState(i, CRegInfo::STATE_UNKNOWN);
}
}
@ -1446,16 +1449,16 @@ bool CCodeSection::FixConstants (DWORD Test)
for (int i = 0; i < 32; i++)
{
if (m_RegEnter.MipsRegState(i) != Parent->m_Cont.RegSet.MipsRegState(i)) {
m_RegEnter.MipsRegState(i) = CRegInfo::STATE_UNKNOWN;
m_RegEnter.SetMipsRegState(i,CRegInfo::STATE_UNKNOWN);
//*Changed = true;
}
m_RegEnter.MipsRegState(i) = CRegInfo::STATE_UNKNOWN;
m_RegEnter.SetMipsRegState(i, CRegInfo::STATE_UNKNOWN);
}
}
if (Parent->m_JumpSection == this) {
for (int i = 0; i < 32; i++) {
if (m_RegEnter.MipsRegState(i) != Parent->m_Jump.RegSet.MipsRegState(i)) {
m_RegEnter.MipsRegState(i) = CRegInfo::STATE_UNKNOWN;
m_RegEnter.SetMipsRegState(i,CRegInfo::STATE_UNKNOWN);
//*Changed = true;
}
}
@ -1538,12 +1541,12 @@ void CCodeSection::InheritConstants( void )
for (int i = 0; i < 32; i++) {
if (IsConst(i)) {
if (cMipsRegState(i) != RegSet->MipsRegState(i)) {
MipsRegState(i) = CRegInfo::STATE_UNKNOWN;
if (MipsRegState(i) != RegSet->MipsRegState(i)) {
m_RegWorkingSet.SetMipsRegState(i,CRegInfo::STATE_UNKNOWN);
} else if (Is32Bit(i) && cMipsRegLo(i) != RegSet->cMipsRegLo(i)) {
MipsRegState(i) = CRegInfo::STATE_UNKNOWN;
} else if (Is64Bit(i) && cMipsReg(i) != RegSet->cMipsReg(i)) {
MipsRegState(i) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(i,CRegInfo::STATE_UNKNOWN);
} else if (Is64Bit(i) && MipsReg(i) != RegSet->MipsReg(i)) {
m_RegWorkingSet.SetMipsRegState(i,CRegInfo::STATE_UNKNOWN);
}
}
}
@ -1570,73 +1573,73 @@ bool CCodeSection::FillSectionInfo(STEP_TYPE StartStepType)
case R4300i_SPECIAL_SLL:
if (Command.rd == 0) { break; }
if (m_InLoop && Command.rt == Command.rd) {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
if (IsConst(Command.rt)) {
MipsRegState(Command.rd) = CRegInfo::STATE_CONST_32;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_CONST_32);
MipsRegLo(Command.rd) = MipsRegLo(Command.rt) << Command.sa;
} else {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
break;
case R4300i_SPECIAL_SRL:
if (Command.rd == 0) { break; }
if (m_InLoop && Command.rt == Command.rd) {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
if (IsConst(Command.rt)) {
MipsRegState(Command.rd) = CRegInfo::STATE_CONST_32;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_CONST_32);
MipsRegLo(Command.rd) = MipsRegLo(Command.rt) >> Command.sa;
} else {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
break;
case R4300i_SPECIAL_SRA:
if (Command.rd == 0) { break; }
if (m_InLoop && Command.rt == Command.rd) {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
if (IsConst(Command.rt)) {
MipsRegState(Command.rd) = CRegInfo::STATE_CONST_32;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_CONST_32);
MipsRegLo(Command.rd) = MipsRegLo_S(Command.rt) >> Command.sa;
} else {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
break;
case R4300i_SPECIAL_SLLV:
if (Command.rd == 0) { break; }
if (m_InLoop && (Command.rt == Command.rd || Command.rs == Command.rd)) {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
if (IsConst(Command.rt) && IsConst(Command.rs)) {
MipsRegState(Command.rd) = CRegInfo::STATE_CONST_32;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_CONST_32);
MipsRegLo(Command.rd) = MipsRegLo(Command.rt) << (MipsRegLo(Command.rs) & 0x1F);
} else {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
break;
case R4300i_SPECIAL_SRLV:
if (Command.rd == 0) { break; }
if (m_InLoop && (Command.rt == Command.rd || Command.rs == Command.rd)) {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
if (IsConst(Command.rt) && IsConst(Command.rs)) {
MipsRegState(Command.rd) = CRegInfo::STATE_CONST_32;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_CONST_32);
MipsRegLo(Command.rd) = MipsRegLo(Command.rt) >> (MipsRegLo(Command.rs) & 0x1F);
} else {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
break;
case R4300i_SPECIAL_SRAV:
if (Command.rd == 0) { break; }
if (m_InLoop && (Command.rt == Command.rd || Command.rs == Command.rd)) {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
if (IsConst(Command.rt) && IsConst(Command.rs)) {
MipsRegState(Command.rd) = CRegInfo::STATE_CONST_32;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_CONST_32);
MipsRegLo(Command.rd) = MipsRegLo_S(Command.rt) >> (MipsRegLo(Command.rs) & 0x1F);
} else {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
break;
case R4300i_SPECIAL_JR:
@ -1649,7 +1652,7 @@ bool CCodeSection::FillSectionInfo(STEP_TYPE StartStepType)
break;
case R4300i_SPECIAL_JALR:
MipsRegLo(Command.rd) = CompilePC() + 8;
MipsRegState(Command.rd) = CRegInfo::STATE_CONST_32;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_CONST_32);
if (IsConst(Command.rs)) {
m_Jump.TargetPC = MipsRegLo(Command.rs);
} else {
@ -1662,44 +1665,44 @@ bool CCodeSection::FillSectionInfo(STEP_TYPE StartStepType)
m_NextInstruction = END_BLOCK;
m_CompilePC -= 4;
break;
case R4300i_SPECIAL_MFHI: MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN; break;
case R4300i_SPECIAL_MFHI: m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN); break;
case R4300i_SPECIAL_MTHI: break;
case R4300i_SPECIAL_MFLO: MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN; break;
case R4300i_SPECIAL_MFLO: m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN); break;
case R4300i_SPECIAL_MTLO: break;
case R4300i_SPECIAL_DSLLV:
if (Command.rd == 0) { break; }
if (m_InLoop && (Command.rt == Command.rd || Command.rs == Command.rd)) {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
if (IsConst(Command.rt) && IsConst(Command.rs)) {
MipsRegState(Command.rd) = CRegInfo::STATE_CONST_64;
MipsReg(Command.rd) = Is64Bit(Command.rt)?cMipsReg(Command.rt):(QWORD)MipsRegLo_S(Command.rt) << (MipsRegLo(Command.rs) & 0x3F);
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_CONST_64);
m_RegWorkingSet.SetMipsReg(Command.rd, Is64Bit(Command.rt)?MipsReg(Command.rt):(QWORD)MipsRegLo_S(Command.rt) << (MipsRegLo(Command.rs) & 0x3F));
} else {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
break;
case R4300i_SPECIAL_DSRLV:
if (Command.rd == 0) { break; }
if (m_InLoop && (Command.rt == Command.rd || Command.rs == Command.rd)) {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
if (IsConst(Command.rt) && IsConst(Command.rs)) {
MipsRegState(Command.rd) = CRegInfo::STATE_CONST_64;
MipsReg(Command.rd) = Is64Bit(Command.rt)?cMipsReg(Command.rt):(QWORD)MipsRegLo_S(Command.rt) >> (MipsRegLo(Command.rs) & 0x3F);
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_CONST_64);
m_RegWorkingSet.SetMipsReg(Command.rd,Is64Bit(Command.rt)?MipsReg(Command.rt):(QWORD)MipsRegLo_S(Command.rt) >> (MipsRegLo(Command.rs) & 0x3F));
} else {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
break;
case R4300i_SPECIAL_DSRAV:
if (Command.rd == 0) { break; }
if (m_InLoop && (Command.rt == Command.rd || Command.rs == Command.rd)) {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
if (IsConst(Command.rt) && IsConst(Command.rs)) {
MipsRegState(Command.rd) = CRegInfo::STATE_CONST_64;
MipsReg(Command.rd) = Is64Bit(Command.rt)?cMipsReg_S(Command.rt):(_int64)MipsRegLo_S(Command.rt) >> (MipsRegLo(Command.rs) & 0x3F);
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_CONST_64);
m_RegWorkingSet.SetMipsReg(Command.rd,Is64Bit(Command.rt)?cMipsReg_S(Command.rt):(_int64)MipsRegLo_S(Command.rt) >> (MipsRegLo(Command.rs) & 0x3F));
} else {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
break;
case R4300i_SPECIAL_MULT: break;
@ -1714,122 +1717,122 @@ bool CCodeSection::FillSectionInfo(STEP_TYPE StartStepType)
case R4300i_SPECIAL_ADDU:
if (Command.rd == 0) { break; }
if (m_InLoop && (Command.rt == Command.rd || Command.rs == Command.rd)) {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
if (IsConst(Command.rt) && IsConst(Command.rs)) {
MipsRegLo(Command.rd) = MipsRegLo(Command.rs) + MipsRegLo(Command.rt);
MipsRegState(Command.rd) = CRegInfo::STATE_CONST_32;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_CONST_32);
} else {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
break;
case R4300i_SPECIAL_SUB:
case R4300i_SPECIAL_SUBU:
if (Command.rd == 0) { break; }
if (m_InLoop && (Command.rt == Command.rd || Command.rs == Command.rd)) {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
if (IsConst(Command.rt) && IsConst(Command.rs)) {
MipsRegLo(Command.rd) = MipsRegLo(Command.rs) - MipsRegLo(Command.rt);
MipsRegState(Command.rd) = CRegInfo::STATE_CONST_32;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_CONST_32);
} else {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
break;
case R4300i_SPECIAL_AND:
if (Command.rd == 0) { break; }
if (m_InLoop && (Command.rt == Command.rd || Command.rs == Command.rd)) {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
if (IsConst(Command.rt) && IsConst(Command.rs)) {
if (Is64Bit(Command.rt) && Is64Bit(Command.rs)) {
MipsReg(Command.rd) = cMipsReg(Command.rt) & cMipsReg(Command.rs);
MipsRegState(Command.rd) = CRegInfo::STATE_CONST_64;
m_RegWorkingSet.SetMipsReg(Command.rd,MipsReg(Command.rt) & MipsReg(Command.rs));
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_CONST_64);
} else if (Is64Bit(Command.rt) || Is64Bit(Command.rs)) {
if (Is64Bit(Command.rt)) {
MipsReg(Command.rd) = cMipsReg(Command.rt) & MipsRegLo(Command.rs);
m_RegWorkingSet.SetMipsReg(Command.rd, MipsReg(Command.rt) & MipsRegLo(Command.rs));
} else {
MipsReg(Command.rd) = MipsRegLo(Command.rt) & cMipsReg(Command.rs);
m_RegWorkingSet.SetMipsReg(Command.rd, MipsRegLo(Command.rt) & MipsReg(Command.rs));
}
MipsRegState(Command.rd) = CRegInfo::ConstantsType(cMipsReg(Command.rd));
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::ConstantsType(MipsReg(Command.rd)));
} else {
MipsRegLo(Command.rd) = MipsRegLo(Command.rt) & MipsRegLo(Command.rs);
MipsRegState(Command.rd) = CRegInfo::STATE_CONST_32;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_CONST_32);
}
} else {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
break;
case R4300i_SPECIAL_OR:
if (Command.rd == 0) { break; }
if (m_InLoop && (Command.rt == Command.rd || Command.rs == Command.rd)) {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
if (IsConst(Command.rt) && IsConst(Command.rs)) {
if (Is64Bit(Command.rt) && Is64Bit(Command.rs)) {
MipsReg(Command.rd) = cMipsReg(Command.rt) | cMipsReg(Command.rs);
MipsRegState(Command.rd) = CRegInfo::STATE_CONST_64;
m_RegWorkingSet.SetMipsReg(Command.rd,MipsReg(Command.rt) | MipsReg(Command.rs));
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_CONST_64);
} else if (Is64Bit(Command.rt) || Is64Bit(Command.rs)) {
if (Is64Bit(Command.rt)) {
MipsReg(Command.rd) = cMipsReg(Command.rt) | MipsRegLo(Command.rs);
m_RegWorkingSet.SetMipsReg(Command.rd,MipsReg(Command.rt) | MipsRegLo(Command.rs));
} else {
MipsReg(Command.rd) = MipsRegLo(Command.rt) | cMipsReg(Command.rs);
m_RegWorkingSet.SetMipsReg(Command.rd,MipsRegLo(Command.rt) | MipsReg(Command.rs));
}
MipsRegState(Command.rd) = CRegInfo::STATE_CONST_64;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_CONST_64);
} else {
MipsRegLo(Command.rd) = MipsRegLo(Command.rt) | MipsRegLo(Command.rs);
MipsRegState(Command.rd) = CRegInfo::STATE_CONST_32;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_CONST_32);
}
} else {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
break;
case R4300i_SPECIAL_XOR:
if (Command.rd == 0) { break; }
if (m_InLoop && (Command.rt == Command.rd || Command.rs == Command.rd)) {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
if (IsConst(Command.rt) && IsConst(Command.rs)) {
if (Is64Bit(Command.rt) && Is64Bit(Command.rs)) {
MipsReg(Command.rd) = cMipsReg(Command.rt) ^ cMipsReg(Command.rs);
MipsRegState(Command.rd) = CRegInfo::STATE_CONST_64;
m_RegWorkingSet.SetMipsReg(Command.rd,MipsReg(Command.rt) ^ MipsReg(Command.rs));
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_CONST_64);
} else if (Is64Bit(Command.rt) || Is64Bit(Command.rs)) {
if (Is64Bit(Command.rt)) {
MipsReg(Command.rd) = cMipsReg(Command.rt) ^ MipsRegLo(Command.rs);
m_RegWorkingSet.SetMipsReg(Command.rd, MipsReg(Command.rt) ^ MipsRegLo(Command.rs));
} else {
MipsReg(Command.rd) = MipsRegLo(Command.rt) ^ cMipsReg(Command.rs);
m_RegWorkingSet.SetMipsReg(Command.rd, MipsRegLo(Command.rt) ^ MipsReg(Command.rs));
}
MipsRegState(Command.rd) = CRegInfo::STATE_CONST_64;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_CONST_64);
} else {
MipsRegLo(Command.rd) = MipsRegLo(Command.rt) ^ MipsRegLo(Command.rs);
MipsRegState(Command.rd) = CRegInfo::STATE_CONST_32;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_CONST_32);
}
} else {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
break;
case R4300i_SPECIAL_NOR:
if (Command.rd == 0) { break; }
if (m_InLoop && (Command.rt == Command.rd || Command.rs == Command.rd)) {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
if (IsConst(Command.rt) && IsConst(Command.rs)) {
if (Is64Bit(Command.rt) && Is64Bit(Command.rs)) {
MipsReg(Command.rd) = ~(cMipsReg(Command.rt) | cMipsReg(Command.rs));
MipsRegState(Command.rd) = CRegInfo::STATE_CONST_64;
m_RegWorkingSet.SetMipsReg(Command.rd,~(MipsReg(Command.rt) | MipsReg(Command.rs)));
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_CONST_64);
} else if (Is64Bit(Command.rt) || Is64Bit(Command.rs)) {
if (Is64Bit(Command.rt)) {
MipsReg(Command.rd) = ~(cMipsReg(Command.rt) | MipsRegLo(Command.rs));
m_RegWorkingSet.SetMipsReg(Command.rd, ~(MipsReg(Command.rt) | MipsRegLo(Command.rs)));
} else {
MipsReg(Command.rd) = ~(MipsRegLo(Command.rt) | cMipsReg(Command.rs));
m_RegWorkingSet.SetMipsReg(Command.rd, ~(MipsRegLo(Command.rt) | MipsReg(Command.rs)));
}
MipsRegState(Command.rd) = CRegInfo::STATE_CONST_64;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_CONST_64);
} else {
MipsRegLo(Command.rd) = ~(MipsRegLo(Command.rt) | MipsRegLo(Command.rs));
MipsRegState(Command.rd) = CRegInfo::STATE_CONST_32;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_CONST_32);
}
} else {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
break;
case R4300i_SPECIAL_SLT:
@ -1844,9 +1847,9 @@ bool CCodeSection::FillSectionInfo(STEP_TYPE StartStepType)
} else {
MipsRegLo(Command.rd) = (MipsRegLo_S(Command.rs) < MipsRegLo_S(Command.rt))?1:0;
}
MipsRegState(Command.rd) = CRegInfo::STATE_CONST_32;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_CONST_32);
} else {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
break;
case R4300i_SPECIAL_SLTU:
@ -1854,118 +1857,120 @@ bool CCodeSection::FillSectionInfo(STEP_TYPE StartStepType)
if (IsConst(Command.rt) && IsConst(Command.rs)) {
if (Is64Bit(Command.rt) || Is64Bit(Command.rs)) {
if (Is64Bit(Command.rt)) {
MipsRegLo(Command.rd) = (MipsRegLo(Command.rs) < cMipsReg(Command.rt))?1:0;
MipsRegLo(Command.rd) = (MipsRegLo(Command.rs) < MipsReg(Command.rt))?1:0;
} else {
MipsRegLo(Command.rd) = (cMipsReg(Command.rs) < MipsRegLo(Command.rt))?1:0;
MipsRegLo(Command.rd) = (MipsReg(Command.rs) < MipsRegLo(Command.rt))?1:0;
}
} else {
MipsRegLo(Command.rd) = (MipsRegLo(Command.rs) < MipsRegLo(Command.rt))?1:0;
}
MipsRegState(Command.rd) = CRegInfo::STATE_CONST_32;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_CONST_32);
} else {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
break;
case R4300i_SPECIAL_DADD:
case R4300i_SPECIAL_DADDU:
if (Command.rd == 0) { break; }
if (m_InLoop && (Command.rt == Command.rd || Command.rs == Command.rd)) {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
if (IsConst(Command.rt) && IsConst(Command.rs)) {
MipsReg(Command.rd) =
Is64Bit(Command.rs)?cMipsReg(Command.rs):(_int64)MipsRegLo_S(Command.rs) +
Is64Bit(Command.rt)?cMipsReg(Command.rt):(_int64)MipsRegLo_S(Command.rt);
MipsRegState(Command.rd) = CRegInfo::STATE_CONST_64;
m_RegWorkingSet.SetMipsReg(Command.rd,
Is64Bit(Command.rs)?MipsReg(Command.rs):(_int64)MipsRegLo_S(Command.rs) +
Is64Bit(Command.rt)?MipsReg(Command.rt):(_int64)MipsRegLo_S(Command.rt)
);
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_CONST_64);
} else {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
break;
case R4300i_SPECIAL_DSUB:
case R4300i_SPECIAL_DSUBU:
if (Command.rd == 0) { break; }
if (m_InLoop && (Command.rt == Command.rd || Command.rs == Command.rd)) {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
if (IsConst(Command.rt) && IsConst(Command.rs)) {
MipsReg(Command.rd) =
Is64Bit(Command.rs)?cMipsReg(Command.rs):(_int64)MipsRegLo_S(Command.rs) -
Is64Bit(Command.rt)?cMipsReg(Command.rt):(_int64)MipsRegLo_S(Command.rt);
MipsRegState(Command.rd) = CRegInfo::STATE_CONST_64;
m_RegWorkingSet.SetMipsReg(Command.rd,
Is64Bit(Command.rs)?MipsReg(Command.rs):(_int64)MipsRegLo_S(Command.rs) -
Is64Bit(Command.rt)?MipsReg(Command.rt):(_int64)MipsRegLo_S(Command.rt)
);
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_CONST_64);
} else {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
break;
case R4300i_SPECIAL_DSLL:
if (Command.rd == 0) { break; }
if (m_InLoop && Command.rt == Command.rd) {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
if (IsConst(Command.rt)) {
MipsRegState(Command.rd) = CRegInfo::STATE_CONST_64;
MipsReg(Command.rd) = Is64Bit(Command.rt)?cMipsReg(Command.rt):(_int64)MipsRegLo_S(Command.rt) << Command.sa;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_CONST_64);
m_RegWorkingSet.SetMipsReg(Command.rd,Is64Bit(Command.rt)?MipsReg(Command.rt):(_int64)MipsRegLo_S(Command.rt) << Command.sa);
} else {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
break;
case R4300i_SPECIAL_DSRL:
if (Command.rd == 0) { break; }
if (m_InLoop && Command.rt == Command.rd) {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
if (IsConst(Command.rt)) {
MipsRegState(Command.rd) = CRegInfo::STATE_CONST_64;
MipsReg(Command.rd) = Is64Bit(Command.rt)?cMipsReg(Command.rt):(QWORD)MipsRegLo_S(Command.rt) >> Command.sa;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_CONST_64);
m_RegWorkingSet.SetMipsReg(Command.rd, Is64Bit(Command.rt)?MipsReg(Command.rt):(QWORD)MipsRegLo_S(Command.rt) >> Command.sa);
} else {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
break;
case R4300i_SPECIAL_DSRA:
if (Command.rd == 0) { break; }
if (m_InLoop && Command.rt == Command.rd) {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
if (IsConst(Command.rt)) {
MipsRegState(Command.rd) = CRegInfo::STATE_CONST_64;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_CONST_64);
MipsReg_S(Command.rd) = Is64Bit(Command.rt)?cMipsReg_S(Command.rt):(_int64)MipsRegLo_S(Command.rt) >> Command.sa;
} else {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
break;
case R4300i_SPECIAL_DSLL32:
if (Command.rd == 0) { break; }
if (m_InLoop && Command.rt == Command.rd) {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
if (IsConst(Command.rt)) {
MipsRegState(Command.rd) = CRegInfo::STATE_CONST_64;
MipsReg(Command.rd) = MipsRegLo(Command.rt) << (Command.sa + 32);
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_CONST_64);
m_RegWorkingSet.SetMipsReg(Command.rd, MipsRegLo(Command.rt) << (Command.sa + 32));
} else {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
break;
case R4300i_SPECIAL_DSRL32:
if (Command.rd == 0) { break; }
if (m_InLoop && Command.rt == Command.rd) {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
if (IsConst(Command.rt)) {
MipsRegState(Command.rd) = CRegInfo::STATE_CONST_32;
MipsRegLo(Command.rd) = (DWORD)(cMipsReg(Command.rt) >> (Command.sa + 32));
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_CONST_32);
MipsRegLo(Command.rd) = (DWORD)(MipsReg(Command.rt) >> (Command.sa + 32));
} else {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
break;
case R4300i_SPECIAL_DSRA32:
if (Command.rd == 0) { break; }
if (m_InLoop && Command.rt == Command.rd) {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
if (IsConst(Command.rt)) {
MipsRegState(Command.rd) = CRegInfo::STATE_CONST_32;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_CONST_32);
MipsRegLo(Command.rd) = (DWORD)(cMipsReg_S(Command.rt) >> (Command.sa + 32));
} else {
MipsRegState(Command.rd) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rd,CRegInfo::STATE_UNKNOWN);
}
break;
default:
@ -2004,7 +2009,7 @@ bool CCodeSection::FillSectionInfo(STEP_TYPE StartStepType)
break;
case R4300i_REGIMM_BLTZAL:
MipsRegLo(31) = CompilePC() + 8;
MipsRegState(31) = CRegInfo::STATE_CONST_32;
m_RegWorkingSet.SetMipsRegState(31,CRegInfo::STATE_CONST_32);
m_Cont.TargetPC = CompilePC() + 8;
m_Jump.TargetPC = CompilePC() + ((short)Command.offset << 2) + 4;
if (CompilePC() == m_Jump.TargetPC) {
@ -2026,7 +2031,7 @@ bool CCodeSection::FillSectionInfo(STEP_TYPE StartStepType)
}
if (Value >= 0) {
MipsRegLo(31) = CompilePC() + 8;
MipsRegState(31) = CRegInfo::STATE_CONST_32;
m_RegWorkingSet.SetMipsRegState(31,CRegInfo::STATE_CONST_32);
m_Jump.TargetPC = CompilePC() + ((short)Command.offset << 2) + 4;
if (CompilePC() == m_Jump.TargetPC) {
if (!DelaySlotEffectsCompare(CompilePC(),31,0)) {
@ -2039,7 +2044,7 @@ bool CCodeSection::FillSectionInfo(STEP_TYPE StartStepType)
MipsRegLo(31) = CompilePC() + 8;
MipsRegState(31) = CRegInfo::STATE_CONST_32;
m_RegWorkingSet.SetMipsRegState(31,CRegInfo::STATE_CONST_32);
m_Cont.TargetPC = CompilePC() + 8;
m_Jump.TargetPC = CompilePC() + ((short)Command.offset << 2) + 4;
if (CompilePC() == m_Jump.TargetPC) {
@ -2061,7 +2066,7 @@ bool CCodeSection::FillSectionInfo(STEP_TYPE StartStepType)
case R4300i_JAL:
m_NextInstruction = DELAY_SLOT;
MipsRegLo(31) = CompilePC() + 8;
MipsRegState(31) = CRegInfo::STATE_CONST_32;
m_RegWorkingSet.SetMipsRegState(31,CRegInfo::STATE_CONST_32);
m_Jump.TargetPC = (CompilePC() & 0xF0000000) + (Command.target << 2);
if (CompilePC() == m_Jump.TargetPC) {
if (!DelaySlotEffectsCompare(CompilePC(),31,0)) {
@ -2120,13 +2125,13 @@ bool CCodeSection::FillSectionInfo(STEP_TYPE StartStepType)
case R4300i_ADDIU:
if (Command.rt == 0) { break; }
if (m_InLoop && Command.rs == Command.rt) {
MipsRegState(Command.rt) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rt,CRegInfo::STATE_UNKNOWN);
}
if (IsConst(Command.rs)) {
MipsRegLo(Command.rt) = MipsRegLo(Command.rs) + (short)Command.immediate;
MipsRegState(Command.rt) = CRegInfo::STATE_CONST_32;
m_RegWorkingSet.SetMipsRegState(Command.rt,CRegInfo::STATE_CONST_32);
} else {
MipsRegState(Command.rt) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rt,CRegInfo::STATE_UNKNOWN);
}
break;
case R4300i_SLTI:
@ -2137,70 +2142,70 @@ bool CCodeSection::FillSectionInfo(STEP_TYPE StartStepType)
} else {
MipsRegLo(Command.rt) = (MipsRegLo_S(Command.rs) < (int)((short)Command.immediate))?1:0;
}
MipsRegState(Command.rt) = CRegInfo::STATE_CONST_32;
m_RegWorkingSet.SetMipsRegState(Command.rt,CRegInfo::STATE_CONST_32);
} else {
MipsRegState(Command.rt) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rt,CRegInfo::STATE_UNKNOWN);
}
break;
case R4300i_SLTIU:
if (Command.rt == 0) { break; }
if (IsConst(Command.rs)) {
if (Is64Bit(Command.rs)) {
MipsRegLo(Command.rt) = (cMipsReg(Command.rs) < (unsigned _int64)((short)Command.immediate))?1:0;
MipsRegLo(Command.rt) = (MipsReg(Command.rs) < (unsigned _int64)((short)Command.immediate))?1:0;
} else {
MipsRegLo(Command.rt) = (MipsRegLo(Command.rs) < (DWORD)((short)Command.immediate))?1:0;
}
MipsRegState(Command.rt) = CRegInfo::STATE_CONST_32;
m_RegWorkingSet.SetMipsRegState(Command.rt,CRegInfo::STATE_CONST_32);
} else {
MipsRegState(Command.rt) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rt,CRegInfo::STATE_UNKNOWN);
}
break;
case R4300i_LUI:
if (Command.rt == 0) { break; }
MipsRegLo(Command.rt) = ((short)Command.offset << 16);
MipsRegState(Command.rt) = CRegInfo::STATE_CONST_32;
m_RegWorkingSet.SetMipsRegState(Command.rt,CRegInfo::STATE_CONST_32);
break;
case R4300i_ANDI:
if (Command.rt == 0) { break; }
if (m_InLoop && Command.rs == Command.rt) {
MipsRegState(Command.rt) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rt,CRegInfo::STATE_UNKNOWN);
}
if (IsConst(Command.rs)) {
MipsRegState(Command.rt) = CRegInfo::STATE_CONST_32;
m_RegWorkingSet.SetMipsRegState(Command.rt,CRegInfo::STATE_CONST_32);
MipsRegLo(Command.rt) = MipsRegLo(Command.rs) & Command.immediate;
} else {
MipsRegState(Command.rt) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rt,CRegInfo::STATE_UNKNOWN);
}
break;
case R4300i_ORI:
if (Command.rt == 0) { break; }
if (m_InLoop && Command.rs == Command.rt) {
MipsRegState(Command.rt) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rt,CRegInfo::STATE_UNKNOWN);
}
if (IsConst(Command.rs)) {
MipsRegState(Command.rt) = CRegInfo::STATE_CONST_32;
m_RegWorkingSet.SetMipsRegState(Command.rt,CRegInfo::STATE_CONST_32);
MipsRegLo(Command.rt) = MipsRegLo(Command.rs) | Command.immediate;
} else {
MipsRegState(Command.rt) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rt,CRegInfo::STATE_UNKNOWN);
}
break;
case R4300i_XORI:
if (Command.rt == 0) { break; }
if (m_InLoop && Command.rs == Command.rt) {
MipsRegState(Command.rt) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rt,CRegInfo::STATE_UNKNOWN);
}
if (IsConst(Command.rs)) {
MipsRegState(Command.rt) = CRegInfo::STATE_CONST_32;
m_RegWorkingSet.SetMipsRegState(Command.rt,CRegInfo::STATE_CONST_32);
MipsRegLo(Command.rt) = MipsRegLo(Command.rs) ^ Command.immediate;
} else {
MipsRegState(Command.rt) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rt,CRegInfo::STATE_UNKNOWN);
}
break;
case R4300i_CP0:
switch (Command.rs) {
case R4300i_COP0_MF:
if (Command.rt == 0) { break; }
MipsRegState(Command.rt) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rt,CRegInfo::STATE_UNKNOWN);
break;
case R4300i_COP0_MT: break;
default:
@ -2235,7 +2240,7 @@ bool CCodeSection::FillSectionInfo(STEP_TYPE StartStepType)
case R4300i_COP1_MF:
case R4300i_COP1_DMF:
if (Command.rt == 0) { break; }
MipsRegState(Command.rt) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rt,CRegInfo::STATE_UNKNOWN);
break;
case R4300i_COP1_BC:
switch (Command.ft) {
@ -2330,7 +2335,7 @@ bool CCodeSection::FillSectionInfo(STEP_TYPE StartStepType)
case R4300i_DADDIU:
if (Command.rt == 0) { break; }
if (m_InLoop && Command.rs == Command.rt) {
MipsRegState(Command.rt) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rt,CRegInfo::STATE_UNKNOWN);
}
if (IsConst(Command.rs)) {
if (Is64Bit(Command.rs)) {
@ -2340,9 +2345,9 @@ bool CCodeSection::FillSectionInfo(STEP_TYPE StartStepType)
} else {
MipsReg_S(Command.rt) = MipsRegLo_S(Command.rs) + (short)Command.immediate;
}
MipsRegState(Command.rt) = CRegInfo::STATE_CONST_64;
m_RegWorkingSet.SetMipsRegState(Command.rt,CRegInfo::STATE_CONST_64);
} else {
MipsRegState(Command.rt) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rt,CRegInfo::STATE_UNKNOWN);
}
break;
case R4300i_LDR:
@ -2358,7 +2363,7 @@ bool CCodeSection::FillSectionInfo(STEP_TYPE StartStepType)
case R4300i_LWR:
case R4300i_SC:
if (Command.rt == 0) { break; }
MipsRegState(Command.rt) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rt,CRegInfo::STATE_UNKNOWN);
break;
case R4300i_SB: break;
case R4300i_SH: break;
@ -2373,7 +2378,7 @@ bool CCodeSection::FillSectionInfo(STEP_TYPE StartStepType)
case R4300i_LDC1: break;
case R4300i_LD:
if (Command.rt == 0) { break; }
MipsRegState(Command.rt) = CRegInfo::STATE_UNKNOWN;
m_RegWorkingSet.SetMipsRegState(Command.rt,CRegInfo::STATE_UNKNOWN);
break;
case R4300i_SDC1: break;
case R4300i_SD: break;
@ -2393,7 +2398,7 @@ bool CCodeSection::FillSectionInfo(STEP_TYPE StartStepType)
// if (CompilePC() == 0x8005E4B8) {
//CPU_Message("%X: %s %s = %d",CompilePC(),R4300iOpcodeName(Command.Hex,CompilePC()),
// CRegName::GPR[8],cMipsRegState(8));
// CRegName::GPR[8],MipsRegState(8));
//_asm int 3
// }
switch (m_NextInstruction) {
@ -2723,13 +2728,13 @@ bool CCodeSection::InheritParentInfo ( void )
case CRegInfo::STATE_MAPPED_32_ZERO: break;
case CRegInfo::STATE_MAPPED_32_SIGN:
if (IsUnsigned(i2)) {
MipsRegState(i2) = CRegInfo::STATE_MAPPED_32_SIGN;
m_RegWorkingSet.SetMipsRegState(i2,CRegInfo::STATE_MAPPED_32_SIGN);
}
break;
case CRegInfo::STATE_CONST_64: Map_GPR_64bit(i2,i2); break;
case CRegInfo::STATE_CONST_32:
if ((RegSet->MipsRegLo_S(i2) < 0) && IsUnsigned(i2)) {
MipsRegState(i2) = CRegInfo::STATE_MAPPED_32_SIGN;
m_RegWorkingSet.SetMipsRegState(i2,CRegInfo::STATE_MAPPED_32_SIGN);
}
break;
case CRegInfo::STATE_UNKNOWN:

732
Source/Project64/N64 System/Recompiler/Recompiler Ops.cpp
View File

File diff suppressed because it is too large Load Diff

15
Source/Project64/N64 System/Recompiler/Recompiler Ops.h
View File

@ -209,27 +209,22 @@ protected:
/********* Helper Functions *********/
typedef CRegInfo::REG_STATE REG_STATE;
static inline REG_STATE cMipsRegState ( int Reg ) { return m_RegWorkingSet.cMipsRegState(Reg); }
static inline unsigned __int64 cMipsReg ( int Reg ) { return m_RegWorkingSet.cMipsReg(Reg); }
static inline __int64 cMipsReg_S ( int Reg ) { return m_RegWorkingSet.cMipsReg_S(Reg); }
static inline DWORD cMipsRegLo ( int Reg ) { return m_RegWorkingSet.cMipsRegLo(Reg); }
static inline long cMipsRegLo_S ( int Reg ) { return m_RegWorkingSet.cMipsRegLo_S(Reg); }
static inline DWORD cMipsRegHi ( int Reg ) { return m_RegWorkingSet.cMipsRegHi(Reg); }
static inline long cMipsRegHi_S ( int Reg ) { return m_RegWorkingSet.cMipsRegHi_S(Reg); }
static inline CX86Ops::x86Reg cMipsRegMapLo ( int Reg ) { return m_RegWorkingSet.cMipsRegMapLo(Reg); }
static inline CX86Ops::x86Reg cMipsRegMapHi ( int Reg ) { return m_RegWorkingSet.cMipsRegMapHi(Reg); }
static inline bool cX86Protected ( x86Reg Reg ) { return m_RegWorkingSet.cX86Protected(Reg); }
static inline REG_STATE & MipsRegState ( int Reg ) { return m_RegWorkingSet.MipsRegState(Reg); }
static inline unsigned _int64 & MipsReg ( int Reg ) { return m_RegWorkingSet.MipsReg(Reg); }
static inline REG_STATE MipsRegState ( int Reg ) { return m_RegWorkingSet.MipsRegState(Reg); }
static inline unsigned __int64 MipsReg ( int Reg ) { return m_RegWorkingSet.MipsReg(Reg); }
static inline _int64 & MipsReg_S ( int Reg ) { return m_RegWorkingSet.MipsReg_S(Reg); }
static inline DWORD & MipsRegLo ( int Reg ) { return m_RegWorkingSet.MipsRegLo(Reg); }
static inline long & MipsRegLo_S ( int Reg ) { return m_RegWorkingSet.MipsRegLo_S(Reg); }
static inline DWORD & MipsRegHi ( int Reg ) { return m_RegWorkingSet.MipsRegHi(Reg); }
static inline long & MipsRegHi_S ( int Reg ) { return m_RegWorkingSet.MipsRegHi_S(Reg); }
static inline CX86Ops::x86Reg & MipsRegMapLo ( int Reg ) { return m_RegWorkingSet.MipsRegMapLo(Reg); }
static inline CX86Ops::x86Reg & MipsRegMapHi ( int Reg ) { return m_RegWorkingSet.MipsRegMapHi(Reg); }
static inline bool & X86Protected ( x86Reg Reg ) { return m_RegWorkingSet.X86Protected(Reg); }
static inline CX86Ops::x86Reg MipsRegMapLo ( int Reg ) { return m_RegWorkingSet.MipsRegMapLo(Reg); }
static inline CX86Ops::x86Reg MipsRegMapHi ( int Reg ) { return m_RegWorkingSet.MipsRegMapHi(Reg); }
static inline bool X86Protected ( x86Reg Reg ) { return m_RegWorkingSet.X86Protected(Reg); }
static inline bool IsKnown ( int Reg ) { return m_RegWorkingSet.IsKnown(Reg); }
static inline bool IsUnknown ( int Reg ) { return m_RegWorkingSet.IsUnknown(Reg); }

46
Source/Project64/N64 System/Recompiler/Reg Info.cpp
View File

@ -512,8 +512,8 @@ void CRegInfo::Map_GPR_32bit (int MipsReg, BOOL SignValue, int MipsRegToLoad)
}
SetX86Mapped(Reg,GPR_Mapped);
SetX86Protected(Reg,TRUE);
MipsRegMapLo(MipsReg) = Reg;
MipsRegState(MipsReg) = SignValue ? STATE_MAPPED_32_SIGN : STATE_MAPPED_32_ZERO;
SetMipsRegMapLo(MipsReg,Reg);
SetMipsRegState(MipsReg,SignValue ? STATE_MAPPED_32_SIGN : STATE_MAPPED_32_ZERO);
}
void CRegInfo::Map_GPR_64bit ( int MipsReg, int MipsRegToLoad)
@ -605,9 +605,9 @@ CPU_Message("Map_GPR_64bit 11");
}
SetX86Mapped(x86Hi,GPR_Mapped);
SetX86Mapped(x86lo,GPR_Mapped);
MipsRegMapHi(MipsReg) = x86Hi;
MipsRegMapLo(MipsReg) = x86lo;
MipsRegState(MipsReg) = STATE_MAPPED_64;
SetMipsRegMapHi(MipsReg,x86Hi);
SetMipsRegMapLo(MipsReg,x86lo);
SetMipsRegState(MipsReg,STATE_MAPPED_64);
}
CX86Ops::x86Reg CRegInfo::Map_TempReg (CX86Ops::x86Reg Reg, int MipsReg, BOOL LoadHiWord)
@ -667,7 +667,7 @@ CX86Ops::x86Reg CRegInfo::Map_TempReg (CX86Ops::x86Reg Reg, int MipsReg, BOOL Lo
{
continue;
}
if (cMipsRegMapLo(count) == Reg)
if (MipsRegMapLo(count) == Reg)
{
if (NewReg == x86_Unknown)
{
@ -677,12 +677,12 @@ CX86Ops::x86Reg CRegInfo::Map_TempReg (CX86Ops::x86Reg Reg, int MipsReg, BOOL Lo
CPU_Message(" regcache: change allocation of %s from %s to %s",CRegName::GPR[count],x86_Name(Reg),x86_Name(NewReg));
SetX86Mapped(NewReg,GPR_Mapped);
SetX86MapOrder(NewReg,GetX86MapOrder(Reg));
MipsRegMapLo(count) = NewReg;
SetMipsRegMapLo(count,NewReg);
MoveX86RegToX86Reg(Reg,NewReg);
if (MipsReg == count && LoadHiWord == FALSE) { MipsReg = -1; }
break;
}
if (Is64Bit(count) && cMipsRegMapHi(count) == Reg)
if (Is64Bit(count) && MipsRegMapHi(count) == Reg)
{
if (NewReg == x86_Unknown)
{
@ -692,7 +692,7 @@ CX86Ops::x86Reg CRegInfo::Map_TempReg (CX86Ops::x86Reg Reg, int MipsReg, BOOL Lo
CPU_Message(" regcache: change allocation of %s from %s to %s",CRegName::GPR_Hi[count],x86_Name(Reg),x86_Name(NewReg));
SetX86Mapped(NewReg,GPR_Mapped);
SetX86MapOrder(NewReg,GetX86MapOrder(Reg));
MipsRegMapHi(count) = NewReg;
SetMipsRegMapHi(count,NewReg);
MoveX86RegToX86Reg(Reg,NewReg);
if (MipsReg == count && LoadHiWord == TRUE) { MipsReg = -1; }
break;
@ -714,9 +714,9 @@ CX86Ops::x86Reg CRegInfo::Map_TempReg (CX86Ops::x86Reg Reg, int MipsReg, BOOL Lo
else if (IsMapped(MipsReg))
{
if (Is64Bit(MipsReg)) {
MoveX86RegToX86Reg(cMipsRegMapHi(MipsReg),Reg);
MoveX86RegToX86Reg(MipsRegMapHi(MipsReg),Reg);
} else if (IsSigned(MipsReg)){
MoveX86RegToX86Reg(cMipsRegMapLo(MipsReg),Reg);
MoveX86RegToX86Reg(MipsRegMapLo(MipsReg),Reg);
ShiftRightSignImmed(Reg,31);
} else {
MoveConstToX86reg(0,Reg);
@ -907,13 +907,13 @@ void CRegInfo::UnMap_GPR (DWORD Reg, bool WriteBackValue)
//CPU_Message("UnMap_GPR: State: %X\tReg: %s\tWriteBack: %s",State,CRegName::GPR[Reg],WriteBackValue?"TRUE":"FALSE");
if (IsConst(Reg)) {
if (!WriteBackValue) {
MipsRegState(Reg) = STATE_UNKNOWN;
SetMipsRegState(Reg,STATE_UNKNOWN);
return;
}
if (Is64Bit(Reg)) {
MoveConstToVariable(MipsRegHi(Reg),&_GPR[Reg].UW[1],CRegName::GPR_Hi[Reg]);
MoveConstToVariable(MipsRegLo(Reg),&_GPR[Reg].UW[0],CRegName::GPR_Lo[Reg]);
MipsRegState(Reg) = STATE_UNKNOWN;
SetMipsRegState(Reg,STATE_UNKNOWN);
return;
}
if ((MipsRegLo(Reg) & 0x80000000) != 0) {
@ -922,7 +922,7 @@ void CRegInfo::UnMap_GPR (DWORD Reg, bool WriteBackValue)
MoveConstToVariable(0,&_GPR[Reg].UW[1],CRegName::GPR_Hi[Reg]);
}
MoveConstToVariable(MipsRegLo(Reg),&_GPR[Reg].UW[0],CRegName::GPR_Lo[Reg]);
MipsRegState(Reg) = STATE_UNKNOWN;
SetMipsRegState(Reg,STATE_UNKNOWN);
return;
}
if (Is64Bit(Reg)) {
@ -931,18 +931,18 @@ void CRegInfo::UnMap_GPR (DWORD Reg, bool WriteBackValue)
SetX86Protected(MipsRegMapHi(Reg),FALSE);
}
CPU_Message(" regcache: unallocate %s from %s",x86_Name(MipsRegMapLo(Reg)),CRegName::GPR_Lo[Reg]);
SetX86Mapped(cMipsRegMapLo(Reg),NotMapped);
SetX86Protected(cMipsRegMapLo(Reg),FALSE);
SetX86Mapped(MipsRegMapLo(Reg),NotMapped);
SetX86Protected(MipsRegMapLo(Reg),FALSE);
if (!WriteBackValue)
{
MipsRegState(Reg) = STATE_UNKNOWN;
SetMipsRegState(Reg,STATE_UNKNOWN);
return;
}
MoveX86regToVariable(MipsRegMapLo(Reg),&_GPR[Reg].UW[0],CRegName::GPR_Lo[Reg]);
if (Is64Bit(Reg)) {
MipsRegMapLo(Reg) = x86_Unknown;
SetMipsRegMapLo(Reg, x86_Unknown);
MoveX86regToVariable(MipsRegMapHi(Reg),&_GPR[Reg].UW[1],CRegName::GPR_Hi[Reg]);
MipsRegMapHi(Reg) = x86_Unknown;
SetMipsRegMapHi(Reg,x86_Unknown);
} else {
if (!m_b32bitCore) {
if (IsSigned(Reg)) {
@ -952,9 +952,9 @@ void CRegInfo::UnMap_GPR (DWORD Reg, bool WriteBackValue)
MoveConstToVariable(0,&_GPR[Reg].UW[1],CRegName::GPR_Hi[Reg]);
}
}
MipsRegMapLo(Reg) = x86_Unknown;
SetMipsRegMapLo(Reg, x86_Unknown);
}
MipsRegState(Reg) = STATE_UNKNOWN;
SetMipsRegState(Reg,STATE_UNKNOWN);
}
CX86Ops::x86Reg CRegInfo::UnMap_TempReg ( void )
@ -1090,7 +1090,7 @@ void CRegInfo::WriteBackRegisters ()
} else
MoveConstToVariable(MipsRegLo(count),&_GPR[count].UW[0],CRegName::GPR_Lo[count]);
MipsRegState(count) = CRegInfo::STATE_UNKNOWN;
SetMipsRegState(count, CRegInfo::STATE_UNKNOWN);
break;
case CRegInfo::STATE_CONST_64:
if (MipsRegLo(count) == 0 || MipsRegHi(count) == 0) {
@ -1117,7 +1117,7 @@ void CRegInfo::WriteBackRegisters ()
} else {
MoveConstToVariable(MipsRegLo(count),&_GPR[count].UW[0],CRegName::GPR_Lo[count]);
}
MipsRegState(count) = CRegInfo::STATE_UNKNOWN;
SetMipsRegState(count, CRegInfo::STATE_UNKNOWN);
break;
#ifndef EXTERNAL_RELEASE
default:

47
Source/Project64/N64 System/Recompiler/Reg Info.h
View File

@ -74,42 +74,37 @@ public:
bool UnMap_X86reg ( x86Reg Reg );
void WriteBackRegisters ( void );
inline bool IsKnown(int Reg) const { return ((cMipsRegState(Reg) & STATE_KNOWN_VALUE) != 0); }
inline bool IsUnknown(int Reg) const { return ((cMipsRegState(Reg) & STATE_KNOWN_VALUE) == 0); }
inline bool IsKnown(int Reg) const { return ((MipsRegState(Reg) & STATE_KNOWN_VALUE) != 0); }
inline bool IsUnknown(int Reg) const { return ((MipsRegState(Reg) & STATE_KNOWN_VALUE) == 0); }
inline bool IsMapped(int Reg) const { return ((cMipsRegState(Reg) & (STATE_KNOWN_VALUE | STATE_X86_MAPPED)) == (STATE_KNOWN_VALUE | STATE_X86_MAPPED)); }
inline bool IsConst(int Reg) const { return ((cMipsRegState(Reg) & (STATE_KNOWN_VALUE | STATE_X86_MAPPED)) == STATE_KNOWN_VALUE); }
inline bool IsMapped(int Reg) const { return ((MipsRegState(Reg) & (STATE_KNOWN_VALUE | STATE_X86_MAPPED)) == (STATE_KNOWN_VALUE | STATE_X86_MAPPED)); }
inline bool IsConst(int Reg) const { return ((MipsRegState(Reg) & (STATE_KNOWN_VALUE | STATE_X86_MAPPED)) == STATE_KNOWN_VALUE); }
inline bool IsSigned(int Reg) const { return ((cMipsRegState(Reg) & (STATE_KNOWN_VALUE | STATE_SIGN)) == (STATE_KNOWN_VALUE | STATE_SIGN)); }
inline bool IsUnsigned(int Reg) const { return ((cMipsRegState(Reg) & (STATE_KNOWN_VALUE | STATE_SIGN)) == STATE_KNOWN_VALUE); }
inline bool IsSigned(int Reg) const { return ((MipsRegState(Reg) & (STATE_KNOWN_VALUE | STATE_SIGN)) == (STATE_KNOWN_VALUE | STATE_SIGN)); }
inline bool IsUnsigned(int Reg) const { return ((MipsRegState(Reg) & (STATE_KNOWN_VALUE | STATE_SIGN)) == STATE_KNOWN_VALUE); }
inline bool Is32Bit(int Reg) const { return ((cMipsRegState(Reg) & (STATE_KNOWN_VALUE | STATE_32BIT)) == (STATE_KNOWN_VALUE | STATE_32BIT)); }
inline bool Is64Bit(int Reg) const { return ((cMipsRegState(Reg) & (STATE_KNOWN_VALUE | STATE_32BIT)) == STATE_KNOWN_VALUE); }
inline bool Is32Bit(int Reg) const { return ((MipsRegState(Reg) & (STATE_KNOWN_VALUE | STATE_32BIT)) == (STATE_KNOWN_VALUE | STATE_32BIT)); }
inline bool Is64Bit(int Reg) const { return ((MipsRegState(Reg) & (STATE_KNOWN_VALUE | STATE_32BIT)) == STATE_KNOWN_VALUE); }
inline bool Is32BitMapped(int Reg) const { return ((cMipsRegState(Reg) & (STATE_KNOWN_VALUE | STATE_32BIT | STATE_X86_MAPPED)) == (STATE_KNOWN_VALUE | STATE_32BIT | STATE_X86_MAPPED)); }
inline bool Is64BitMapped(int Reg) const { return ((cMipsRegState(Reg) & (STATE_KNOWN_VALUE | STATE_32BIT | STATE_X86_MAPPED)) == (STATE_KNOWN_VALUE | STATE_X86_MAPPED)); }
inline bool Is32BitMapped(int Reg) const { return ((MipsRegState(Reg) & (STATE_KNOWN_VALUE | STATE_32BIT | STATE_X86_MAPPED)) == (STATE_KNOWN_VALUE | STATE_32BIT | STATE_X86_MAPPED)); }
inline bool Is64BitMapped(int Reg) const { return ((MipsRegState(Reg) & (STATE_KNOWN_VALUE | STATE_32BIT | STATE_X86_MAPPED)) == (STATE_KNOWN_VALUE | STATE_X86_MAPPED)); }
inline REG_STATE cMipsRegState ( int Reg ) const { return MIPS_RegState[Reg]; }
inline unsigned _int64 cMipsReg ( int Reg ) const { return MIPS_RegVal[Reg].UDW; }
inline _int64 cMipsReg_S ( int Reg ) const { return MIPS_RegVal[Reg].DW; }
inline DWORD cMipsRegLo ( int Reg ) const { return MIPS_RegVal[Reg].UW[0]; }
inline long cMipsRegLo_S ( int Reg ) const { return MIPS_RegVal[Reg].W[0]; }
inline DWORD cMipsRegHi ( int Reg ) const { return MIPS_RegVal[Reg].UW[1]; }
inline long cMipsRegHi_S ( int Reg ) const { return MIPS_RegVal[Reg].W[1]; }
inline CX86Ops::x86Reg cMipsRegMapLo ( int Reg ) const { return RegMapLo[Reg]; }
inline CX86Ops::x86Reg cMipsRegMapHi ( int Reg ) const { return RegMapHi[Reg]; }
inline bool cX86Protected ( x86Reg Reg ) const { return x86reg_Protected[Reg]; }
inline REG_STATE & MipsRegState ( int Reg ) { return MIPS_RegState[Reg]; }
inline unsigned _int64 & MipsReg ( int Reg ) { return MIPS_RegVal[Reg].UDW; }
inline REG_STATE MipsRegState ( int Reg ) const { return MIPS_RegState[Reg]; }
inline unsigned _int64 MipsReg ( int Reg ) const { return MIPS_RegVal[Reg].UDW; }
inline _int64 & MipsReg_S ( int Reg ) { return MIPS_RegVal[Reg].DW; }
inline DWORD & MipsRegLo ( int Reg ) { return MIPS_RegVal[Reg].UW[0]; }
inline long & MipsRegLo_S ( int Reg ) { return MIPS_RegVal[Reg].W[0]; }
inline DWORD & MipsRegHi ( int Reg ) { return MIPS_RegVal[Reg].UW[1]; }
inline long & MipsRegHi_S ( int Reg ) { return MIPS_RegVal[Reg].W[1]; }
inline CX86Ops::x86Reg & MipsRegMapLo ( int Reg ) { return RegMapLo[Reg]; }
inline CX86Ops::x86Reg & MipsRegMapHi ( int Reg ) { return RegMapHi[Reg]; }
inline bool & X86Protected ( x86Reg Reg ) { return x86reg_Protected[Reg]; }
inline CX86Ops::x86Reg MipsRegMapLo ( int Reg ) const { return RegMapLo[Reg]; }
inline CX86Ops::x86Reg MipsRegMapHi ( int Reg ) const { return RegMapHi[Reg]; }
inline bool X86Protected ( x86Reg Reg ) const { return x86reg_Protected[Reg]; }
inline DWORD GetX86MapOrder ( x86Reg Reg ) const { return x86reg_MapOrder[Reg]; }
inline bool GetX86Protected ( x86Reg Reg ) const { return x86reg_Protected[Reg]; }
@ -117,10 +112,22 @@ public:
inline DWORD GetBlockCycleCount ( void ) const { return m_CycleCount; }
inline void SetMipsReg ( int Reg, unsigned __int64 value ) { MIPS_RegVal[Reg].UDW = value; }
inline void SetMipsRegMapLo ( int MipsReg, x86Reg Reg )
{
RegMapLo[MipsReg] = Reg;
}
inline void SetMipsRegMapHi ( int MipsReg, x86Reg Reg )
{
RegMapHi[MipsReg] = Reg;
}
inline void SetMipsRegState ( int MipsReg, REG_STATE State ) { MIPS_RegState[MipsReg] = State; }
inline void SetX86MapOrder ( x86Reg Reg, DWORD Order ) { x86reg_MapOrder[Reg] = Order; }
inline void SetX86Protected ( x86Reg Reg, bool Protected ) { x86reg_Protected[Reg] = Protected; }
inline void SetX86Mapped ( x86Reg Reg, REG_MAPPED Mapping ) { x86reg_MappedTo[Reg] = Mapping; }
inline void SetBlockCycleCount ( DWORD CyleCount ) { m_CycleCount = CyleCount; }
inline int & StackTopPos ( void ) { return Stack_TopPos; }