ShuriZma
/
project64
mirror of https://github.com/project64/project64.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Update hle.h 

Remove leftover header, remove title case, fix flag names, convert multi line comments into single line comments
This commit is contained in:
Derek "Turtle" Roe 2021-03-16 00:31:26 -05:00
parent 4b0930956c
commit 94e7a2dfae
1 changed files with 55 additions and 59 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

114
Source/Android/PluginRSP/hle.h
View File

@ -1,69 +1,65 @@
// Project64 - A Nintendo 64 emulator
// http://www.pj64-emu.com/
// Copyright(C) 2001-2021 Project64
// Copyright(C) 2014 Bobby Smiles
// GNU/GPLv2 licensed: https://gnu.org/licenses/gpl-2.0.html
#pragma once
#include <Common/stdtypes.h>
#include "Rsp.h"
#include "ucodes.h"
//Signal Processor interface flags
// Signal processor interface flags
enum
{
SP_CLR_HALT = 0x00001, /* Bit 0: clear halt */
SP_SET_HALT = 0x00002, /* Bit 1: set halt */
SP_CLR_BROKE = 0x00004, /* Bit 2: clear broke */
SP_CLR_INTR = 0x00008, /* Bit 3: clear intr */
SP_SET_INTR = 0x00010, /* Bit 4: set intr */
SP_CLR_SSTEP = 0x00020, /* Bit 5: clear sstep */
SP_SET_SSTEP = 0x00040, /* Bit 6: set sstep */
SP_CLR_INTR_BREAK = 0x00080, /* Bit 7: clear intr on break */
SP_SET_INTR_BREAK = 0x00100, /* Bit 8: set intr on break */
SP_CLR_SIG0 = 0x00200, /* Bit 9: clear signal 0 */
SP_SET_SIG0 = 0x00400, /* Bit 10: set signal 0 */
SP_CLR_SIG1 = 0x00800, /* Bit 11: clear signal 1 */
SP_SET_SIG1 = 0x01000, /* Bit 12: set signal 1 */
SP_CLR_SIG2 = 0x02000, /* Bit 13: clear signal 2 */
SP_SET_SIG2 = 0x04000, /* Bit 14: set signal 2 */
SP_CLR_SIG3 = 0x08000, /* Bit 15: clear signal 3 */
SP_SET_SIG3 = 0x10000, /* Bit 16: set signal 3 */
SP_CLR_SIG4 = 0x20000, /* Bit 17: clear signal 4 */
SP_SET_SIG4 = 0x40000, /* Bit 18: set signal 4 */
SP_CLR_SIG5 = 0x80000, /* Bit 19: clear signal 5 */
SP_SET_SIG5 = 0x100000, /* Bit 20: set signal 5 */
SP_CLR_SIG6 = 0x200000, /* Bit 21: clear signal 6 */
SP_SET_SIG6 = 0x400000, /* Bit 22: set signal 6 */
SP_CLR_SIG7 = 0x800000, /* Bit 23: clear signal 7 */
SP_SET_SIG7 = 0x1000000, /* Bit 24: set signal 7 */
SP_CLR_HALT = 0x00001, /* Bit 0: Clear halt */
SP_SET_HALT = 0x00002, /* Bit 1: Set halt */
SP_CLR_BROKE = 0x00004, /* Bit 2: Clear broke */
SP_CLR_INTR = 0x00008, /* Bit 3: Clear INTR */
SP_SET_INTR = 0x00010, /* Bit 4: Set INTR */
SP_CLR_SSTEP = 0x00020, /* Bit 5: Clear SSTEP */
SP_SET_SSTEP = 0x00040, /* Bit 6: Set SSTEP */
SP_CLR_INTR_BREAK = 0x00080, /* Bit 7: Clear INTR on break */
SP_SET_INTR_BREAK = 0x00100, /* Bit 8: Set INTR on break */
SP_CLR_SIG0 = 0x00200, /* Bit 9: Clear signal 0 */
SP_SET_SIG0 = 0x00400, /* Bit 10: Set signal 0 */
SP_CLR_SIG1 = 0x00800, /* Bit 11: Clear signal 1 */
SP_SET_SIG1 = 0x01000, /* Bit 12: Set signal 1 */
SP_CLR_SIG2 = 0x02000, /* Bit 13: Clear signal 2 */
SP_SET_SIG2 = 0x04000, /* Bit 14: Set signal 2 */
SP_CLR_SIG3 = 0x08000, /* Bit 15: Clear signal 3 */
SP_SET_SIG3 = 0x10000, /* Bit 16: Set signal 3 */
SP_CLR_SIG4 = 0x20000, /* Bit 17: Clear signal 4 */
SP_SET_SIG4 = 0x40000, /* Bit 18: Set signal 4 */
SP_CLR_SIG5 = 0x80000, /* Bit 19: Clear signal 5 */
SP_SET_SIG5 = 0x100000, /* Bit 20: Set signal 5 */
SP_CLR_SIG6 = 0x200000, /* Bit 21: Clear signal 6 */
SP_SET_SIG6 = 0x400000, /* Bit 22: Set signal 6 */
SP_CLR_SIG7 = 0x800000, /* Bit 23: Clear signal 7 */
SP_SET_SIG7 = 0x1000000, /* Bit 24: Set signal 7 */
SP_STATUS_HALT = 0x001, /* Bit 0: halt */
SP_STATUS_BROKE = 0x002, /* Bit 1: broke */
SP_STATUS_DMA_BUSY = 0x004, /* Bit 2: dma busy */
SP_STATUS_DMA_FULL = 0x008, /* Bit 3: dma full */
SP_STATUS_IO_FULL = 0x010, /* Bit 4: io full */
SP_STATUS_SSTEP = 0x020, /* Bit 5: single step */
SP_STATUS_INTR_BREAK = 0x040, /* Bit 6: interrupt on break */
SP_STATUS_SIG0 = 0x080, /* Bit 7: signal 0 set */
SP_STATUS_SIG1 = 0x100, /* Bit 8: signal 1 set */
SP_STATUS_SIG2 = 0x200, /* Bit 9: signal 2 set */
SP_STATUS_SIG3 = 0x400, /* Bit 10: signal 3 set */
SP_STATUS_SIG4 = 0x800, /* Bit 11: signal 4 set */
SP_STATUS_SIG5 = 0x1000, /* Bit 12: signal 5 set */
SP_STATUS_SIG6 = 0x2000, /* Bit 13: signal 6 set */
SP_STATUS_SIG7 = 0x4000, /* Bit 14: signal 7 set */
SP_STATUS_HALT = 0x001, /* Bit 0: Halt */
SP_STATUS_BROKE = 0x002, /* Bit 1: Broke */
SP_STATUS_DMA_BUSY = 0x004, /* Bit 2: DMA busy */
SP_STATUS_DMA_FULL = 0x008, /* Bit 3: DMA full */
SP_STATUS_IO_FULL = 0x010, /* Bit 4: IO full */
SP_STATUS_SSTEP = 0x020, /* Bit 5: Single step */
SP_STATUS_INTR_BREAK = 0x040, /* Bit 6: Interrupt on break */
SP_STATUS_SIG0 = 0x080, /* Bit 7: Signal 0 set */
SP_STATUS_SIG1 = 0x100, /* Bit 8: Signal 1 set */
SP_STATUS_SIG2 = 0x200, /* Bit 9: Signal 2 set */
SP_STATUS_SIG3 = 0x400, /* Bit 10: Signal 3 set */
SP_STATUS_SIG4 = 0x800, /* Bit 11: Signal 4 set */
SP_STATUS_SIG5 = 0x1000, /* Bit 12: Signal 5 set */
SP_STATUS_SIG6 = 0x2000, /* Bit 13: Signal 6 set */
SP_STATUS_SIG7 = 0x4000, /* Bit 14: Signal 7 set */
};
//Mips interface flags
// MIPS interface flags
enum
{
MI_INTR_SP = 0x01, /* Bit 0: SP intr */
MI_INTR_SI = 0x02, /* Bit 1: SI intr */
MI_INTR_AI = 0x04, /* Bit 2: AI intr */
MI_INTR_VI = 0x08, /* Bit 3: VI intr */
MI_INTR_PI = 0x10, /* Bit 4: PI intr */
MI_INTR_DP = 0x20, /* Bit 5: DP intr */
MI_INTR_SP = 0x01, /* Bit 0: SP INTR */
MI_INTR_SI = 0x02, /* Bit 1: SI INTR */
MI_INTR_AI = 0x04, /* Bit 2: AI INTR */
MI_INTR_VI = 0x08, /* Bit 3: VI INTR */
MI_INTR_PI = 0x10, /* Bit 4: PI INTR */
MI_INTR_DP = 0x20, /* Bit 5: DP INTR */
};
class CHle
@ -134,19 +130,19 @@ private:
void(*m_ProcessRdpList)(void);
void(*m_ShowCFB)(void);
/* alist.cpp */
// alist.cpp
uint8_t m_alist_buffer[0x1000];
/* alist_audio.cpp */
// alist_audio.cpp
struct alist_audio_t m_alist_audio;
/* alist_naudio.cpp */
// alist_naudio.cpp
struct alist_naudio_t m_alist_naudio;
/* alist_nead.cpp */
// alist_nead.cpp
struct alist_nead_t m_alist_nead;
/* mp3.cpp */
// mp3.cpp
uint8_t m_mp3_buffer[0x1000];
bool m_AudioHle;