From 928dfe3a16e745e73c4e0990fd385d678f37fcbd Mon Sep 17 00:00:00 2001 From: zilmar Date: Fri, 4 Mar 2022 22:53:30 +1030 Subject: [PATCH] Core: Add MIPSInterfaceHandler --- Source/Project64-core/Logging.cpp | 26 +- .../MemoryHandler/MIPSInterfaceHandler.cpp | 169 +++++++++ .../MemoryHandler/MIPSInterfaceHandler.h | 47 +++ .../N64System/Mips/MemoryVirtualMem.cpp | 118 +----- .../N64System/Mips/MemoryVirtualMem.h | 8 +- .../N64System/Mips/Register.cpp | 14 +- .../Project64-core/N64System/Mips/Register.h | 344 +++++++++--------- .../Recompiler/x86/x86RecompilerOps.cpp | 9 +- Source/Project64-core/Plugins/Plugin.h | 2 +- Source/Project64-core/Project64-core.vcxproj | 2 + .../Project64-core.vcxproj.filters | 6 + 11 files changed, 407 insertions(+), 338 deletions(-) create mode 100644 Source/Project64-core/N64System/MemoryHandler/MIPSInterfaceHandler.cpp create mode 100644 Source/Project64-core/N64System/MemoryHandler/MIPSInterfaceHandler.h diff --git a/Source/Project64-core/Logging.cpp b/Source/Project64-core/Logging.cpp index 88984c917..2050b2367 100644 --- a/Source/Project64-core/Logging.cpp +++ b/Source/Project64-core/Logging.cpp @@ -55,19 +55,7 @@ void CLogging::Log_LW(uint32_t PC, uint32_t VAddr) } if (VAddr >= 0xA4300000 && VAddr <= 0xA430000C) { - if (!LogMIPSInterface()) - { - return; - } - g_MMU->LW_VAddr(VAddr, Value); - - switch (VAddr) - { - case 0xA4300000: LogMessage("%08X: read from MI_INIT_MODE_REG/MI_MODE_REG (%08X)", PC, Value); return; - case 0xA4300004: LogMessage("%08X: read from MI_VERSION_REG/MI_NOOP_REG (%08X)", PC, Value); return; - case 0xA4300008: LogMessage("%08X: read from MI_INTR_REG (%08X)", PC, Value); return; - case 0xA430000C: LogMessage("%08X: read from MI_INTR_MASK_REG (%08X)", PC, Value); return; - } + return; } if (VAddr >= 0xA4400000 && VAddr <= 0xA4400034) { @@ -261,17 +249,7 @@ void CLogging::Log_SW(uint32_t PC, uint32_t VAddr, uint32_t Value) if (VAddr >= 0xA4300000 && VAddr <= 0xA430000C) { - if (!LogMIPSInterface()) - { - return; - } - switch (VAddr) - { - case 0xA4300000: LogMessage("%08X: Writing 0x%08X to MI_INIT_MODE_REG/MI_MODE_REG", PC, Value); return; - case 0xA4300004: LogMessage("%08X: Writing 0x%08X to MI_VERSION_REG/MI_NOOP_REG", PC, Value); return; - case 0xA4300008: LogMessage("%08X: Writing 0x%08X to MI_INTR_REG", PC, Value); return; - case 0xA430000C: LogMessage("%08X: Writing 0x%08X to MI_INTR_MASK_REG", PC, Value); return; - } + return; } if (VAddr >= 0xA4400000 && VAddr <= 0xA4400034) { diff --git a/Source/Project64-core/N64System/MemoryHandler/MIPSInterfaceHandler.cpp b/Source/Project64-core/N64System/MemoryHandler/MIPSInterfaceHandler.cpp new file mode 100644 index 000000000..c6bdfa03d --- /dev/null +++ b/Source/Project64-core/N64System/MemoryHandler/MIPSInterfaceHandler.cpp @@ -0,0 +1,169 @@ +#include "stdafx.h" +#include "MIPSInterfaceHandler.h" +#include +#include + +MIPSInterfaceReg::MIPSInterfaceReg(uint32_t * MipsInterface) : + MI_INIT_MODE_REG(MipsInterface[0]), + MI_MODE_REG(MipsInterface[0]), + MI_VERSION_REG(MipsInterface[1]), + MI_NOOP_REG(MipsInterface[1]), + MI_INTR_REG(MipsInterface[2]), + MI_INTR_MASK_REG(MipsInterface[3]) +{ +} + +MIPSInterfaceHandler::MIPSInterfaceHandler(CRegisters & Reg) : + MIPSInterfaceReg(Reg.m_Mips_Interface), + m_Reg(Reg), + m_PC(Reg.m_PROGRAM_COUNTER) +{ +} + +bool MIPSInterfaceHandler::Read32(uint32_t Address, uint32_t & Value) +{ + switch (Address & 0x1FFFFFFF) + { + case 0x04300000: Value = MI_MODE_REG; break; + case 0x04300004: Value = MI_VERSION_REG; break; + case 0x04300008: Value = MI_INTR_REG; break; + case 0x0430000C: Value = MI_INTR_MASK_REG; break; + default: + Value = 0; + if (HaveDebugger()) + { + g_Notify->BreakPoint(__FILE__, __LINE__); + } + } + + if (LogMIPSInterface()) + { + switch (Address & 0x1FFFFFFF) + { + case 0x04300000: LogMessage("%08X: read from MI_INIT_MODE_REG/MI_MODE_REG (%08X)", m_PC, Value); break; + case 0x04300004: LogMessage("%08X: read from MI_VERSION_REG/MI_NOOP_REG (%08X)", m_PC, Value); break; + case 0x04300008: LogMessage("%08X: read from MI_INTR_REG (%08X)", m_PC, Value); break; + case 0x0430000C: LogMessage("%08X: read from MI_INTR_MASK_REG (%08X)", m_PC, Value); break; + default: + if (HaveDebugger()) + { + g_Notify->BreakPoint(__FILE__, __LINE__); + } + } + } + return true; +} + +bool MIPSInterfaceHandler::Write32(uint32_t Address, uint32_t Value, uint32_t Mask) +{ + if (LogMIPSInterface()) + { + switch (Address & 0x1FFFFFFF) + { + case 0x04300000: LogMessage("%08X: Writing 0x%08X (Mask: 0x%08X) to MI_INIT_MODE_REG/MI_MODE_REG", m_PC, Value, Mask); break; + case 0x04300004: LogMessage("%08X: Writing 0x%08X (Mask: 0x%08X) to MI_VERSION_REG/MI_NOOP_REG", m_PC, Value, Mask); break; + case 0x04300008: LogMessage("%08X: Writing 0x%08X (Mask: 0x%08X) to MI_INTR_REG", m_PC, Value, Mask); break; + case 0x0430000C: LogMessage("%08X: Writing 0x%08X (Mask: 0x%08X) to MI_INTR_MASK_REG", m_PC, Value, Mask); break; + default: + if (HaveDebugger()) + { + g_Notify->BreakPoint(__FILE__, __LINE__); + } + } + } + + uint32_t MaskedValue = Value & Mask; + switch (Address & 0x1FFFFFFF) + { + case 0x04300000: + MI_MODE_REG &= ~0x7F; + MI_MODE_REG |= (MaskedValue & 0x7F); + if ((MaskedValue & MI_CLR_INIT) != 0) + { + MI_MODE_REG &= ~MI_MODE_INIT; + } + if ((MaskedValue & MI_SET_INIT) != 0) + { + MI_MODE_REG |= MI_MODE_INIT; + } + if ((MaskedValue & MI_CLR_EBUS) != 0) + { + MI_MODE_REG &= ~MI_MODE_EBUS; + } + if ((MaskedValue & MI_SET_EBUS) != 0) + { + MI_MODE_REG |= MI_MODE_EBUS; + } + if ((MaskedValue & MI_CLR_DP_INTR) != 0) + { + MI_INTR_REG &= ~MI_INTR_DP; + m_Reg.m_GfxIntrReg &= ~MI_INTR_DP; + m_Reg.CheckInterrupts(); + } + if ((MaskedValue & MI_CLR_RDRAM) != 0) + { + MI_MODE_REG &= ~MI_MODE_RDRAM; + } + if ((MaskedValue & MI_SET_RDRAM) != 0) + { + MI_MODE_REG |= MI_MODE_RDRAM; + } + break; + case 0x0430000C: + if ((MaskedValue & MI_INTR_MASK_CLR_SP) != 0) + { + MI_INTR_MASK_REG &= ~MI_INTR_MASK_SP; + } + if ((MaskedValue & MI_INTR_MASK_SET_SP) != 0) + { + MI_INTR_MASK_REG |= MI_INTR_MASK_SP; + } + if ((MaskedValue & MI_INTR_MASK_CLR_SI) != 0) + { + MI_INTR_MASK_REG &= ~MI_INTR_MASK_SI; + } + if ((MaskedValue & MI_INTR_MASK_SET_SI) != 0) + { + MI_INTR_MASK_REG |= MI_INTR_MASK_SI; + } + if ((MaskedValue & MI_INTR_MASK_CLR_AI) != 0) + { + MI_INTR_MASK_REG &= ~MI_INTR_MASK_AI; + } + if ((MaskedValue & MI_INTR_MASK_SET_AI) != 0) + { + MI_INTR_MASK_REG |= MI_INTR_MASK_AI; + } + if ((MaskedValue & MI_INTR_MASK_CLR_VI) != 0) + { + MI_INTR_MASK_REG &= ~MI_INTR_MASK_VI; + } + if ((MaskedValue & MI_INTR_MASK_SET_VI) != 0) + { + MI_INTR_MASK_REG |= MI_INTR_MASK_VI; + } + if ((MaskedValue & MI_INTR_MASK_CLR_PI) != 0) + { + MI_INTR_MASK_REG &= ~MI_INTR_MASK_PI; + } + if ((MaskedValue & MI_INTR_MASK_SET_PI) != 0) + { + MI_INTR_MASK_REG |= MI_INTR_MASK_PI; + } + if ((MaskedValue & MI_INTR_MASK_CLR_DP) != 0) + { + MI_INTR_MASK_REG &= ~MI_INTR_MASK_DP; + } + if ((MaskedValue & MI_INTR_MASK_SET_DP) != 0) + { + MI_INTR_MASK_REG |= MI_INTR_MASK_DP; + } + break; + default: + if (HaveDebugger()) + { + g_Notify->BreakPoint(__FILE__, __LINE__); + } + } + return true; +} \ No newline at end of file diff --git a/Source/Project64-core/N64System/MemoryHandler/MIPSInterfaceHandler.h b/Source/Project64-core/N64System/MemoryHandler/MIPSInterfaceHandler.h new file mode 100644 index 000000000..56986ca23 --- /dev/null +++ b/Source/Project64-core/N64System/MemoryHandler/MIPSInterfaceHandler.h @@ -0,0 +1,47 @@ +#pragma once +#include "MemoryHandler.h" +#include +#include +#include + +class MIPSInterfaceReg +{ +protected: + MIPSInterfaceReg(uint32_t * MipsInterface); + +public: + uint32_t & MI_INIT_MODE_REG; + uint32_t & MI_MODE_REG; + uint32_t & MI_VERSION_REG; + uint32_t & MI_NOOP_REG; + uint32_t & MI_INTR_REG; + uint32_t & MI_INTR_MASK_REG; + +private: + MIPSInterfaceReg(); + MIPSInterfaceReg(const MIPSInterfaceReg&); + MIPSInterfaceReg& operator=(const MIPSInterfaceReg&); +}; + +class CRegisters; + +class MIPSInterfaceHandler : + public MemoryHandler, + private MIPSInterfaceReg, + private CDebugSettings, + private CLogging +{ +public: + MIPSInterfaceHandler(CRegisters & Reg); + + bool Read32(uint32_t Address, uint32_t & Value); + bool Write32(uint32_t Address, uint32_t Value, uint32_t Mask); + +private: + MIPSInterfaceHandler(); + MIPSInterfaceHandler(const MIPSInterfaceHandler &); + MIPSInterfaceHandler & operator=(const MIPSInterfaceHandler &); + + CRegisters & m_Reg; + uint32_t & m_PC; +}; diff --git a/Source/Project64-core/N64System/Mips/MemoryVirtualMem.cpp b/Source/Project64-core/N64System/Mips/MemoryVirtualMem.cpp index fa859c2e7..b8753dc7b 100755 --- a/Source/Project64-core/N64System/Mips/MemoryVirtualMem.cpp +++ b/Source/Project64-core/N64System/Mips/MemoryVirtualMem.cpp @@ -30,6 +30,7 @@ CMipsMemoryVM::CMipsMemoryVM(CN64System & System, CRegisters & Reg, bool SavesRe m_RDRAMRegistersHandler(Reg), m_RomMapped(false), m_DPCommandRegistersHandler(System, System.GetPlugins(), Reg), + m_MIPSInterfaceHandler(Reg), m_PeripheralInterfaceHandler(*this, Reg), m_RDRAMInterfaceHandler(Reg), m_SPRegistersHandler(System, *this, Reg), @@ -644,7 +645,7 @@ bool CMipsMemoryVM::LW_NonMemory(uint32_t PAddr, uint32_t* Value) case 0x03F00000: m_RDRAMRegistersHandler.Read32(PAddr, m_MemLookupValue.UW[0]); break; case 0x04000000: m_SPRegistersHandler.Read32(PAddr, m_MemLookupValue.UW[0]); break; case 0x04100000: m_DPCommandRegistersHandler.Read32(PAddr, m_MemLookupValue.UW[0]); break; - case 0x04300000: Load32MIPSInterface(); break; + case 0x04300000: m_MIPSInterfaceHandler.Read32(PAddr, m_MemLookupValue.UW[0]); break; case 0x04400000: Load32VideoInterface(); break; case 0x04500000: Load32AudioInterface(); break; case 0x04600000: m_PeripheralInterfaceHandler.Read32(PAddr, m_MemLookupValue.UW[0]); break; @@ -764,7 +765,7 @@ bool CMipsMemoryVM::SW_NonMemory(uint32_t PAddr, uint32_t Value) } break; case 0x04100000: m_DPCommandRegistersHandler.Write32(PAddr, Value, 0xFFFFFFFF); break; - case 0x04300000: Write32MIPSInterface(); break; + case 0x04300000: m_MIPSInterfaceHandler.Write32(PAddr, Value, 0xFFFFFFFF); break; case 0x04400000: Write32VideoInterface(); break; case 0x04500000: Write32AudioInterface(); break; case 0x04600000: m_PeripheralInterfaceHandler.Write32(PAddr, Value, 0xFFFFFFFF); break; @@ -1120,23 +1121,6 @@ void CMipsMemoryVM::ChangeMiIntrMask() } } -void CMipsMemoryVM::Load32MIPSInterface(void) -{ - switch (m_MemLookupAddress & 0x1FFFFFFF) - { - case 0x04300000: m_MemLookupValue.UW[0] = g_Reg->MI_MODE_REG; break; - case 0x04300004: m_MemLookupValue.UW[0] = g_Reg->MI_VERSION_REG; break; - case 0x04300008: m_MemLookupValue.UW[0] = g_Reg->MI_INTR_REG; break; - case 0x0430000C: m_MemLookupValue.UW[0] = g_Reg->MI_INTR_MASK_REG; break; - default: - m_MemLookupValue.UW[0] = 0; - if (HaveDebugger()) - { - g_Notify->BreakPoint(__FILE__, __LINE__); - } - } -} - void CMipsMemoryVM::Load32VideoInterface(void) { switch (m_MemLookupAddress & 0x1FFFFFFF) @@ -1366,102 +1350,6 @@ void CMipsMemoryVM::Load32Rom(void) } } -void CMipsMemoryVM::Write32MIPSInterface(void) -{ - switch ((m_MemLookupAddress & 0xFFFFFFF)) - { - case 0x04300000: - g_Reg->MI_MODE_REG &= ~0x7F; - g_Reg->MI_MODE_REG |= (m_MemLookupValue.UW[0] & 0x7F); - if ((m_MemLookupValue.UW[0] & MI_CLR_INIT) != 0) - { - g_Reg->MI_MODE_REG &= ~MI_MODE_INIT; - } - if ((m_MemLookupValue.UW[0] & MI_SET_INIT) != 0) - { - g_Reg->MI_MODE_REG |= MI_MODE_INIT; - } - if ((m_MemLookupValue.UW[0] & MI_CLR_EBUS) != 0) - { - g_Reg->MI_MODE_REG &= ~MI_MODE_EBUS; - } - if ((m_MemLookupValue.UW[0] & MI_SET_EBUS) != 0) - { - g_Reg->MI_MODE_REG |= MI_MODE_EBUS; - } - if ((m_MemLookupValue.UW[0] & MI_CLR_DP_INTR) != 0) - { - g_Reg->MI_INTR_REG &= ~MI_INTR_DP; - g_Reg->m_GfxIntrReg &= ~MI_INTR_DP; - g_Reg->CheckInterrupts(); - } - if ((m_MemLookupValue.UW[0] & MI_CLR_RDRAM) != 0) - { - g_Reg->MI_MODE_REG &= ~MI_MODE_RDRAM; - } - if ((m_MemLookupValue.UW[0] & MI_SET_RDRAM) != 0) - { - g_Reg->MI_MODE_REG |= MI_MODE_RDRAM; - } - break; - case 0x0430000C: - if ((m_MemLookupValue.UW[0] & MI_INTR_MASK_CLR_SP) != 0) - { - g_Reg->MI_INTR_MASK_REG &= ~MI_INTR_MASK_SP; - } - if ((m_MemLookupValue.UW[0] & MI_INTR_MASK_SET_SP) != 0) - { - g_Reg->MI_INTR_MASK_REG |= MI_INTR_MASK_SP; - } - if ((m_MemLookupValue.UW[0] & MI_INTR_MASK_CLR_SI) != 0) - { - g_Reg->MI_INTR_MASK_REG &= ~MI_INTR_MASK_SI; - } - if ((m_MemLookupValue.UW[0] & MI_INTR_MASK_SET_SI) != 0) - { - g_Reg->MI_INTR_MASK_REG |= MI_INTR_MASK_SI; - } - if ((m_MemLookupValue.UW[0] & MI_INTR_MASK_CLR_AI) != 0) - { - g_Reg->MI_INTR_MASK_REG &= ~MI_INTR_MASK_AI; - } - if ((m_MemLookupValue.UW[0] & MI_INTR_MASK_SET_AI) != 0) - { - g_Reg->MI_INTR_MASK_REG |= MI_INTR_MASK_AI; - } - if ((m_MemLookupValue.UW[0] & MI_INTR_MASK_CLR_VI) != 0) - { - g_Reg->MI_INTR_MASK_REG &= ~MI_INTR_MASK_VI; - } - if ((m_MemLookupValue.UW[0] & MI_INTR_MASK_SET_VI) != 0) - { - g_Reg->MI_INTR_MASK_REG |= MI_INTR_MASK_VI; - } - if ((m_MemLookupValue.UW[0] & MI_INTR_MASK_CLR_PI) != 0) - { - g_Reg->MI_INTR_MASK_REG &= ~MI_INTR_MASK_PI; - } - if ((m_MemLookupValue.UW[0] & MI_INTR_MASK_SET_PI) != 0) - { - g_Reg->MI_INTR_MASK_REG |= MI_INTR_MASK_PI; - } - if ((m_MemLookupValue.UW[0] & MI_INTR_MASK_CLR_DP) != 0) - { - g_Reg->MI_INTR_MASK_REG &= ~MI_INTR_MASK_DP; - } - if ((m_MemLookupValue.UW[0] & MI_INTR_MASK_SET_DP) != 0) - { - g_Reg->MI_INTR_MASK_REG |= MI_INTR_MASK_DP; - } - break; - default: - if (HaveDebugger()) - { - g_Notify->BreakPoint(__FILE__, __LINE__); - } - } -} - void CMipsMemoryVM::Write32VideoInterface(void) { switch ((m_MemLookupAddress & 0xFFFFFFF)) diff --git a/Source/Project64-core/N64System/Mips/MemoryVirtualMem.h b/Source/Project64-core/N64System/Mips/MemoryVirtualMem.h index edfe7d1b5..8f12de14e 100644 --- a/Source/Project64-core/N64System/Mips/MemoryVirtualMem.h +++ b/Source/Project64-core/N64System/Mips/MemoryVirtualMem.h @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -136,7 +137,6 @@ private: bool SH_NonMemory(uint32_t PAddr, uint16_t Value); bool SW_NonMemory(uint32_t PAddr, uint32_t Value); - static void Load32MIPSInterface(void); static void Load32VideoInterface(void); static void Load32AudioInterface(void); static void Load32SerialInterface(void); @@ -147,7 +147,6 @@ private: static void Load32PifRam(void); static void Load32Rom(void); - static void Write32MIPSInterface(void); static void Write32VideoInterface(void); static void Write32AudioInterface(void); static void Write32SerialInterface(void); @@ -180,10 +179,11 @@ private: void FreeMemory(); static uint8_t * m_Reserve1, *m_Reserve2; - CRegisters & m_Reg; + CRegisters & m_Reg; DisplayControlRegHandler m_DPCommandRegistersHandler; + MIPSInterfaceHandler m_MIPSInterfaceHandler; PeripheralInterfaceHandler m_PeripheralInterfaceHandler; - RDRAMInterfaceHandler m_RDRAMInterfaceHandler; + RDRAMInterfaceHandler m_RDRAMInterfaceHandler; RDRAMRegistersHandler m_RDRAMRegistersHandler; SPRegistersHandler m_SPRegistersHandler; uint8_t * m_RDRAM, *m_DMEM, *m_IMEM; diff --git a/Source/Project64-core/N64System/Mips/Register.cpp b/Source/Project64-core/N64System/Mips/Register.cpp index 94a517446..accc98807 100644 --- a/Source/Project64-core/N64System/Mips/Register.cpp +++ b/Source/Project64-core/N64System/Mips/Register.cpp @@ -75,16 +75,6 @@ CP0registers::CP0registers(uint32_t * _CP0) : { } -Mips_InterfaceReg::Mips_InterfaceReg(uint32_t * _MipsInterface) : - MI_INIT_MODE_REG(_MipsInterface[0]), - MI_MODE_REG(_MipsInterface[0]), - MI_VERSION_REG(_MipsInterface[1]), - MI_NOOP_REG(_MipsInterface[1]), - MI_INTR_REG(_MipsInterface[2]), - MI_INTR_MASK_REG(_MipsInterface[3]) -{ -} - Video_InterfaceReg::Video_InterfaceReg(uint32_t * _VideoInterface) : VI_STATUS_REG(_VideoInterface[0]), VI_CONTROL_REG(_VideoInterface[0]), @@ -170,8 +160,8 @@ Disk_InterfaceReg::Disk_InterfaceReg(uint32_t * DiskInterface) : CRegisters::CRegisters(CN64System * System, CSystemEvents * SystemEvents) : CP0registers(m_CP0), - RDRAMRegistersReg(m_RDRAM_Registers), - Mips_InterfaceReg(m_Mips_Interface), + RDRAMRegistersReg(m_RDRAM_Registers), + MIPSInterfaceReg(m_Mips_Interface), Video_InterfaceReg(m_Video_Interface), AudioInterfaceReg(m_Audio_Interface), PeripheralInterfaceReg(m_Peripheral_Interface), diff --git a/Source/Project64-core/N64System/Mips/Register.h b/Source/Project64-core/N64System/Mips/Register.h index a073db087..41fd4b96f 100644 --- a/Source/Project64-core/N64System/Mips/Register.h +++ b/Source/Project64-core/N64System/Mips/Register.h @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -48,136 +49,117 @@ private: enum { // Status register - STATUS_IE = 0x00000001, STATUS_EXL = 0x00000002, STATUS_ERL = 0x00000004, + STATUS_IE = 0x00000001, STATUS_EXL = 0x00000002, STATUS_ERL = 0x00000004, STATUS_IP0 = 0x00000100, STATUS_IP1 = 0x00000200, STATUS_IP2 = 0x00000400, STATUS_IP3 = 0x00000800, STATUS_IP4 = 0x00001000, STATUS_IP5 = 0x00002000, STATUS_IP6 = 0x00004000, STATUS_IP7 = 0x00008000, STATUS_BEV = 0x00400000, - STATUS_FR = 0x04000000, STATUS_CU0 = 0x10000000, STATUS_CU1 = 0x20000000, + STATUS_FR = 0x04000000, STATUS_CU0 = 0x10000000, STATUS_CU1 = 0x20000000, // Cause flags - CAUSE_EXC_CODE = 0xFF, - CAUSE_IP0 = 0x100, - CAUSE_IP1 = 0x200, - CAUSE_IP2 = 0x400, - CAUSE_IP3 = 0x800, - CAUSE_IP4 = 0x1000, - CAUSE_IP5 = 0x2000, - CAUSE_IP6 = 0x4000, - CAUSE_IP7 = 0x8000, - CAUSE_BD = 0x80000000, + CAUSE_EXC_CODE = 0xFF, + CAUSE_IP0 = 0x100, + CAUSE_IP1 = 0x200, + CAUSE_IP2 = 0x400, + CAUSE_IP3 = 0x800, + CAUSE_IP4 = 0x1000, + CAUSE_IP5 = 0x2000, + CAUSE_IP6 = 0x4000, + CAUSE_IP7 = 0x8000, + CAUSE_BD = 0x80000000, // Cause exception ID's - EXC_INT = 0, // Interrupt - EXC_MOD = 4, // TLB mod - EXC_RMISS = 8, // Read TLB miss - EXC_WMISS = 12, // Write TLB miss - EXC_RADE = 16, // Read address error - EXC_WADE = 20, // Write address error - EXC_IBE = 24, // Instruction bus error - EXC_DBE = 28, // Data bus error - EXC_SYSCALL = 32, // Syscall - EXC_BREAK = 36, // Breakpoint - EXC_II = 40, // Illegal instruction - EXC_CPU = 44, // Co-processor unusable - EXC_OV = 48, // Overflow - EXC_TRAP = 52, // Trap exception - EXC_VCEI = 56, // Virtual coherency on instruction fetch - EXC_FPE = 60, // Floating point exception - EXC_WATCH = 92, // Watchpoint reference - EXC_VCED = 124, // Virtual coherency on data read + EXC_INT = 0, // Interrupt + EXC_MOD = 4, // TLB mod + EXC_RMISS = 8, // Read TLB miss + EXC_WMISS = 12, // Write TLB miss + EXC_RADE = 16, // Read address error + EXC_WADE = 20, // Write address error + EXC_IBE = 24, // Instruction bus error + EXC_DBE = 28, // Data bus error + EXC_SYSCALL = 32, // Syscall + EXC_BREAK = 36, // Breakpoint + EXC_II = 40, // Illegal instruction + EXC_CPU = 44, // Co-processor unusable + EXC_OV = 48, // Overflow + EXC_TRAP = 52, // Trap exception + EXC_VCEI = 56, // Virtual coherency on instruction fetch + EXC_FPE = 60, // Floating point exception + EXC_WATCH = 92, // Watchpoint reference + EXC_VCED = 124, // Virtual coherency on data read }; // Float point control status register flags enum { - FPCSR_FS = 0x01000000, // Flush denormalization to zero - FPCSR_C = 0x00800000, // Condition bit - FPCSR_CE = 0x00020000, // Cause: unimplemented operation - FPCSR_CV = 0x00010000, // Cause: invalid operation - FPCSR_CZ = 0x00008000, // Cause: division by zero - FPCSR_CO = 0x00004000, // Cause: overflow - FPCSR_CU = 0x00002000, // Cause: underflow - FPCSR_CI = 0x00001000, // Cause: inexact operation - FPCSR_EV = 0x00000800, // Enable: invalid operation - FPCSR_EZ = 0x00000400, // Enable: division by zero - FPCSR_EO = 0x00000200, // Enable: overflow - FPCSR_EU = 0x00000100, // Enable: underflow - FPCSR_EI = 0x00000080, // Enable: inexact operation - FPCSR_FV = 0x00000040, // Flag: invalid operation - FPCSR_FZ = 0x00000020, // Flag: division by zero - FPCSR_FO = 0x00000010, // Flag: overflow - FPCSR_FU = 0x00000008, // Flag: underflow - FPCSR_FI = 0x00000004, // Flag: inexact operation - FPCSR_RM_MASK = 0x00000003, // Rounding mode mask - FPCSR_RM_RN = 0x00000000, // Round to nearest - FPCSR_RM_RZ = 0x00000001, // Round to zero - FPCSR_RM_RP = 0x00000002, // Round to positive infinity - FPCSR_RM_RM = 0x00000003, // Round to negative infinity + FPCSR_FS = 0x01000000, // Flush denormalization to zero + FPCSR_C = 0x00800000, // Condition bit + FPCSR_CE = 0x00020000, // Cause: unimplemented operation + FPCSR_CV = 0x00010000, // Cause: invalid operation + FPCSR_CZ = 0x00008000, // Cause: division by zero + FPCSR_CO = 0x00004000, // Cause: overflow + FPCSR_CU = 0x00002000, // Cause: underflow + FPCSR_CI = 0x00001000, // Cause: inexact operation + FPCSR_EV = 0x00000800, // Enable: invalid operation + FPCSR_EZ = 0x00000400, // Enable: division by zero + FPCSR_EO = 0x00000200, // Enable: overflow + FPCSR_EU = 0x00000100, // Enable: underflow + FPCSR_EI = 0x00000080, // Enable: inexact operation + FPCSR_FV = 0x00000040, // Flag: invalid operation + FPCSR_FZ = 0x00000020, // Flag: division by zero + FPCSR_FO = 0x00000010, // Flag: overflow + FPCSR_FU = 0x00000008, // Flag: underflow + FPCSR_FI = 0x00000004, // Flag: inexact operation + FPCSR_RM_MASK = 0x00000003, // Rounding mode mask + FPCSR_RM_RN = 0x00000000, // Round to nearest + FPCSR_RM_RZ = 0x00000001, // Round to zero + FPCSR_RM_RP = 0x00000002, // Round to positive infinity + FPCSR_RM_RM = 0x00000003, // Round to negative infinity }; -// MIPS interface registers -class Mips_InterfaceReg -{ -protected: - Mips_InterfaceReg (uint32_t * _MipsInterface); - -public: - uint32_t & MI_INIT_MODE_REG; - uint32_t & MI_MODE_REG; - uint32_t & MI_VERSION_REG; - uint32_t & MI_NOOP_REG; - uint32_t & MI_INTR_REG; - uint32_t & MI_INTR_MASK_REG; - -private: - Mips_InterfaceReg(); - Mips_InterfaceReg(const Mips_InterfaceReg&); - Mips_InterfaceReg& operator=(const Mips_InterfaceReg&); -}; // MIPS interface flags enum { - MI_MODE_INIT = 0x0080, // Bit 7: Initialization mode - MI_MODE_EBUS = 0x0100, // Bit 8: EBUS test mode - MI_MODE_RDRAM = 0x0200, // Bit 9: RDRAM register mode + MI_MODE_INIT = 0x0080, // Bit 7: Initialization mode + MI_MODE_EBUS = 0x0100, // Bit 8: EBUS test mode + MI_MODE_RDRAM = 0x0200, // Bit 9: RDRAM register mode - MI_CLR_INIT = 0x0080, // Bit 7: Clear initialization mode - MI_SET_INIT = 0x0100, // Bit 8: Set initialization mode - MI_CLR_EBUS = 0x0200, // Bit 9: Clear EBUS test - MI_SET_EBUS = 0x0400, // Bit 10: Set EBUS test mode - MI_CLR_DP_INTR = 0x0800, // Bit 11: Clear DP interrupt - MI_CLR_RDRAM = 0x1000, // Bit 12: Clear RDRAM register - MI_SET_RDRAM = 0x2000, // Bit 13: Set RDRAM register mode + MI_CLR_INIT = 0x0080, // Bit 7: Clear initialization mode + MI_SET_INIT = 0x0100, // Bit 8: Set initialization mode + MI_CLR_EBUS = 0x0200, // Bit 9: Clear EBUS test + MI_SET_EBUS = 0x0400, // Bit 10: Set EBUS test mode + MI_CLR_DP_INTR = 0x0800, // Bit 11: Clear DP interrupt + MI_CLR_RDRAM = 0x1000, // Bit 12: Clear RDRAM register + MI_SET_RDRAM = 0x2000, // Bit 13: Set RDRAM register mode // Flags for writing to MI_INTR_MASK_REG - MI_INTR_MASK_CLR_SP = 0x0001, // Bit 0: Clear SP mask - MI_INTR_MASK_SET_SP = 0x0002, // Bit 1: Set SP mask - MI_INTR_MASK_CLR_SI = 0x0004, // Bit 2: Clear SI mask - MI_INTR_MASK_SET_SI = 0x0008, // Bit 3: Set SI mask - MI_INTR_MASK_CLR_AI = 0x0010, // Bit 4: Clear AI mask - MI_INTR_MASK_SET_AI = 0x0020, // Bit 5: Set AI mask - MI_INTR_MASK_CLR_VI = 0x0040, // Bit 6: Clear VI mask - MI_INTR_MASK_SET_VI = 0x0080, // Bit 7: Set VI mask - MI_INTR_MASK_CLR_PI = 0x0100, // Bit 8: Clear PI mask - MI_INTR_MASK_SET_PI = 0x0200, // Bit 9: Set PI mask - MI_INTR_MASK_CLR_DP = 0x0400, // Bit 10: Clear DP mask - MI_INTR_MASK_SET_DP = 0x0800, // Bit 11: Set DP mask + MI_INTR_MASK_CLR_SP = 0x0001, // Bit 0: Clear SP mask + MI_INTR_MASK_SET_SP = 0x0002, // Bit 1: Set SP mask + MI_INTR_MASK_CLR_SI = 0x0004, // Bit 2: Clear SI mask + MI_INTR_MASK_SET_SI = 0x0008, // Bit 3: Set SI mask + MI_INTR_MASK_CLR_AI = 0x0010, // Bit 4: Clear AI mask + MI_INTR_MASK_SET_AI = 0x0020, // Bit 5: Set AI mask + MI_INTR_MASK_CLR_VI = 0x0040, // Bit 6: Clear VI mask + MI_INTR_MASK_SET_VI = 0x0080, // Bit 7: Set VI mask + MI_INTR_MASK_CLR_PI = 0x0100, // Bit 8: Clear PI mask + MI_INTR_MASK_SET_PI = 0x0200, // Bit 9: Set PI mask + MI_INTR_MASK_CLR_DP = 0x0400, // Bit 10: Clear DP mask + MI_INTR_MASK_SET_DP = 0x0800, // Bit 11: Set DP mask // Flags for reading from MI_INTR_MASK_REG - MI_INTR_MASK_SP = 0x01, // Bit 0: SP INTR mask - MI_INTR_MASK_SI = 0x02, // Bit 1: SI INTR mask - MI_INTR_MASK_AI = 0x04, // Bit 2: AI INTR mask - MI_INTR_MASK_VI = 0x08, // Bit 3: VI INTR mask - MI_INTR_MASK_PI = 0x10, // Bit 4: PI INTR mask - MI_INTR_MASK_DP = 0x20, // Bit 5: DP INTR mask + MI_INTR_MASK_SP = 0x01, // Bit 0: SP INTR mask + MI_INTR_MASK_SI = 0x02, // Bit 1: SI INTR mask + MI_INTR_MASK_AI = 0x04, // Bit 2: AI INTR mask + MI_INTR_MASK_VI = 0x08, // Bit 3: VI INTR mask + MI_INTR_MASK_PI = 0x10, // Bit 4: PI INTR mask + MI_INTR_MASK_DP = 0x20, // Bit 5: DP INTR mask - MI_INTR_SP = 0x01, // Bit 0: SP INTR - MI_INTR_SI = 0x02, // Bit 1: SI INTR - MI_INTR_AI = 0x04, // Bit 2: AI INTR - MI_INTR_VI = 0x08, // Bit 3: VI INTR - MI_INTR_PI = 0x10, // Bit 4: PI INTR - MI_INTR_DP = 0x20, // Bit 5: DP INTR + MI_INTR_SP = 0x01, // Bit 0: SP INTR + MI_INTR_SI = 0x02, // Bit 1: SI INTR + MI_INTR_AI = 0x04, // Bit 2: AI INTR + MI_INTR_VI = 0x08, // Bit 3: VI INTR + MI_INTR_PI = 0x10, // Bit 4: PI INTR + MI_INTR_DP = 0x20, // Bit 5: DP INTR }; // MIPS interface registers @@ -239,65 +221,65 @@ private: enum { - AI_STATUS_FIFO_FULL = 0x80000000, // Bit 31: Full - AI_STATUS_DMA_BUSY = 0x40000000, // Bit 30: Busy + AI_STATUS_FIFO_FULL = 0x80000000, // Bit 31: Full + AI_STATUS_DMA_BUSY = 0x40000000, // Bit 30: Busy }; // Signal processor interface flags enum { - SP_CLR_HALT = 0x00001, // Bit 0: Clear halt - SP_SET_HALT = 0x00002, // Bit 1: Set halt - SP_CLR_BROKE = 0x00004, // Bit 2: Clear broke - SP_CLR_INTR = 0x00008, // Bit 3: Clear INTR - SP_SET_INTR = 0x00010, // Bit 4: Set INTR - SP_CLR_SSTEP = 0x00020, // Bit 5: Clear SSTEP - SP_SET_SSTEP = 0x00040, // Bit 6: Set SSTEP - SP_CLR_INTR_BREAK = 0x00080, // Bit 7: Clear INTR on break - SP_SET_INTR_BREAK = 0x00100, // Bit 8: Set INTR on break - SP_CLR_SIG0 = 0x00200, // Bit 9: Clear signal 0 - SP_SET_SIG0 = 0x00400, // Bit 10: Set signal 0 - SP_CLR_SIG1 = 0x00800, // Bit 11: Clear signal 1 - SP_SET_SIG1 = 0x01000, // Bit 12: Set signal 1 - SP_CLR_SIG2 = 0x02000, // Bit 13: Clear signal 2 - SP_SET_SIG2 = 0x04000, // Bit 14: Set signal 2 - SP_CLR_SIG3 = 0x08000, // Bit 15: Clear signal 3 - SP_SET_SIG3 = 0x10000, // Bit 16: Set signal 3 - SP_CLR_SIG4 = 0x20000, // Bit 17: Clear signal 4 - SP_SET_SIG4 = 0x40000, // Bit 18: Set signal 4 - SP_CLR_SIG5 = 0x80000, // Bit 19: Clear signal 5 - SP_SET_SIG5 = 0x100000, // Bit 20: Set signal 5 - SP_CLR_SIG6 = 0x200000, // Bit 21: Clear signal 6 - SP_SET_SIG6 = 0x400000, // Bit 22: Set signal 6 - SP_CLR_SIG7 = 0x800000, // Bit 23: Clear signal 7 - SP_SET_SIG7 = 0x1000000, // Bit 24: Set signal 7 + SP_CLR_HALT = 0x00001, // Bit 0: Clear halt + SP_SET_HALT = 0x00002, // Bit 1: Set halt + SP_CLR_BROKE = 0x00004, // Bit 2: Clear broke + SP_CLR_INTR = 0x00008, // Bit 3: Clear INTR + SP_SET_INTR = 0x00010, // Bit 4: Set INTR + SP_CLR_SSTEP = 0x00020, // Bit 5: Clear SSTEP + SP_SET_SSTEP = 0x00040, // Bit 6: Set SSTEP + SP_CLR_INTR_BREAK = 0x00080, // Bit 7: Clear INTR on break + SP_SET_INTR_BREAK = 0x00100, // Bit 8: Set INTR on break + SP_CLR_SIG0 = 0x00200, // Bit 9: Clear signal 0 + SP_SET_SIG0 = 0x00400, // Bit 10: Set signal 0 + SP_CLR_SIG1 = 0x00800, // Bit 11: Clear signal 1 + SP_SET_SIG1 = 0x01000, // Bit 12: Set signal 1 + SP_CLR_SIG2 = 0x02000, // Bit 13: Clear signal 2 + SP_SET_SIG2 = 0x04000, // Bit 14: Set signal 2 + SP_CLR_SIG3 = 0x08000, // Bit 15: Clear signal 3 + SP_SET_SIG3 = 0x10000, // Bit 16: Set signal 3 + SP_CLR_SIG4 = 0x20000, // Bit 17: Clear signal 4 + SP_SET_SIG4 = 0x40000, // Bit 18: Set signal 4 + SP_CLR_SIG5 = 0x80000, // Bit 19: Clear signal 5 + SP_SET_SIG5 = 0x100000, // Bit 20: Set signal 5 + SP_CLR_SIG6 = 0x200000, // Bit 21: Clear signal 6 + SP_SET_SIG6 = 0x400000, // Bit 22: Set signal 6 + SP_CLR_SIG7 = 0x800000, // Bit 23: Clear signal 7 + SP_SET_SIG7 = 0x1000000, // Bit 24: Set signal 7 - SP_STATUS_HALT = 0x001, // Bit 0: Halt - SP_STATUS_BROKE = 0x002, // Bit 1: Broke - SP_STATUS_DMA_BUSY = 0x004, // Bit 2: DMA busy - SP_STATUS_DMA_FULL = 0x008, // Bit 3: DMA full - SP_STATUS_IO_FULL = 0x010, // Bit 4: IO full - SP_STATUS_SSTEP = 0x020, // Bit 5: Single step - SP_STATUS_INTR_BREAK = 0x040, // Bit 6: Interrupt on break - SP_STATUS_SIG0 = 0x080, // Bit 7: Signal 0 set - SP_STATUS_SIG1 = 0x100, // Bit 8: Signal 1 set - SP_STATUS_SIG2 = 0x200, // Bit 9: Signal 2 set - SP_STATUS_SIG3 = 0x400, // Bit 10: Signal 3 set - SP_STATUS_SIG4 = 0x800, // Bit 11: Signal 4 set - SP_STATUS_SIG5 = 0x1000, // Bit 12: Signal 5 set - SP_STATUS_SIG6 = 0x2000, // Bit 13: Signal 6 set - SP_STATUS_SIG7 = 0x4000, // Bit 14: Signal 7 set + SP_STATUS_HALT = 0x001, // Bit 0: Halt + SP_STATUS_BROKE = 0x002, // Bit 1: Broke + SP_STATUS_DMA_BUSY = 0x004, // Bit 2: DMA busy + SP_STATUS_DMA_FULL = 0x008, // Bit 3: DMA full + SP_STATUS_IO_FULL = 0x010, // Bit 4: IO full + SP_STATUS_SSTEP = 0x020, // Bit 5: Single step + SP_STATUS_INTR_BREAK = 0x040, // Bit 6: Interrupt on break + SP_STATUS_SIG0 = 0x080, // Bit 7: Signal 0 set + SP_STATUS_SIG1 = 0x100, // Bit 8: Signal 1 set + SP_STATUS_SIG2 = 0x200, // Bit 9: Signal 2 set + SP_STATUS_SIG3 = 0x400, // Bit 10: Signal 3 set + SP_STATUS_SIG4 = 0x800, // Bit 11: Signal 4 set + SP_STATUS_SIG5 = 0x1000, // Bit 12: Signal 5 set + SP_STATUS_SIG6 = 0x2000, // Bit 13: Signal 6 set + SP_STATUS_SIG7 = 0x4000, // Bit 14: Signal 7 set }; // Peripheral interface flags enum { - PI_STATUS_DMA_BUSY = 0x01, - PI_STATUS_IO_BUSY = 0x02, - PI_STATUS_ERROR = 0x04, + PI_STATUS_DMA_BUSY = 0x01, + PI_STATUS_IO_BUSY = 0x02, + PI_STATUS_ERROR = 0x04, - PI_SET_RESET = 0x01, - PI_CLR_INTR = 0x02, + PI_SET_RESET = 0x01, + PI_CLR_INTR = 0x02, }; class Serial_InterfaceReg @@ -320,10 +302,10 @@ private: // Serial interface flags enum { - SI_STATUS_DMA_BUSY = 0x0001, - SI_STATUS_RD_BUSY = 0x0002, - SI_STATUS_DMA_ERROR = 0x0008, - SI_STATUS_INTERRUPT = 0x1000, + SI_STATUS_DMA_BUSY = 0x0001, + SI_STATUS_RD_BUSY = 0x0002, + SI_STATUS_DMA_ERROR = 0x0008, + SI_STATUS_INTERRUPT = 0x1000, }; // Disk interface @@ -365,31 +347,31 @@ private: // Disk interface flags enum { - DD_STATUS_DATA_RQ = 0x40000000, - DD_STATUS_C2_XFER = 0x10000000, - DD_STATUS_BM_ERR = 0x08000000, - DD_STATUS_BM_INT = 0x04000000, - DD_STATUS_MECHA_INT = 0x02000000, - DD_STATUS_DISK_PRES = 0x01000000, - DD_STATUS_BUSY_STATE = 0x00800000, - DD_STATUS_RST_STATE = 0x00400000, - DD_STATUS_MTR_N_SPIN = 0x00100000, - DD_STATUS_HEAD_RTRCT = 0x00080000, - DD_STATUS_WR_PR_ERR = 0x00040000, - DD_STATUS_MECHA_ERR = 0x00020000, - DD_STATUS_DISK_CHNG = 0x00010000, + DD_STATUS_DATA_RQ = 0x40000000, + DD_STATUS_C2_XFER = 0x10000000, + DD_STATUS_BM_ERR = 0x08000000, + DD_STATUS_BM_INT = 0x04000000, + DD_STATUS_MECHA_INT = 0x02000000, + DD_STATUS_DISK_PRES = 0x01000000, + DD_STATUS_BUSY_STATE = 0x00800000, + DD_STATUS_RST_STATE = 0x00400000, + DD_STATUS_MTR_N_SPIN = 0x00100000, + DD_STATUS_HEAD_RTRCT = 0x00080000, + DD_STATUS_WR_PR_ERR = 0x00040000, + DD_STATUS_MECHA_ERR = 0x00020000, + DD_STATUS_DISK_CHNG = 0x00010000, - DD_BM_STATUS_RUNNING = 0x80000000, - DD_BM_STATUS_ERROR = 0x04000000, - DD_BM_STATUS_MICRO = 0x02000000, - DD_BM_STATUS_BLOCK = 0x01000000, + DD_BM_STATUS_RUNNING = 0x80000000, + DD_BM_STATUS_ERROR = 0x04000000, + DD_BM_STATUS_MICRO = 0x02000000, + DD_BM_STATUS_BLOCK = 0x01000000, - DD_BM_CTL_START = 0x80000000, - DD_BM_CTL_MNGRMODE = 0x40000000, - DD_BM_CTL_INTMASK = 0x20000000, - DD_BM_CTL_RESET = 0x10000000, - DD_BM_CTL_BLK_TRANS = 0x02000000, - DD_BM_CTL_MECHA_RST = 0x01000000 + DD_BM_CTL_START = 0x80000000, + DD_BM_CTL_MNGRMODE = 0x40000000, + DD_BM_CTL_INTMASK = 0x20000000, + DD_BM_CTL_RESET = 0x10000000, + DD_BM_CTL_BLK_TRANS = 0x02000000, + DD_BM_CTL_MECHA_RST = 0x01000000 }; class CRegName @@ -429,7 +411,7 @@ class CRegisters : protected CSystemRegisters, public CP0registers, public RDRAMRegistersReg, - public Mips_InterfaceReg, + public MIPSInterfaceReg, public Video_InterfaceReg, public AudioInterfaceReg, public PeripheralInterfaceReg, diff --git a/Source/Project64-core/N64System/Recompiler/x86/x86RecompilerOps.cpp b/Source/Project64-core/N64System/Recompiler/x86/x86RecompilerOps.cpp index fc0a04056..59abbb814 100644 --- a/Source/Project64-core/N64System/Recompiler/x86/x86RecompilerOps.cpp +++ b/Source/Project64-core/N64System/Recompiler/x86/x86RecompilerOps.cpp @@ -11095,7 +11095,14 @@ void CX86RecompilerOps::SW_Register(x86Reg Reg, uint32_t VAddr) MoveX86regToVariable(Reg, &CMipsMemoryVM::m_MemLookupValue.UW[0], "CMipsMemoryVM::m_MemLookupValue.UW[0]"); MoveConstToVariable(PAddr, &CMipsMemoryVM::m_MemLookupAddress, "m_MemLookupAddress"); m_RegWorkingSet.BeforeCallDirect(); - Call_Direct((void *)CMipsMemoryVM::Write32MIPSInterface, "CMipsMemoryVM::Write32MIPSInterface"); +#ifdef _MSC_VER + MoveConstToX86reg((uint32_t)(MemoryHandler*)&g_MMU->m_MIPSInterfaceHandler, x86_ECX); + Call_Direct((void*)((long**)(MemoryHandler*)&g_MMU->m_MIPSInterfaceHandler)[0][1], "MIPSInterfaceHandler::Write32"); +#else + PushImm32((uint32_t)&g_MMU->m_MIPSInterfaceHandler); + Call_Direct(AddressOf(&SPRegistersHandler::Write32), "MIPSInterfaceHandler::Write32"); + AddConstToX86Reg(x86_ESP, 16); +#endif m_RegWorkingSet.AfterCallDirect(); break; case 0x0430000C: diff --git a/Source/Project64-core/Plugins/Plugin.h b/Source/Project64-core/Plugins/Plugin.h index db6962282..a810f1e92 100644 --- a/Source/Project64-core/Plugins/Plugin.h +++ b/Source/Project64-core/Plugins/Plugin.h @@ -60,7 +60,7 @@ typedef struct void(*FlushSettings) (void * handle); } PLUGIN_SETTINGS3; -typedef struct +typedef struct _PLUGIN_SETTINGS_NOTIFICATION { typedef void(*SettingChangedFunc)(void *); diff --git a/Source/Project64-core/Project64-core.vcxproj b/Source/Project64-core/Project64-core.vcxproj index 957c94312..56f745490 100644 --- a/Source/Project64-core/Project64-core.vcxproj +++ b/Source/Project64-core/Project64-core.vcxproj @@ -54,6 +54,7 @@ + @@ -155,6 +156,7 @@ + diff --git a/Source/Project64-core/Project64-core.vcxproj.filters b/Source/Project64-core/Project64-core.vcxproj.filters index 244f67ffd..c1398d52d 100644 --- a/Source/Project64-core/Project64-core.vcxproj.filters +++ b/Source/Project64-core/Project64-core.vcxproj.filters @@ -372,6 +372,9 @@ Source Files\N64 System\MemoryHandler + + Source Files\N64 System\MemoryHandler + @@ -710,6 +713,9 @@ Header Files\N64 System\MemoryHandler + + Header Files\N64 System\MemoryHandler +